]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
pci: intel: Fix configuration type based on secondary number
authorLey Foon Tan <ley.foon.tan@intel.com>
Fri, 24 May 2019 02:30:00 +0000 (10:30 +0800)
committerTom Rini <trini@konsulko.com>
Sun, 11 Aug 2019 20:43:41 +0000 (16:43 -0400)
This fix issue when access config from PCIe switch.

The PCIe controller need to send Type 0 config TLP if the targeting bus
matches with the secondary bus number, which is when the TLP is targeting
the immediate device on the link.

The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
drivers/pci/pcie_intel_fpga.c

index a096d1c697bb657ad87fa5723e8fbca1e158fb6a..a5ea4888f344d4595730282c4b6f67542d8742a8 100644 (file)
 
 #define RP_CFG_ADDR(pcie, reg)                                         \
                ((pcie->hip_base) + (reg) + (1 << 20))
+#define RP_SECONDARY(pcie)                                             \
+       readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
 #define TLP_REQ_ID(bus, devfn)         (((bus) << 8) | (devfn))
 
 #define TLP_CFGRD_DW0(pcie, bus)                                       \
-       ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0              \
-                                     : TLP_FMTTYPE_CFGRD1) << 24) |    \
+       ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1              \
+                                     : TLP_FMTTYPE_CFGRD0) << 24) |    \
                                        TLP_PAYLOAD_SIZE)
 
 #define TLP_CFGWR_DW0(pcie, bus)                                       \
-       ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0              \
-                                     : TLP_FMTTYPE_CFGWR1) << 24) |    \
+       ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1              \
+                                     : TLP_FMTTYPE_CFGWR0) << 24) |    \
                                        TLP_PAYLOAD_SIZE)
 
 #define TLP_CFG_DW1(pcie, tag, be)                                     \