ARM: DTS: stm32: add pwrcfg node for stm32f746

This node is needed to enable performance mode
when system frequency is set up to 200Mhz.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi
index 5f77f578af81f07715cbd38dad8b890333c4774f..a56ae9312100631e2a27f5cd561332f5d33d4797 100644 (file)
--- a/arch/arm/dts/stm32f7-u-boot.dtsi
+++ b/arch/arm/dts/stm32f7-u-boot.dtsi
@@ -22,3 +22,7 @@
                 u-boot,dm-pre-reloc;
        };
 };
+
+&pwrcfg {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 783d4e734e5873f428d6f3a992d2fde24d68a388..b95cca21b620b8877851f87a51cc1f3b232380cc 100644 (file)
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -99,12 +99,19 @@
                        status = "disabled";
                        u-boot,dm-pre-reloc;
                };
+
+               pwrcfg: power-config@58024800 {
+                       compatible = "syscon";
+                       reg = <0x40007000 0x400>;
+               };
+
                rcc: rcc@40023810 {
                        #reset-cells = <1>;
                        #clock-cells = <2>;
                        compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
                        reg = <0x40023800 0x400>;
                        clocks = <&clk_hse>;
+                       st,syscfg = <&pwrcfg>;
                        u-boot,dm-pre-reloc;
                };