arm: mvebu: a38x: serdes: Add comments and use macros in PCIe code

Replace magic register offsets by macros to make code more readable.
Add comments about what this code is doing.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index bb7d24b4b7ba586bcd7420085d85c1fc3ce0fa10..7b4710501dff6f46ef11a1f2bf21c3621ccc5b2c 100644 (file)
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -1721,31 +1721,44 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
                                        reg_data &= ~0x4000;
                                reg_write(SOC_CONTROL_REG1, reg_data);
 
-                               reg_data =
-                                   reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
-                                             0x6c));
+                               /* Set Maximum Link Width to X1 or X4 */
+                               reg_data = reg_read(PEX_CFG_DIRECT_ACCESS(
+                                                    pex_idx,
+                                                    PEX_LINK_CAPABILITY_REG));
                                reg_data &= ~0x3f0;
                                if (is_pex_by1 == 1)
                                        reg_data |= 0x10;
                                else
                                        reg_data |= 0x40;
-                               reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
+                               reg_write(PEX_CFG_DIRECT_ACCESS(
+                                          pex_idx,
+                                          PEX_LINK_CAPABILITY_REG),
                                          reg_data);
 
-                               reg_data =
-                                   reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
-                                             0x6c));
+                               /* Set Maximum Link Speed to 5 GT/s */
+                               reg_data = reg_read(PEX_CFG_DIRECT_ACCESS(
+                                                    pex_idx,
+                                                    PEX_LINK_CAPABILITY_REG));
                                reg_data &= ~0xf;
                                reg_data |= 0x2;
-                               reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
+                               reg_write(PEX_CFG_DIRECT_ACCESS(
+                                          pex_idx,
+                                          PEX_LINK_CAPABILITY_REG),
                                          reg_data);
 
-                               reg_data =
-                                   reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
-                                             0x70));
+                               /*
+                                * Set Common Clock Configuration to indicates
+                                * that both devices on the link use a
+                                * distributed common reference clock.
+                                */
+                               reg_data = reg_read(PEX_CFG_DIRECT_ACCESS(
+                                                    pex_idx,
+                                                    PEX_LINK_CTRL_STAT_REG));
                                reg_data &= ~0x40;
                                reg_data |= 0x40;
-                               reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70),
+                               reg_write(PEX_CFG_DIRECT_ACCESS(
+                                          pex_idx,
+                                          PEX_LINK_CTRL_STAT_REG),
                                          reg_data);
                        }