riscv: dts: move out AE350 L2 node from cpus node

When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13f16d0941ac79cc3e6dd420d321b849e82..97b7cee983db4a6c84059cf8726981733b3c1928 100644 (file)
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@
                                compatible = "riscv,cpu-intc";
                        };
                };
+       };
 
-               L2: l2-cache@e0500000 {
-                       compatible = "cache";
-                       cache-level = <2>;
-                       cache-size = <0x40000>;
-                       reg = <0x0 0xe0500000 0x0 0x40000>;
-               };
+       L2: l2-cache@e0500000 {
+               compatible = "v5l2cache";
+               cache-level = <2>;
+               cache-size = <0x40000>;
+               reg = <0xe0500000 0x40000>;
+               andes,inst-prefetch = <3>;
+               andes,data-prefetch = <3>;
+               /* The value format is <XRAMOCTL XRAMICTL> */
+               andes,tag-ram-ctl = <0 0>;
+               andes,data-ram-ctl = <0 0>;
        };
 
        memory@0 {

diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a8e4d82da42b5c5852763cb30fc6790443..d8f00f8d3a7b82a89828ad4ba89e57183c70bbfa 100644 (file)
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@
                                compatible = "riscv,cpu-intc";
                        };
                };
+       };
 
-               L2: l2-cache@e0500000 {
-                       compatible = "cache";
-                       cache-level = <2>;
-                       cache-size = <0x40000>;
-                       reg = <0x0 0xe0500000 0x0 0x40000>;
-               };
+       L2: l2-cache@e0500000 {
+               compatible = "v5l2cache";
+               cache-level = <2>;
+               cache-size = <0x40000>;
+               reg = <0x0 0xe0500000 0x0 0x40000>;
+               andes,inst-prefetch = <3>;
+               andes,data-prefetch = <3>;
+               /* The value format is <XRAMOCTL XRAMICTL> */
+               andes,tag-ram-ctl = <0 0>;
+               andes,data-ram-ctl = <0 0>;
        };
 
        memory@0 {