sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/

The p2wi interface is only available on sun6i, adjust the gpio pinmux and
base address defines for it to reflect this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c
index 48613bd0eae950c82eb596f882fc0f1c8d3a553c..26a9cfc68bf33ff90bac65008b8b4b4e5add5486 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/p2wi.c
+++ b/arch/arm/cpu/armv7/sunxi/p2wi.c
@@ -26,13 +26,13 @@
 
 void p2wi_init(void)
 {
-       struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+       struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 
        /* Enable p2wi and PIO clk, and de-assert their resets */
        prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
 
-       sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
-       sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
+       sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
+       sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
 
        /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
        writel(P2WI_CTRL_RESET, &p2wi->ctrl);
@@ -43,7 +43,7 @@ void p2wi_init(void)
 
 int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
 {
-       struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+       struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
        unsigned long tmo = timer_get_us() + 1000000;
 
        writel(P2WI_PM_DEV_ADDR(slave_addr) |
@@ -62,7 +62,7 @@ int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
 
 static int p2wi_await_trans(void)
 {
-       struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+       struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
        unsigned long tmo = timer_get_us() + 1000000;
        int ret;
        u8 reg;
@@ -88,7 +88,7 @@ static int p2wi_await_trans(void)
 
 int p2wi_read(const u8 addr, u8 *data)
 {
-       struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+       struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
        int ret;
 
        writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
@@ -105,7 +105,7 @@ int p2wi_read(const u8 addr, u8 *data)
 
 int p2wi_write(const u8 addr, u8 data)
 {
-       struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+       struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 
        writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
        writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);

diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index 9500262ca93ac79a4eb78aed2f6c58f53669afaa..adf203ab96c4fdbf8326202780b4c7b91df885a7 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -128,7 +128,7 @@
 #define SUN6I_CPUCFG_BASE              0x01f01c00
 #define SUNXI_R_UART_BASE              0x01f02800
 #define SUNXI_R_PIO_BASE               0x01f02c00
-#define SUNXI_P2WI_BASE                        0x01f03400
+#define SUN6I_P2WI_BASE                        0x01f03400
 
 /* CoreSight Debug Module */
 #define SUNXI_CSDM_BASE                        0x3f500000

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 366c0dc45ac119ea428a795b89edacf90b5a47b6..9f972cefd91f20d1d7c4f3279c3f3e4eeee42c20 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -173,8 +173,8 @@ enum sunxi_gpio_number {
 
 #define SUN4I_GPI4_SDC3                2
 
-#define SUNXI_GPL0_R_P2WI_SCK  3
-#define SUNXI_GPL1_R_P2WI_SDA  3
+#define SUN6I_GPL0_R_P2WI_SCK  3
+#define SUN6I_GPL1_R_P2WI_SDA  3
 
 #define SUN8I_GPL2_R_UART_TX   2
 #define SUN8I_GPL3_R_UART_RX   2