ARM: dts: stm32: Add timer support for STM32F7

Add missing timer node to enable timer5 for STM32F7 SoCs family

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi
index 9a9e4e5f3718b8fe5534c7a3314d682ebac1ff86..4a677192a2dd925b99c5ec36afeae3f46e51c708 100644 (file)
--- a/arch/arm/dts/stm32f7-u-boot.dtsi
+++ b/arch/arm/dts/stm32f7-u-boot.dtsi
@@ -1,3 +1,11 @@
+/{
+       soc {
+               timer5: timer@40000c00 {
+                       u-boot,dm-pre-reloc;
+               };
+       };
+};
+
 &pinctrl {
        usart1_pins_a: usart1@0 {
                u-boot,dm-pre-reloc;

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 46d148eab2c83b0916b453039ab62264b56a0cb5..8c6fa133e0ab5807153951873391e350a33ec3cb 100644 (file)
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -323,6 +323,13 @@
                        pinctrl-names = "default", "opendrain";
                        max-frequency = <48000000>;
                };
+
+               timer5: timer@40000c00 {
+                       compatible = "st,stm32-timer";
+                       reg = <0x40000c00 0x400>;
+                       interrupts = <50>;
+                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
+               };
        };
 };