ARM: dts: uniphier: sync with Linux 5.1-rc4

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index 31ba52b14e99bac5fcb916502cad710a8569a250..a3cd475b48d2bace6ee45bb78fcbe63955b2a923 100644 (file)
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -33,7 +33,7 @@
 
                cpu0: cpu@0 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0 0x000>;
                        clocks = <&sys_clk 33>;
                        enable-method = "psci";
@@ -42,7 +42,7 @@
 
                cpu1: cpu@1 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0 0x001>;
                        clocks = <&sys_clk 33>;
                        enable-method = "psci";

diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index b9ed613ace9ae45bb5e4f6941d8f36088de55ba4..baf23268366f0f73fdaec6bfff5c6a095e1b3704 100644 (file)
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -43,7 +43,7 @@
 
                cpu0: cpu@0 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a72", "arm,armv8";
+                       compatible = "arm,cortex-a72";
                        reg = <0 0x000>;
                        clocks = <&sys_clk 32>;
                        enable-method = "psci";
@@ -53,7 +53,7 @@
 
                cpu1: cpu@1 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a72", "arm,armv8";
+                       compatible = "arm,cortex-a72";
                        reg = <0 0x001>;
                        clocks = <&sys_clk 32>;
                        enable-method = "psci";
@@ -63,7 +63,7 @@
 
                cpu2: cpu@100 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0 0x100>;
                        clocks = <&sys_clk 33>;
                        enable-method = "psci";
@@ -73,7 +73,7 @@
 
                cpu3: cpu@101 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0 0x101>;
                        clocks = <&sys_clk 33>;
                        enable-method = "psci";
@@ -206,13 +206,10 @@
                        cooling-maps {
                                map0 {
                                        trip = <&cpu_alert>;
-                                       cooling-device = <&cpu0
-                                           THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-                               };
-                               map1 {
-                                       trip = <&cpu_alert>;
-                                       cooling-device = <&cpu2
-                                           THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };
@@ -891,6 +888,53 @@
                        };
                };
 
+               pcie: pcie@66000000 {
+                       compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+                       status = "disabled";
+                       reg-names = "dbi", "link", "config";
+                       reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
+                             <0x2fff0000 0x10000>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       clocks = <&sys_clk 24>;
+                       resets = <&sys_rst 24>;
+                       num-lanes = <1>;
+                       num-viewport = <1>;
+                       bus-range = <0x0 0xff>;
+                       device_type = "pci";
+                       ranges =
+                       /* downstream I/O */
+                               <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
+                       /* non-prefetchable memory */
+                               <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
+                       #interrupt-cells = <1>;
+                       interrupt-names = "dma", "msi";
+                       interrupts = <0 224 4>, <0 225 4>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
+                                       <0 0 0 2 &pcie_intc 1>, /* INTB */
+                                       <0 0 0 3 &pcie_intc 2>, /* INTC */
+                                       <0 0 0 4 &pcie_intc 3>; /* INTD */
+                       phy-names = "pcie-phy";
+                       phys = <&pcie_phy>;
+
+                       pcie_intc: legacy-interrupt-controller {
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                               interrupt-parent = <&gic>;
+                               interrupts = <0 226 4>;
+                       };
+               };
+
+               pcie_phy: phy@66038000 {
+                       compatible = "socionext,uniphier-ld20-pcie-phy";
+                       reg = <0x66038000 0x4000>;
+                       #phy-cells = <0>;
+                       clocks = <&sys_clk 24>;
+                       resets = <&sys_rst 24>;
+                       socionext,syscon = <&soc_glue>;
+               };
+
                nand: nand@68000000 {
                        compatible = "socionext,uniphier-denali-nand-v5b";
                        status = "disabled";

diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index b73d594b6dcd472de158e2e98a9223719160624b..c2706cef0b8a1105ab539f3be9efd18c1dcab1ee 100644 (file)
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -235,6 +235,16 @@
                        };
                };
 
+               dmac: dma-controller@5a000000 {
+                       compatible = "socionext,uniphier-mio-dmac";
+                       reg = <0x5a000000 0x1000>;
+                       interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+                                    <0 71 4>, <0 72 4>, <0 73 4>;
+                       clocks = <&mio_clk 7>;
+                       resets = <&mio_rst 7>;
+                       #dma-cells = <1>;
+               };
+
                sd: sdhc@5a400000 {
                        compatible = "socionext,uniphier-sd-v2.91";
                        status = "disabled";
@@ -246,6 +256,8 @@
                        clocks = <&mio_clk 0>;
                        reset-names = "host", "bridge";
                        resets = <&mio_rst 0>, <&mio_rst 3>;
+                       dma-names = "rx-tx";
+                       dmas = <&dmac 4>;
                        bus-width = <4>;
                        cap-sd-highspeed;
                        sd-uhs-sdr12;
@@ -263,6 +275,8 @@
                        clocks = <&mio_clk 1>;
                        reset-names = "host", "bridge", "hw";
                        resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+                       dma-names = "rx-tx";
+                       dmas = <&dmac 6>;
                        bus-width = <8>;
                        cap-mmc-highspeed;
                        cap-mmc-hw-reset;

diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index ef342088e1c562d388b7bb3eee6df1739fb172d4..d090fc7e2d8bdc849f053ba5db6bf02ac2148afd 100644 (file)
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -269,6 +269,16 @@
                        };
                };
 
+               dmac: dma-controller@5a000000 {
+                       compatible = "socionext,uniphier-mio-dmac";
+                       reg = <0x5a000000 0x1000>;
+                       interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+                                    <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
+                       clocks = <&mio_clk 7>;
+                       resets = <&mio_rst 7>;
+                       #dma-cells = <1>;
+               };
+
                sd: sdhc@5a400000 {
                        compatible = "socionext,uniphier-sd-v2.91";
                        status = "disabled";
@@ -280,6 +290,8 @@
                        clocks = <&mio_clk 0>;
                        reset-names = "host", "bridge";
                        resets = <&mio_rst 0>, <&mio_rst 3>;
+                       dma-names = "rx-tx";
+                       dmas = <&dmac 4>;
                        bus-width = <4>;
                        cap-sd-highspeed;
                        sd-uhs-sdr12;
@@ -297,6 +309,8 @@
                        clocks = <&mio_clk 1>;
                        reset-names = "host", "bridge", "hw";
                        resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+                       dma-names = "rx-tx";
+                       dmas = <&dmac 5>;
                        bus-width = <8>;
                        cap-mmc-highspeed;
                        cap-mmc-hw-reset;
@@ -313,6 +327,8 @@
                        clocks = <&mio_clk 2>;
                        reset-names = "host", "bridge";
                        resets = <&mio_rst 2>, <&mio_rst 5>;
+                       dma-names = "rx-tx";
+                       dmas = <&dmac 6>;
                        bus-width = <4>;
                        cap-sd-highspeed;
                };

diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index fa25ffd97f63449acc6100f227c952474234399d..4e11e85d8dd71e954c075edf93ff2d7a97f438d4 100644 (file)
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -141,8 +141,10 @@
                        cooling-maps {
                                map {
                                        trip = <&cpu_alert>;
-                                       cooling-device = <&cpu0
-                                           THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };

diff --git a/arch/arm/dts/uniphier-pxs3-ref.dts b/arch/arm/dts/uniphier-pxs3-ref.dts
index 4fb12b8a675edbfac8154f2f3e06961c0a242595..1965e4dfe4a4778de7b914605d8c78f96560f0d0 100644 (file)
--- a/arch/arm/dts/uniphier-pxs3-ref.dts
+++ b/arch/arm/dts/uniphier-pxs3-ref.dts
@@ -109,6 +109,10 @@
        status = "okay";
 };
 
+&pcie {
+       status = "okay";
+};
+
 &nand {
        status = "okay";
 };

diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi
index f629c6a862f7a81b49606f6bea60188fa14a2cc9..961d4d3621f4fd39c5e23adb0f257362f5b3576f 100644 (file)
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -39,7 +39,7 @@
 
                cpu0: cpu@0 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0 0x000>;
                        clocks = <&sys_clk 33>;
                        enable-method = "psci";
@@ -48,7 +48,7 @@
 
                cpu1: cpu@1 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0 0x001>;
                        clocks = <&sys_clk 33>;
                        enable-method = "psci";
@@ -57,7 +57,7 @@
 
                cpu2: cpu@2 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0 0x002>;
                        clocks = <&sys_clk 33>;
                        enable-method = "psci";
@@ -66,7 +66,7 @@
 
                cpu3: cpu@3 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0 0x003>;
                        clocks = <&sys_clk 33>;
                        enable-method = "psci";
@@ -765,6 +765,53 @@
                        };
                };
 
+               pcie: pcie@66000000 {
+                       compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+                       status = "disabled";
+                       reg-names = "dbi", "link", "config";
+                       reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
+                             <0x2fff0000 0x10000>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       clocks = <&sys_clk 24>;
+                       resets = <&sys_rst 24>;
+                       num-lanes = <1>;
+                       num-viewport = <1>;
+                       bus-range = <0x0 0xff>;
+                       device_type = "pci";
+                       ranges =
+                       /* downstream I/O */
+                               <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
+                       /* non-prefetchable memory */
+                               <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
+                       #interrupt-cells = <1>;
+                       interrupt-names = "dma", "msi";
+                       interrupts = <0 224 4>, <0 225 4>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
+                                       <0 0 0 2 &pcie_intc 1>, /* INTB */
+                                       <0 0 0 3 &pcie_intc 2>, /* INTC */
+                                       <0 0 0 4 &pcie_intc 3>; /* INTD */
+                       phy-names = "pcie-phy";
+                       phys = <&pcie_phy>;
+
+                       pcie_intc: legacy-interrupt-controller {
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                               interrupt-parent = <&gic>;
+                               interrupts = <0 226 4>;
+                       };
+               };
+
+               pcie_phy: phy@66038000 {
+                       compatible = "socionext,uniphier-pxs3-pcie-phy";
+                       reg = <0x66038000 0x4000>;
+                       #phy-cells = <0>;
+                       clocks = <&sys_clk 24>;
+                       resets = <&sys_rst 24>;
+                       socionext,syscon = <&soc_glue>;
+               };
+
                nand: nand@68000000 {
                        compatible = "socionext,uniphier-denali-nand-v5b";
                        status = "disabled";

diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index f7fcf6b45995953e08dd0157ff6d14f4d00c97ec..efce02768b6fb5b44798ca291f1c5d699a7e00c4 100644 (file)
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -239,6 +239,16 @@
                        };
                };
 
+               dmac: dma-controller@5a000000 {
+                       compatible = "socionext,uniphier-mio-dmac";
+                       reg = <0x5a000000 0x1000>;
+                       interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+                                    <0 71 4>, <0 72 4>, <0 73 4>;
+                       clocks = <&mio_clk 7>;
+                       resets = <&mio_rst 7>;
+                       #dma-cells = <1>;
+               };
+
                sd: sdhc@5a400000 {
                        compatible = "socionext,uniphier-sd-v2.91";
                        status = "disabled";
@@ -250,6 +260,8 @@
                        clocks = <&mio_clk 0>;
                        reset-names = "host", "bridge";
                        resets = <&mio_rst 0>, <&mio_rst 3>;
+                       dma-names = "rx-tx";
+                       dmas = <&dmac 4>;
                        bus-width = <4>;
                        cap-sd-highspeed;
                        sd-uhs-sdr12;
@@ -267,6 +279,8 @@
                        clocks = <&mio_clk 1>;
                        reset-names = "host", "bridge", "hw";
                        resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+                       dma-names = "rx-tx";
+                       dmas = <&dmac 6>;
                        bus-width = <8>;
                        cap-mmc-highspeed;
                        cap-mmc-hw-reset;