clk_dm(SANDBOX_CLK_ECSPI_ROOT,
sandbox_clk_divider("ecspi_root", "pll3_60m", ®, 19, 6));
+ reg = 0;
+ clk_dm(SANDBOX_CLK_ECSPI0,
+ sandbox_clk_gate("ecspi0", "ecspi_root", ®, 0, 0));
+
clk_dm(SANDBOX_CLK_ECSPI1,
sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
reg, shift, width, 0);
}
+static inline struct clk *sandbox_clk_gate(const char *name, const char *parent,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags)
+{
+ return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, bit_idx, clk_gate_flags, NULL);
+}
+
struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
const char *parent_name,
unsigned long flags,
rate = clk_get_parent_rate(clk);
ut_asserteq(rate, 20000000);
+ /* test the gate of CCF */
+ ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("ecspi0", clk->dev->name);
+
+ rate = clk_get_parent_rate(clk);
+ ut_asserteq(rate, 20000000);
+
/* Test the mux of CCF */
ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
ut_assertok(ret);