fpga: zynqpl: Flush dcache only for non-bitstream data

In case of aes decryption destination address range must be flushed
before transferring decrypted data to destination.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 90bb850833112f3497bcbf258ec7198e2e7195d3..a11e4855253471d614e0eb7f0462237cb27f530a 100644 (file)
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -548,8 +548,9 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
         * Flush destination address range only if image is not
         * bitstream.
         */
-       flush_dcache_range((u32)dstaddr, (u32)dstaddr +
-                          roundup(dstlen << 2, ARCH_DMA_MINALIGN));
+       if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
+               flush_dcache_range((u32)dstaddr, (u32)dstaddr +
+                                  roundup(dstlen << 2, ARCH_DMA_MINALIGN));
 
        if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
                return FPGA_FAIL;