riscv: ax25: add SPL support

The U-Boot SPL will boot in M mode and load the FIT image which
include OpenSBI and U-Boot proper images. After loading progress,
it will jump to OpenSBI first and then U-Boot proper which will
run in S mode.

Also remove V5L2_CACHE due to U-Boot SPL code size consideration.
Without this concern, it can be enable manually for performance.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index d411a79c211f80b6d76017b4633d5ff23ebc3046..8d8d71dcbf970e64a92849b35e366078cd68218e 100644 (file)
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -6,7 +6,9 @@ config RISCV_NDS
        imply RISCV_TIMER
        imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
        imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
-       imply V5L2_CACHE
+       imply SPL_CPU_SUPPORT
+       imply SPL_OPENSBI
+       imply SPL_LOAD_FIT
        help
          Run U-Boot on AndeStar V5 platforms and use some specific features
          which are provided by Andes Technology AndeStar V5 families.