powerpc/mpc85xx: Add workaround for erratum A007212

Erratum A007212 for DDR is about a runaway condition for DDR PLL
oscilliator. Please refer to erratum document for detail.
For this workaround to work, DDR PLL needs to be disabled in RCW.
However, u-boot needs to know the expected PLL ratio. We put the
ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
if DDR PLL ratio is set, or the reserved field is not set.

Workaround for erratum A007212 applies to selected versions of
B4/T4 SoCs. It is safe to apply the workaround to all versions. It
is helpful for upgrading SoC without changing u-boot. In case DDR
PLL is disabled by RCW (part of the erratum workaround), we need this
u-boot workround to bring up DDR clock.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index ee063fd8e94865d9b3e91c29fc2af40947679e07..9d8acd0aa173ff29fa89b6aac8cef02e70e2393a 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -113,6 +113,21 @@ static void check_erratum_a4580(uint32_t svr)
 }
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+/*
+ * This workaround can be implemented in PBI, or by u-boot.
+ */
+static void check_erratum_a007212(void)
+{
+       u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
+
+       if (in_be32(plldgdcr) & 0x1fe) {
+               /* check if PLL ratio is set by workaround */
+               puts("Work-around for Erratum A007212 enabled\n");
+       }
+}
+#endif
+
 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
@@ -281,6 +296,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        if (has_erratum_a006261())
                puts("Work-around for Erratum A006261 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+       check_erratum_a007212();
+#endif
+
        return 0;
 }
 

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 0a33e8dbc1f69f5c53b8e60e1059e99c1738ffa2..941c20e00a58f2994d5859ca5cb4321ba249836d 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -280,6 +280,71 @@ static void corenet_tb_init(void)
 }
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+void fsl_erratum_a007212_workaround(void)
+{
+       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 ddr_pll_ratio;
+       u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
+       u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
+       u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+       u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
+       u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+       u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
+       u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
+#endif
+#endif
+       /*
+        * Even this workaround applies to selected version of SoCs, it is
+        * safe to apply to all versions, with the limitation of odd ratios.
+        * If RCW has disabled DDR PLL, we have to apply this workaround,
+        * otherwise DDR will not work.
+        */
+       ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
+               FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
+               FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+       /* check if RCW sets ratio to 0, required by this workaround */
+       if (ddr_pll_ratio != 0)
+               return;
+       ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
+               FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
+               FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+       /* check if reserved bits have the desired ratio */
+       if (ddr_pll_ratio == 0) {
+               printf("Error: Unknown DDR PLL ratio!\n");
+               return;
+       }
+       ddr_pll_ratio >>= 1;
+
+       setbits_be32(plldadcr1, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+       setbits_be32(plldadcr2, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+       setbits_be32(plldadcr3, 0x02000001);
+#endif
+#endif
+       setbits_be32(dpdovrcr4, 0xe0000000);
+       out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+       out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+       out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
+#endif
+#endif
+       udelay(100);
+       clrbits_be32(plldadcr1, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+       clrbits_be32(plldadcr2, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+       clrbits_be32(plldadcr3, 0x02000001);
+#endif
+#endif
+       clrbits_be32(dpdovrcr4, 0xe0000000);
+}
+#endif
+
 void cpu_init_f (void)
 {
        extern void m8560_cpm_reset (void);
@@ -349,6 +414,10 @@ void cpu_init_f (void)
        in_be32(&gur->dcsrcr);
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+       fsl_erratum_a007212_workaround();
+#endif
+
 }
 
 /* Implement a dummy function for those platforms w/o SERDES */

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 488fd5ea767e17485d52e854a57e29eabeab9d1f..35dfb0a9a962d7854e545413b68019cd673e2cd5 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -107,6 +107,13 @@ void get_sys_info(sys_info_t *sys_info)
        mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
                        FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
                        & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+       if (mem_pll_rat == 0) {
+               mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
+                       FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
+                       FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+       }
+#endif
        /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
         * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
         * it uses 6.

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 502e7ccf25df5171e7349dc66612255695bae0fa..864e74c0c761d8240f26fa0576928f0bfdd1d248 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -679,6 +679,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A007075
 #define CONFIG_SYS_FSL_ERRATUM_A006475
 #define CONFIG_SYS_FSL_ERRATUM_A006384
+#define CONFIG_SYS_FSL_ERRATUM_A007212
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 
 #ifdef CONFIG_PPC_B4860
@@ -792,6 +793,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v3.0"
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A007212
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_ISBC_VER                2

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 4bda0f193444b3bbbe9b5d14fd0894e8961d3b22..1ec30337cb831d27c12c8f75dbfc61c7520c989c 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1739,6 +1739,8 @@ typedef struct ccsr_gur {
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT   16
+/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT      8
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK    0x3f
 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xfc000000