powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled
for P1020, P1021, P1024, P1025 and P2020 RDB boards.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index e07d2a178ff6c13b91be49be9a28cf3192b5d468..1481d683e5c34c1475ee8b03a4404a4355a56e97 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -207,8 +207,6 @@
 
 #define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -572,44 +570,56 @@
  */
 
 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME          "PCIe SLOT"
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xc0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
 #endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT       0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xfffc10000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
 #endif
-#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME          "mini PCIe SLOT"
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
 #endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT       0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xfffc00000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc00000
 #endif
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE2_NAME          "PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xc0000000
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
+
+#define CONFIG_SYS_PCIE1_NAME          "mini PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
+#endif
 
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #endif /* CONFIG_PCI */