]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ARM: dts: am33xx-clocks: add spread spectrum support
authorDario Binacchi <dariobin@libero.it>
Sun, 26 Sep 2021 09:58:56 +0000 (11:58 +0200)
committerTom Rini <trini@konsulko.com>
Mon, 11 Oct 2021 18:27:32 +0000 (14:27 -0400)
Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruh73x RM, SSC is supported only for LCD
and MPU PLLs, but the CM_SSC_DELTAMSTEP_DPLL_XXX and
CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the
CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR,
PER, DISP).

Link: https://lore.kernel.org/r/20210606202253.31649-4-dariobin@libero.it
Signed-off-by: Dario Binacchi <dariobin@libero.it>
arch/arm/dts/am33xx-clocks.dtsi

index 92218243904806258ec63d6db17df3afe7049020..44b6268ae32670a3c6d8a02c696cae7cdca0e8db 100644 (file)
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-core-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x0490>, <0x045c>, <0x0468>;
+               reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
        };
 
        dpll_core_x2_ck: dpll_core_x2_ck {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x0488>, <0x0420>, <0x042c>;
+               reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
        };
 
        dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x0494>, <0x0434>, <0x0440>;
+               reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
        };
 
        dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x0498>, <0x0448>, <0x0454>;
+               reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
        };
 
        dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-j-type-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x048c>, <0x0470>, <0x049c>;
+               reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
        };
 
        dpll_per_m2_ck: dpll_per_m2_ck@4ac {