]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB
authorMadalin Bucur <madalin.bucur@oss.nxp.com>
Thu, 23 Apr 2020 13:25:13 +0000 (16:25 +0300)
committerPriyanka Jain <priyanka.jain@nxp.com>
Wed, 29 Apr 2020 05:40:54 +0000 (11:10 +0530)
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1043ARDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/arm/dts/fsl-ls1043a-rdb.dts
arch/arm/dts/fsl-ls1043a.dtsi

index 721b158169db43cf42b23bfea044a173d21621cd..6e4ea5b40c7858d99f4023e161f4db16fc20729a 100644 (file)
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  *
  * Copyright (C) 2015, Freescale Semiconductor
+ * Copyright 2020 NXP
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
 &duart1 {
        status = "okay";
 };
+
+#include "fsl-ls1043-post.dtsi"
+
+&fman0 {
+       ethernet@e0000 {
+               phy-handle = <&qsgmii_phy1>;
+               phy-connection-type = "qsgmii";
+               status = "okay";
+       };
+
+       ethernet@e2000 {
+               phy-handle = <&qsgmii_phy2>;
+               phy-connection-type = "qsgmii";
+               status = "okay";
+       };
+
+       ethernet@e4000 {
+               phy-handle = <&rgmii_phy1>;
+               phy-connection-type = "rgmii-txid";
+               status = "okay";
+       };
+
+       ethernet@e6000 {
+               phy-handle = <&rgmii_phy2>;
+               phy-connection-type = "rgmii-txid";
+               status = "okay";
+       };
+
+       ethernet@e8000 {
+               phy-handle = <&qsgmii_phy3>;
+               phy-connection-type = "qsgmii";
+               status = "okay";
+       };
+
+       ethernet@ea000 {
+               phy-handle = <&qsgmii_phy4>;
+               phy-connection-type = "qsgmii";
+               status = "okay";
+       };
+
+       ethernet@f0000 { /* 10GEC1 */
+               phy-handle = <&aqr105_phy>;
+               phy-connection-type = "xgmii";
+               status = "okay";
+       };
+
+       mdio@fc000 {
+               rgmii_phy1: ethernet-phy@1 {
+                       reg = <0x1>;
+               };
+
+               rgmii_phy2: ethernet-phy@2 {
+                       reg = <0x2>;
+               };
+
+               qsgmii_phy1: ethernet-phy@4 {
+                       reg = <0x4>;
+               };
+
+               qsgmii_phy2: ethernet-phy@5 {
+                       reg = <0x5>;
+               };
+
+               qsgmii_phy3: ethernet-phy@6 {
+                       reg = <0x6>;
+               };
+
+               qsgmii_phy4: ethernet-phy@7 {
+                       reg = <0x7>;
+               };
+       };
+
+       mdio@fd000 {
+               aqr105_phy: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       interrupts = <0 132 4>;
+                       reg = <0x1>;
+               };
+       };
+};
index b159c3ca732e2dd2304d88f6a77cb8959f8da78f..0a959f0f2d2732e7c828cdc8b626c78c33b62c25 100644 (file)
@@ -31,7 +31,7 @@
                interrupts = <1 9 0xf08>;
        };
 
-       soc {
+       soc: soc {
                compatible = "simple-bus";
                #address-cells = <2>;
                #size-cells = <2>;