ARM: tegra: import latest Jetson TK1 spreadsheet

This imports v11 of "Jetson TK1 Development Platform Pin Mux" from
https://developer.nvidia.com/embedded/downloads.

The new version defines the mux option for the MIPI pad ctrl selection.
The OWR pin no longer has an entry in the configuration table because
the only mux option it support is OWR, that feature isn't supported, and
hence can't conflict with any other pin. This pin can only usefully be
used as a GPIO.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c
index 14f0ce54554ef02c335db8b881af6ca0149e5656..a66b710cddab7154c6c92aabb1127b4cce6db959 100644 (file)
--- a/board/nvidia/jetson-tk1/jetson-tk1.c
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -31,6 +31,9 @@ void pinmux_init(void)
 
        pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
                                   ARRAY_SIZE(jetson_tk1_drvgrps));
+
+       pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
+                                       ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
 }
 
 #ifdef CONFIG_PCI_TEGRA

diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
index b2b2057e3bd3c01397de2f316fcbacd2d2478e1a..00e0cdc4b8c061e2c6665aecc4d429ba053828c3 100644 (file)
--- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -276,7 +276,6 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
        PINCFG(CPU_PWR_REQ,            CPU,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
        PINCFG(PWR_INT_N,              PMI,          UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
        PINCFG(RESET_OUT_N,            RESET_OUT_N,  NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
-       PINCFG(OWR,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, NORMAL),
        PINCFG(CLK_32K_IN,             CLK,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
        PINCFG(JTAG_RTCK,              RTCK,         UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
 };
@@ -296,4 +295,15 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
 static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
 };
 
+#define MIPIPADCTRLCFG(_grp, _mux) \
+       {                                                       \
+               .grp            = PMUX_MIPIPADCTRLGRP_##_grp,   \
+               .func           = PMUX_FUNC_##_mux,             \
+       }
+
+static const struct pmux_mipipadctrlgrp_config jetson_tk1_mipipadctrlgrps[] = {
+       /*             grp,   mux */
+       MIPIPADCTRLCFG(DSI_B, DSI_B),
+};
+
 #endif /* PINMUX_CONFIG_JETSON_TK1_H */