pci: Move some PCIe register offset definitions to a common header

Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>

diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index df7b37a5924b8e07207c54550f85d50ccb990ca2..1f51854ccc6f676d420356c5f5eedf33dedd060e 100644 (file)
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -118,14 +118,6 @@
 #define RCAR_PCI_MAX_RESOURCES 4
 #define MAX_NR_INBOUND_MAPS    6
 
-#define PCI_EXP_FLAGS          2               /* Capabilities register */
-#define PCI_EXP_FLAGS_TYPE     0x00f0          /* Device/Port type */
-#define PCI_EXP_TYPE_ROOT_PORT 0x4             /* Root Port */
-#define PCI_EXP_LNKCAP         12              /* Link Capabilities */
-#define PCI_EXP_LNKCAP_DLLLARC 0x00100000      /* Data Link Layer Link Active Reporting Capable */
-#define PCI_EXP_SLTCAP         20              /* Slot Capabilities */
-#define PCI_EXP_SLTCAP_PSN     0xfff80000      /* Physical Slot Number */
-
 enum {
        RCAR_PCI_ACCESS_READ,
        RCAR_PCI_ACCESS_WRITE,

diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index aa1903e547ce83d54e225ba74f50113f8a810006..9f102c64c6025486330432b39e49e570f922264c 100644 (file)
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -67,9 +67,6 @@
 #define IS_ROOT_PORT(pcie, bdf)                                \
                ((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
 
-#define PCI_EXP_LNKSTA         18      /* Link Status */
-#define PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
-
 /**
  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
  * @bus: Pointer to the PCI bus

diff --git a/include/pci.h b/include/pci.h
index 19c9244b9459bad06d9ce61d4bccb33487c28a69..9cd85644361b2f01ac500730a35d7ca8cc8a4f42 100644 (file)
--- a/include/pci.h
+++ b/include/pci.h
@@ -471,10 +471,19 @@
 #define  PCI_EA_FIELD_MASK     0xfffffffc      /* For Base & Max Offset */
 
 /* PCI Express capabilities */
+#define PCI_EXP_FLAGS          2       /* Capabilities register */
+#define  PCI_EXP_FLAGS_TYPE    0x00f0  /* Device/Port type */
+#define  PCI_EXP_TYPE_ROOT_PORT 0x4    /* Root Port */
 #define PCI_EXP_DEVCAP         4       /* Device capabilities */
-#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
+#define  PCI_EXP_DEVCAP_FLR    0x10000000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL         8       /* Device Control */
-#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
+#define  PCI_EXP_DEVCTL_BCR_FLR        0x8000  /* Bridge Configuration Retry / FLR */
+#define PCI_EXP_LNKCAP         12      /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_DLLLARC        0x00100000 /* Data Link Layer Link Active Reporting Capable */
+#define PCI_EXP_LNKSTA         18      /* Link Status */
+#define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
+#define PCI_EXP_SLTCAP         20      /* Slot Capabilities */
+#define  PCI_EXP_SLTCAP_PSN    0xfff80000 /* Physical Slot Number */
 
 /* Include the ID list */