net: gmac_rockchip: Add rk3328 gmac support

The GMAC2IO in the RK3328 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3328-specific logic necessary to reuse this driver.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index cfffe2979d1b31548c9f7af293ee6854449c2183..551c2309ad4f904858f7a472996da6f88a0c9371 100644 (file)
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3328.h>
 #include <asm/arch/grf_rk3368.h>
 #include <asm/arch/grf_rk3399.h>
 #include <asm/arch/grf_rv1108.h>
@@ -94,6 +95,39 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
        return 0;
 }
 
+static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+       struct rk3328_grf_regs *grf;
+       int clk;
+       enum {
+               RK3328_GMAC_CLK_SEL_SHIFT = 11,
+               RK3328_GMAC_CLK_SEL_MASK  = GENMASK(12, 11),
+               RK3328_GMAC_CLK_SEL_125M  = 0 << 11,
+               RK3328_GMAC_CLK_SEL_25M   = 3 << 11,
+               RK3328_GMAC_CLK_SEL_2_5M  = 2 << 11,
+       };
+
+       switch (priv->phydev->speed) {
+       case 10:
+               clk = RK3328_GMAC_CLK_SEL_2_5M;
+               break;
+       case 100:
+               clk = RK3328_GMAC_CLK_SEL_25M;
+               break;
+       case 1000:
+               clk = RK3328_GMAC_CLK_SEL_125M;
+               break;
+       default:
+               debug("Unknown phy speed: %d\n", priv->phydev->speed);
+               return -EINVAL;
+       }
+
+       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+       rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
+
+       return 0;
+}
+
 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
        struct rk3368_grf *grf;
@@ -207,6 +241,50 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
                     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
 
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+       struct rk3328_grf_regs *grf;
+       enum {
+               RK3328_RMII_MODE_SHIFT = 9,
+               RK3328_RMII_MODE_MASK  = BIT(9),
+
+               RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
+               RK3328_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+               RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+               RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+               RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+               RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+               RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+               RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+               RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+       };
+       enum {
+               RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+               RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+               RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+               RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+       };
+
+       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+       rk_clrsetreg(&grf->mac_con[1],
+                    RK3328_RMII_MODE_MASK |
+                    RK3328_GMAC_PHY_INTF_SEL_MASK |
+                    RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+                    RK3328_TXCLK_DLY_ENA_GMAC_MASK,
+                    RK3328_GMAC_PHY_INTF_SEL_RGMII |
+                    RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+                    RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+       rk_clrsetreg(&grf->mac_con[0],
+                    RK3328_CLK_RX_DL_CFG_GMAC_MASK |
+                    RK3328_CLK_TX_DL_CFG_GMAC_MASK,
+                    pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
+                    pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
        struct rk3368_grf *grf;
@@ -375,6 +453,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
        .set_to_rgmii = rk3288_gmac_set_to_rgmii,
 };
 
+const struct rk_gmac_ops rk3328_gmac_ops = {
+       .fix_mac_speed = rk3328_gmac_fix_mac_speed,
+       .set_to_rgmii = rk3328_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3368_gmac_ops = {
        .fix_mac_speed = rk3368_gmac_fix_mac_speed,
        .set_to_rgmii = rk3368_gmac_set_to_rgmii,
@@ -393,6 +476,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
 static const struct udevice_id rockchip_gmac_ids[] = {
        { .compatible = "rockchip,rk3288-gmac",
          .data = (ulong)&rk3288_gmac_ops },
+       { .compatible = "rockchip,rk3328-gmac",
+         .data = (ulong)&rk3328_gmac_ops },
        { .compatible = "rockchip,rk3368-gmac",
          .data = (ulong)&rk3368_gmac_ops },
        { .compatible = "rockchip,rk3399-gmac",