source "drivers/mtd/nand/Kconfig"
+config SYS_NAND_MAX_CHIPS
+ int "NAND max chips"
+ depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \
+ SPL_OMAP3_ID_NAND
+ default 1
+ help
+ The maximum number of NAND chips per device to be supported.
+
source "drivers/mtd/spi/Kconfig"
source "drivers/mtd/ubi/Kconfig"
not available while configuring controller. So a static CONFIG_NAND_xx
is needed to know the device's bus-width in advance.
-config SYS_NAND_MAX_CHIPS
- int "NAND max chips"
- default 1
- depends on NAND_ARASAN
- help
- The maximum number of NAND chips per device to be supported.
-
if SPL
config SYS_NAND_5_ADDR_CYCLE
/* NAND configuration part */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x0C000000
#endif /* __CONFIG_H */
/* NAND */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* APBH DMA is required for NAND support */
#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
-
#undef CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_MAX_NAND_DEVICE 3
#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */
*/
#define CONFIG_SYS_NAND_BASE 0xE1000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_NAND_FSL_ELBC
#define NAND_CACHE_PAGES 64
/* When runtime detection fails this is the default */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
/*
* Ethernet Driver configuration
/* nand driver parameters */
#ifdef CONFIG_TARGET_PRESIDIO_ASIC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
- #define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#define DFU_ALT_INFO_MMC \
#ifndef __LINUX_MTD_BBM_H
#define __LINUX_MTD_BBM_H
-/* The maximum number of NAND chips in an array */
-#ifndef CONFIG_SYS_NAND_MAX_CHIPS
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
-#endif
-
/**
* struct nand_bbt_descr - bad block table descriptor
* @options: options for this descriptor