ARM: vf610: ddrmc: program Dummy DDRBYTE1/2

The Vybrid reference manual VFXXXRM Rev. 0 10/2016 states in chapter
5.2.6.1 DUMMY PADS (DDR/QuadSPI) that those pads need to be programed
for correct operation of DDR. Assume the default DDR pin configuration
which seems to work well on a Colibri VF50.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index c0eeaa7e7dd7ffe1735b2cedf1526062100681ef..01bc2998b81ece22821d4dce0e527595b7cea5d3 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -244,6 +244,8 @@ enum {
        VF610_PAD_DDR_WE__DDR_WE_B              = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_ODT1__DDR_ODT_0           = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_ODT0__DDR_ODT_1           = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+       VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1    = IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+       VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2    = IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 };
 
 #endif /* __IOMUX_VF610_H__ */

diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c
index 3d7da1c25eec57957ee426303a21d552806bbd88..7cc8f5d2c0c7114e67e56bbdb3ed47c42ee7ead9 100644 (file)
--- a/arch/arm/mach-imx/ddrmc-vf610.c
+++ b/arch/arm/mach-imx/ddrmc-vf610.c
@@ -61,6 +61,8 @@ void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
                VF610_PAD_DDR_WE__DDR_WE_B,
                VF610_PAD_DDR_ODT1__DDR_ODT_0,
                VF610_PAD_DDR_ODT0__DDR_ODT_1,
+               VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
+               VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2,
                VF610_PAD_DDR_RESETB,
        };