sunxi: clock: support D1/R528 PLL6 clock

The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is
new P0 divider at bits [18:16], and the M divider is 1.

Add code to support this version of "PLL6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 9895c2c220e2294aa5ab7e65b8fc9bc05e72be6b..8471e11aa02a6cda8f6776f6345225ca6ce5dd87 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -249,6 +249,8 @@ struct sunxi_ccm_reg {
 #define CCM_PLL6_CTRL_EN               BIT(31)
 #define CCM_PLL6_LOCK_EN               BIT(29)
 #define CCM_PLL6_LOCK                  BIT(28)
+#define CCM_PLL6_CTRL_P0_SHIFT         16
+#define CCM_PLL6_CTRL_P0_MASK          (0x7 << CCM_PLL6_CTRL_P0_SHIFT)
 #define CCM_PLL6_CTRL_N_SHIFT          8
 #define CCM_PLL6_CTRL_N_MASK           (0xff << CCM_PLL6_CTRL_N_SHIFT)
 #define CCM_PLL6_CTRL_DIV1_SHIFT       0

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index d32e33465f59cffb7b91603e33bd791e06684d1d..daae994787e74476fd3de4d10fe20f18cedb3681 100644 (file)
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -110,16 +110,26 @@ unsigned int clock_get_pll6(void)
 {
        struct sunxi_ccm_reg *const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-       int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2;
-
        uint32_t rval = readl(&ccm->pll6_cfg);
        int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
-       int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
-                       CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
        int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
-                       CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
-       /* The register defines PLL6-2X or PLL6-4X, not plain PLL6 */
-       return 24000000 / m * n / div1 / div2;
+                   CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
+       int div1, m;
+
+       if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
+               div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
+                       CCM_PLL6_CTRL_P0_SHIFT) + 1;
+               m = 1;
+       } else {
+               div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
+                       CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
+               if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+                       m = 4;
+               else
+                       m = 2;
+       }
+
+       return 24000000U * n / m / div1 / div2;
 }
 
 int clock_twi_onoff(int port, int state)