ram: rk3399: migrate to use common code

For there are some structures and functions are common for all rockchip SoCs,
migrate to use the common code so that we can clean up reduandent codes.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
index 3708bd674b820a7eb25e1591de7c7b9865f46cfe..7fae249536bb6789b915f7add5767ac651e146fc 100644 (file)
--- a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
@@ -13,6 +13,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x80120e12
                0x11030802
@@ -28,6 +30,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x80120e12
                0x11030802

diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
index fcd01f8b462f2a6209eac7b1aed3e6bf4c64647f..23c7c34a9ac253bc461126e01c7767893eb5402c 100644 (file)
--- a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
@@ -13,6 +13,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x80151015
                0x14040902
@@ -28,6 +30,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x80151015
                0x14040902

diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
index c46c1996bec4e4b9143e219ecb6c65dc3923a55c..ea029ca90afddcfd0e0a9224136fc51161259a93 100644 (file)
--- a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
@@ -13,6 +13,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x80181219
                0x17050a03
@@ -28,6 +30,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x80181219
                0x17050a03

diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
index d14e833d228484334fe3b2b573fd2bb10d6b3509..7296dbb80e0ee1f7e3c233e82c1b86388820656d 100644 (file)
--- a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
@@ -14,6 +14,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x1d191519
                0x14040808
@@ -29,6 +31,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x1d191519
                0x14040808

diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
index fc4cccb6a0d3f30db00dbc48d6459095b0fe0fac..bf429c21e4eec8dc570e1ae4adbf750a9df695b8 100644 (file)
--- a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
@@ -13,6 +13,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x1d191519
                0x14040808
@@ -28,6 +30,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x1d191519
                0x14040808

diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi
index 2a627e1be5742ca8744309989182b23232e1a862..96f459fd0b7886e01f98ac56c19cb612cba943e3 100644 (file)
--- a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi
@@ -13,6 +13,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
 
                0x801d181e
@@ -30,6 +32,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
 
                0x801d181e

diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
index 4a4414a960fc14317129a6b4a61402137f7b7eae..f0c478d189ed38d61762efbf3326c069a3a0c39b 100644 (file)
--- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
@@ -15,6 +15,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x80241d22
                0x15050f08
@@ -30,6 +32,8 @@
                0x0
                0xf
                0xf
+               0xf
+               0xf
                1
                0x80241d22
                0x15050f08

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index 485bb3d8896eb78ad102f8eaa01a3e58c545dea7..f0a664478f673c590573ee1f0f1ef6ab5c504468 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -6,6 +6,7 @@
 #ifndef _ASM_ARCH_SDRAM_RK3399_H
 #define _ASM_ARCH_SDRAM_RK3399_H
 #include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram_msch.h>
 
 struct rk3399_ddr_pctl_regs {
        u32 denali_ctl[332];
@@ -19,55 +20,6 @@ struct rk3399_ddr_pi_regs {
        u32 denali_pi[200];
 };
 
-union noc_ddrtimingc0 {
-       u32 d32;
-       struct {
-               unsigned burstpenalty : 4;
-               unsigned reserved0 : 4;
-               unsigned wrtomwr : 6;
-               unsigned reserved1 : 18;
-       } b;
-};
-
-union noc_ddrmode {
-       u32 d32;
-       struct {
-               unsigned autoprecharge : 1;
-               unsigned bypassfiltering : 1;
-               unsigned fawbank : 1;
-               unsigned burstsize : 2;
-               unsigned mwrsize : 2;
-               unsigned reserved2 : 1;
-               unsigned forceorder : 8;
-               unsigned forceorderstate : 8;
-               unsigned reserved3 : 8;
-       } b;
-};
-
-struct rk3399_msch_regs {
-       u32 coreid;
-       u32 revisionid;
-       u32 ddrconf;
-       u32 ddrsize;
-       u32 ddrtiminga0;
-       u32 ddrtimingb0;
-       u32 ddrtimingc0;
-       u32 devtodev0;
-       u32 reserved0[(0x110 - 0x20) / 4];
-       u32 ddrmode;
-       u32 reserved1[(0x1000 - 0x114) / 4];
-       u32 agingx0;
-};
-
-struct rk3399_msch_timings {
-       u32 ddrtiminga0;
-       u32 ddrtimingb0;
-       union noc_ddrtimingc0 ddrtimingc0;
-       u32 devtodev0;
-       union noc_ddrmode ddrmode;
-       u32 agingx0;
-};
-
 struct rk3399_ddr_cic_regs {
        u32 cic_ctrl0;
        u32 cic_ctrl1;
@@ -84,14 +36,38 @@ struct rk3399_ddr_cic_regs {
 #define START          1
 
 /* DENALI_CTL_68 */
-#define PWRUP_SREFRESH_EXIT    (1 << 16)
+#define PWRUP_SREFRESH_EXIT    BIT(16)
 
 /* DENALI_CTL_274 */
 #define MEM_RST_VALID  1
 
+struct msch_regs {
+       u32 coreid;
+       u32 revisionid;
+       u32 ddrconf;
+       u32 ddrsize;
+       union noc_ddrtiminga0 ddrtiminga0;
+       union noc_ddrtimingb0 ddrtimingb0;
+       union noc_ddrtimingc0 ddrtimingc0;
+       union noc_devtodev0 devtodev0;
+       u32 reserved0[(0x110 - 0x20) / 4];
+       union noc_ddrmode ddrmode;
+       u32 reserved1[(0x1000 - 0x114) / 4];
+       u32 agingx0;
+};
+
+struct sdram_msch_timings {
+       union noc_ddrtiminga0 ddrtiminga0;
+       union noc_ddrtimingb0 ddrtimingb0;
+       union noc_ddrtimingc0 ddrtimingc0;
+       union noc_devtodev0 devtodev0;
+       union noc_ddrmode ddrmode;
+       u32 agingx0;
+};
+
 struct rk3399_sdram_channel {
        struct sdram_cap_info cap_info;
-       struct rk3399_msch_timings noc_timings;
+       struct sdram_msch_timings noc_timings;
 };
 
 struct rk3399_sdram_params {
@@ -102,11 +78,11 @@ struct rk3399_sdram_params {
        struct rk3399_ddr_publ_regs phy_regs;
 };
 
-#define PI_CA_TRAINING         (1 << 0)
-#define PI_WRITE_LEVELING      (1 << 1)
-#define PI_READ_GATE_TRAINING  (1 << 2)
-#define PI_READ_LEVELING       (1 << 3)
-#define PI_WDQ_LEVELING                (1 << 4)
+#define PI_CA_TRAINING         BIT(0)
+#define PI_WRITE_LEVELING      BIT(1)
+#define PI_READ_GATE_TRAINING  BIT(2)
+#define PI_READ_LEVELING       BIT(3)
+#define PI_WDQ_LEVELING                BIT(4)
 #define PI_FULL_TRAINING       0xff
 
 #endif

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 5f1ad51cacb38328d339ffe7a665f45e69441a61..7746b661e5bd8f1f688594034e1098118a57c61a 100644 (file)
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -184,6 +184,7 @@ config ROCKCHIP_RK3399
        select DM_REGULATOR_FIXED
        select BOARD_LATE_INIT
        imply ROCKCHIP_COMMON_BOARD
+       imply ROCKCHIP_SDRAM_COMMON
        imply SPL_ROCKCHIP_COMMON_BOARD
        imply TPL_SERIAL_SUPPORT
        imply TPL_LIBCOMMON_SUPPORT

diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
index daa561385eac8a4c47370815ca64137e7c41080b..b75d581f579722b0de832772f695e83f8e8c518f 100644 (file)
--- a/drivers/ram/rockchip/Kconfig
+++ b/drivers/ram/rockchip/Kconfig
@@ -11,8 +11,6 @@ config ROCKCHIP_SDRAM_COMMON
        help
          This enable sdram common driver
 
-if RAM_ROCKCHIP
-
 config RAM_ROCKCHIP_DEBUG
        bool "Rockchip ram drivers debugging"
        default y
@@ -23,18 +21,10 @@ config RAM_ROCKCHIP_DEBUG
          This is an option for developers to understand the ram drivers
          initialization, configurations and etc.
 
-config RAM_RK3399
-       bool "Ram driver for Rockchip RK3399"
-       default ROCKCHIP_RK3399
-       help
-         This enables ram drivers support for the platforms based on
-         Rockchip RK3399 SoC.
-
 config RAM_RK3399_LPDDR4
        bool "LPDDR4 support for Rockchip RK3399"
-       depends on RAM_RK3399
+       depends on RAM_ROCKCHIP && ROCKCHIP_RK3399
        help
          This enables LPDDR4 sdram code support for the platforms based
          on Rockchip RK3399 SoC.
 
-endif # RAM_ROCKCHIP

diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index b477f701021babca09fd4835076cf6370befa842..217366b5d5a57d163bc0aee15a8b53806ea12fba 100644 (file)
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -10,5 +10,5 @@ obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
-obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
 obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o

diff --git a/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc b/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
index c50a03d9dd231b1560895dbc12d4390edc3309bb..6ddc01c49d80e7012119a34aabec29a2fb800e1e 100644 (file)
--- a/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
+++ b/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
@@ -16,15 +16,23 @@
                                .row_3_4 = 0x0,
                                .cs0_row = 0xF,
                                .cs1_row = 0xF,
+                               .cs0_high16bit_row = 0xF,
+                               .cs1_high16bit_row = 0xF,
                                .ddrconfig = 1,
                        },
                        {
-                               .ddrtiminga0 = 0x80241d22,
-                               .ddrtimingb0 = 0x15050f08,
+                               .ddrtiminga0 = {
+                                       0x80241d22,
+                               },
+                               .ddrtimingb0 = {
+                                       0x15050f08,
+                               },
                                .ddrtimingc0 = {
                                        0x00000602,
                                },
-                               .devtodev0 = 0x00002122,
+                               .devtodev0 = {
+                                       0x00002122,
+                               },
                                .ddrmode = {
                                        0x0000004c,
                                },
@@ -41,15 +49,23 @@
                                .row_3_4 = 0x0,
                                .cs0_row = 0xF,
                                .cs1_row = 0xF,
+                               .cs0_high16bit_row = 0xF,
+                               .cs1_high16bit_row = 0xF,
                                .ddrconfig = 1,
                        },
                        {
-                               .ddrtiminga0 = 0x80241d22,
-                               .ddrtimingb0 = 0x15050f08,
+                               .ddrtiminga0 = {
+                                       0x80241d22,
+                               },
+                               .ddrtimingb0 = {
+                                       0x15050f08,
+                               },
                                .ddrtimingc0 = {
                                        0x00000602,
                                },
-                               .devtodev0 = 0x00002122,
+                               .devtodev0 = {
+                                       0x00002122,
+                               },
                                .ddrmode = {
                                        0x0000004c,
                                },

diff --git a/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc b/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
index d8ae3359a394c5d7131479f091443fc9b85c1f2e..307f6ee458e70a70334a03ccee8c01357c373fd7 100644 (file)
--- a/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
+++ b/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
@@ -16,15 +16,23 @@
                                .row_3_4 = 0x0,
                                .cs0_row = 0xF,
                                .cs1_row = 0xF,
+                               .cs0_high16bit_row = 0xF,
+                               .cs1_high16bit_row = 0xF,
                                .ddrconfig = 1,
                        },
                        {
-                               .ddrtiminga0 = 0x80241d22,
-                               .ddrtimingb0 = 0x15050f08,
+                               .ddrtiminga0 = {
+                                       0x80241d22,
+                               },
+                               .ddrtimingb0 = {
+                                       0x15050f08,
+                               },
                                .ddrtimingc0 = {
                                        0x00000602,
                                },
-                               .devtodev0 = 0x00002122,
+                               .devtodev0 = {
+                                       0x00002122,
+                               },
                                .ddrmode = {
                                        0x0000004c,
                                },
@@ -41,15 +49,23 @@
                                .row_3_4 = 0x0,
                                .cs0_row = 0xF,
                                .cs1_row = 0xF,
+                               .cs0_high16bit_row = 0xF,
+                               .cs1_high16bit_row = 0xF,
                                .ddrconfig = 1,
                        },
                        {
-                               .ddrtiminga0 = 0x80241d22,
-                               .ddrtimingb0 = 0x15050f08,
+                               .ddrtiminga0 = {
+                                       0x80241d22,
+                               },
+                               .ddrtimingb0 = {
+                                       0x15050f08,
+                               },
                                .ddrtimingc0 = {
                                        0x00000602,
                                },
-                               .devtodev0 = 0x00002122,
+                               .devtodev0 = {
+                                       0x00002122,
+                               },
                                .ddrmode = {
                                        0x0000004c,
                                },

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 9b7de4ae418e6cadaa23f3ea06657abca9beb76b..a4eabb5c2591c62f48fde72887e5cfa473bc52a7 100644 (file)
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -52,7 +52,7 @@ struct chan_info {
        struct rk3399_ddr_pctl_regs *pctl;
        struct rk3399_ddr_pi_regs *pi;
        struct rk3399_ddr_publ_regs *publ;
-       struct rk3399_msch_regs *msch;
+       struct msch_regs *msch;
 };
 
 struct dram_info {
@@ -196,11 +196,6 @@ struct io_setting {
        },
 };
 
-/**
- * phy = 0, PHY boot freq
- * phy = 1, PHY index 0
- * phy = 2, PHY index 1
- */
 static struct io_setting *
 lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
 {
@@ -223,16 +218,16 @@ lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
        return io;
 }
 
-static void *get_denali_phy(const struct chan_info *chan,
+static void *get_denali_ctl(const struct chan_info *chan,
                            struct rk3399_sdram_params *params, bool reg)
 {
-       return reg ? &chan->publ->denali_phy : &params->phy_regs.denali_phy;
+       return reg ? &chan->pctl->denali_ctl : &params->pctl_regs.denali_ctl;
 }
 
-static void *get_denali_ctl(const struct chan_info *chan,
+static void *get_denali_phy(const struct chan_info *chan,
                            struct rk3399_sdram_params *params, bool reg)
 {
-       return reg ? &chan->pctl->denali_ctl : &params->pctl_regs.denali_ctl;
+       return reg ? &chan->publ->denali_phy : &params->phy_regs.denali_phy;
 }
 
 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
@@ -240,17 +235,6 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
        return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
 }
 
-static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
-{
-       int i;
-
-       for (i = 0; i < n / sizeof(u32); i++) {
-               writel(*src, dest);
-               src++;
-               dest++;
-       }
-}
-
 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
                            u32 phy)
 {
@@ -866,8 +850,8 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
         * work around controller bug:
         * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
         */
-       copy_to_reg(&denali_ctl[1], &params_ctl[1],
-                   sizeof(struct rk3399_ddr_pctl_regs) - 4);
+       sdram_copy_to_reg(&denali_ctl[1], &params_ctl[1],
+                         sizeof(struct rk3399_ddr_pctl_regs) - 4);
        writel(params_ctl[0], &denali_ctl[0]);
 
        /*
@@ -884,8 +868,8 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
                writel(tmp + tmp1, &denali_ctl[14]);
        }
 
-       copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
-                   sizeof(struct rk3399_ddr_pi_regs));
+       sdram_copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
+                         sizeof(struct rk3399_ddr_pi_regs));
 
        /* rank count need to set for init */
        set_memory_map(chan, channel, params);
@@ -927,14 +911,21 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
                }
        }
 
-       copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
-       copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
-       copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
-       copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
-       copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
-       copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
-       copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
-       copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
+       sdram_copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
+       sdram_copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
+       sdram_copy_to_reg(&denali_phy[128], &params_phy[128],
+                         (218 - 128 + 1) * 4);
+       sdram_copy_to_reg(&denali_phy[256], &params_phy[256],
+                         (346 - 256 + 1) * 4);
+       sdram_copy_to_reg(&denali_phy[384], &params_phy[384],
+                         (474 - 384 + 1) * 4);
+       sdram_copy_to_reg(&denali_phy[512], &params_phy[512],
+                         (549 - 512 + 1) * 4);
+       sdram_copy_to_reg(&denali_phy[640], &params_phy[640],
+                         (677 - 640 + 1) * 4);
+       sdram_copy_to_reg(&denali_phy[768], &params_phy[768],
+                         (805 - 768 + 1) * 4);
+
        set_ds_odt(chan, params, true, 0);
 
        /*
@@ -1392,7 +1383,7 @@ static void set_ddrconfig(const struct chan_info *chan,
                          unsigned char channel, u32 ddrconfig)
 {
        /* only need to set ddrconfig */
-       struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
+       struct msch_regs *ddr_msch_regs = chan->msch;
        unsigned int cs0_cap = 0;
        unsigned int cs1_cap = 0;
 
@@ -1413,52 +1404,43 @@ static void set_ddrconfig(const struct chan_info *chan,
               &ddr_msch_regs->ddrsize);
 }
 
+static void sdram_msch_config(struct msch_regs *msch,
+                             struct sdram_msch_timings *noc_timings)
+{
+       writel(noc_timings->ddrtiminga0.d32,
+              &msch->ddrtiminga0.d32);
+       writel(noc_timings->ddrtimingb0.d32,
+              &msch->ddrtimingb0.d32);
+       writel(noc_timings->ddrtimingc0.d32,
+              &msch->ddrtimingc0.d32);
+       writel(noc_timings->devtodev0.d32,
+              &msch->devtodev0.d32);
+       writel(noc_timings->ddrmode.d32,
+              &msch->ddrmode.d32);
+}
+
 static void dram_all_config(struct dram_info *dram,
-                           const struct rk3399_sdram_params *params)
+                           struct rk3399_sdram_params *params)
 {
        u32 sys_reg2 = 0;
        u32 sys_reg3 = 0;
        unsigned int channel, idx;
 
-       sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
-       sys_reg2 |= SYS_REG_ENC_NUM_CH(params->base.num_channels);
-
        for (channel = 0, idx = 0;
             (idx < params->base.num_channels) && (channel < 2);
             channel++) {
-               const struct rk3399_sdram_channel *info = &params->ch[channel];
-               struct rk3399_msch_regs *ddr_msch_regs;
-               const struct rk3399_msch_timings *noc_timing;
+               struct msch_regs *ddr_msch_regs;
+               struct sdram_msch_timings *noc_timing;
 
                if (params->ch[channel].cap_info.col == 0)
                        continue;
                idx++;
-               sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
-               sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
-               sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
-               sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
-               sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
-               sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
-               sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
-               SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
-               if (info->cap_info.cs1_row)
-                       SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
-                                           sys_reg3, channel);
-               sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
-               sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
-
+               sdram_org_config(&params->ch[channel].cap_info,
+                                &params->base, &sys_reg2,
+                                &sys_reg3, channel);
                ddr_msch_regs = dram->chan[channel].msch;
                noc_timing = &params->ch[channel].noc_timings;
-               writel(noc_timing->ddrtiminga0,
-                      &ddr_msch_regs->ddrtiminga0);
-               writel(noc_timing->ddrtimingb0,
-                      &ddr_msch_regs->ddrtimingb0);
-               writel(noc_timing->ddrtimingc0.d32,
-                      &ddr_msch_regs->ddrtimingc0);
-               writel(noc_timing->devtodev0,
-                      &ddr_msch_regs->devtodev0);
-               writel(noc_timing->ddrmode.d32,
-                      &ddr_msch_regs->ddrmode);
+               sdram_msch_config(ddr_msch_regs, noc_timing);
 
                /**
                 * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
@@ -1494,7 +1476,7 @@ static void set_cap_relate_config(const struct chan_info *chan,
 {
        u32 *denali_ctl = chan->pctl->denali_ctl;
        u32 tmp;
-       struct rk3399_msch_timings *noc_timing;
+       struct sdram_msch_timings *noc_timing;
 
        if (params->base.dramtype == LPDDR3) {
                tmp = (8 << params->ch[channel].cap_info.bw) /
@@ -2112,14 +2094,14 @@ static void lpddr4_copy_phy(struct dram_info *dram,
         * phy_clk_wrdqz_slave_delay_x
         * phy_clk_wrdqs_slave_delay_x
         */
-       copy_to_reg((u32 *)&denali_phy[59], (u32 *)&denali_phy_params[59],
-                   (63 - 58) * 4);
-       copy_to_reg((u32 *)&denali_phy[187], (u32 *)&denali_phy_params[187],
-                   (191 - 186) * 4);
-       copy_to_reg((u32 *)&denali_phy[315], (u32 *)&denali_phy_params[315],
-                   (319 - 314) * 4);
-       copy_to_reg((u32 *)&denali_phy[443], (u32 *)&denali_phy_params[443],
-                   (447 - 442) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[59],
+                         (u32 *)&denali_phy_params[59], (63 - 58) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[187],
+                         (u32 *)&denali_phy_params[187], (191 - 186) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[315],
+                         (u32 *)&denali_phy_params[315], (319 - 314) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[443],
+                         (u32 *)&denali_phy_params[443], (447 - 442) * 4);
 
        /*
         * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8
@@ -2218,31 +2200,30 @@ static void lpddr4_copy_phy(struct dram_info *dram,
         * phy_wrlvl_delay_period_threshold_x
         * phy_wrlvl_early_force_zero_x
         */
-       copy_to_reg((u32 *)&denali_phy[64], (u32 *)&denali_phy_params[64],
-                   (67 - 63) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[64],
+                         (u32 *)&denali_phy_params[64], (67 - 63) * 4);
        clrsetbits_le32(&denali_phy[68], 0xfffffc00,
                        denali_phy_params[68] & 0xfffffc00);
-       copy_to_reg((u32 *)&denali_phy[69], (u32 *)&denali_phy_params[69],
-                   (79 - 68) * 4);
-       copy_to_reg((u32 *)&denali_phy[192], (u32 *)&denali_phy_params[192],
-                   (195 - 191) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[69],
+                         (u32 *)&denali_phy_params[69], (79 - 68) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[192],
+                         (u32 *)&denali_phy_params[192], (195 - 191) * 4);
        clrsetbits_le32(&denali_phy[196], 0xfffffc00,
                        denali_phy_params[196] & 0xfffffc00);
-       copy_to_reg((u32 *)&denali_phy[197], (u32 *)&denali_phy_params[197],
-                   (207 - 196) * 4);
-       copy_to_reg((u32 *)&denali_phy[320], (u32 *)&denali_phy_params[320],
-                   (323 - 319) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[197],
+                         (u32 *)&denali_phy_params[197], (207 - 196) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[320],
+                         (u32 *)&denali_phy_params[320], (323 - 319) * 4);
        clrsetbits_le32(&denali_phy[324], 0xfffffc00,
                        denali_phy_params[324] & 0xfffffc00);
-       copy_to_reg((u32 *)&denali_phy[325], (u32 *)&denali_phy_params[325],
-                   (335 - 324) * 4);
-
-       copy_to_reg((u32 *)&denali_phy[448], (u32 *)&denali_phy_params[448],
-                   (451 - 447) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[325],
+                         (u32 *)&denali_phy_params[325], (335 - 324) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[448],
+                         (u32 *)&denali_phy_params[448], (451 - 447) * 4);
        clrsetbits_le32(&denali_phy[452], 0xfffffc00,
                        denali_phy_params[452] & 0xfffffc00);
-       copy_to_reg((u32 *)&denali_phy[453], (u32 *)&denali_phy_params[453],
-                   (463 - 452) * 4);
+       sdram_copy_to_reg((u32 *)&denali_phy[453],
+                         (u32 *)&denali_phy_params[453], (463 - 452) * 4);
 
        /* phy_two_cyc_preamble_x */
        clrsetbits_le32(&denali_phy[7], 0x3 << 24,