riscv: ax25: add imply v5l2 cache controller

Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index f4b59cb71d63f1ede1f2bbf2b05126ed5d93fc66..d411a79c211f80b6d76017b4633d5ff23ebc3046 100644 (file)
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -6,6 +6,7 @@ config RISCV_NDS
        imply RISCV_TIMER
        imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
        imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
+       imply V5L2_CACHE
        help
          Run U-Boot on AndeStar V5 platforms and use some specific features
          which are provided by Andes Technology AndeStar V5 families.