]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
board: developerbox: move mem_map setup later
authorJassi Brar <jaswinder.singh@linaro.org>
Mon, 12 Sep 2022 17:05:29 +0000 (12:05 -0500)
committerTom Rini <trini@konsulko.com>
Fri, 7 Oct 2022 01:05:17 +0000 (21:05 -0400)
dram_init() can't modify global/static variables, so
move the mem_map setup later when bss is available.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
board/socionext/developerbox/developerbox.c

index e14bb7f929ea90b74a5e7ccecb985c5eb0284efc..6415c90c1c1d7231de2838dcdf678f27a7f50e98 100644 (file)
@@ -89,8 +89,6 @@ struct draminfo {
        struct draminfo_entry   entry[3];
 };
 
-struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #define LOAD_OFFSET 0x100
@@ -137,21 +135,44 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 int dram_init(void)
 {
+       struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
+       struct draminfo_entry *ent = synquacer_draminfo->entry;
+
+       gd->ram_size = ent[0].size;
+       gd->ram_base = ent[0].base;
+
+       return 0;
+}
+
+int dram_init_banksize(void)
+{
+       struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
+       struct draminfo_entry *ent = synquacer_draminfo->entry;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
+               if (i < synquacer_draminfo->nr_regions) {
+                       debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
+                       gd->bd->bi_dram[i].start = ent[i].base;
+                       gd->bd->bi_dram[i].size = ent[i].size;
+               }
+       }
+
+       return 0;
+}
+
+void build_mem_map(void)
+{
+       struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
        struct draminfo_entry *ent = synquacer_draminfo->entry;
        struct mm_region *mr;
        int i, ri;
 
        if (synquacer_draminfo->nr_regions < 1) {
                log_err("Failed to get correct DRAM information\n");
-               return -1;
+               return;
        }
 
-       /*
-        * U-Boot RAM size must be under the first DRAM region so that it doesn't
-        * access secure memory which is at the end of the first DRAM region.
-        */
-       gd->ram_size = ent[0].size;
-
        /* Update memory region maps */
        for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
                if (i >= MAX_DDR_REGIONS)
@@ -167,24 +188,14 @@ int dram_init(void)
                mr = &mem_map[DDR_REGION_INDEX(0)];
                mem_map[ri].attrs = mr->attrs;
        }
-
-       return 0;
 }
 
-int dram_init_banksize(void)
+void enable_caches(void)
 {
-       struct draminfo_entry *ent = synquacer_draminfo->entry;
-       int i;
-
-       for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
-               if (i < synquacer_draminfo->nr_regions) {
-                       debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
-                       gd->bd->bi_dram[i].start = ent[i].base;
-                       gd->bd->bi_dram[i].size = ent[i].size;
-               }
-       }
+       build_mem_map();
 
-       return 0;
+       icache_enable();
+       dcache_enable();
 }
 
 int print_cpuinfo(void)