ARM: Introduce erratum workaround for 801819

Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "

Recommended workaround is as follows:
Do both of the following:

1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.

For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:

3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111

So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.

Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.

Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
might not meet the condition for the erratum to occur when they donot
have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
Extensions). Such SoCs will need the work around handled in the SoC
specific manner, since there is no ARM generic manner to detect such
configurations.

Based on ARM errata Document revision 18.0 (22 Nov 2013)

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/README b/README
index 1bcb63c7e39b8316ca8642dce640f543a5f6b012..95f2d9d2fe97026f2200dfee9f61c500b6aaa3f9 100644 (file)
--- a/README
+++ b/README
@@ -705,6 +705,7 @@ The following options need to be configured:
                CONFIG_ARM_ERRATA_454179
                CONFIG_ARM_ERRATA_621766
                CONFIG_ARM_ERRATA_798870
+               CONFIG_ARM_ERRATA_801819
 
 - Tegra SoC options:
                CONFIG_TEGRA_SUPPORT_NON_SECURE

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 1c7e6f01f9414c09bac40a5a4d81381d98bae4c5..b18094447b0601e8a7ff539c0b286c693c66d5da 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -187,6 +187,27 @@ ENTRY(cpu_init_cp15)
 skip_errata_798870:
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_801819
+       cmp     r2, #0x24               @ Applies to lt including R2p4
+       bgt     skip_errata_801819      @ skip if not affected rev
+       cmp     r2, #0x20               @ Applies to including and above R2p0
+       blt     skip_errata_801819      @ skip if not affected rev
+       mrc     p15, 0, r0, c0, c0, 6   @ pick up REVIDR reg
+       and     r0, r0, #1 << 3         @ check REVIDR[3]
+       cmp     r0, #1 << 3
+       beq     skip_errata_801819      @ skip erratum if REVIDR[3] is set
+
+       mrc     p15, 0, r0, c1, c0, 1   @ read auxilary control register
+       orr     r0, r0, #3 << 27        @ Disables streaming. All write-allocate
+                                       @ lines allocate in the L1 or L2 cache.
+       orr     r0, r0, #3 << 25        @ Disables streaming. All write-allocate
+                                       @ lines allocate in the L1 cache.
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+skip_errata_801819:
+#endif
+
 #ifdef CONFIG_ARM_ERRATA_454179
        cmp     r2, #0x21               @ Only on < r2p1
        bge     skip_errata_454179