davinci: omapl138_lcdk: configure ddr2

The SPL is unable to load u-boot because the DDR2 is not configured.
Configure the DDR2.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 067b6c386b063cf07008e299ef40e0aa184c4e75..c593dadf682743519b14d2da65b0743a1ae5231a 100644 (file)
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -23,6 +23,7 @@ config TARGET_OMAPL138_LCDK
        bool "OMAPL138 LCDK"
        select SUPPORT_SPL
        select SYS_DA850_PLL_INIT
+       select SYS_DA850_DDR_INIT
 
 config TARGET_CALIMAIN
        bool "Calimain board"

diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 854fc478ad75b12bc67904278484aa98607550ca..9db9cea723a6850c5eade5ca3fb5fc61fae304d8 100644 (file)
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -78,6 +78,47 @@
 #define CONFIG_SYS_DA850_PLL0_PLLM     24
 #define CONFIG_SYS_DA850_PLL1_PLLM     21
 
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+                                       DV_DDR_PHY_EXT_STRBEN | \
+                                       (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (            \
+       (1 << DV_DDR_SDCR_DDR2EN_SHIFT)         | \
+       (1 << DV_DDR_SDCR_DDREN_SHIFT)          | \
+       (1 << DV_DDR_SDCR_SDRAMEN_SHIFT)        | \
+       (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)      | \
+       (4 << DV_DDR_SDCR_CL_SHIFT)             | \
+       (3 << DV_DDR_SDCR_IBANK_SHIFT)          | \
+       (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (           \
+       (19 << DV_DDR_SDTMR1_RFC_SHIFT)         | \
+       (1 << DV_DDR_SDTMR1_RP_SHIFT)           | \
+       (1 << DV_DDR_SDTMR1_RCD_SHIFT)          | \
+       (2 << DV_DDR_SDTMR1_WR_SHIFT)           | \
+       (6 << DV_DDR_SDTMR1_RAS_SHIFT)          | \
+       (8 << DV_DDR_SDTMR1_RC_SHIFT)           | \
+       (1 << DV_DDR_SDTMR1_RRD_SHIFT)          | \
+       (1 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (                  \
+       (7 << DV_DDR_SDTMR2_RASMAX_SHIFT)       | \
+       (2 << DV_DDR_SDTMR2_XP_SHIFT)           | \
+       (0 << DV_DDR_SDTMR2_ODT_SHIFT)          | \
+       (10 << DV_DDR_SDTMR2_XSNR_SHIFT)        | \
+       (199 << DV_DDR_SDTMR2_XSRD_SHIFT)       | \
+       (1 << DV_DDR_SDTMR2_RTP_SHIFT)          | \
+       (2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
+#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+
 /*
  * Serial Driver info
  */