ARM: uniphier: move PLLCTRL register macros to each SoC .c file

The new SoC PXs3 changed the address of PLL, but still uses the
same PLL name.  We can not define SC_*PLLCTRL in the common header.
Move them to per-SoC .c file.  Also, fix some PLL comments.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
index b4a97d21610f1027f3b30b7a85eb50a9866a9cd2..1a7ec295252408a9aca747334c49fdb9af7e83ad 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -11,6 +11,17 @@
 #include "../sc64-regs.h"
 #include "pll.h"
 
+/* PLL type: SSC */
+#define SC_CPLLCTRL    (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
+#define SC_SPLLCTRL    (SC_BASE_ADDR | 0x1410) /* misc */
+#define SC_MPLLCTRL    (SC_BASE_ADDR | 0x1430) /* DSP */
+#define SC_VSPLLCTRL   (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
+#define SC_DPLLCTRL    (SC_BASE_ADDR | 0x1460) /* DDR memory */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+
 void uniphier_ld11_pll_init(void)
 {
        uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2);     /* 2000MHz -> 1960MHz */

diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c
index 50b91598d64d9189071e3a503d36f03c62cd2f4b..5e072c6dff77bc3559b00d573cbac8a4bd66d77a 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld20.c
@@ -11,6 +11,25 @@
 #include "../sc64-regs.h"
 #include "pll.h"
 
+/* PLL type: SSC */
+#define SC_CPLLCTRL    (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
+#define SC_SPLLCTRL    (SC_BASE_ADDR | 0x1410) /* misc */
+#define SC_SPLL2CTRL   (SC_BASE_ADDR | 0x1420) /* DSP */
+#define SC_MPLLCTRL    (SC_BASE_ADDR | 0x1430) /* Video codec */
+#define SC_VPPLLCTRL   (SC_BASE_ADDR | 0x1440) /* VPE etc. */
+#define SC_GPPLLCTRL   (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
+#define SC_DPLL0CTRL   (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
+#define SC_DPLL1CTRL   (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
+#define SC_DPLL2CTRL   (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+
+/* PLL type: DSPLL */
+#define SC_VPLL8KCTRL  (SC_BASE_ADDR | 0x1540)
+#define SC_A2PLLCTRL   (SC_BASE_ADDR | 0x15C0)
+
 void uniphier_ld20_pll_init(void)
 {
        uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);

diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index d3aa18530d97593bd0b43ce071f10363d59f09d6..d0a51f239c3808c2beede8c86631089d3b5bed59 100644 (file)
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -12,27 +12,6 @@
 
 #define SC_BASE_ADDR           0x61840000
 
-/* PLL type: SSC */
-#define SC_CPLLCTRL    (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */
-#define SC_SPLLCTRL    (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */
-#define SC_SPLL2CTRL   (SC_BASE_ADDR | 0x1420) /* LD20: IPP */
-#define SC_MPLLCTRL    (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */
-#define SC_VSPLLCTRL   (SC_BASE_ADDR | 0x1440) /* LD11 */
-#define SC_VPPLLCTRL   (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */
-#define SC_GPPLLCTRL   (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */
-#define SC_DPLLCTRL    (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */
-#define SC_DPLL0CTRL   (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */
-#define SC_DPLL1CTRL   (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */
-#define SC_DPLL2CTRL   (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */
-
-/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
-
-/* PLL type: DSPLL */
-#define SC_VPLL8KCTRL  (SC_BASE_ADDR | 0x1540)
-#define SC_A2PLLCTRL   (SC_BASE_ADDR | 0x15C0)
-
 #define SC_RSTCTRL             (SC_BASE_ADDR | 0x2000)
 #define SC_RSTCTRL3            (SC_BASE_ADDR | 0x2008)
 #define SC_RSTCTRL4            (SC_BASE_ADDR | 0x200c)