clk: imxrt: Use dts for anatop base address

In Linux IMX and IMXRT use the device tree to hold the anatop address.
The anatop is used in clock drivers as it controls the internal PLLs
This will move the macro from asm/arch-imxrt to the device tree.
This presumably should also be done with the other IMX boards as well.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>

diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 121665a2d226bee3f4bc5b74abd18ad2575a5b30..9e1b074d2e7606ef7219798f4a53f2ad21c8be01 100644 (file)
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -22,6 +22,10 @@
        u-boot,dm-spl;
 };
 
+&anatop {
+       u-boot,dm-spl;
+};
+
 &clks {
        u-boot,dm-spl;
 };

diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 5ba314f99534ab75ae9e954311917b8775c203e6..13511ebb18ecbc6e36b269f396effc66bf374d8e 100644 (file)
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -67,6 +67,11 @@
                        fsl,mux_mask = <0x7>;
                };
 
+               anatop: anatop@400d8000 {
+                       compatible = "fsl,imxrt-anatop";
+                       reg = <0x400d8000 0x4000>;
+               };
+
                clks: ccm@400fc000 {
                        compatible = "fsl,imxrt1020-ccm";
                        reg = <0x400fc000 0x4000>;

diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 3168c2df2cf5587467d42e9a10fb8d37fcdcc4bc..617cece448af7e2118658d3216d3a86cd5844695 100644 (file)
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -22,6 +22,10 @@
        u-boot,dm-spl;
 };
 
+&anatop {
+       u-boot,dm-spl;
+};
+
 &clks {
        u-boot,dm-spl;
 };

diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 6560a3827f06bad970d1178074ced59e63dfef13..09f4712af681a9e7cb0be4e69b0f7885386f1fd0 100644 (file)
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -59,6 +59,11 @@
                        fsl,mux_mask = <0x7>;
                };
 
+               anatop: anatop@400d8000 {
+                       compatible = "fsl,imxrt-anatop";
+                       reg = <0x400d8000 0x4000>;
+               };
+
                clks: ccm@400fc000 {
                        compatible = "fsl,imxrt1050-ccm";
                        reg = <0x400fc000 0x4000>;

diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h
index d01e6ca2e02a804715e206c96b5fab9f9d9089a2..ad739caae928c6d62de1340ad6c9c0a85423a8a1 100644 (file)
--- a/arch/arm/include/asm/arch-imxrt/imx-regs.h
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -15,8 +15,6 @@
 #define GPIO4_BASE_ADDR                0x401C4000
 #define GPIO5_BASE_ADDR                0x400C0000
 
-#define ANATOP_BASE_ADDR       0x400d8000
-
 #define MXS_LCDIF_BASE         0x402b8000
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))

diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
index 3f8b4df3c5a060ec53c654595cfd2f3c30fe67bc..dc91ac5adbf15b0494e2bc9e904f906a71c739aa 100644 (file)
--- a/drivers/clk/imx/clk-imxrt1020.c
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -36,7 +36,7 @@ static int imxrt1020_clk_probe(struct udevice *dev)
        void *base;
 
        /* Anatop clocks */
-       base = (void *)ANATOP_BASE_ADDR;
+       base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
        clk_dm(IMXRT1020_CLK_PLL2_SYS,
               imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",

diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 5cb5e3bc15a5984411e3b8753a741557fefff63a..d40635d17a4aadf4ef2cc5ba0e95467a42f8e1b4 100644 (file)
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -34,7 +34,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
        void *base;
 
        /* Anatop clocks */
-       base = (void *)ANATOP_BASE_ADDR;
+       base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
        clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
               imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,