#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
+#include <mach/fw_info.h>
/* Armada 7k/8k */
#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
static struct mm_region mvebu_mem_map[] = {
/* Armada 80x0 memory regions include the CP1 (slave) units */
{
- /* RAM */
+ /* RAM 0-64MB */
.phys = 0x0UL,
.virt = 0x0UL,
+ .size = ATF_REGION_START,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ /* ATF and TEE region 0x4000000-0x5400000 not mapped */
+ {
+ /* RAM 66MB-2GB */
+ .phys = ATF_REGION_END,
+ .virt = ATF_REGION_END,
.size = SZ_2G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+#ifndef _FW_INFO_H_
+#define _FW_INFO_H_
+
+/* Protected ATF and TEE region */
+#define ATF_REGION_START 0x4000000
+#define ATF_REGION_END 0x5400000
+
+#endif /* _FW_INFO_H_ */