arm64: dts: rockchip: add USB3 DRD controllers on rk3588

Add both USB3 dual-role controllers to the RK3588 devicetree.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 33f393a2a990e16f56931ca708295f31d2b44415 ]

(cherry picked from commit c7ed588e14f7dd04a92fb55f12680f94c7b14edf)
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 4fdd047c9eb9869b5f753508f2a557d0bec7b986..5984016b5f96de290d9840f81b5f55061e3448d0 100644 (file)
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -7,6 +7,26 @@
 #include "rk3588-pinctrl.dtsi"
 
 / {
+       usb_host1_xhci: usb@fc400000 {
+               compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+               reg = <0x0 0xfc400000 0x0 0x400000>;
+               interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
+                        <&cru ACLK_USB3OTG1>;
+               clock-names = "ref_clk", "suspend_clk", "bus_clk";
+               dr_mode = "otg";
+               phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
+               phy-names = "usb2-phy", "usb3-phy";
+               phy_type = "utmi_wide";
+               power-domains = <&power RK3588_PD_USB>;
+               resets = <&cru SRST_A_USB3OTG1>;
+               snps,dis_enblslpm_quirk;
+               snps,dis-u2-freeclk-exists-quirk;
+               snps,dis-del-phy-power-chg-quirk;
+               snps,dis-tx-ipgap-linecheck-quirk;
+               status = "disabled";
+       };
+
        pcie30_phy_grf: syscon@fd5b8000 {
                compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
                reg = <0x0 0xfd5b8000 0x0 0x10000>;

diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 9063c0bb0f02ba727fe6e34ffeacfd5e55e935ce..b0a59ec5183b75a80130df0e7728c90f924710bf 100644 (file)
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -492,6 +492,28 @@
                };
        };
 
+       usb_host0_xhci: usb@fc000000 {
+               compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+               reg = <0x0 0xfc000000 0x0 0x400000>;
+               interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
+                        <&cru ACLK_USB3OTG0>;
+               clock-names = "ref_clk", "suspend_clk", "bus_clk";
+               dr_mode = "otg";
+               phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
+               phy-names = "usb2-phy", "usb3-phy";
+               phy_type = "utmi_wide";
+               power-domains = <&power RK3588_PD_USB>;
+               resets = <&cru SRST_A_USB3OTG0>;
+               snps,dis_enblslpm_quirk;
+               snps,dis-u1-entry-quirk;
+               snps,dis-u2-entry-quirk;
+               snps,dis-u2-freeclk-exists-quirk;
+               snps,dis-del-phy-power-chg-quirk;
+               snps,dis-tx-ipgap-linecheck-quirk;
+               status = "disabled";
+       };
+
        usb_host0_ehci: usb@fc800000 {
                compatible = "rockchip,rk3588-ehci", "generic-ehci";
                reg = <0x0 0xfc800000 0x0 0x40000>;