There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.
Signed-off-by: Heiko Schocher <hs@denx.de>
CONFIG_SCSI * SCSI Support
CONFIG_CMD_SDRAM * print SDRAM configuration information
(requires CONFIG_CMD_I2C)
- CONFIG_CMD_SETGETDCR Support for DCR Register access
- (4xx only)
CONFIG_CMD_SF * Read/write/erase SPI NOR flash
CONFIG_CMD_SOFTSWITCH * Soft switch setting command for BF60x
CONFIG_CMD_SOURCE "source" command Support
sequences.
U-Boot uses the following memory types:
- - PPC4xx: data cache
- CONFIG_SYS_GBL_DATA_OFFSET:
CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
-- CONFIG_PCI_DISABLE_PCIE:
- Disable PCI-Express on systems where it is supported but not
- required.
-
- CONFIG_PCI_ENUM_ONLY
Only scan through and get the devices on the buses.
Don't do any setup work, presumably because someone or
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
-config 4xx
- bool "PPC4xx"
- select CREATE_ARCH_SYMLINK
- imply CMD_IRQ
-
endchoice
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc86xx/Kconfig"
-source "arch/powerpc/cpu/ppc4xx/Kconfig"
endmenu
#
head-y := arch/powerpc/cpu/$(CPU)/start.o
-head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o
head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
libs-y += arch/powerpc/cpu/$(CPU)/
+++ /dev/null
-/*
- * arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
- * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
- * SDRAM controller. Those are all current 405 PPC's.
- *
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
- *
- * Based on code by:
- *
- * Kenneth Johansson ,Ericsson AB.
- * kenneth.johansson@etx.ericsson.se
- *
- * hacked up by bill hunter. fixed so we could run before
- * serial_init and console_init. previous version avoided this by
- * running out of cache memory during serial/console init, then running
- * this code later.
- *
- * (C) Copyright 2002
- * Jun Gu, Artesyn Technology, jung@artesyncp.com
- * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <asm/ppc4xx.h>
-
-#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
-
-/*
- * Set default values
- */
-#define ONE_BILLION 1000000000
-
-#define SDRAM0_CFG_DCE 0x80000000
-#define SDRAM0_CFG_SRE 0x40000000
-#define SDRAM0_CFG_PME 0x20000000
-#define SDRAM0_CFG_MEMCHK 0x10000000
-#define SDRAM0_CFG_REGEN 0x08000000
-#define SDRAM0_CFG_ECCDD 0x00400000
-#define SDRAM0_CFG_EMDULR 0x00200000
-#define SDRAM0_CFG_DRW_SHIFT (31-6)
-#define SDRAM0_CFG_BRPF_SHIFT (31-8)
-
-#define SDRAM0_TR_CASL_SHIFT (31-8)
-#define SDRAM0_TR_PTA_SHIFT (31-13)
-#define SDRAM0_TR_CTP_SHIFT (31-15)
-#define SDRAM0_TR_LDF_SHIFT (31-17)
-#define SDRAM0_TR_RFTA_SHIFT (31-29)
-#define SDRAM0_TR_RCD_SHIFT (31-31)
-
-#define SDRAM0_RTR_SHIFT (31-15)
-#define SDRAM0_ECCCFG_SHIFT (31-11)
-
-/* SDRAM0_CFG enable macro */
-#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
-
-#define SDRAM0_BXCR_SZ_MASK 0x000e0000
-#define SDRAM0_BXCR_AM_MASK 0x0000e000
-
-#define SDRAM0_BXCR_SZ_SHIFT (31-14)
-#define SDRAM0_BXCR_AM_SHIFT (31-18)
-
-#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
-#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
-
-#ifdef CONFIG_SPDDRAM_SILENT
-# define SPD_ERR(x) do { return 0; } while (0)
-#else
-# define SPD_ERR(x) do { printf(x); return(0); } while (0)
-#endif
-
-#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
-
-/* function prototypes */
-int spd_read(uint addr);
-
-
-/*
- * This function is reading data from the DIMM module EEPROM over the SPD bus
- * and uses that to program the sdram controller.
- *
- * This works on boards that has the same schematics that the AMCC walnut has.
- *
- * Input: null for default I2C spd functions or a pointer to a custom function
- * returning spd_data.
- */
-
-long int spd_sdram(int(read_spd)(uint addr))
-{
- int tmp,row,col;
- int total_size,bank_size,bank_code;
- int mode;
- int bank_cnt;
-
- int sdram0_pmit=0x07c00000;
- int sdram0_b0cr;
- int sdram0_b1cr = 0;
-#ifndef CONFIG_405EP /* not on PPC405EP */
- int sdram0_b2cr = 0;
- int sdram0_b3cr = 0;
- int sdram0_besr0 = -1;
- int sdram0_besr1 = -1;
- int sdram0_eccesr = -1;
- int sdram0_ecccfg;
- int ecc_on;
-#endif
-
- int sdram0_rtr=0;
- int sdram0_tr=0;
-
- int sdram0_cfg=0;
-
- int t_rp;
- int t_rcd;
- int t_ras;
- int t_rc;
- int min_cas;
-
- PPC4xx_SYS_INFO sys_info;
- unsigned long bus_period_x_10;
-
- /*
- * get the board info
- */
- get_sys_info(&sys_info);
- bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
-
- if (read_spd == 0){
- read_spd=spd_read;
- /*
- * Make sure I2C controller is initialized
- * before continuing.
- */
- i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
- }
-
- /* Make shure we are using SDRAM */
- if (read_spd(2) != 0x04) {
- SPD_ERR("SDRAM - non SDRAM memory module found\n");
- }
-
- /* ------------------------------------------------------------------
- * configure memory timing register
- *
- * data from DIMM:
- * 27 IN Row Precharge Time ( t RP)
- * 29 MIN RAS to CAS Delay ( t RCD)
- * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
- * -------------------------------------------------------------------*/
-
- /*
- * first figure out which cas latency mode to use
- * use the min supported mode
- */
-
- tmp = read_spd(127) & 0x6;
- if (tmp == 0x02) { /* only cas = 2 supported */
- min_cas = 2;
-/* t_ck = read_spd(9); */
-/* t_ac = read_spd(10); */
- } else if (tmp == 0x04) { /* only cas = 3 supported */
- min_cas = 3;
-/* t_ck = read_spd(9); */
-/* t_ac = read_spd(10); */
- } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
- min_cas = 2;
-/* t_ck = read_spd(23); */
-/* t_ac = read_spd(24); */
- } else {
- SPD_ERR("SDRAM - unsupported CAS latency \n");
- }
-
- /* get some timing values, t_rp,t_rcd,t_ras,t_rc
- */
- t_rp = read_spd(27);
- t_rcd = read_spd(29);
- t_ras = read_spd(30);
- t_rc = t_ras + t_rp;
-
- /* The following timing calcs subtract 1 before deviding.
- * this has effect of using ceiling instead of floor rounding,
- * and also subtracting 1 to convert number to reg value
- */
- /* set up CASL */
- sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
- /* set up PTA */
- sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
- /* set up CTP */
- tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
- if (tmp < 1)
- tmp = 1;
- sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
- /* set LDF = 2 cycles, reg value = 1 */
- sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
- /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
- tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
- if (tmp < 0)
- tmp = 0;
- if (tmp > 6)
- tmp = 6;
- sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
- /* set RCD = t_rcd/bus_period*/
- sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
-
-
- /*------------------------------------------------------------------
- * configure RTR register
- * -------------------------------------------------------------------*/
- row = read_spd(3);
- col = read_spd(4);
- tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
- switch (tmp) {
- case 0x00:
- tmp = 15625;
- break;
- case 0x01:
- tmp = 15625 / 4;
- break;
- case 0x02:
- tmp = 15625 / 2;
- break;
- case 0x03:
- tmp = 15625 * 2;
- break;
- case 0x04:
- tmp = 15625 * 4;
- break;
- case 0x05:
- tmp = 15625 * 8;
- break;
- default:
- SPD_ERR("SDRAM - Bad refresh period \n");
- }
- /* convert from nsec to bus cycles */
- tmp = (tmp * 10) / bus_period_x_10;
- sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
-
- /*------------------------------------------------------------------
- * determine the number of banks used
- * -------------------------------------------------------------------*/
- /* byte 7:6 is module data width */
- if (read_spd(7) != 0)
- SPD_ERR("SDRAM - unsupported module width\n");
- tmp = read_spd(6);
- if (tmp < 32)
- SPD_ERR("SDRAM - unsupported module width\n");
- else if (tmp < 64)
- bank_cnt = 1; /* one bank per sdram side */
- else if (tmp < 73)
- bank_cnt = 2; /* need two banks per side */
- else if (tmp < 161)
- bank_cnt = 4; /* need four banks per side */
- else
- SPD_ERR("SDRAM - unsupported module width\n");
-
- /* byte 5 is the module row count (refered to as dimm "sides") */
- tmp = read_spd(5);
- if (tmp == 1)
- ;
- else if (tmp==2)
- bank_cnt *= 2;
- else if (tmp==4)
- bank_cnt *= 4;
- else
- bank_cnt = 8; /* 8 is an error code */
-
- if (bank_cnt > 4) /* we only have 4 banks to work with */
- SPD_ERR("SDRAM - unsupported module rows for this width\n");
-
-#ifndef CONFIG_405EP /* not on PPC405EP */
- /* now check for ECC ability of module. We only support ECC
- * on 32 bit wide devices with 8 bit ECC.
- */
- if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
- sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
- ecc_on = 1;
- } else {
- sdram0_ecccfg = 0;
- ecc_on = 0;
- }
-#endif
-
- /*------------------------------------------------------------------
- * calculate total size
- * -------------------------------------------------------------------*/
- /* calculate total size and do sanity check */
- tmp = read_spd(31);
- total_size = 1 << 22; /* total_size = 4MB */
- /* now multiply 4M by the smallest device row density */
- /* note that we don't support asymetric rows */
- while (((tmp & 0x0001) == 0) && (tmp != 0)) {
- total_size = total_size << 1;
- tmp = tmp >> 1;
- }
- total_size *= read_spd(5); /* mult by module rows (dimm sides) */
-
- /*------------------------------------------------------------------
- * map rows * cols * banks to a mode
- * -------------------------------------------------------------------*/
-
- switch (row) {
- case 11:
- switch (col) {
- case 8:
- mode=4; /* mode 5 */
- break;
- case 9:
- case 10:
- mode=0; /* mode 1 */
- break;
- default:
- SPD_ERR("SDRAM - unsupported mode\n");
- }
- break;
- case 12:
- switch (col) {
- case 8:
- mode=3; /* mode 4 */
- break;
- case 9:
- case 10:
- mode=1; /* mode 2 */
- break;
- default:
- SPD_ERR("SDRAM - unsupported mode\n");
- }
- break;
- case 13:
- switch (col) {
- case 8:
- mode=5; /* mode 6 */
- break;
- case 9:
- case 10:
- if (read_spd(17) == 2)
- mode = 6; /* mode 7 */
- else
- mode = 2; /* mode 3 */
- break;
- case 11:
- mode = 2; /* mode 3 */
- break;
- default:
- SPD_ERR("SDRAM - unsupported mode\n");
- }
- break;
- default:
- SPD_ERR("SDRAM - unsupported mode\n");
- }
-
- /*------------------------------------------------------------------
- * using the calculated values, compute the bank
- * config register values.
- * -------------------------------------------------------------------*/
-
- /* compute the size of each bank */
- bank_size = total_size / bank_cnt;
- /* convert bank size to bank size code for ppc4xx
- by takeing log2(bank_size) - 22 */
- tmp = bank_size; /* start with tmp = bank_size */
- bank_code = 0; /* and bank_code = 0 */
- while (tmp > 1) { /* this takes log2 of tmp */
- bank_code++; /* and stores result in bank_code */
- tmp = tmp >> 1;
- } /* bank_code is now log2(bank_size) */
- bank_code -= 22; /* subtract 22 to get the code */
-
- tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
- sdram0_b0cr = (bank_size * 0) | tmp;
-#ifndef CONFIG_405EP /* not on PPC405EP */
- if (bank_cnt > 1)
- sdram0_b2cr = (bank_size * 1) | tmp;
- if (bank_cnt > 2)
- sdram0_b1cr = (bank_size * 2) | tmp;
- if (bank_cnt > 3)
- sdram0_b3cr = (bank_size * 3) | tmp;
-#else
- /* PPC405EP chip only supports two SDRAM banks */
- if (bank_cnt > 1)
- sdram0_b1cr = (bank_size * 1) | tmp;
- if (bank_cnt > 2)
- total_size = 2 * bank_size;
-#endif
-
- /*
- * enable sdram controller DCE=1
- * enable burst read prefetch to 32 bytes BRPF=2
- * leave other functions off
- */
-
- /*------------------------------------------------------------------
- * now that we've done our calculations, we are ready to
- * program all the registers.
- * -------------------------------------------------------------------*/
-
- /* disable memcontroller so updates work */
- mtsdram(SDRAM0_CFG, 0);
-
-#ifndef CONFIG_405EP /* not on PPC405EP */
- mtsdram(SDRAM0_BESR0, sdram0_besr0);
- mtsdram(SDRAM0_BESR1, sdram0_besr1);
- mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg);
- mtsdram(SDRAM0_ECCESR, sdram0_eccesr);
-#endif
- mtsdram(SDRAM0_RTR, sdram0_rtr);
- mtsdram(SDRAM0_PMIT, sdram0_pmit);
- mtsdram(SDRAM0_B0CR, sdram0_b0cr);
- mtsdram(SDRAM0_B1CR, sdram0_b1cr);
-#ifndef CONFIG_405EP /* not on PPC405EP */
- mtsdram(SDRAM0_B2CR, sdram0_b2cr);
- mtsdram(SDRAM0_B3CR, sdram0_b3cr);
-#endif
- mtsdram(SDRAM0_TR, sdram0_tr);
-
- /* SDRAM have a power on delay, 500 micro should do */
- udelay(500);
- sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
-#ifndef CONFIG_405EP /* not on PPC405EP */
- if (ecc_on)
- sdram0_cfg |= SDRAM0_CFG_MEMCHK;
-#endif
- mtsdram(SDRAM0_CFG, sdram0_cfg);
-
- return (total_size);
-}
-
-int spd_read(uint addr)
-{
- uchar data[2];
-
- if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
- return (int)data[0];
- else
- return 0;
-}
-
-#endif /* CONFIG_SPD_EEPROM */
+++ /dev/null
-/*
- * arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
- * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
- * DDR controller. Those are 440GP/GX/EP/GR.
- *
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
- *
- * Based on code by:
- *
- * Kenneth Johansson ,Ericsson AB.
- * kenneth.johansson@etx.ericsson.se
- *
- * hacked up by bill hunter. fixed so we could run before
- * serial_init and console_init. previous version avoided this by
- * running out of cache memory during serial/console init, then running
- * this code later.
- *
- * (C) Copyright 2002
- * Jun Gu, Artesyn Technology, jung@artesyncp.com
- * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
- *
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <asm/ppc4xx.h>
-#include <asm/mmu.h>
-
-#include "ecc.h"
-
-#if defined(CONFIG_SPD_EEPROM) && \
- (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR))
-
-/*
- * Set default values
- */
-#define ONE_BILLION 1000000000
-
-/*
- * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
- */
-void __spd_ddr_init_hang (void)
-{
- hang ();
-}
-void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
-
-/*-----------------------------------------------------------------------------+
- | General Definition
- +-----------------------------------------------------------------------------*/
-#define DEFAULT_SPD_ADDR1 0x53
-#define DEFAULT_SPD_ADDR2 0x52
-#define MAXBANKS 4 /* at most 4 dimm banks */
-#define MAX_SPD_BYTES 256
-#define NUMHALFCYCLES 4
-#define NUMMEMTESTS 8
-#define NUMMEMWORDS 8
-#define MAXBXCR 4
-
-/*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
- * region. Right now the cache should still be disabled in U-Boot because of the
- * EMAC driver, that need it's buffer descriptor to be located in non cached
- * memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#ifdef CONFIG_4xx_DCACHE
-#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
-#else
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
-#endif
-
-/* bank_parms is used to sort the bank sizes by descending order */
-struct bank_param {
- unsigned long cr;
- unsigned long bank_size_bytes;
-};
-
-typedef struct bank_param BANKPARMS;
-
-#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
-extern const unsigned char cfg_simulate_spd_eeprom[128];
-#endif
-
-static unsigned char spd_read(uchar chip, uint addr);
-static void get_spd_info(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void check_mem_type(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void check_volt_type(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_cfg0(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_cfg1(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_rtr(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_tr0(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_tr1(void);
-
-static unsigned long program_bxcr(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-
-/*
- * This function is reading data from the DIMM module EEPROM over the SPD bus
- * and uses that to program the sdram controller.
- *
- * This works on boards that has the same schematics that the AMCC walnut has.
- *
- * BUG: Don't handle ECC memory
- * BUG: A few values in the TR register is currently hardcoded
- */
-long int spd_sdram(void) {
- unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
- unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
- unsigned long total_size;
- unsigned long cfg0;
- unsigned long mcsts;
- unsigned long num_dimm_banks; /* on board dimm banks */
-
- num_dimm_banks = sizeof(iic0_dimm_addr);
-
- /*
- * Make sure I2C controller is initialized
- * before continuing.
- */
- i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
-
- /*
- * Read the SPD information using I2C interface. Check to see if the
- * DIMM slots are populated.
- */
- get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * Check the memory type for the dimms plugged.
- */
- check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * Check the voltage type for the dimms plugged.
- */
- check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
- /*
- * Soft-reset SDRAM controller.
- */
- mtsdr(SDR0_SRST, SDR0_SRST_DMC);
- mtsdr(SDR0_SRST, 0x00000000);
-#endif
-
- /*
- * program 440GP SDRAM controller options (SDRAM0_CFG0)
- */
- program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * program 440GP SDRAM controller options (SDRAM0_CFG1)
- */
- program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * program SDRAM refresh register (SDRAM0_RTR)
- */
- program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * program SDRAM Timing Register 0 (SDRAM0_TR0)
- */
- program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*
- * program the BxCR registers to find out total sdram installed
- */
- total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
- num_dimm_banks);
-
-#ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
- /* and program tlb entries for this size (dynamic) */
- program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
-#endif
-
- /*
- * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
- */
- mtsdram(SDRAM0_CLKTR, 0x40000000);
-
- /*
- * delay to ensure 200 usec has elapsed
- */
- udelay(400);
-
- /*
- * enable the memory controller
- */
- mfsdram(SDRAM0_CFG0, cfg0);
- mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN);
-
- /*
- * wait for SDRAM_CFG0_DC_EN to complete
- */
- while (1) {
- mfsdram(SDRAM0_MCSTS, mcsts);
- if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
- break;
- }
-
- /*
- * program SDRAM Timing Register 1, adding some delays
- */
- program_tr1();
-
-#ifdef CONFIG_DDR_ECC
- /*
- * If ecc is enabled, initialize the parity bits.
- */
- ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
-#endif
-
- return total_size;
-}
-
-static unsigned char spd_read(uchar chip, uint addr)
-{
- unsigned char data[2];
-
-#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
- if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
- /*
- * Onboard spd eeprom requested -> simulate values
- */
- return cfg_simulate_spd_eeprom[addr];
- }
-#endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
-
- if (i2c_probe(chip) == 0) {
- if (i2c_read(chip, addr, 1, data, 1) == 0) {
- return data[0];
- }
- }
-
- return 0;
-}
-
-static void get_spd_info(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long dimm_found;
- unsigned char num_of_bytes;
- unsigned char total_size;
-
- dimm_found = false;
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- num_of_bytes = 0;
- total_size = 0;
-
- num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
- total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
-
- if ((num_of_bytes != 0) && (total_size != 0)) {
- dimm_populated[dimm_num] = true;
- dimm_found = true;
- debug("DIMM slot %lu: populated\n", dimm_num);
- } else {
- dimm_populated[dimm_num] = false;
- debug("DIMM slot %lu: Not populated\n", dimm_num);
- }
- }
-
- if (dimm_found == false) {
- printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
- spd_ddr_init_hang ();
- }
-}
-
-static void check_mem_type(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned char dimm_type;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == true) {
- dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
- switch (dimm_type) {
- case 7:
- debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
- break;
- default:
- printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
- dimm_num);
- printf("Only DDR SDRAM DIMMs are supported.\n");
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- break;
- }
- }
- }
-}
-
-static void check_volt_type(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long voltage_type;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == true) {
- voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
- if (voltage_type != 0x04) {
- printf("ERROR: DIMM %lu with unsupported voltage level.\n",
- dimm_num);
- spd_ddr_init_hang ();
- } else {
- debug("DIMM %lu voltage level supported.\n", dimm_num);
- }
- break;
- }
- }
-}
-
-static void program_cfg0(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long cfg0;
- unsigned long ecc_enabled;
- unsigned char ecc;
- unsigned char attributes;
- unsigned long data_width;
-
- /*
- * get Memory Controller Options 0 data
- */
- mfsdram(SDRAM0_CFG0, cfg0);
-
- /*
- * clear bits
- */
- cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
- SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
- SDRAM_CFG0_DMWD_MASK |
- SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
-
-
- /*
- * FIXME: assume the DDR SDRAMs in both banks are the same
- */
- ecc_enabled = true;
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == true) {
- ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
- if (ecc != 0x02) {
- ecc_enabled = false;
- }
-
- /*
- * program Registered DIMM Enable
- */
- attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
- if ((attributes & 0x02) != 0x00) {
- cfg0 |= SDRAM_CFG0_RDEN;
- }
-
- /*
- * program DDR SDRAM Data Width
- */
- data_width =
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
- (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
- if (data_width == 64 || data_width == 72) {
- cfg0 |= SDRAM_CFG0_DMWD_64;
- } else if (data_width == 32 || data_width == 40) {
- cfg0 |= SDRAM_CFG0_DMWD_32;
- } else {
- printf("WARNING: DIMM with datawidth of %lu bits.\n",
- data_width);
- printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
- spd_ddr_init_hang ();
- }
- break;
- }
- }
-
- /*
- * program Memory Data Error Checking
- */
- if (ecc_enabled == true) {
- cfg0 |= SDRAM_CFG0_MCHK_GEN;
- } else {
- cfg0 |= SDRAM_CFG0_MCHK_NON;
- }
-
- /*
- * program Page Management Unit (0 == enabled)
- */
- cfg0 &= ~SDRAM_CFG0_PMUD;
-
- /*
- * program Memory Controller Options 0
- * Note: DCEN must be enabled after all DDR SDRAM controller
- * configuration registers get initialized.
- */
- mtsdram(SDRAM0_CFG0, cfg0);
-}
-
-static void program_cfg1(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long cfg1;
- mfsdram(SDRAM0_CFG1, cfg1);
-
- /*
- * Self-refresh exit, disable PM
- */
- cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
-
- /*
- * program Memory Controller Options 1
- */
- mtsdram(SDRAM0_CFG1, cfg1);
-}
-
-static void program_rtr(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long bus_period_x_10;
- unsigned long refresh_rate = 0;
- unsigned char refresh_rate_type;
- unsigned long refresh_interval;
- unsigned long sdram_rtr;
- PPC4xx_SYS_INFO sys_info;
-
- /*
- * get the board info
- */
- get_sys_info(&sys_info);
- bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == true) {
- refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
- switch (refresh_rate_type) {
- case 0x00:
- refresh_rate = 15625;
- break;
- case 0x01:
- refresh_rate = 15625/4;
- break;
- case 0x02:
- refresh_rate = 15625/2;
- break;
- case 0x03:
- refresh_rate = 15626*2;
- break;
- case 0x04:
- refresh_rate = 15625*4;
- break;
- case 0x05:
- refresh_rate = 15625*8;
- break;
- default:
- printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
- dimm_num);
- printf("Replace the DIMM module with a supported DIMM.\n");
- break;
- }
-
- break;
- }
- }
-
- refresh_interval = refresh_rate * 10 / bus_period_x_10;
- sdram_rtr = (refresh_interval & 0x3ff8) << 16;
-
- /*
- * program Refresh Timer Register (SDRAM0_RTR)
- */
- mtsdram(SDRAM0_RTR, sdram_rtr);
-}
-
-static void program_tr0(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long tr0;
- unsigned char wcsbc;
- unsigned char t_rp_ns;
- unsigned char t_rcd_ns;
- unsigned char t_ras_ns;
- unsigned long t_rp_clk;
- unsigned long t_ras_rcd_clk;
- unsigned long t_rcd_clk;
- unsigned long t_rfc_clk;
- unsigned long plb_check;
- unsigned char cas_bit;
- unsigned long cas_index;
- unsigned char cas_2_0_available;
- unsigned char cas_2_5_available;
- unsigned char cas_3_0_available;
- unsigned long cycle_time_ns_x_10[3];
- unsigned long tcyc_3_0_ns_x_10;
- unsigned long tcyc_2_5_ns_x_10;
- unsigned long tcyc_2_0_ns_x_10;
- unsigned long tcyc_reg;
- unsigned long bus_period_x_10;
- PPC4xx_SYS_INFO sys_info;
- unsigned long residue;
-
- /*
- * get the board info
- */
- get_sys_info(&sys_info);
- bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
-
- /*
- * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
- */
- mfsdram(SDRAM0_TR0, tr0);
- tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
- SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
- SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
- SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
-
- /*
- * initialization
- */
- wcsbc = 0;
- t_rp_ns = 0;
- t_rcd_ns = 0;
- t_ras_ns = 0;
- cas_2_0_available = true;
- cas_2_5_available = true;
- cas_3_0_available = true;
- tcyc_2_0_ns_x_10 = 0;
- tcyc_2_5_ns_x_10 = 0;
- tcyc_3_0_ns_x_10 = 0;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == true) {
- wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
- t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
- t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
- t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
- cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
-
- for (cas_index = 0; cas_index < 3; cas_index++) {
- switch (cas_index) {
- case 0:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
- break;
- case 1:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
- break;
- default:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
- break;
- }
-
- if ((tcyc_reg & 0x0F) >= 10) {
- printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
- dimm_num);
- spd_ddr_init_hang ();
- }
-
- cycle_time_ns_x_10[cas_index] =
- (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
- }
-
- cas_index = 0;
-
- if ((cas_bit & 0x80) != 0) {
- cas_index += 3;
- } else if ((cas_bit & 0x40) != 0) {
- cas_index += 2;
- } else if ((cas_bit & 0x20) != 0) {
- cas_index += 1;
- }
-
- if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
- tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
- cas_index++;
- } else {
- if (cas_index != 0) {
- cas_index++;
- }
- cas_3_0_available = false;
- }
-
- if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
- tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
- cas_index++;
- } else {
- if (cas_index != 0) {
- cas_index++;
- }
- cas_2_5_available = false;
- }
-
- if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
- tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
- cas_index++;
- } else {
- if (cas_index != 0) {
- cas_index++;
- }
- cas_2_0_available = false;
- }
-
- break;
- }
- }
-
- /*
- * Program SD_WR and SD_WCSBC fields
- */
- tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
- switch (wcsbc) {
- case 0:
- tr0 |= SDRAM_TR0_SDWD_0_CLK;
- break;
- default:
- tr0 |= SDRAM_TR0_SDWD_1_CLK;
- break;
- }
-
- /*
- * Program SD_CASL field
- */
- if ((cas_2_0_available == true) &&
- (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
- tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
- } else if ((cas_2_5_available == true) &&
- (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
- tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
- } else if ((cas_3_0_available == true) &&
- (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
- tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
- } else {
- printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
- printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
- printf("Make sure the PLB speed is within the supported range.\n");
- spd_ddr_init_hang ();
- }
-
- /*
- * Calculate Trp in clock cycles and round up if necessary
- * Program SD_PTA field
- */
- t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
- plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
- if (sys_info.freqPLB != plb_check) {
- t_rp_clk++;
- }
- switch ((unsigned long)t_rp_clk) {
- case 0:
- case 1:
- case 2:
- tr0 |= SDRAM_TR0_SDPA_2_CLK;
- break;
- case 3:
- tr0 |= SDRAM_TR0_SDPA_3_CLK;
- break;
- default:
- tr0 |= SDRAM_TR0_SDPA_4_CLK;
- break;
- }
-
- /*
- * Program SD_CTP field
- */
- t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
- plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
- if (sys_info.freqPLB != plb_check) {
- t_ras_rcd_clk++;
- }
- switch (t_ras_rcd_clk) {
- case 0:
- case 1:
- case 2:
- tr0 |= SDRAM_TR0_SDCP_2_CLK;
- break;
- case 3:
- tr0 |= SDRAM_TR0_SDCP_3_CLK;
- break;
- case 4:
- tr0 |= SDRAM_TR0_SDCP_4_CLK;
- break;
- default:
- tr0 |= SDRAM_TR0_SDCP_5_CLK;
- break;
- }
-
- /*
- * Program SD_LDF field
- */
- tr0 |= SDRAM_TR0_SDLD_2_CLK;
-
- /*
- * Program SD_RFTA field
- * FIXME tRFC hardcoded as 75 nanoseconds
- */
- t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
- residue = sys_info.freqPLB % (ONE_BILLION / 75);
- if (residue >= (ONE_BILLION / 150)) {
- t_rfc_clk++;
- }
- switch (t_rfc_clk) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- tr0 |= SDRAM_TR0_SDRA_6_CLK;
- break;
- case 7:
- tr0 |= SDRAM_TR0_SDRA_7_CLK;
- break;
- case 8:
- tr0 |= SDRAM_TR0_SDRA_8_CLK;
- break;
- case 9:
- tr0 |= SDRAM_TR0_SDRA_9_CLK;
- break;
- case 10:
- tr0 |= SDRAM_TR0_SDRA_10_CLK;
- break;
- case 11:
- tr0 |= SDRAM_TR0_SDRA_11_CLK;
- break;
- case 12:
- tr0 |= SDRAM_TR0_SDRA_12_CLK;
- break;
- default:
- tr0 |= SDRAM_TR0_SDRA_13_CLK;
- break;
- }
-
- /*
- * Program SD_RCD field
- */
- t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
- plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
- if (sys_info.freqPLB != plb_check) {
- t_rcd_clk++;
- }
- switch (t_rcd_clk) {
- case 0:
- case 1:
- case 2:
- tr0 |= SDRAM_TR0_SDRD_2_CLK;
- break;
- case 3:
- tr0 |= SDRAM_TR0_SDRD_3_CLK;
- break;
- default:
- tr0 |= SDRAM_TR0_SDRD_4_CLK;
- break;
- }
-
- debug("tr0: %lx\n", tr0);
- mtsdram(SDRAM0_TR0, tr0);
-}
-
-static int short_mem_test(void)
-{
- unsigned long i, j;
- unsigned long bxcr_num;
- unsigned long *membase;
- const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
- {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
- {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
- {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
- {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
- {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
- {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
- {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
- {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
-
- for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2));
- if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
- /* Bank is enabled */
- membase = (unsigned long*)
- (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK);
-
- /*
- * Run the short memory test
- */
- for (i = 0; i < NUMMEMTESTS; i++) {
- for (j = 0; j < NUMMEMWORDS; j++) {
- /* printf("bank enabled base:%x\n", &membase[j]); */
- membase[j] = test[i][j];
- ppcDcbf((unsigned long)&(membase[j]));
- }
-
- for (j = 0; j < NUMMEMWORDS; j++) {
- if (membase[j] != test[i][j]) {
- ppcDcbf((unsigned long)&(membase[j]));
- return 0;
- }
- ppcDcbf((unsigned long)&(membase[j]));
- }
-
- if (j < NUMMEMWORDS)
- return 0;
- }
-
- /*
- * see if the rdclt value passed
- */
- if (i < NUMMEMTESTS)
- return 0;
- }
- }
-
- return 1;
-}
-
-static void program_tr1(void)
-{
- unsigned long tr0;
- unsigned long tr1;
- unsigned long cfg0;
- unsigned long ecc_temp;
- unsigned long dlycal;
- unsigned long dly_val;
- unsigned long k;
- unsigned long max_pass_length;
- unsigned long current_pass_length;
- unsigned long current_fail_length;
- unsigned long current_start;
- unsigned long rdclt;
- unsigned long rdclt_offset;
- long max_start;
- long max_end;
- long rdclt_average;
- unsigned char window_found;
- unsigned char fail_found;
- unsigned char pass_found;
- PPC4xx_SYS_INFO sys_info;
-
- /*
- * get the board info
- */
- get_sys_info(&sys_info);
-
- /*
- * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
- */
- mfsdram(SDRAM0_TR1, tr1);
- tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
- SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
-
- mfsdram(SDRAM0_TR0, tr0);
- if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
- (sys_info.freqPLB > 100000000)) {
- tr1 |= SDRAM_TR1_RDSS_TR2;
- tr1 |= SDRAM_TR1_RDSL_STAGE3;
- tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
- } else {
- tr1 |= SDRAM_TR1_RDSS_TR1;
- tr1 |= SDRAM_TR1_RDSL_STAGE2;
- tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
- }
-
- /*
- * save CFG0 ECC setting to a temporary variable and turn ECC off
- */
- mfsdram(SDRAM0_CFG0, cfg0);
- ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
- mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
-
- /*
- * get the delay line calibration register value
- */
- mfsdram(SDRAM0_DLYCAL, dlycal);
- dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
-
- max_pass_length = 0;
- max_start = 0;
- max_end = 0;
- current_pass_length = 0;
- current_fail_length = 0;
- current_start = 0;
- rdclt_offset = 0;
- window_found = false;
- fail_found = false;
- pass_found = false;
- debug("Starting memory test ");
-
- for (k = 0; k < NUMHALFCYCLES; k++) {
- for (rdclt = 0; rdclt < dly_val; rdclt++) {
- /*
- * Set the timing reg for the test.
- */
- mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
-
- if (short_mem_test()) {
- if (fail_found == true) {
- pass_found = true;
- if (current_pass_length == 0) {
- current_start = rdclt_offset + rdclt;
- }
-
- current_fail_length = 0;
- current_pass_length++;
-
- if (current_pass_length > max_pass_length) {
- max_pass_length = current_pass_length;
- max_start = current_start;
- max_end = rdclt_offset + rdclt;
- }
- }
- } else {
- current_pass_length = 0;
- current_fail_length++;
-
- if (current_fail_length >= (dly_val>>2)) {
- if (fail_found == false) {
- fail_found = true;
- } else if (pass_found == true) {
- window_found = true;
- break;
- }
- }
- }
- }
- debug(".");
-
- if (window_found == true)
- break;
-
- tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
- rdclt_offset += dly_val;
- }
- debug("\n");
-
- /*
- * make sure we find the window
- */
- if (window_found == false) {
- printf("ERROR: Cannot determine a common read delay.\n");
- spd_ddr_init_hang ();
- }
-
- /*
- * restore the orignal ECC setting
- */
- mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
-
- /*
- * set the SDRAM TR1 RDCD value
- */
- tr1 &= ~SDRAM_TR1_RDCD_MASK;
- if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
- tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
- } else {
- tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
- }
-
- /*
- * set the SDRAM TR1 RDCLT value
- */
- tr1 &= ~SDRAM_TR1_RDCT_MASK;
- while (max_end >= (dly_val << 1)) {
- max_end -= (dly_val << 1);
- max_start -= (dly_val << 1);
- }
-
- rdclt_average = ((max_start + max_end) >> 1);
-
- if (rdclt_average < 0) {
- rdclt_average = 0;
- }
-
- if (rdclt_average >= dly_val) {
- rdclt_average -= dly_val;
- tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
- }
- tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
-
- debug("tr1: %lx\n", tr1);
-
- /*
- * program SDRAM Timing Register 1 TR1
- */
- mtsdram(SDRAM0_TR1, tr1);
-}
-
-static unsigned long program_bxcr(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long bank_base_addr;
- unsigned long cr;
- unsigned long i;
- unsigned long j;
- unsigned long temp;
- unsigned char num_row_addr;
- unsigned char num_col_addr;
- unsigned char num_banks;
- unsigned char bank_size_id;
- unsigned long ctrl_bank_num[MAXBANKS];
- unsigned long bx_cr_num;
- unsigned long largest_size_index;
- unsigned long largest_size;
- unsigned long current_size_index;
- BANKPARMS bank_parms[MAXBXCR];
- unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
- unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
-
- /*
- * Set the BxCR regs. First, wipe out the bank config registers.
- */
- for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
- mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2));
- mtdcr(SDRAM0_CFGDATA, 0x00000000);
- bank_parms[bx_cr_num].bank_size_bytes = 0;
- }
-
-#ifdef CONFIG_BAMBOO
- /*
- * This next section is hardware dependent and must be programmed
- * to match the hardware. For bamboo, the following holds...
- * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
- * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
- * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
- * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
- * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
- */
- ctrl_bank_num[0] = 0;
- ctrl_bank_num[1] = 1;
- ctrl_bank_num[2] = 3;
-#else
- /*
- * Ocotea, Ebony and the other IBM/AMCC eval boards have
- * 2 DIMM slots with each max 2 banks
- */
- ctrl_bank_num[0] = 0;
- ctrl_bank_num[1] = 2;
-#endif
-
- /*
- * reset the bank_base address
- */
- bank_base_addr = CONFIG_SYS_SDRAM_BASE;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == true) {
- num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
- num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
- num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
- bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
- debug("DIMM%ld: row=%d col=%d banks=%d\n", dimm_num,
- num_row_addr, num_col_addr, num_banks);
-
- /*
- * Set the SDRAM0_BxCR regs
- */
- cr = 0;
- switch (bank_size_id) {
- case 0x02:
- cr |= SDRAM_BXCR_SDSZ_8;
- break;
- case 0x04:
- cr |= SDRAM_BXCR_SDSZ_16;
- break;
- case 0x08:
- cr |= SDRAM_BXCR_SDSZ_32;
- break;
- case 0x10:
- cr |= SDRAM_BXCR_SDSZ_64;
- break;
- case 0x20:
- cr |= SDRAM_BXCR_SDSZ_128;
- break;
- case 0x40:
- cr |= SDRAM_BXCR_SDSZ_256;
- break;
- case 0x80:
- cr |= SDRAM_BXCR_SDSZ_512;
- break;
- default:
- printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
- dimm_num);
- printf("ERROR: Unsupported value for the banksize: %d.\n",
- bank_size_id);
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- }
-
- switch (num_col_addr) {
- case 0x08:
- cr |= SDRAM_BXCR_SDAM_1;
- break;
- case 0x09:
- cr |= SDRAM_BXCR_SDAM_2;
- break;
- case 0x0A:
- cr |= SDRAM_BXCR_SDAM_3;
- break;
- case 0x0B:
- cr |= SDRAM_BXCR_SDAM_4;
- break;
- default:
- printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
- dimm_num);
- printf("ERROR: Unsupported value for number of "
- "column addresses: %d.\n", num_col_addr);
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- }
-
- /*
- * enable the bank
- */
- cr |= SDRAM_BXCR_SDBE;
-
- for (i = 0; i < num_banks; i++) {
- bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
- (4 << 20) * bank_size_id;
- bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
- debug("DIMM%ld-bank %ld (SDRAM0_B%ldCR): "
- "bank_size_bytes=%ld\n",
- dimm_num, i,
- ctrl_bank_num[dimm_num] + i,
- bank_parms[ctrl_bank_num[dimm_num] + i].bank_size_bytes);
- }
- }
- }
-
- /* Initialize sort tables */
- for (i = 0; i < MAXBXCR; i++) {
- sorted_bank_num[i] = i;
- sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
- }
-
- for (i = 0; i < MAXBXCR-1; i++) {
- largest_size = sorted_bank_size[i];
- largest_size_index = 255;
-
- /* Find the largest remaining value */
- for (j = i + 1; j < MAXBXCR; j++) {
- if (sorted_bank_size[j] > largest_size) {
- /* Save largest remaining value and its index */
- largest_size = sorted_bank_size[j];
- largest_size_index = j;
- }
- }
-
- if (largest_size_index != 255) {
- /* Swap the current and largest values */
- current_size_index = sorted_bank_num[largest_size_index];
- sorted_bank_size[largest_size_index] = sorted_bank_size[i];
- sorted_bank_size[i] = largest_size;
- sorted_bank_num[largest_size_index] = sorted_bank_num[i];
- sorted_bank_num[i] = current_size_index;
- }
- }
-
- /* Set the SDRAM0_BxCR regs thanks to sort tables */
- for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
- if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
- mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2));
- temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
- SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
- temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
- bank_parms[sorted_bank_num[bx_cr_num]].cr;
- mtdcr(SDRAM0_CFGDATA, temp);
- bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
- debug("SDRAM0_B%ldCR=0x%08lx\n",
- sorted_bank_num[bx_cr_num], temp);
- }
- }
-
- return(bank_base_addr);
-}
-#endif /* CONFIG_SPD_EEPROM */
+++ /dev/null
-/*
- * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
- * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
- * DDR2 controller (non Denali Core). Those currently are:
- *
- * 405: 405EX(r)
- * 440/460: 440SP/440SPe/460EX/460GT
- *
- * Copyright (c) 2008 Nuovation System Designs, LLC
- * Grant Erickson <gerickson@nuovations.com>
-
- * (C) Copyright 2007-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * COPYRIGHT AMCC CORPORATION 2004
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc4xx.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-
-#include "ecc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
- do { \
- u32 data; \
- mfsdram(SDRAM_##mnemonic, data); \
- printf("%20s[%02x] = 0x%08X\n", \
- "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
- } while (0)
-
-#define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \
- do { \
- u32 data; \
- data = mfdcr(SDRAM_##mnemonic); \
- printf("%20s[%02x] = 0x%08X\n", \
- "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
- } while (0)
-
-static void update_rdcc(void)
-{
- u32 val;
-
- /*
- * Complete RDSS configuration as mentioned on page 7 of the AMCC
- * PowerPC440SP/SPe DDR2 application note:
- * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
- *
- * Or item #10 "10. Complete RDSS configuration" in chapter
- * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
- * manual.
- */
- mfsdram(SDRAM_RTSR, val);
- if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
- mfsdram(SDRAM_RDCC, val);
- if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
- val += 0x40000000;
- mtsdram(SDRAM_RDCC, val);
- }
- }
-}
-
-#if defined(CONFIG_440)
-/*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
- * memory region. Right now the cache should still be disabled in U-Boot
- * because of the EMAC driver, that need its buffer descriptor to be located
- * in non cached memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#ifdef CONFIG_4xx_DCACHE
-/* enable caching on SDRAM */
-#define MY_TLB_WORD2_I_ENABLE 0
-#else
-/* disable caching on SDRAM */
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
-#endif /* CONFIG_4xx_DCACHE */
-
-void dcbz_area(u32 start_address, u32 num_bytes);
-#endif /* CONFIG_440 */
-
-#define MAXRANKS 4
-#define MAXBXCF 4
-
-#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
-
-/*-----------------------------------------------------------------------------+
- * sdram_memsize
- *-----------------------------------------------------------------------------*/
-phys_size_t sdram_memsize(void)
-{
- phys_size_t mem_size;
- unsigned long mcopt2;
- unsigned long mcstat;
- unsigned long mb0cf;
- unsigned long sdsz;
- unsigned long i;
-
- mem_size = 0;
-
- mfsdram(SDRAM_MCOPT2, mcopt2);
- mfsdram(SDRAM_MCSTAT, mcstat);
-
- /* DDR controller must be enabled and not in self-refresh. */
- /* Otherwise memsize is zero. */
- if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
- && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
- && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
- == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
- for (i = 0; i < MAXBXCF; i++) {
- mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
- /* Banks enabled */
- if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
-#if defined(CONFIG_440)
- sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
-#else
- sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
-#endif
- switch(sdsz) {
- case SDRAM_RXBAS_SDSZ_8:
- mem_size+=8;
- break;
- case SDRAM_RXBAS_SDSZ_16:
- mem_size+=16;
- break;
- case SDRAM_RXBAS_SDSZ_32:
- mem_size+=32;
- break;
- case SDRAM_RXBAS_SDSZ_64:
- mem_size+=64;
- break;
- case SDRAM_RXBAS_SDSZ_128:
- mem_size+=128;
- break;
- case SDRAM_RXBAS_SDSZ_256:
- mem_size+=256;
- break;
- case SDRAM_RXBAS_SDSZ_512:
- mem_size+=512;
- break;
- case SDRAM_RXBAS_SDSZ_1024:
- mem_size+=1024;
- break;
- case SDRAM_RXBAS_SDSZ_2048:
- mem_size+=2048;
- break;
- case SDRAM_RXBAS_SDSZ_4096:
- mem_size+=4096;
- break;
- default:
- printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
- , sdsz);
- mem_size=0;
- break;
- }
- }
- }
- }
-
- return mem_size << 20;
-}
-
-/*-----------------------------------------------------------------------------+
- * is_ecc_enabled
- *-----------------------------------------------------------------------------*/
-static unsigned long is_ecc_enabled(void)
-{
- unsigned long val;
-
- mfsdram(SDRAM_MCOPT1, val);
-
- return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
-}
-
-/*-----------------------------------------------------------------------------+
- * board_add_ram_info
- *-----------------------------------------------------------------------------*/
-void board_add_ram_info(int use_default)
-{
- PPC4xx_SYS_INFO board_cfg;
- u32 val;
-
- if (is_ecc_enabled())
- puts(" (ECC");
- else
- puts(" (ECC not");
-
- get_sys_info(&board_cfg);
-
-#if defined(CONFIG_405EX)
- val = board_cfg.freqPLB;
-#else
- mfsdr(SDR0_DDR0, val);
- val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
-#endif
- printf(" enabled, %d MHz", (val * 2) / 1000000);
-
- mfsdram(SDRAM_MMODE, val);
- val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
- printf(", CL%d)", val);
-}
-
-#if defined(CONFIG_SPD_EEPROM)
-
-/*-----------------------------------------------------------------------------+
- * Defines
- *-----------------------------------------------------------------------------*/
-#define SDRAM_DDR1 1
-#define SDRAM_DDR2 2
-#define SDRAM_NONE 0
-
-#define MAXDIMMS 2
-#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
-
-#define ONE_BILLION 1000000000
-
-#define CMD_NOP (7 << 19)
-#define CMD_PRECHARGE (2 << 19)
-#define CMD_REFRESH (1 << 19)
-#define CMD_EMR (0 << 19)
-#define CMD_READ (5 << 19)
-#define CMD_WRITE (4 << 19)
-
-#define SELECT_MR (0 << 16)
-#define SELECT_EMR (1 << 16)
-#define SELECT_EMR2 (2 << 16)
-#define SELECT_EMR3 (3 << 16)
-
-/* MR */
-#define DLL_RESET 0x00000100
-
-#define WRITE_RECOV_2 (1 << 9)
-#define WRITE_RECOV_3 (2 << 9)
-#define WRITE_RECOV_4 (3 << 9)
-#define WRITE_RECOV_5 (4 << 9)
-#define WRITE_RECOV_6 (5 << 9)
-
-#define BURST_LEN_4 0x00000002
-
-/* EMR */
-#define ODT_0_OHM 0x00000000
-#define ODT_50_OHM 0x00000044
-#define ODT_75_OHM 0x00000004
-#define ODT_150_OHM 0x00000040
-
-#define ODS_FULL 0x00000000
-#define ODS_REDUCED 0x00000002
-#define OCD_CALIB_DEF 0x00000380
-
-/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
-#define ODT_EB0R (0x80000000 >> 8)
-#define ODT_EB0W (0x80000000 >> 7)
-#define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
-#define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
-#define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
-
-/* Defines for the Read Cycle Delay test */
-#define NUMMEMTESTS 8
-#define NUMMEMWORDS 8
-#define NUMLOOPS 64 /* memory test loops */
-
-/*
- * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
- * To support such configurations, we "only" map the first 2GB via the TLB's. We
- * need some free virtual address space for the remaining peripherals like, SoC
- * devices, FLASH etc.
- *
- * Note that ECC is currently not supported on configurations with more than 2GB
- * SDRAM. This is because we only map the first 2GB on such systems, and therefore
- * the ECC parity byte of the remaining area can't be written.
- */
-
-/*
- * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
- */
-void __spd_ddr_init_hang (void)
-{
- hang ();
-}
-void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
-
-/*
- * To provide an interface for board specific config values in this common
- * DDR setup code, we implement he "weak" default functions here. They return
- * the default value back to the caller.
- *
- * Please see include/configs/yucca.h for an example fora board specific
- * implementation.
- */
-u32 __ddr_wrdtr(u32 default_val)
-{
- return default_val;
-}
-u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
-
-u32 __ddr_clktr(u32 default_val)
-{
- return default_val;
-}
-u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
-
-
-/* Private Structure Definitions */
-
-/* enum only to ease code for cas latency setting */
-typedef enum ddr_cas_id {
- DDR_CAS_2 = 20,
- DDR_CAS_2_5 = 25,
- DDR_CAS_3 = 30,
- DDR_CAS_4 = 40,
- DDR_CAS_5 = 50
-} ddr_cas_id_t;
-
-/*-----------------------------------------------------------------------------+
- * Prototypes
- *-----------------------------------------------------------------------------*/
-static void get_spd_info(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void check_mem_type(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void check_frequency(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void check_rank_number(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void check_voltage_type(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_memory_queue(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_codt(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_mode(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks,
- ddr_cas_id_t *selected_cas,
- int *write_recovery);
-static void program_tr(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_rtr(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_bxcf(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_copt1(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-static void program_initplr(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks,
- ddr_cas_id_t selected_cas,
- int write_recovery);
-#ifdef CONFIG_DDR_ECC
-static void program_ecc(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks,
- unsigned long tlb_word2_i_value);
-#endif
-#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-static void program_DQS_calibration(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
-#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
-static void test(void);
-#else
-static void DQS_calibration_process(void);
-#endif
-#endif
-
-static unsigned char spd_read(uchar chip, uint addr)
-{
- unsigned char data[2];
-
- if (i2c_probe(chip) == 0)
- if (i2c_read(chip, addr, 1, data, 1) == 0)
- return data[0];
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------------+
- * dram_init. Initializes the 440SP Memory Queue and DDR SDRAM controller.
- * Note: This routine runs from flash with a stack set up in the chip's
- * sram space. It is important that the routine does not require .sbss, .bss or
- * .data sections. It also cannot call routines that require these sections.
- *-----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------
- * Function: dram_init
- * Description: Configures SDRAM memory banks for DDR operation.
- * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
- * via the IIC bus and then configures the DDR SDRAM memory
- * banks appropriately. If Auto Memory Configuration is
- * not used, it is assumed that no DIMM is plugged
- *-----------------------------------------------------------------------------*/
-int dram_init(void)
-{
- unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
- unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
- unsigned long num_dimm_banks; /* on board dimm banks */
- unsigned long val;
- ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
- int write_recovery;
- phys_size_t dram_size = 0;
-
- if (IS_ENABLED(CONFIG_SYS_RAMBOOT)) {
- /*
- * Reduce RAM size to avoid overwriting memory used by
- * current stack? Not sure what is happening.
- */
- gd->ram_size = sdram_memsize() / 2;
-
- return 0;
- }
-
- num_dimm_banks = sizeof(iic0_dimm_addr);
-
- /*------------------------------------------------------------------
- * Reset the DDR-SDRAM controller.
- *-----------------------------------------------------------------*/
- mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
- mtsdr(SDR0_SRST, 0x00000000);
-
- /*
- * Make sure I2C controller is initialized
- * before continuing.
- */
-
- /* switch to correct I2C bus */
- i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
-
- /*------------------------------------------------------------------
- * Clear out the serial presence detect buffers.
- * Perform IIC reads from the dimm. Fill in the spds.
- * Check to see if the dimm slots are populated
- *-----------------------------------------------------------------*/
- get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Check the memory type for the dimms plugged.
- *-----------------------------------------------------------------*/
- check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Check the frequency supported for the dimms plugged.
- *-----------------------------------------------------------------*/
- check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Check the total rank number.
- *-----------------------------------------------------------------*/
- check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Check the voltage type for the dimms plugged.
- *-----------------------------------------------------------------*/
- check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Program SDRAM controller options 2 register
- * Except Enabling of the memory controller.
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_MCOPT2, val);
- mtsdram(SDRAM_MCOPT2,
- (val &
- ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
- SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
- SDRAM_MCOPT2_ISIE_MASK))
- | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
- SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
- SDRAM_MCOPT2_ISIE_ENABLE));
-
- /*------------------------------------------------------------------
- * Program SDRAM controller options 1 register
- * Note: Does not enable the memory controller.
- *-----------------------------------------------------------------*/
- program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Set the SDRAM Controller On Die Termination Register
- *-----------------------------------------------------------------*/
- program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Program SDRAM refresh register.
- *-----------------------------------------------------------------*/
- program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Program SDRAM mode register.
- *-----------------------------------------------------------------*/
- program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
- &selected_cas, &write_recovery);
-
- /*------------------------------------------------------------------
- * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_WRDTR, val);
- mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
- ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
-
- /*------------------------------------------------------------------
- * Set the SDRAM Clock Timing Register
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_CLKTR, val);
- mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
- ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
-
- /*------------------------------------------------------------------
- * Program the BxCF registers.
- *-----------------------------------------------------------------*/
- program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Program SDRAM timing registers.
- *-----------------------------------------------------------------*/
- program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Set the Extended Mode register
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_MEMODE, val);
- mtsdram(SDRAM_MEMODE,
- (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
- SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
- (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
- | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
-
- /*------------------------------------------------------------------
- * Program Initialization preload registers.
- *-----------------------------------------------------------------*/
- program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
- selected_cas, write_recovery);
-
- /*------------------------------------------------------------------
- * Delay to ensure 200usec have elapsed since reset.
- *-----------------------------------------------------------------*/
- udelay(400);
-
- /*------------------------------------------------------------------
- * Set the memory queue core base addr.
- *-----------------------------------------------------------------*/
- program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Program SDRAM controller options 2 register
- * Enable the memory controller.
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_MCOPT2, val);
- mtsdram(SDRAM_MCOPT2,
- (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
- SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
- SDRAM_MCOPT2_IPTR_EXECUTE);
-
- /*------------------------------------------------------------------
- * Wait for IPTR_EXECUTE init sequence to complete.
- *-----------------------------------------------------------------*/
- do {
- mfsdram(SDRAM_MCSTAT, val);
- } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
-
- /* enable the controller only after init sequence completes */
- mfsdram(SDRAM_MCOPT2, val);
- mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
-
- /* Make sure delay-line calibration is done before proceeding */
- do {
- mfsdram(SDRAM_DLCR, val);
- } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
-
- /* get installed memory size */
- dram_size = sdram_memsize();
-
- /*
- * Limit size to 2GB
- */
- if (dram_size > CONFIG_MAX_MEM_MAPPED)
- dram_size = CONFIG_MAX_MEM_MAPPED;
-
- /* and program tlb entries for this size (dynamic) */
-
- /*
- * Program TLB entries with caches enabled, for best performace
- * while auto-calibrating and ECC generation
- */
- program_tlb(0, 0, dram_size, 0);
-
- /*------------------------------------------------------------------
- * DQS calibration.
- *-----------------------------------------------------------------*/
-#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
- DQS_autocalibration();
-#else
- program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-#endif
- /*
- * Now complete RDSS configuration as mentioned on page 7 of the AMCC
- * PowerPC440SP/SPe DDR2 application note:
- * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
- */
- update_rdcc();
-
-#ifdef CONFIG_DDR_ECC
- /*------------------------------------------------------------------
- * If ecc is enabled, initialize the parity bits.
- *-----------------------------------------------------------------*/
- program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
-#endif
-
- /*
- * Flush the dcache before removing the TLB with caches
- * enabled. Otherwise this might lead to problems later on,
- * e.g. while booting Linux (as seen on ICON-440SPe).
- */
- flush_dcache();
-
- /*
- * Now after initialization (auto-calibration and ECC generation)
- * remove the TLB entries with caches enabled and program again with
- * desired cache functionality
- */
- remove_tlb(0, dram_size);
- program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
-
- ppc4xx_ibm_ddr2_register_dump();
-
- /*
- * Clear potential errors resulting from auto-calibration.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- gd->ram_size = sdram_memsize();
-
- return 0;
-}
-
-static void get_spd_info(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long dimm_found;
- unsigned char num_of_bytes;
- unsigned char total_size;
-
- dimm_found = false;
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- num_of_bytes = 0;
- total_size = 0;
-
- num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
- debug("\nspd_read(0x%x) returned %d\n",
- iic0_dimm_addr[dimm_num], num_of_bytes);
- total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
- debug("spd_read(0x%x) returned %d\n",
- iic0_dimm_addr[dimm_num], total_size);
-
- if ((num_of_bytes != 0) && (total_size != 0)) {
- dimm_populated[dimm_num] = true;
- dimm_found = true;
- debug("DIMM slot %lu: populated\n", dimm_num);
- } else {
- dimm_populated[dimm_num] = false;
- debug("DIMM slot %lu: Not populated\n", dimm_num);
- }
- }
-
- if (dimm_found == false) {
- printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
- spd_ddr_init_hang ();
- }
-}
-
-
-/*------------------------------------------------------------------
- * For the memory DIMMs installed, this routine verifies that they
- * really are DDR specific DIMMs.
- *-----------------------------------------------------------------*/
-static void check_mem_type(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long dimm_type;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == true) {
- dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
- switch (dimm_type) {
- case 1:
- printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
- "slot %d.\n", (unsigned int)dimm_num);
- printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- break;
- case 2:
- printf("ERROR: EDO DIMM detected in slot %d.\n",
- (unsigned int)dimm_num);
- printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- break;
- case 3:
- printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
- (unsigned int)dimm_num);
- printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- break;
- case 4:
- printf("ERROR: SDRAM DIMM detected in slot %d.\n",
- (unsigned int)dimm_num);
- printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- break;
- case 5:
- printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
- (unsigned int)dimm_num);
- printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- break;
- case 6:
- printf("ERROR: SGRAM DIMM detected in slot %d.\n",
- (unsigned int)dimm_num);
- printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- break;
- case 7:
- debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
- dimm_populated[dimm_num] = SDRAM_DDR1;
- break;
- case 8:
- debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
- dimm_populated[dimm_num] = SDRAM_DDR2;
- break;
- default:
- printf("ERROR: Unknown DIMM detected in slot %d.\n",
- (unsigned int)dimm_num);
- printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- break;
- }
- }
- }
- for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
- if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
- && (dimm_populated[dimm_num] != SDRAM_NONE)
- && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
- printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
- spd_ddr_init_hang ();
- }
- }
-}
-
-/*------------------------------------------------------------------
- * For the memory DIMMs installed, this routine verifies that
- * frequency previously calculated is supported.
- *-----------------------------------------------------------------*/
-static void check_frequency(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long tcyc_reg;
- unsigned long cycle_time;
- unsigned long calc_cycle_time;
- unsigned long sdram_freq;
- unsigned long sdr_ddrpll;
- PPC4xx_SYS_INFO board_cfg;
-
- /*------------------------------------------------------------------
- * Get the board configuration info.
- *-----------------------------------------------------------------*/
- get_sys_info(&board_cfg);
-
- mfsdr(SDR0_DDR0, sdr_ddrpll);
- sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
-
- /*
- * calc_cycle_time is calculated from DDR frequency set by board/chip
- * and is expressed in multiple of 10 picoseconds
- * to match the way DIMM cycle time is calculated below.
- */
- calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
- /*
- * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
- * the higher order nibble (bits 4-7) designates the cycle time
- * to a granularity of 1ns;
- * the value presented by the lower order nibble (bits 0-3)
- * has a granularity of .1ns and is added to the value designated
- * by the higher nibble. In addition, four lines of the lower order
- * nibble are assigned to support +.25,+.33, +.66 and +.75.
- */
- /* Convert from hex to decimal */
- if ((tcyc_reg & 0x0F) == 0x0D)
- cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
- else if ((tcyc_reg & 0x0F) == 0x0C)
- cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
- else if ((tcyc_reg & 0x0F) == 0x0B)
- cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
- else if ((tcyc_reg & 0x0F) == 0x0A)
- cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
- else
- cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
- ((tcyc_reg & 0x0F)*10);
- debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
-
- if (cycle_time > (calc_cycle_time + 10)) {
- /*
- * the provided sdram cycle_time is too small
- * for the available DIMM cycle_time.
- * The additionnal 100ps is here to accept a small incertainty.
- */
- printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
- "slot %d \n while calculated cycle time is %d ps.\n",
- (unsigned int)(cycle_time*10),
- (unsigned int)dimm_num,
- (unsigned int)(calc_cycle_time*10));
- printf("Replace the DIMM, or change DDR frequency via "
- "strapping bits.\n\n");
- spd_ddr_init_hang ();
- }
- }
- }
-}
-
-/*------------------------------------------------------------------
- * For the memory DIMMs installed, this routine verifies two
- * ranks/banks maximum are availables.
- *-----------------------------------------------------------------*/
-static void check_rank_number(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long dimm_rank;
- unsigned long total_rank = 0;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
- dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
- if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
- dimm_rank = (dimm_rank & 0x0F) +1;
- else
- dimm_rank = dimm_rank & 0x0F;
-
-
- if (dimm_rank > MAXRANKS) {
- printf("ERROR: DRAM DIMM detected with %lu ranks in "
- "slot %lu is not supported.\n", dimm_rank, dimm_num);
- printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- } else
- total_rank += dimm_rank;
- }
- if (total_rank > MAXRANKS) {
- printf("ERROR: DRAM DIMM detected with a total of %d ranks "
- "for all slots.\n", (unsigned int)total_rank);
- printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
- printf("Remove one of the DIMM modules.\n\n");
- spd_ddr_init_hang ();
- }
- }
-}
-
-/*------------------------------------------------------------------
- * only support 2.5V modules.
- * This routine verifies this.
- *-----------------------------------------------------------------*/
-static void check_voltage_type(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long voltage_type;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
- voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
- switch (voltage_type) {
- case 0x00:
- printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
- printf("This DIMM is 5.0 Volt/TTL.\n");
- printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
- (unsigned int)dimm_num);
- spd_ddr_init_hang ();
- break;
- case 0x01:
- printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
- printf("This DIMM is LVTTL.\n");
- printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
- (unsigned int)dimm_num);
- spd_ddr_init_hang ();
- break;
- case 0x02:
- printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
- printf("This DIMM is 1.5 Volt.\n");
- printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
- (unsigned int)dimm_num);
- spd_ddr_init_hang ();
- break;
- case 0x03:
- printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
- printf("This DIMM is 3.3 Volt/TTL.\n");
- printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
- (unsigned int)dimm_num);
- spd_ddr_init_hang ();
- break;
- case 0x04:
- /* 2.5 Voltage only for DDR1 */
- break;
- case 0x05:
- /* 1.8 Voltage only for DDR2 */
- break;
- default:
- printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
- printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
- (unsigned int)dimm_num);
- spd_ddr_init_hang ();
- break;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------------+
- * program_copt1.
- *-----------------------------------------------------------------------------*/
-static void program_copt1(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long mcopt1;
- unsigned long ecc_enabled;
- unsigned long ecc = 0;
- unsigned long data_width = 0;
- unsigned long dimm_32bit;
- unsigned long dimm_64bit;
- unsigned long registered = 0;
- unsigned long attribute = 0;
- unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
- unsigned long bankcount;
- unsigned long val;
-
-#ifdef CONFIG_DDR_ECC
- ecc_enabled = true;
-#else
- ecc_enabled = false;
-#endif
- dimm_32bit = false;
- dimm_64bit = false;
- buf0 = false;
- buf1 = false;
-
- /*------------------------------------------------------------------
- * Set memory controller options reg 1, SDRAM_MCOPT1.
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_MCOPT1, val);
- mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
- SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
- SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
- SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
- SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
- SDRAM_MCOPT1_DREF_MASK);
-
- mcopt1 |= SDRAM_MCOPT1_QDEP;
- mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
- mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
- mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
- mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
- mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
- /* test ecc support */
- ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
- if (ecc != 0x02) /* ecc not supported */
- ecc_enabled = false;
-
- /* test bank count */
- bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
- if (bankcount == 0x04) /* bank count = 4 */
- mcopt1 |= SDRAM_MCOPT1_4_BANKS;
- else /* bank count = 8 */
- mcopt1 |= SDRAM_MCOPT1_8_BANKS;
-
- /* test for buffered/unbuffered, registered, differential clocks */
- registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
- attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
-
- /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
- if (dimm_num == 0) {
- if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
- mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
- if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
- mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
- if (registered == 1) { /* DDR2 always buffered */
- /* TODO: what about above comments ? */
- mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf0 = true;
- } else {
- /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
- if ((attribute & 0x02) == 0x00) {
- /* buffered not supported */
- buf0 = false;
- } else {
- mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf0 = true;
- }
- }
- }
- else if (dimm_num == 1) {
- if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
- mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
- if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
- mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
- if (registered == 1) {
- /* DDR2 always buffered */
- mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf1 = true;
- } else {
- if ((attribute & 0x02) == 0x00) {
- /* buffered not supported */
- buf1 = false;
- } else {
- mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf1 = true;
- }
- }
- }
-
- /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
- data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
- (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
-
- switch (data_width) {
- case 72:
- case 64:
- dimm_64bit = true;
- break;
- case 40:
- case 32:
- dimm_32bit = true;
- break;
- default:
- printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
- data_width);
- printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
- break;
- }
- }
- }
-
- /* verify matching properties */
- if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
- if (buf0 != buf1) {
- printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
- spd_ddr_init_hang ();
- }
- }
-
- if ((dimm_64bit == true) && (dimm_32bit == true)) {
- printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
- spd_ddr_init_hang ();
- } else if ((dimm_64bit == true) && (dimm_32bit == false)) {
- mcopt1 |= SDRAM_MCOPT1_DMWD_64;
- } else if ((dimm_64bit == false) && (dimm_32bit == true)) {
- mcopt1 |= SDRAM_MCOPT1_DMWD_32;
- } else {
- printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
- spd_ddr_init_hang ();
- }
-
- if (ecc_enabled == true)
- mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
- else
- mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
-
- mtsdram(SDRAM_MCOPT1, mcopt1);
-}
-
-/*-----------------------------------------------------------------------------+
- * program_codt.
- *-----------------------------------------------------------------------------*/
-static void program_codt(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long codt;
- unsigned long modt0 = 0;
- unsigned long modt1 = 0;
- unsigned long modt2 = 0;
- unsigned long modt3 = 0;
- unsigned char dimm_num;
- unsigned char dimm_rank;
- unsigned char total_rank = 0;
- unsigned char total_dimm = 0;
- unsigned char dimm_type = 0;
- unsigned char firstSlot = 0;
-
- /*------------------------------------------------------------------
- * Set the SDRAM Controller On Die Termination Register
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_CODT, codt);
- codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
- codt |= SDRAM_CODT_IO_NMODE;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
- dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
- if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
- dimm_rank = (dimm_rank & 0x0F) + 1;
- dimm_type = SDRAM_DDR2;
- } else {
- dimm_rank = dimm_rank & 0x0F;
- dimm_type = SDRAM_DDR1;
- }
-
- total_rank += dimm_rank;
- total_dimm++;
- if ((dimm_num == 0) && (total_dimm == 1))
- firstSlot = true;
- else
- firstSlot = false;
- }
- }
- if (dimm_type == SDRAM_DDR2) {
- codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
- if ((total_dimm == 1) && (firstSlot == true)) {
- if (total_rank == 1) { /* PUUU */
- codt |= CALC_ODT_R(0);
- modt0 = CALC_ODT_W(0);
- modt1 = 0x00000000;
- modt2 = 0x00000000;
- modt3 = 0x00000000;
- }
- if (total_rank == 2) { /* PPUU */
- codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
- modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
- modt1 = 0x00000000;
- modt2 = 0x00000000;
- modt3 = 0x00000000;
- }
- } else if ((total_dimm == 1) && (firstSlot != true)) {
- if (total_rank == 1) { /* UUPU */
- codt |= CALC_ODT_R(2);
- modt0 = 0x00000000;
- modt1 = 0x00000000;
- modt2 = CALC_ODT_W(2);
- modt3 = 0x00000000;
- }
- if (total_rank == 2) { /* UUPP */
- codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
- modt0 = 0x00000000;
- modt1 = 0x00000000;
- modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
- modt3 = 0x00000000;
- }
- }
- if (total_dimm == 2) {
- if (total_rank == 2) { /* PUPU */
- codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
- modt0 = CALC_ODT_RW(2);
- modt1 = 0x00000000;
- modt2 = CALC_ODT_RW(0);
- modt3 = 0x00000000;
- }
- if (total_rank == 4) { /* PPPP */
- codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
- CALC_ODT_R(2) | CALC_ODT_R(3);
- modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
- modt1 = 0x00000000;
- modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
- modt3 = 0x00000000;
- }
- }
- } else {
- codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
- modt0 = 0x00000000;
- modt1 = 0x00000000;
- modt2 = 0x00000000;
- modt3 = 0x00000000;
-
- if (total_dimm == 1) {
- if (total_rank == 1)
- codt |= 0x00800000;
- if (total_rank == 2)
- codt |= 0x02800000;
- }
- if (total_dimm == 2) {
- if (total_rank == 2)
- codt |= 0x08800000;
- if (total_rank == 4)
- codt |= 0x2a800000;
- }
- }
-
- debug("nb of dimm %d\n", total_dimm);
- debug("nb of rank %d\n", total_rank);
- if (total_dimm == 1)
- debug("dimm in slot %d\n", firstSlot);
-
- mtsdram(SDRAM_CODT, codt);
- mtsdram(SDRAM_MODT0, modt0);
- mtsdram(SDRAM_MODT1, modt1);
- mtsdram(SDRAM_MODT2, modt2);
- mtsdram(SDRAM_MODT3, modt3);
-}
-
-/*-----------------------------------------------------------------------------+
- * program_initplr.
- *-----------------------------------------------------------------------------*/
-static void program_initplr(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks,
- ddr_cas_id_t selected_cas,
- int write_recovery)
-{
- u32 cas = 0;
- u32 odt = 0;
- u32 ods = 0;
- u32 mr;
- u32 wr;
- u32 emr;
- u32 emr2;
- u32 emr3;
- int dimm_num;
- int total_dimm = 0;
-
- /******************************************************
- ** Assumption: if more than one DIMM, all DIMMs are the same
- ** as already checked in check_memory_type
- ******************************************************/
-
- if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
- mtsdram(SDRAM_INITPLR0, 0x81B80000);
- mtsdram(SDRAM_INITPLR1, 0x81900400);
- mtsdram(SDRAM_INITPLR2, 0x81810000);
- mtsdram(SDRAM_INITPLR3, 0xff800162);
- mtsdram(SDRAM_INITPLR4, 0x81900400);
- mtsdram(SDRAM_INITPLR5, 0x86080000);
- mtsdram(SDRAM_INITPLR6, 0x86080000);
- mtsdram(SDRAM_INITPLR7, 0x81000062);
- } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
- switch (selected_cas) {
- case DDR_CAS_3:
- cas = 3 << 4;
- break;
- case DDR_CAS_4:
- cas = 4 << 4;
- break;
- case DDR_CAS_5:
- cas = 5 << 4;
- break;
- default:
- printf("ERROR: ucode error on selected_cas value %d", selected_cas);
- spd_ddr_init_hang ();
- break;
- }
-
-#if 0
- /*
- * ToDo - Still a problem with the write recovery:
- * On the Corsair CM2X512-5400C4 module, setting write recovery
- * in the INITPLR reg to the value calculated in program_mode()
- * results in not correctly working DDR2 memory (crash after
- * relocation).
- *
- * So for now, set the write recovery to 3. This seems to work
- * on the Corair module too.
- *
- * 2007-03-01, sr
- */
- switch (write_recovery) {
- case 3:
- wr = WRITE_RECOV_3;
- break;
- case 4:
- wr = WRITE_RECOV_4;
- break;
- case 5:
- wr = WRITE_RECOV_5;
- break;
- case 6:
- wr = WRITE_RECOV_6;
- break;
- default:
- printf("ERROR: write recovery not support (%d)", write_recovery);
- spd_ddr_init_hang ();
- break;
- }
-#else
- wr = WRITE_RECOV_3; /* test-only, see description above */
-#endif
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
- if (dimm_populated[dimm_num] != SDRAM_NONE)
- total_dimm++;
- if (total_dimm == 1) {
- odt = ODT_150_OHM;
- ods = ODS_FULL;
- } else if (total_dimm == 2) {
- odt = ODT_75_OHM;
- ods = ODS_REDUCED;
- } else {
- printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
- spd_ddr_init_hang ();
- }
-
- mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
- emr = CMD_EMR | SELECT_EMR | odt | ods;
- emr2 = CMD_EMR | SELECT_EMR2;
- emr3 = CMD_EMR | SELECT_EMR3;
- /* NOP - Wait 106 MemClk cycles */
- mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
- SDRAM_INITPLR_IMWT_ENCODE(106));
- udelay(1000);
- /* precharge 4 MemClk cycles */
- mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
- SDRAM_INITPLR_IMWT_ENCODE(4));
- /* EMR2 - Wait tMRD (2 MemClk cycles) */
- mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
- SDRAM_INITPLR_IMWT_ENCODE(2));
- /* EMR3 - Wait tMRD (2 MemClk cycles) */
- mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
- SDRAM_INITPLR_IMWT_ENCODE(2));
- /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
- mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
- SDRAM_INITPLR_IMWT_ENCODE(2));
- /* MR w/ DLL reset - 200 cycle wait for DLL reset */
- mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
- SDRAM_INITPLR_IMWT_ENCODE(200));
- udelay(1000);
- /* precharge 4 MemClk cycles */
- mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
- SDRAM_INITPLR_IMWT_ENCODE(4));
- /* Refresh 25 MemClk cycles */
- mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
- SDRAM_INITPLR_IMWT_ENCODE(25));
- /* Refresh 25 MemClk cycles */
- mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
- SDRAM_INITPLR_IMWT_ENCODE(25));
- /* Refresh 25 MemClk cycles */
- mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
- SDRAM_INITPLR_IMWT_ENCODE(25));
- /* Refresh 25 MemClk cycles */
- mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
- SDRAM_INITPLR_IMWT_ENCODE(25));
- /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
- mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
- SDRAM_INITPLR_IMWT_ENCODE(2));
- /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
- mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
- SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
- /* EMR OCD Exit */
- mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
- SDRAM_INITPLR_IMWT_ENCODE(2));
- } else {
- printf("ERROR: ucode error as unknown DDR type in program_initplr");
- spd_ddr_init_hang ();
- }
-}
-
-/*------------------------------------------------------------------
- * This routine programs the SDRAM_MMODE register.
- * the selected_cas is an output parameter, that will be passed
- * by caller to call the above program_initplr( )
- *-----------------------------------------------------------------*/
-static void program_mode(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks,
- ddr_cas_id_t *selected_cas,
- int *write_recovery)
-{
- unsigned long dimm_num;
- unsigned long sdram_ddr1;
- unsigned long t_wr_ns;
- unsigned long t_wr_clk;
- unsigned long cas_bit;
- unsigned long cas_index;
- unsigned long sdram_freq;
- unsigned long ddr_check;
- unsigned long mmode;
- unsigned long tcyc_reg;
- unsigned long cycle_2_0_clk;
- unsigned long cycle_2_5_clk;
- unsigned long cycle_3_0_clk;
- unsigned long cycle_4_0_clk;
- unsigned long cycle_5_0_clk;
- unsigned long max_2_0_tcyc_ns_x_100;
- unsigned long max_2_5_tcyc_ns_x_100;
- unsigned long max_3_0_tcyc_ns_x_100;
- unsigned long max_4_0_tcyc_ns_x_100;
- unsigned long max_5_0_tcyc_ns_x_100;
- unsigned long cycle_time_ns_x_100[3];
- PPC4xx_SYS_INFO board_cfg;
- unsigned char cas_2_0_available;
- unsigned char cas_2_5_available;
- unsigned char cas_3_0_available;
- unsigned char cas_4_0_available;
- unsigned char cas_5_0_available;
- unsigned long sdr_ddrpll;
-
- /*------------------------------------------------------------------
- * Get the board configuration info.
- *-----------------------------------------------------------------*/
- get_sys_info(&board_cfg);
-
- mfsdr(SDR0_DDR0, sdr_ddrpll);
- sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
- debug("sdram_freq=%lu\n", sdram_freq);
-
- /*------------------------------------------------------------------
- * Handle the timing. We need to find the worst case timing of all
- * the dimm modules installed.
- *-----------------------------------------------------------------*/
- t_wr_ns = 0;
- cas_2_0_available = true;
- cas_2_5_available = true;
- cas_3_0_available = true;
- cas_4_0_available = true;
- cas_5_0_available = true;
- max_2_0_tcyc_ns_x_100 = 10;
- max_2_5_tcyc_ns_x_100 = 10;
- max_3_0_tcyc_ns_x_100 = 10;
- max_4_0_tcyc_ns_x_100 = 10;
- max_5_0_tcyc_ns_x_100 = 10;
- sdram_ddr1 = true;
-
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
- if (dimm_populated[dimm_num] == SDRAM_DDR1)
- sdram_ddr1 = true;
- else
- sdram_ddr1 = false;
-
- cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
- debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
-
- /* For a particular DIMM, grab the three CAS values it supports */
- for (cas_index = 0; cas_index < 3; cas_index++) {
- switch (cas_index) {
- case 0:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
- break;
- case 1:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
- break;
- default:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
- break;
- }
-
- if ((tcyc_reg & 0x0F) >= 10) {
- if ((tcyc_reg & 0x0F) == 0x0D) {
- /* Convert from hex to decimal */
- cycle_time_ns_x_100[cas_index] =
- (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
- } else {
- printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
- "in slot %d\n", (unsigned int)dimm_num);
- spd_ddr_init_hang ();
- }
- } else {
- /* Convert from hex to decimal */
- cycle_time_ns_x_100[cas_index] =
- (((tcyc_reg & 0xF0) >> 4) * 100) +
- ((tcyc_reg & 0x0F)*10);
- }
- debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
- cycle_time_ns_x_100[cas_index]);
- }
-
- /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
- /* supported for a particular DIMM. */
- cas_index = 0;
-
- if (sdram_ddr1) {
- /*
- * DDR devices use the following bitmask for CAS latency:
- * Bit 7 6 5 4 3 2 1 0
- * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
- */
- if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
- (cycle_time_ns_x_100[cas_index] != 0)) {
- max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
- cycle_time_ns_x_100[cas_index]);
- cas_index++;
- } else {
- if (cas_index != 0)
- cas_index++;
- cas_4_0_available = false;
- }
-
- if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
- (cycle_time_ns_x_100[cas_index] != 0)) {
- max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
- cycle_time_ns_x_100[cas_index]);
- cas_index++;
- } else {
- if (cas_index != 0)
- cas_index++;
- cas_3_0_available = false;
- }
-
- if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
- (cycle_time_ns_x_100[cas_index] != 0)) {
- max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
- cycle_time_ns_x_100[cas_index]);
- cas_index++;
- } else {
- if (cas_index != 0)
- cas_index++;
- cas_2_5_available = false;
- }
-
- if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
- (cycle_time_ns_x_100[cas_index] != 0)) {
- max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
- cycle_time_ns_x_100[cas_index]);
- cas_index++;
- } else {
- if (cas_index != 0)
- cas_index++;
- cas_2_0_available = false;
- }
- } else {
- /*
- * DDR2 devices use the following bitmask for CAS latency:
- * Bit 7 6 5 4 3 2 1 0
- * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
- */
- if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
- (cycle_time_ns_x_100[cas_index] != 0)) {
- max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
- cycle_time_ns_x_100[cas_index]);
- cas_index++;
- } else {
- if (cas_index != 0)
- cas_index++;
- cas_5_0_available = false;
- }
-
- if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
- (cycle_time_ns_x_100[cas_index] != 0)) {
- max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
- cycle_time_ns_x_100[cas_index]);
- cas_index++;
- } else {
- if (cas_index != 0)
- cas_index++;
- cas_4_0_available = false;
- }
-
- if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
- (cycle_time_ns_x_100[cas_index] != 0)) {
- max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
- cycle_time_ns_x_100[cas_index]);
- cas_index++;
- } else {
- if (cas_index != 0)
- cas_index++;
- cas_3_0_available = false;
- }
- }
- }
- }
-
- /*------------------------------------------------------------------
- * Set the SDRAM mode, SDRAM_MMODE
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_MMODE, mmode);
- mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
-
- /* add 10 here because of rounding problems */
- cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
- cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
- cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
- cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
- cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
- debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
- debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
- debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
-
- if (sdram_ddr1 == true) { /* DDR1 */
- if ((cas_2_0_available == true) &&
- (sdram_freq <= cycle_2_0_clk)) {
- mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
- *selected_cas = DDR_CAS_2;
- } else if ((cas_2_5_available == true) &&
- (sdram_freq <= cycle_2_5_clk)) {
- mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
- *selected_cas = DDR_CAS_2_5;
- } else if ((cas_3_0_available == true) &&
- (sdram_freq <= cycle_3_0_clk)) {
- mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
- *selected_cas = DDR_CAS_3;
- } else {
- printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
- printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
- printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
- spd_ddr_init_hang ();
- }
- } else { /* DDR2 */
- debug("cas_3_0_available=%d\n", cas_3_0_available);
- debug("cas_4_0_available=%d\n", cas_4_0_available);
- debug("cas_5_0_available=%d\n", cas_5_0_available);
- if ((cas_3_0_available == true) &&
- (sdram_freq <= cycle_3_0_clk)) {
- mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
- *selected_cas = DDR_CAS_3;
- } else if ((cas_4_0_available == true) &&
- (sdram_freq <= cycle_4_0_clk)) {
- mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
- *selected_cas = DDR_CAS_4;
- } else if ((cas_5_0_available == true) &&
- (sdram_freq <= cycle_5_0_clk)) {
- mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
- *selected_cas = DDR_CAS_5;
- } else {
- printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
- printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
- printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
- printf("cas3=%d cas4=%d cas5=%d\n",
- cas_3_0_available, cas_4_0_available, cas_5_0_available);
- printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
- sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
- spd_ddr_init_hang ();
- }
- }
-
- if (sdram_ddr1 == true)
- mmode |= SDRAM_MMODE_WR_DDR1;
- else {
-
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_populated[dimm_num] != SDRAM_NONE)
- t_wr_ns = max(t_wr_ns, (unsigned long)
- spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
- }
-
- /*
- * convert from nanoseconds to ddr clocks
- * round up if necessary
- */
- t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
- ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
- if (sdram_freq != ddr_check)
- t_wr_clk++;
-
- switch (t_wr_clk) {
- case 0:
- case 1:
- case 2:
- case 3:
- mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
- break;
- case 4:
- mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
- break;
- case 5:
- mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
- break;
- default:
- mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
- break;
- }
- *write_recovery = t_wr_clk;
- }
-
- debug("CAS latency = %d\n", *selected_cas);
- debug("Write recovery = %d\n", *write_recovery);
-
- mtsdram(SDRAM_MMODE, mmode);
-}
-
-/*-----------------------------------------------------------------------------+
- * program_rtr.
- *-----------------------------------------------------------------------------*/
-static void program_rtr(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- PPC4xx_SYS_INFO board_cfg;
- unsigned long max_refresh_rate;
- unsigned long dimm_num;
- unsigned long refresh_rate_type;
- unsigned long refresh_rate;
- unsigned long rint;
- unsigned long sdram_freq;
- unsigned long sdr_ddrpll;
- unsigned long val;
-
- /*------------------------------------------------------------------
- * Get the board configuration info.
- *-----------------------------------------------------------------*/
- get_sys_info(&board_cfg);
-
- /*------------------------------------------------------------------
- * Set the SDRAM Refresh Timing Register, SDRAM_RTR
- *-----------------------------------------------------------------*/
- mfsdr(SDR0_DDR0, sdr_ddrpll);
- sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
-
- max_refresh_rate = 0;
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
-
- refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
- refresh_rate_type &= 0x7F;
- switch (refresh_rate_type) {
- case 0:
- refresh_rate = 15625;
- break;
- case 1:
- refresh_rate = 3906;
- break;
- case 2:
- refresh_rate = 7812;
- break;
- case 3:
- refresh_rate = 31250;
- break;
- case 4:
- refresh_rate = 62500;
- break;
- case 5:
- refresh_rate = 125000;
- break;
- default:
- refresh_rate = 0;
- printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
- (unsigned int)dimm_num);
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- break;
- }
-
- max_refresh_rate = max(max_refresh_rate, refresh_rate);
- }
- }
-
- rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
- mfsdram(SDRAM_RTR, val);
- mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
- (SDRAM_RTR_RINT_ENCODE(rint)));
-}
-
-/*------------------------------------------------------------------
- * This routine programs the SDRAM_TRx registers.
- *-----------------------------------------------------------------*/
-static void program_tr(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long sdram_ddr1;
- unsigned long t_rp_ns;
- unsigned long t_rcd_ns;
- unsigned long t_rrd_ns;
- unsigned long t_ras_ns;
- unsigned long t_rc_ns;
- unsigned long t_rfc_ns;
- unsigned long t_wpc_ns;
- unsigned long t_wtr_ns;
- unsigned long t_rpc_ns;
- unsigned long t_rp_clk;
- unsigned long t_rcd_clk;
- unsigned long t_rrd_clk;
- unsigned long t_ras_clk;
- unsigned long t_rc_clk;
- unsigned long t_rfc_clk;
- unsigned long t_wpc_clk;
- unsigned long t_wtr_clk;
- unsigned long t_rpc_clk;
- unsigned long sdtr1, sdtr2, sdtr3;
- unsigned long ddr_check;
- unsigned long sdram_freq;
- unsigned long sdr_ddrpll;
-
- PPC4xx_SYS_INFO board_cfg;
-
- /*------------------------------------------------------------------
- * Get the board configuration info.
- *-----------------------------------------------------------------*/
- get_sys_info(&board_cfg);
-
- mfsdr(SDR0_DDR0, sdr_ddrpll);
- sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
-
- /*------------------------------------------------------------------
- * Handle the timing. We need to find the worst case timing of all
- * the dimm modules installed.
- *-----------------------------------------------------------------*/
- t_rp_ns = 0;
- t_rrd_ns = 0;
- t_rcd_ns = 0;
- t_ras_ns = 0;
- t_rc_ns = 0;
- t_rfc_ns = 0;
- t_wpc_ns = 0;
- t_wtr_ns = 0;
- t_rpc_ns = 0;
- sdram_ddr1 = true;
-
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
- if (dimm_populated[dimm_num] == SDRAM_DDR2)
- sdram_ddr1 = true;
- else
- sdram_ddr1 = false;
-
- t_rcd_ns = max(t_rcd_ns,
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
- t_rrd_ns = max(t_rrd_ns,
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
- t_rp_ns = max(t_rp_ns,
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
- t_ras_ns = max(t_ras_ns,
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 30));
- t_rc_ns = max(t_rc_ns,
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 41));
- t_rfc_ns = max(t_rfc_ns,
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 42));
- }
- }
-
- /*------------------------------------------------------------------
- * Set the SDRAM Timing Reg 1, SDRAM_TR1
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_SDTR1, sdtr1);
- sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
- SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
-
- /* default values */
- sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
- sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
-
- /* normal operations */
- sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
- sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
-
- mtsdram(SDRAM_SDTR1, sdtr1);
-
- /*------------------------------------------------------------------
- * Set the SDRAM Timing Reg 2, SDRAM_TR2
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_SDTR2, sdtr2);
- sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
- SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
- SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
- SDRAM_SDTR2_RRD_MASK);
-
- /*
- * convert t_rcd from nanoseconds to ddr clocks
- * round up if necessary
- */
- t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
- ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
- if (sdram_freq != ddr_check)
- t_rcd_clk++;
-
- switch (t_rcd_clk) {
- case 0:
- case 1:
- sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
- break;
- case 2:
- sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
- break;
- case 3:
- sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
- break;
- case 4:
- sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
- break;
- default:
- sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
- break;
- }
-
- if (sdram_ddr1 == true) { /* DDR1 */
- if (sdram_freq < 200000000) {
- sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
- sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
- sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
- } else {
- sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
- sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
- sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
- }
- } else { /* DDR2 */
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
- t_wpc_ns = max(t_wtr_ns,
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
- t_wtr_ns = max(t_wtr_ns,
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
- t_rpc_ns = max(t_rpc_ns,
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
- }
- }
-
- /*
- * convert from nanoseconds to ddr clocks
- * round up if necessary
- */
- t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
- ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
- if (sdram_freq != ddr_check)
- t_wpc_clk++;
-
- switch (t_wpc_clk) {
- case 0:
- case 1:
- case 2:
- sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
- break;
- case 3:
- sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
- break;
- case 4:
- sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
- break;
- case 5:
- sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
- break;
- default:
- sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
- break;
- }
-
- /*
- * convert from nanoseconds to ddr clocks
- * round up if necessary
- */
- t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
- ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
- if (sdram_freq != ddr_check)
- t_wtr_clk++;
-
- switch (t_wtr_clk) {
- case 0:
- case 1:
- sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
- break;
- case 2:
- sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
- break;
- case 3:
- sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
- break;
- default:
- sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
- break;
- }
-
- /*
- * convert from nanoseconds to ddr clocks
- * round up if necessary
- */
- t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
- ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
- if (sdram_freq != ddr_check)
- t_rpc_clk++;
-
- switch (t_rpc_clk) {
- case 0:
- case 1:
- case 2:
- sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
- break;
- case 3:
- sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
- break;
- default:
- sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
- break;
- }
- }
-
- /* default value */
- sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
-
- /*
- * convert t_rrd from nanoseconds to ddr clocks
- * round up if necessary
- */
- t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
- ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
- if (sdram_freq != ddr_check)
- t_rrd_clk++;
-
- if (t_rrd_clk == 3)
- sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
- else
- sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
-
- /*
- * convert t_rp from nanoseconds to ddr clocks
- * round up if necessary
- */
- t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
- ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
- if (sdram_freq != ddr_check)
- t_rp_clk++;
-
- switch (t_rp_clk) {
- case 0:
- case 1:
- case 2:
- case 3:
- sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
- break;
- case 4:
- sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
- break;
- case 5:
- sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
- break;
- case 6:
- sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
- break;
- default:
- sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
- break;
- }
-
- mtsdram(SDRAM_SDTR2, sdtr2);
-
- /*------------------------------------------------------------------
- * Set the SDRAM Timing Reg 3, SDRAM_TR3
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_SDTR3, sdtr3);
- sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
- SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
-
- /*
- * convert t_ras from nanoseconds to ddr clocks
- * round up if necessary
- */
- t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
- ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
- if (sdram_freq != ddr_check)
- t_ras_clk++;
-
- sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
-
- /*
- * convert t_rc from nanoseconds to ddr clocks
- * round up if necessary
- */
- t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
- ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
- if (sdram_freq != ddr_check)
- t_rc_clk++;
-
- sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
-
- /* default xcs value */
- sdtr3 |= SDRAM_SDTR3_XCS;
-
- /*
- * convert t_rfc from nanoseconds to ddr clocks
- * round up if necessary
- */
- t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
- ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
- if (sdram_freq != ddr_check)
- t_rfc_clk++;
-
- sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
-
- mtsdram(SDRAM_SDTR3, sdtr3);
-}
-
-/*-----------------------------------------------------------------------------+
- * program_bxcf.
- *-----------------------------------------------------------------------------*/
-static void program_bxcf(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long num_col_addr;
- unsigned long num_ranks;
- unsigned long num_banks;
- unsigned long mode;
- unsigned long ind_rank;
- unsigned long ind;
- unsigned long ind_bank;
- unsigned long bank_0_populated;
-
- /*------------------------------------------------------------------
- * Set the BxCF regs. First, wipe out the bank config registers.
- *-----------------------------------------------------------------*/
- mtsdram(SDRAM_MB0CF, 0x00000000);
- mtsdram(SDRAM_MB1CF, 0x00000000);
- mtsdram(SDRAM_MB2CF, 0x00000000);
- mtsdram(SDRAM_MB3CF, 0x00000000);
-
- mode = SDRAM_BXCF_M_BE_ENABLE;
-
- bank_0_populated = 0;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
- num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
- num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
- if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
- num_ranks = (num_ranks & 0x0F) +1;
- else
- num_ranks = num_ranks & 0x0F;
-
- num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
-
- for (ind_bank = 0; ind_bank < 2; ind_bank++) {
- if (num_banks == 4)
- ind = 0;
- else
- ind = 5 << 8;
- switch (num_col_addr) {
- case 0x08:
- mode |= (SDRAM_BXCF_M_AM_0 + ind);
- break;
- case 0x09:
- mode |= (SDRAM_BXCF_M_AM_1 + ind);
- break;
- case 0x0A:
- mode |= (SDRAM_BXCF_M_AM_2 + ind);
- break;
- case 0x0B:
- mode |= (SDRAM_BXCF_M_AM_3 + ind);
- break;
- case 0x0C:
- mode |= (SDRAM_BXCF_M_AM_4 + ind);
- break;
- default:
- printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
- (unsigned int)dimm_num);
- printf("ERROR: Unsupported value for number of "
- "column addresses: %d.\n", (unsigned int)num_col_addr);
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- }
- }
-
- if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
- bank_0_populated = 1;
-
- for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
- mtsdram(SDRAM_MB0CF +
- ((dimm_num + bank_0_populated + ind_rank) << 2),
- mode);
- }
- }
- }
-}
-
-/*------------------------------------------------------------------
- * program memory queue.
- *-----------------------------------------------------------------*/
-static void program_memory_queue(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- phys_size_t rank_base_addr;
- unsigned long rank_reg;
- phys_size_t rank_size_bytes;
- unsigned long rank_size_id;
- unsigned long num_ranks;
- unsigned long baseadd_size;
- unsigned long i;
- unsigned long bank_0_populated = 0;
- phys_size_t total_size = 0;
-
- /*------------------------------------------------------------------
- * Reset the rank_base_address.
- *-----------------------------------------------------------------*/
- rank_reg = SDRAM_R0BAS;
-
- rank_base_addr = 0x00000000;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] != SDRAM_NONE) {
- num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
- if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
- num_ranks = (num_ranks & 0x0F) + 1;
- else
- num_ranks = num_ranks & 0x0F;
-
- rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
-
- /*------------------------------------------------------------------
- * Set the sizes
- *-----------------------------------------------------------------*/
- baseadd_size = 0;
- switch (rank_size_id) {
- case 0x01:
- baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
- total_size = 1024;
- break;
- case 0x02:
- baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
- total_size = 2048;
- break;
- case 0x04:
- baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
- total_size = 4096;
- break;
- case 0x08:
- baseadd_size |= SDRAM_RXBAS_SDSZ_32;
- total_size = 32;
- break;
- case 0x10:
- baseadd_size |= SDRAM_RXBAS_SDSZ_64;
- total_size = 64;
- break;
- case 0x20:
- baseadd_size |= SDRAM_RXBAS_SDSZ_128;
- total_size = 128;
- break;
- case 0x40:
- baseadd_size |= SDRAM_RXBAS_SDSZ_256;
- total_size = 256;
- break;
- case 0x80:
- baseadd_size |= SDRAM_RXBAS_SDSZ_512;
- total_size = 512;
- break;
- default:
- printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
- (unsigned int)dimm_num);
- printf("ERROR: Unsupported value for the banksize: %d.\n",
- (unsigned int)rank_size_id);
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- spd_ddr_init_hang ();
- }
- rank_size_bytes = total_size << 20;
-
- if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
- bank_0_populated = 1;
-
- for (i = 0; i < num_ranks; i++) {
- mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
- (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
- baseadd_size));
- rank_base_addr += rank_size_bytes;
- }
- }
- }
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
- /*
- * Enable high bandwidth access
- * This is currently not used, but with this setup
- * it is possible to use it later on in e.g. the Linux
- * EMAC driver for performance gain.
- */
- mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
- mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
-
- /*
- * Set optimal value for Memory Queue HB/LL Configuration registers
- */
- mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
- SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
- SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
- mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
- SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
- SDRAM_CONF1LL_RPLM);
- mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
-#endif
-}
-
-#ifdef CONFIG_DDR_ECC
-/*-----------------------------------------------------------------------------+
- * program_ecc.
- *-----------------------------------------------------------------------------*/
-static void program_ecc(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks,
- unsigned long tlb_word2_i_value)
-{
- unsigned long dimm_num;
- unsigned long ecc;
-
- ecc = 0;
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_populated[dimm_num] != SDRAM_NONE)
- ecc = max(ecc,
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11));
- }
- if (ecc == 0)
- return;
-
- do_program_ecc(tlb_word2_i_value);
-}
-#endif
-
-#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-/*-----------------------------------------------------------------------------+
- * program_DQS_calibration.
- *-----------------------------------------------------------------------------*/
-static void program_DQS_calibration(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks)
-{
- unsigned long val;
-
-#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
- mtsdram(SDRAM_RQDC, 0x80000037);
- mtsdram(SDRAM_RDCC, 0x40000000);
- mtsdram(SDRAM_RFDC, 0x000001DF);
-
- test();
-#else
- /*------------------------------------------------------------------
- * Program RDCC register
- * Read sample cycle auto-update enable
- *-----------------------------------------------------------------*/
-
- mfsdram(SDRAM_RDCC, val);
- mtsdram(SDRAM_RDCC,
- (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
- | SDRAM_RDCC_RSAE_ENABLE);
-
- /*------------------------------------------------------------------
- * Program RQDC register
- * Internal DQS delay mechanism enable
- *-----------------------------------------------------------------*/
- mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
-
- /*------------------------------------------------------------------
- * Program RFDC register
- * Set Feedback Fractional Oversample
- * Auto-detect read sample cycle enable
- * Set RFOS to 1/4 of memclk cycle (0x3f)
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_RFDC, val);
- mtsdram(SDRAM_RFDC,
- (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
- SDRAM_RFDC_RFFD_MASK))
- | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
- SDRAM_RFDC_RFFD_ENCODE(0)));
-
- DQS_calibration_process();
-#endif
-}
-
-static int short_mem_test(void)
-{
- u32 *membase;
- u32 bxcr_num;
- u32 bxcf;
- int i;
- int j;
- phys_size_t base_addr;
- u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
- {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
- {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
- {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
- {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
- {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
- {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
- {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
- {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
- int l;
-
- for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
- mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
-
- /* Banks enabled */
- if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
- /* Bank is enabled */
-
- /*
- * Only run test on accessable memory (below 2GB)
- */
- base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
- if (base_addr >= CONFIG_MAX_MEM_MAPPED)
- continue;
-
- /*------------------------------------------------------------------
- * Run the short memory test.
- *-----------------------------------------------------------------*/
- membase = (u32 *)(u32)base_addr;
-
- for (i = 0; i < NUMMEMTESTS; i++) {
- for (j = 0; j < NUMMEMWORDS; j++) {
- membase[j] = test[i][j];
- ppcDcbf((u32)&(membase[j]));
- }
- sync();
- for (l=0; l<NUMLOOPS; l++) {
- for (j = 0; j < NUMMEMWORDS; j++) {
- if (membase[j] != test[i][j]) {
- ppcDcbf((u32)&(membase[j]));
- return 0;
- }
- ppcDcbf((u32)&(membase[j]));
- }
- sync();
- }
- }
- } /* if bank enabled */
- } /* for bxcf_num */
-
- return 1;
-}
-
-#ifndef HARD_CODED_DQS
-/*-----------------------------------------------------------------------------+
- * DQS_calibration_process.
- *-----------------------------------------------------------------------------*/
-static void DQS_calibration_process(void)
-{
- unsigned long rfdc_reg;
- unsigned long rffd;
- unsigned long val;
- long rffd_average;
- long max_start;
- unsigned long dlycal;
- unsigned long dly_val;
- unsigned long max_pass_length;
- unsigned long current_pass_length;
- unsigned long current_fail_length;
- unsigned long current_start;
- long max_end;
- unsigned char fail_found;
- unsigned char pass_found;
-#if !defined(CONFIG_DDR_RQDC_FIXED)
- int window_found;
- u32 rqdc_reg;
- u32 rqfd;
- u32 rqfd_start;
- u32 rqfd_average;
- int loopi = 0;
- char str[] = "Auto calibration -";
- char slash[] = "\\|/-\\|/-";
-
- /*------------------------------------------------------------------
- * Test to determine the best read clock delay tuning bits.
- *
- * Before the DDR controller can be used, the read clock delay needs to be
- * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
- * This value cannot be hardcoded into the program because it changes
- * depending on the board's setup and environment.
- * To do this, all delay values are tested to see if they
- * work or not. By doing this, you get groups of fails with groups of
- * passing values. The idea is to find the start and end of a passing
- * window and take the center of it to use as the read clock delay.
- *
- * A failure has to be seen first so that when we hit a pass, we know
- * that it is truely the start of the window. If we get passing values
- * to start off with, we don't know if we are at the start of the window.
- *
- * The code assumes that a failure will always be found.
- * If a failure is not found, there is no easy way to get the middle
- * of the passing window. I guess we can pretty much pick any value
- * but some values will be better than others. Since the lowest speed
- * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
- * from experimentation it is safe to say you will always have a failure.
- *-----------------------------------------------------------------*/
-
- /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
- rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
-
- puts(str);
-
-calibration_loop:
- mfsdram(SDRAM_RQDC, rqdc_reg);
- mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
- SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
-#else /* CONFIG_DDR_RQDC_FIXED */
- /*
- * On Katmai the complete auto-calibration somehow doesn't seem to
- * produce the best results, meaning optimal values for RQFD/RFFD.
- * This was discovered by GDA using a high bandwidth scope,
- * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
- * so now on Katmai "only" RFFD is auto-calibrated.
- */
- mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
-#endif /* CONFIG_DDR_RQDC_FIXED */
-
- max_start = 0;
-
- max_pass_length = 0;
- max_start = 0;
- max_end = 0;
- current_pass_length = 0;
- current_fail_length = 0;
- current_start = 0;
- fail_found = false;
- pass_found = false;
-
- /*
- * get the delay line calibration register value
- */
- mfsdram(SDRAM_DLCR, dlycal);
- dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
-
- for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
- mfsdram(SDRAM_RFDC, rfdc_reg);
- rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
-
- /*------------------------------------------------------------------
- * Set the timing reg for the test.
- *-----------------------------------------------------------------*/
- mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
-
- /*------------------------------------------------------------------
- * See if the rffd value passed.
- *-----------------------------------------------------------------*/
- if (short_mem_test()) {
- if (fail_found == true) {
- pass_found = true;
- if (current_pass_length == 0)
- current_start = rffd;
-
- current_fail_length = 0;
- current_pass_length++;
-
- if (current_pass_length > max_pass_length) {
- max_pass_length = current_pass_length;
- max_start = current_start;
- max_end = rffd;
- }
- }
- } else {
- current_pass_length = 0;
- current_fail_length++;
-
- if (current_fail_length >= (dly_val >> 2)) {
- if (fail_found == false)
- fail_found = true;
- else if (pass_found == true)
- break;
- }
- }
- } /* for rffd */
-
- /*------------------------------------------------------------------
- * Set the average RFFD value
- *-----------------------------------------------------------------*/
- rffd_average = ((max_start + max_end) >> 1);
-
- if (rffd_average < 0)
- rffd_average = 0;
-
- if (rffd_average > SDRAM_RFDC_RFFD_MAX)
- rffd_average = SDRAM_RFDC_RFFD_MAX;
- /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
- mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
-
-#if !defined(CONFIG_DDR_RQDC_FIXED)
- max_pass_length = 0;
- max_start = 0;
- max_end = 0;
- current_pass_length = 0;
- current_fail_length = 0;
- current_start = 0;
- window_found = false;
- fail_found = false;
- pass_found = false;
-
- for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
- mfsdram(SDRAM_RQDC, rqdc_reg);
- rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
-
- /*------------------------------------------------------------------
- * Set the timing reg for the test.
- *-----------------------------------------------------------------*/
- mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
-
- /*------------------------------------------------------------------
- * See if the rffd value passed.
- *-----------------------------------------------------------------*/
- if (short_mem_test()) {
- if (fail_found == true) {
- pass_found = true;
- if (current_pass_length == 0)
- current_start = rqfd;
-
- current_fail_length = 0;
- current_pass_length++;
-
- if (current_pass_length > max_pass_length) {
- max_pass_length = current_pass_length;
- max_start = current_start;
- max_end = rqfd;
- }
- }
- } else {
- current_pass_length = 0;
- current_fail_length++;
-
- if (fail_found == false) {
- fail_found = true;
- } else if (pass_found == true) {
- window_found = true;
- break;
- }
- }
- }
-
- rqfd_average = ((max_start + max_end) >> 1);
-
- /*------------------------------------------------------------------
- * Make sure we found the valid read passing window. Halt if not
- *-----------------------------------------------------------------*/
- if (window_found == false) {
- if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
- putc('\b');
- putc(slash[loopi++ % 8]);
-
- /* try again from with a different RQFD start value */
- rqfd_start++;
- goto calibration_loop;
- }
-
- printf("\nERROR: Cannot determine a common read delay for the "
- "DIMM(s) installed.\n");
- debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
- ppc4xx_ibm_ddr2_register_dump();
- spd_ddr_init_hang ();
- }
-
- if (rqfd_average < 0)
- rqfd_average = 0;
-
- if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
- rqfd_average = SDRAM_RQDC_RQFD_MAX;
-
- mtsdram(SDRAM_RQDC,
- (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
- SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
-
- blank_string(strlen(str));
-#endif /* CONFIG_DDR_RQDC_FIXED */
-
- mfsdram(SDRAM_DLCR, val);
- debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
- mfsdram(SDRAM_RQDC, val);
- debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
- mfsdram(SDRAM_RFDC, val);
- debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
- mfsdram(SDRAM_RDCC, val);
- debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
-}
-#else /* calibration test with hardvalues */
-/*-----------------------------------------------------------------------------+
- * DQS_calibration_process.
- *-----------------------------------------------------------------------------*/
-static void test(void)
-{
- unsigned long dimm_num;
- unsigned long ecc_temp;
- unsigned long i, j;
- unsigned long *membase;
- unsigned long bxcf[MAXRANKS];
- unsigned long val;
- char window_found;
- char begin_found[MAXDIMMS];
- char end_found[MAXDIMMS];
- char search_end[MAXDIMMS];
- unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
- {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
- {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
- {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
- {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
- {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
- {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
- {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
- {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
-
- /*------------------------------------------------------------------
- * Test to determine the best read clock delay tuning bits.
- *
- * Before the DDR controller can be used, the read clock delay needs to be
- * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
- * This value cannot be hardcoded into the program because it changes
- * depending on the board's setup and environment.
- * To do this, all delay values are tested to see if they
- * work or not. By doing this, you get groups of fails with groups of
- * passing values. The idea is to find the start and end of a passing
- * window and take the center of it to use as the read clock delay.
- *
- * A failure has to be seen first so that when we hit a pass, we know
- * that it is truely the start of the window. If we get passing values
- * to start off with, we don't know if we are at the start of the window.
- *
- * The code assumes that a failure will always be found.
- * If a failure is not found, there is no easy way to get the middle
- * of the passing window. I guess we can pretty much pick any value
- * but some values will be better than others. Since the lowest speed
- * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
- * from experimentation it is safe to say you will always have a failure.
- *-----------------------------------------------------------------*/
- mfsdram(SDRAM_MCOPT1, ecc_temp);
- ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
- mfsdram(SDRAM_MCOPT1, val);
- mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
- SDRAM_MCOPT1_MCHK_NON);
-
- window_found = false;
- begin_found[0] = false;
- end_found[0] = false;
- search_end[0] = false;
- begin_found[1] = false;
- end_found[1] = false;
- search_end[1] = false;
-
- for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
- mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
-
- /* Banks enabled */
- if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
-
- /* Bank is enabled */
- membase =
- (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
-
- /*------------------------------------------------------------------
- * Run the short memory test.
- *-----------------------------------------------------------------*/
- for (i = 0; i < NUMMEMTESTS; i++) {
- for (j = 0; j < NUMMEMWORDS; j++) {
- membase[j] = test[i][j];
- ppcDcbf((u32)&(membase[j]));
- }
- sync();
- for (j = 0; j < NUMMEMWORDS; j++) {
- if (membase[j] != test[i][j]) {
- ppcDcbf((u32)&(membase[j]));
- break;
- }
- ppcDcbf((u32)&(membase[j]));
- }
- sync();
- if (j < NUMMEMWORDS)
- break;
- }
-
- /*------------------------------------------------------------------
- * See if the rffd value passed.
- *-----------------------------------------------------------------*/
- if (i < NUMMEMTESTS) {
- if ((end_found[dimm_num] == false) &&
- (search_end[dimm_num] == true)) {
- end_found[dimm_num] = true;
- }
- if ((end_found[0] == true) &&
- (end_found[1] == true))
- break;
- } else {
- if (begin_found[dimm_num] == false) {
- begin_found[dimm_num] = true;
- search_end[dimm_num] = true;
- }
- }
- } else {
- begin_found[dimm_num] = true;
- end_found[dimm_num] = true;
- }
- }
-
- if ((begin_found[0] == true) && (begin_found[1] == true))
- window_found = true;
-
- /*------------------------------------------------------------------
- * Make sure we found the valid read passing window. Halt if not
- *-----------------------------------------------------------------*/
- if (window_found == false) {
- printf("ERROR: Cannot determine a common read delay for the "
- "DIMM(s) installed.\n");
- spd_ddr_init_hang ();
- }
-
- /*------------------------------------------------------------------
- * Restore the ECC variable to what it originally was
- *-----------------------------------------------------------------*/
- mtsdram(SDRAM_MCOPT1,
- (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
- | ecc_temp);
-}
-#endif /* !HARD_CODED_DQS */
-#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
-
-#else /* CONFIG_SPD_EEPROM */
-
-/*-----------------------------------------------------------------------------
- * Function: dram_init
- * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
- * The configuration is performed using static, compile-
- * time parameters.
- * Configures the PPC405EX(r) and PPC460EX/GT
- *---------------------------------------------------------------------------*/
-int dram_init(void)
-{
- unsigned long val;
-
-#if defined(CONFIG_440)
- mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
- mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
- mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
- mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
- mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
- mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
- mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
- mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
- mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
-#endif
-
- /* Set Memory Bank Configuration Registers */
-
- mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
- mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
- mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
- mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
-
- /* Set Memory Clock Timing Register */
-
- mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
-
- /* Set Refresh Time Register */
-
- mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
-
- /* Set SDRAM Timing Registers */
-
- mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
- mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
- mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
-
- /* Set Mode and Extended Mode Registers */
-
- mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
- mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
-
- /* Set Memory Controller Options 1 Register */
-
- mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
-
- /* Set Manual Initialization Control Registers */
-
- mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
- mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
- mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
- mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
- mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
- mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
- mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
- mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
- mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
- mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
- mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
- mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
- mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
- mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
- mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
- mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
-
- /* Set On-Die Termination Registers */
-
- mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
- mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
- mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
-
- /* Set Write Timing Register */
-
- mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
-
- /*
- * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
- * SDRAM0_MCOPT2[IPTR] = 1
- */
-
- mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
- SDRAM_MCOPT2_IPTR_EXECUTE));
-
- /*
- * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
- * completion of initialization.
- */
-
- do {
- mfsdram(SDRAM_MCSTAT, val);
- } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
-
- /* Set Delay Control Registers */
-
- mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
-
-#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
- mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
- mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
- mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
-#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
-
- /*
- * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
- */
-
- mfsdram(SDRAM_MCOPT2, val);
- mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
-
-#if defined(CONFIG_440)
- /*
- * Program TLB entries with caches enabled, for best performace
- * while auto-calibrating and ECC generation
- */
- program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
-#endif
-
-#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
- /*------------------------------------------------------------------
- | DQS calibration.
- +-----------------------------------------------------------------*/
- DQS_autocalibration();
-#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
-
- /*
- * Now complete RDSS configuration as mentioned on page 7 of the AMCC
- * PowerPC440SP/SPe DDR2 application note:
- * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
- */
- update_rdcc();
-
-#if defined(CONFIG_DDR_ECC)
- do_program_ecc(0);
-#endif /* defined(CONFIG_DDR_ECC) */
-
-#if defined(CONFIG_440)
- /*
- * Now after initialization (auto-calibration and ECC generation)
- * remove the TLB entries with caches enabled and program again with
- * desired cache functionality
- */
- remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
- program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
-#endif
-
- ppc4xx_ibm_ddr2_register_dump();
-
-#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
- /*
- * Clear potential errors resulting from auto-calibration.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
-
- gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
-
- return 0;
-}
-#endif /* CONFIG_SPD_EEPROM */
-
-#if defined(CONFIG_440)
-u32 mfdcr_any(u32 dcr)
-{
- u32 val;
-
- switch (dcr) {
- case SDRAM_R0BAS + 0:
- val = mfdcr(SDRAM_R0BAS + 0);
- break;
- case SDRAM_R0BAS + 1:
- val = mfdcr(SDRAM_R0BAS + 1);
- break;
- case SDRAM_R0BAS + 2:
- val = mfdcr(SDRAM_R0BAS + 2);
- break;
- case SDRAM_R0BAS + 3:
- val = mfdcr(SDRAM_R0BAS + 3);
- break;
- default:
- printf("DCR %d not defined in case statement!!!\n", dcr);
- val = 0; /* just to satisfy the compiler */
- }
-
- return val;
-}
-
-void mtdcr_any(u32 dcr, u32 val)
-{
- switch (dcr) {
- case SDRAM_R0BAS + 0:
- mtdcr(SDRAM_R0BAS + 0, val);
- break;
- case SDRAM_R0BAS + 1:
- mtdcr(SDRAM_R0BAS + 1, val);
- break;
- case SDRAM_R0BAS + 2:
- mtdcr(SDRAM_R0BAS + 2, val);
- break;
- case SDRAM_R0BAS + 3:
- mtdcr(SDRAM_R0BAS + 3, val);
- break;
- default:
- printf("DCR %d not defined in case statement!!!\n", dcr);
- }
-}
-#endif /* defined(CONFIG_440) */
-
-inline void ppc4xx_ibm_ddr2_register_dump(void)
-{
-#if defined(DEBUG)
- printf("\nPPC4xx IBM DDR2 Register Dump:\n");
-
-#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT))
- PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
- PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
- PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
- PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
-#endif /* (defined(CONFIG_440SP) || ... */
-#if defined(CONFIG_405EX)
- PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
-#endif /* defined(CONFIG_405EX) */
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
-#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT))
- PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
- /*
- * OPART is only used as a trigger register.
- *
- * No data is contained in this register, and reading or writing
- * to is can cause bad things to happen (hangs). Just skip it and
- * report "N/A".
- */
- printf("%20s = N/A\n", "SDRAM_OPART");
-#endif /* defined(CONFIG_440SP) || ... */
- PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
-#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT))
- PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
-#endif /* defined(CONFIG_440SP) || ... */
- PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
-#endif /* defined(DEBUG) */
-}
+++ /dev/null
-/*
- * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
- * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
- * DDR2 controller (non Denali Core). Those currently are:
- *
- * 405: 405EX
- * 440/460: 440SP/440SPe/460EX/460GT/460SX
- *
- * (C) Copyright 2008 Applied Micro Circuits Corporation
- * Adam Graham <agraham@amcc.com>
- *
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * COPYRIGHT AMCC CORPORATION 2004
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#undef DEBUG
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-#include "ecc.h"
-
-#define MAXBXCF 4
-#define SDRAM_RXBAS_SHIFT_1M 20
-
-#if defined(CONFIG_SYS_DECREMENT_PATTERNS)
-#define NUMMEMTESTS 24
-#else
-#define NUMMEMTESTS 8
-#endif /* CONFIG_SYS_DECREMENT_PATTERNS */
-#define NUMLOOPS 1 /* configure as you deem approporiate */
-#define NUMMEMWORDS 16
-
-#define SDRAM_RDCC_RDSS_VAL(n) SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n))
-
-/* Private Structure Definitions */
-
-struct autocal_regs {
- u32 rffd;
- u32 rqfd;
-};
-
-struct ddrautocal {
- u32 rffd;
- u32 rffd_min;
- u32 rffd_max;
- u32 rffd_size;
- u32 rqfd;
- u32 rqfd_size;
- u32 rdcc;
- u32 flags;
-};
-
-struct sdram_timing_clks {
- u32 wrdtr;
- u32 clktr;
- u32 rdcc;
- u32 flags;
-};
-
-struct autocal_clks {
- struct sdram_timing_clks clocks;
- struct ddrautocal autocal;
-};
-
-/*--------------------------------------------------------------------------+
- * Prototypes
- *--------------------------------------------------------------------------*/
-#if defined(CONFIG_PPC4xx_DDR_METHOD_A)
-static u32 DQS_calibration_methodA(struct ddrautocal *);
-static u32 program_DQS_calibration_methodA(struct ddrautocal *);
-#else
-static u32 DQS_calibration_methodB(struct ddrautocal *);
-static u32 program_DQS_calibration_methodB(struct ddrautocal *);
-#endif
-static int short_mem_test(u32 *);
-
-/*
- * To provide an interface for board specific config values in this common
- * DDR setup code, we implement he "weak" default functions here. They return
- * the default value back to the caller.
- *
- * Please see include/configs/yucca.h for an example fora board specific
- * implementation.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-u32 __ddr_wrdtr(u32 default_val)
-{
- return default_val;
-}
-u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
-
-u32 __ddr_clktr(u32 default_val)
-{
- return default_val;
-}
-u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
-
-/*
- * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
- */
-void __spd_ddr_init_hang(void)
-{
- hang();
-}
-void
-spd_ddr_init_hang(void) __attribute__((weak, alias("__spd_ddr_init_hang")));
-#endif /* defined(CONFIG_SPD_EEPROM) */
-
-struct sdram_timing *__ddr_scan_option(struct sdram_timing *default_val)
-{
- return default_val;
-}
-struct sdram_timing *ddr_scan_option(struct sdram_timing *)
- __attribute__((weak, alias("__ddr_scan_option")));
-
-u32 __ddr_rdss_opt(u32 default_val)
-{
- return default_val;
-}
-u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt")));
-
-
-static u32 *get_membase(int bxcr_num)
-{
- u32 *membase;
-
-#if defined(SDRAM_R0BAS)
- /* BAS from Memory Queue rank reg. */
- membase =
- (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
-#else
- {
- ulong bxcf;
-
- /* BAS from SDRAM_MBxCF mem rank reg. */
- mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
- membase = (u32 *)((bxcf & 0xfff80000) << 3);
- }
-#endif
-
- return membase;
-}
-
-static inline void ecc_clear_status_reg(void)
-{
- mtsdram(SDRAM_ECCES, 0xffffffff);
-#if defined(SDRAM_R0BAS)
- mtdcr(SDRAM_ERRSTATLL, 0xffffffff);
-#endif
-}
-
-/*
- * Reset and relock memory DLL after SDRAM_CLKTR change
- */
-static inline void relock_memory_DLL(void)
-{
- u32 reg;
-
- mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
-
- do {
- mfsdram(SDRAM_MCSTAT, reg);
- } while (!(reg & SDRAM_MCSTAT_MIC_COMP));
-
- mfsdram(SDRAM_MCOPT2, reg);
- mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
-}
-
-static int ecc_check_status_reg(void)
-{
- u32 ecc_status;
-
- /*
- * Compare suceeded, now check
- * if got ecc error. If got an
- * ecc error, then don't count
- * this as a passing value
- */
- mfsdram(SDRAM_ECCES, ecc_status);
- if (ecc_status != 0x00000000) {
- /* clear on error */
- ecc_clear_status_reg();
- /* ecc check failure */
- return 0;
- }
- ecc_clear_status_reg();
- sync();
-
- return 1;
-}
-
-/* return 1 if passes, 0 if fail */
-static int short_mem_test(u32 *base_address)
-{
- int i, j, l;
- u32 ecc_mode = 0;
-
- ulong test[NUMMEMTESTS][NUMMEMWORDS] = {
- /* 0 */ {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
- /* 1 */ {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
- /* 2 */ {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
- /* 3 */ {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
- /* 4 */ {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
- /* 5 */ {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
- /* 6 */ {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
- /* 7 */ {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55},
-
-#if defined(CONFIG_SYS_DECREMENT_PATTERNS)
- /* 8 */ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff},
- /* 9 */ {0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
- 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
- 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
- 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe},
- /* 10 */{0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
- 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
- 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
- 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd},
- /* 11 */{0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
- 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
- 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
- 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc},
- /* 12 */{0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
- 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
- 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
- 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb},
- /* 13 */{0xfffafffa, 0xfffafffa, 0xfffffffa, 0xfffafffa,
- 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
- 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
- 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa},
- /* 14 */{0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
- 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
- 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
- 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9},
- /* 15 */{0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
- 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
- 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
- 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8},
- /* 16 */{0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
- 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
- 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
- 0xfff7ffff, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7},
- /* 17 */{0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
- 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
- 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
- 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7},
- /* 18 */{0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
- 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
- 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
- 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5},
- /* 19 */{0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
- 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
- 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
- 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4},
- /* 20 */{0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
- 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
- 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
- 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3},
- /* 21 */{0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
- 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
- 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
- 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2},
- /* 22 */{0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
- 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
- 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
- 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1},
- /* 23 */{0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
- 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
- 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
- 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0},
-#endif /* CONFIG_SYS_DECREMENT_PATTERNS */
- };
-
- mfsdram(SDRAM_MCOPT1, ecc_mode);
- if ((ecc_mode & SDRAM_MCOPT1_MCHK_CHK_REP) ==
- SDRAM_MCOPT1_MCHK_CHK_REP) {
- ecc_clear_status_reg();
- sync();
- ecc_mode = 1;
- } else {
- ecc_mode = 0;
- }
-
- /*
- * Run the short memory test.
- */
- for (i = 0; i < NUMMEMTESTS; i++) {
- for (j = 0; j < NUMMEMWORDS; j++) {
- base_address[j] = test[i][j];
- ppcDcbf((ulong)&(base_address[j]));
- }
- sync();
- iobarrier_rw();
- for (l = 0; l < NUMLOOPS; l++) {
- for (j = 0; j < NUMMEMWORDS; j++) {
- if (base_address[j] != test[i][j]) {
- ppcDcbf((u32)&(base_address[j]));
- return 0;
- } else {
- if (ecc_mode) {
- if (!ecc_check_status_reg())
- return 0;
- }
- }
- ppcDcbf((u32)&(base_address[j]));
- } /* for (j = 0; j < NUMMEMWORDS; j++) */
- sync();
- iobarrier_rw();
- } /* for (l=0; l<NUMLOOPS; l++) */
- }
-
- return 1;
-}
-
-#if defined(CONFIG_PPC4xx_DDR_METHOD_A)
-/*-----------------------------------------------------------------------------+
-| program_DQS_calibration_methodA.
-+-----------------------------------------------------------------------------*/
-static u32 program_DQS_calibration_methodA(struct ddrautocal *ddrcal)
-{
- u32 pass_result = 0;
-
-#ifdef DEBUG
- ulong temp;
-
- mfsdram(SDRAM_RDCC, temp);
- debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp);
-#endif
-
- pass_result = DQS_calibration_methodA(ddrcal);
-
- return pass_result;
-}
-
-/*
- * DQS_calibration_methodA()
- *
- * Autocalibration Method A
- *
- * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros
- * ARRAY [Entire FDBK Range] FDBK_Valid_Window; initialized to all zeros
- * MEMWRITE(addr, expected_data);
- * for (i = 0; i < Entire DQS Range; i++) { RQDC.RQFD
- * for (j = 0; j < Entire FDBK Range; j++) { RFDC.RFFD
- * MEMREAD(addr, actual_data);
- * if (actual_data == expected_data) {
- * DQS_Valid_Window[i] = 1; RQDC.RQFD
- * FDBK_Valid_Window[i][j] = 1; RFDC.RFFD
- * }
- * }
- * }
- */
-static u32 DQS_calibration_methodA(struct ddrautocal *cal)
-{
- ulong rfdc_reg;
- ulong rffd;
-
- ulong rqdc_reg;
- ulong rqfd;
-
- u32 *membase;
- ulong bxcf;
- int rqfd_average;
- int bxcr_num;
- int rffd_average;
- int pass;
- u32 passed = 0;
-
- int in_window;
- struct autocal_regs curr_win_min;
- struct autocal_regs curr_win_max;
- struct autocal_regs best_win_min;
- struct autocal_regs best_win_max;
- struct autocal_regs loop_win_min;
- struct autocal_regs loop_win_max;
-
-#ifdef DEBUG
- ulong temp;
-#endif
- ulong rdcc;
-
- char slash[] = "\\|/-\\|/-";
- int loopi = 0;
-
- /* start */
- in_window = 0;
-
- memset(&curr_win_min, 0, sizeof(curr_win_min));
- memset(&curr_win_max, 0, sizeof(curr_win_max));
- memset(&best_win_min, 0, sizeof(best_win_min));
- memset(&best_win_max, 0, sizeof(best_win_max));
- memset(&loop_win_min, 0, sizeof(loop_win_min));
- memset(&loop_win_max, 0, sizeof(loop_win_max));
-
- rdcc = 0;
-
- /*
- * Program RDCC register
- * Read sample cycle auto-update enable
- */
- mtsdram(SDRAM_RDCC,
- ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
-
-#ifdef DEBUG
- mfsdram(SDRAM_RDCC, temp);
- debug("<%s>SDRAM_RDCC=0x%x\n", __func__, temp);
- mfsdram(SDRAM_RTSR, temp);
- debug("<%s>SDRAM_RTSR=0x%x\n", __func__, temp);
- mfsdram(SDRAM_FCSR, temp);
- debug("<%s>SDRAM_FCSR=0x%x\n", __func__, temp);
-#endif
-
- /*
- * Program RQDC register
- * Internal DQS delay mechanism enable
- */
- mtsdram(SDRAM_RQDC,
- SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x00));
-
-#ifdef DEBUG
- mfsdram(SDRAM_RQDC, temp);
- debug("<%s>SDRAM_RQDC=0x%x\n", __func__, temp);
-#endif
-
- /*
- * Program RFDC register
- * Set Feedback Fractional Oversample
- * Auto-detect read sample cycle enable
- */
- mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE |
- SDRAM_RFDC_RFOS_ENCODE(0) | SDRAM_RFDC_RFFD_ENCODE(0));
-
-#ifdef DEBUG
- mfsdram(SDRAM_RFDC, temp);
- debug("<%s>SDRAM_RFDC=0x%x\n", __func__, temp);
-#endif
-
- putc(' ');
- for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
-
- mfsdram(SDRAM_RQDC, rqdc_reg);
- rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
- mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
-
- putc('\b');
- putc(slash[loopi++ % 8]);
-
- curr_win_min.rffd = 0;
- curr_win_max.rffd = 0;
- in_window = 0;
-
- for (rffd = 0, pass = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
- mfsdram(SDRAM_RFDC, rfdc_reg);
- rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
- mtsdram(SDRAM_RFDC,
- rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
-
- for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
- mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
-
- /* Banks enabled */
- if (bxcf & SDRAM_BXCF_M_BE_MASK) {
- /* Bank is enabled */
- membase = get_membase(bxcr_num);
- pass = short_mem_test(membase);
- } /* if bank enabled */
- } /* for bxcr_num */
-
- /* If this value passed update RFFD windows */
- if (pass && !in_window) { /* at the start of window */
- in_window = 1;
- curr_win_min.rffd = curr_win_max.rffd = rffd;
- curr_win_min.rqfd = curr_win_max.rqfd = rqfd;
- mfsdram(SDRAM_RDCC, rdcc); /*record this value*/
- } else if (!pass && in_window) { /* at end of window */
- in_window = 0;
- } else if (pass && in_window) { /* within the window */
- curr_win_max.rffd = rffd;
- curr_win_max.rqfd = rqfd;
- }
- /* else if (!pass && !in_window)
- skip - no pass, not currently in a window */
-
- if (in_window) {
- if ((curr_win_max.rffd - curr_win_min.rffd) >
- (best_win_max.rffd - best_win_min.rffd)) {
- best_win_min.rffd = curr_win_min.rffd;
- best_win_max.rffd = curr_win_max.rffd;
-
- best_win_min.rqfd = curr_win_min.rqfd;
- best_win_max.rqfd = curr_win_max.rqfd;
- cal->rdcc = rdcc;
- }
- passed = 1;
- }
- } /* RFDC.RFFD */
-
- /*
- * save-off the best window results of the RFDC.RFFD
- * for this RQDC.RQFD setting
- */
- /*
- * if (just ended RFDC.RFDC loop pass window) >
- * (prior RFDC.RFFD loop pass window)
- */
- if ((best_win_max.rffd - best_win_min.rffd) >
- (loop_win_max.rffd - loop_win_min.rffd)) {
- loop_win_min.rffd = best_win_min.rffd;
- loop_win_max.rffd = best_win_max.rffd;
- loop_win_min.rqfd = rqfd;
- loop_win_max.rqfd = rqfd;
- debug("RQFD.min 0x%08x, RQFD.max 0x%08x, "
- "RFFD.min 0x%08x, RFFD.max 0x%08x\n",
- loop_win_min.rqfd, loop_win_max.rqfd,
- loop_win_min.rffd, loop_win_max.rffd);
- }
- } /* RQDC.RQFD */
-
- putc('\b');
-
- debug("\n");
-
- if ((loop_win_min.rffd == 0) && (loop_win_max.rffd == 0) &&
- (best_win_min.rffd == 0) && (best_win_max.rffd == 0) &&
- (best_win_min.rqfd == 0) && (best_win_max.rqfd == 0)) {
- passed = 0;
- }
-
- /*
- * Need to program RQDC before RFDC.
- */
- debug("<%s> RQFD Min: 0x%x\n", __func__, loop_win_min.rqfd);
- debug("<%s> RQFD Max: 0x%x\n", __func__, loop_win_max.rqfd);
- rqfd_average = loop_win_max.rqfd;
-
- if (rqfd_average < 0)
- rqfd_average = 0;
-
- if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
- rqfd_average = SDRAM_RQDC_RQFD_MAX;
-
- debug("<%s> RFFD average: 0x%08x\n", __func__, rqfd_average);
- mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
- SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
-
- debug("<%s> RFFD Min: 0x%08x\n", __func__, loop_win_min.rffd);
- debug("<%s> RFFD Max: 0x%08x\n", __func__, loop_win_max.rffd);
- rffd_average = ((loop_win_min.rffd + loop_win_max.rffd) / 2);
-
- if (rffd_average < 0)
- rffd_average = 0;
-
- if (rffd_average > SDRAM_RFDC_RFFD_MAX)
- rffd_average = SDRAM_RFDC_RFFD_MAX;
-
- debug("<%s> RFFD average: 0x%08x\n", __func__, rffd_average);
- mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
-
- /* if something passed, then return the size of the largest window */
- if (passed != 0) {
- passed = loop_win_max.rffd - loop_win_min.rffd;
- cal->rqfd = rqfd_average;
- cal->rffd = rffd_average;
- cal->rffd_min = loop_win_min.rffd;
- cal->rffd_max = loop_win_max.rffd;
- }
-
- return (u32)passed;
-}
-
-#else /* !defined(CONFIG_PPC4xx_DDR_METHOD_A) */
-
-/*-----------------------------------------------------------------------------+
-| program_DQS_calibration_methodB.
-+-----------------------------------------------------------------------------*/
-static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal)
-{
- u32 pass_result = 0;
-
-#ifdef DEBUG
- ulong temp;
-#endif
-
- /*
- * Program RDCC register
- * Read sample cycle auto-update enable
- */
- mtsdram(SDRAM_RDCC,
- ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
-
-#ifdef DEBUG
- mfsdram(SDRAM_RDCC, temp);
- debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp);
-#endif
-
- /*
- * Program RQDC register
- * Internal DQS delay mechanism enable
- */
- mtsdram(SDRAM_RQDC,
-#if defined(CONFIG_DDR_RQDC_START_VAL)
- SDRAM_RQDC_RQDE_ENABLE |
- SDRAM_RQDC_RQFD_ENCODE(CONFIG_DDR_RQDC_START_VAL));
-#else
- SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x38));
-#endif
-
-#ifdef DEBUG
- mfsdram(SDRAM_RQDC, temp);
- debug("<%s>SDRAM_RQDC=0x%08x\n", __func__, temp);
-#endif
-
- /*
- * Program RFDC register
- * Set Feedback Fractional Oversample
- * Auto-detect read sample cycle enable
- */
- mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE |
- SDRAM_RFDC_RFOS_ENCODE(0) |
- SDRAM_RFDC_RFFD_ENCODE(0));
-
-#ifdef DEBUG
- mfsdram(SDRAM_RFDC, temp);
- debug("<%s>SDRAM_RFDC=0x%08x\n", __func__, temp);
-#endif
-
- pass_result = DQS_calibration_methodB(ddrcal);
-
- return pass_result;
-}
-
-/*
- * DQS_calibration_methodB()
- *
- * Autocalibration Method B
- *
- * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros
- * ARRAY [Entire Feedback Range] FDBK_Valid_Window; initialized to all zeros
- * MEMWRITE(addr, expected_data);
- * Initialialize the DQS delay to 80 degrees (MCIF0_RRQDC[RQFD]=0x38).
- *
- * for (j = 0; j < Entire Feedback Range; j++) {
- * MEMREAD(addr, actual_data);
- * if (actual_data == expected_data) {
- * FDBK_Valid_Window[j] = 1;
- * }
- * }
- *
- * Set MCIF0_RFDC[RFFD] to the middle of the FDBK_Valid_Window.
- *
- * for (i = 0; i < Entire DQS Range; i++) {
- * MEMREAD(addr, actual_data);
- * if (actual_data == expected_data) {
- * DQS_Valid_Window[i] = 1;
- * }
- * }
- *
- * Set MCIF0_RRQDC[RQFD] to the middle of the DQS_Valid_Window.
- */
-/*-----------------------------------------------------------------------------+
-| DQS_calibration_methodB.
-+-----------------------------------------------------------------------------*/
-static u32 DQS_calibration_methodB(struct ddrautocal *cal)
-{
- ulong rfdc_reg;
-#ifndef CONFIG_DDR_RFDC_FIXED
- ulong rffd;
-#endif
-
- ulong rqdc_reg;
- ulong rqfd;
-
- ulong rdcc;
-
- u32 *membase;
- ulong bxcf;
- int rqfd_average;
- int bxcr_num;
- int rffd_average;
- int pass;
- uint passed = 0;
-
- int in_window;
- u32 curr_win_min, curr_win_max;
- u32 best_win_min, best_win_max;
- u32 size = 0;
-
- /*------------------------------------------------------------------
- | Test to determine the best read clock delay tuning bits.
- |
- | Before the DDR controller can be used, the read clock delay needs to
- | be set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
- | This value cannot be hardcoded into the program because it changes
- | depending on the board's setup and environment.
- | To do this, all delay values are tested to see if they
- | work or not. By doing this, you get groups of fails with groups of
- | passing values. The idea is to find the start and end of a passing
- | window and take the center of it to use as the read clock delay.
- |
- | A failure has to be seen first so that when we hit a pass, we know
- | that it is truely the start of the window. If we get passing values
- | to start off with, we don't know if we are at the start of the window
- |
- | The code assumes that a failure will always be found.
- | If a failure is not found, there is no easy way to get the middle
- | of the passing window. I guess we can pretty much pick any value
- | but some values will be better than others. Since the lowest speed
- | we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
- | from experimentation it is safe to say you will always have a failure
- +-----------------------------------------------------------------*/
-
- debug("\n\n");
-
-#if defined(CONFIG_DDR_RFDC_FIXED)
- mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
- size = 512;
- rffd_average = CONFIG_DDR_RFDC_FIXED & SDRAM_RFDC_RFFD_MASK;
- mfsdram(SDRAM_RDCC, rdcc); /* record this value */
- cal->rdcc = rdcc;
-#else /* CONFIG_DDR_RFDC_FIXED */
- in_window = 0;
- rdcc = 0;
-
- curr_win_min = curr_win_max = 0;
- best_win_min = best_win_max = 0;
- for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
- mfsdram(SDRAM_RFDC, rfdc_reg);
- rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
- mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
-
- pass = 1;
- for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
- mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
-
- /* Banks enabled */
- if (bxcf & SDRAM_BXCF_M_BE_MASK) {
- /* Bank is enabled */
- membase = get_membase(bxcr_num);
- pass &= short_mem_test(membase);
- } /* if bank enabled */
- } /* for bxcf_num */
-
- /* If this value passed */
- if (pass && !in_window) { /* start of passing window */
- in_window = 1;
- curr_win_min = curr_win_max = rffd;
- mfsdram(SDRAM_RDCC, rdcc); /* record this value */
- } else if (!pass && in_window) { /* end passing window */
- in_window = 0;
- } else if (pass && in_window) { /* within the passing window */
- curr_win_max = rffd;
- }
-
- if (in_window) {
- if ((curr_win_max - curr_win_min) >
- (best_win_max - best_win_min)) {
- best_win_min = curr_win_min;
- best_win_max = curr_win_max;
- cal->rdcc = rdcc;
- }
- passed = 1;
- }
- } /* for rffd */
-
- if ((best_win_min == 0) && (best_win_max == 0))
- passed = 0;
- else
- size = best_win_max - best_win_min;
-
- debug("RFFD Min: 0x%x\n", best_win_min);
- debug("RFFD Max: 0x%x\n", best_win_max);
- rffd_average = ((best_win_min + best_win_max) / 2);
-
- cal->rffd_min = best_win_min;
- cal->rffd_max = best_win_max;
-
- if (rffd_average < 0)
- rffd_average = 0;
-
- if (rffd_average > SDRAM_RFDC_RFFD_MAX)
- rffd_average = SDRAM_RFDC_RFFD_MAX;
-
- mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
-#endif /* CONFIG_DDR_RFDC_FIXED */
-
- in_window = 0;
-
- curr_win_min = curr_win_max = 0;
- best_win_min = best_win_max = 0;
- for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
- mfsdram(SDRAM_RQDC, rqdc_reg);
- rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
- mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
-
- pass = 1;
- for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
-
- mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
-
- /* Banks enabled */
- if (bxcf & SDRAM_BXCF_M_BE_MASK) {
- /* Bank is enabled */
- membase = get_membase(bxcr_num);
- pass &= short_mem_test(membase);
- } /* if bank enabled */
- } /* for bxcf_num */
-
- /* If this value passed */
- if (pass && !in_window) {
- in_window = 1;
- curr_win_min = curr_win_max = rqfd;
- } else if (!pass && in_window) {
- in_window = 0;
- } else if (pass && in_window) {
- curr_win_max = rqfd;
- }
-
- if (in_window) {
- if ((curr_win_max - curr_win_min) >
- (best_win_max - best_win_min)) {
- best_win_min = curr_win_min;
- best_win_max = curr_win_max;
- }
- passed = 1;
- }
- } /* for rqfd */
-
- if ((best_win_min == 0) && (best_win_max == 0))
- passed = 0;
-
- debug("RQFD Min: 0x%x\n", best_win_min);
- debug("RQFD Max: 0x%x\n", best_win_max);
- rqfd_average = ((best_win_min + best_win_max) / 2);
-
- if (rqfd_average < 0)
- rqfd_average = 0;
-
- if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
- rqfd_average = SDRAM_RQDC_RQFD_MAX;
-
- mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
- SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
-
- mfsdram(SDRAM_RQDC, rqdc_reg);
- mfsdram(SDRAM_RFDC, rfdc_reg);
-
- /*
- * Need to program RQDC before RFDC. The value is read above.
- * That is the reason why auto cal not work.
- * See, comments below.
- */
- mtsdram(SDRAM_RQDC, rqdc_reg);
- mtsdram(SDRAM_RFDC, rfdc_reg);
-
- debug("RQDC: 0x%08lX\n", rqdc_reg);
- debug("RFDC: 0x%08lX\n", rfdc_reg);
-
- /* if something passed, then return the size of the largest window */
- if (passed != 0) {
- passed = size;
- cal->rqfd = rqfd_average;
- cal->rffd = rffd_average;
- }
-
- return (uint)passed;
-}
-#endif /* defined(CONFIG_PPC4xx_DDR_METHOD_A) */
-
-/*
- * Default table for DDR auto-calibration of all
- * possible WRDTR and CLKTR values.
- * Table format is:
- * {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]}
- *
- * Table is terminated with {-1, -1} value pair.
- *
- * Board vendors can specify their own board specific subset of
- * known working {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} value
- * pairs via a board defined ddr_scan_option() function.
- */
-static struct sdram_timing full_scan_options[] = {
- {0, 0}, {0, 1}, {0, 2}, {0, 3},
- {1, 0}, {1, 1}, {1, 2}, {1, 3},
- {2, 0}, {2, 1}, {2, 2}, {2, 3},
- {3, 0}, {3, 1}, {3, 2}, {3, 3},
- {4, 0}, {4, 1}, {4, 2}, {4, 3},
- {5, 0}, {5, 1}, {5, 2}, {5, 3},
- {6, 0}, {6, 1}, {6, 2}, {6, 3},
- {-1, -1}
-};
-
-/*---------------------------------------------------------------------------+
-| DQS_calibration.
-+----------------------------------------------------------------------------*/
-u32 DQS_autocalibration(void)
-{
- u32 wdtr;
- u32 clkp;
- u32 result = 0;
- u32 best_result = 0;
- u32 best_rdcc;
- struct ddrautocal ddrcal;
- struct autocal_clks tcal;
- ulong rfdc_reg;
- ulong rqdc_reg;
- u32 val;
- int verbose_lvl = 0;
- char *str;
- char slash[] = "\\|/-\\|/-";
- int loopi = 0;
- struct sdram_timing *scan_list;
-
-#if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
- int i;
- char tmp[64]; /* long enough for environment variables */
-#endif
-
- memset(&tcal, 0, sizeof(tcal));
-
- scan_list = ddr_scan_option(full_scan_options);
-
- mfsdram(SDRAM_MCOPT1, val);
- if ((val & SDRAM_MCOPT1_MCHK_CHK_REP) == SDRAM_MCOPT1_MCHK_CHK_REP)
- str = "ECC Auto calibration -";
- else
- str = "Auto calibration -";
-
- puts(str);
-
-#if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
- i = getenv_f("autocalib", tmp, sizeof(tmp));
- if (i < 0)
- strcpy(tmp, CONFIG_AUTOCALIB);
-
- if (strcmp(tmp, "final") == 0) {
- /* display the final autocalibration results only */
- verbose_lvl = 1;
- } else if (strcmp(tmp, "loop") == 0) {
- /* display summary autocalibration info per iteration */
- verbose_lvl = 2;
- } else if (strcmp(tmp, "display") == 0) {
- /* display full debug autocalibration window info. */
- verbose_lvl = 3;
- }
-#endif /* (DEBUG_PPC4xx_DDR_AUTOCALIBRATION) */
-
- best_rdcc = (SDRAM_RDCC_RDSS_T4 >> 30);
-
- while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) {
- wdtr = scan_list->wrdtr;
- clkp = scan_list->clktr;
-
- mfsdram(SDRAM_WRDTR, val);
- val &= ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK);
- mtsdram(SDRAM_WRDTR, (val |
- ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | (wdtr << 25))));
-
- mtsdram(SDRAM_CLKTR, clkp << 30);
-
- relock_memory_DLL();
-
- putc('\b');
- putc(slash[loopi++ % 8]);
-
-#ifdef DEBUG
- debug("\n");
- debug("*** --------------\n");
- mfsdram(SDRAM_WRDTR, val);
- debug("*** SDRAM_WRDTR set to 0x%08x\n", val);
- mfsdram(SDRAM_CLKTR, val);
- debug("*** SDRAM_CLKTR set to 0x%08x\n", val);
-#endif
-
- debug("\n");
- if (verbose_lvl > 2) {
- printf("*** SDRAM_WRDTR (wdtr) set to %d\n", wdtr);
- printf("*** SDRAM_CLKTR (clkp) set to %d\n", clkp);
- }
-
- memset(&ddrcal, 0, sizeof(ddrcal));
-
- /*
- * DQS calibration.
- */
- /*
- * program_DQS_calibration_method[A|B]() returns 0 if no
- * passing RFDC.[RFFD] window is found or returns the size
- * of the best passing window; in the case of a found passing
- * window, the ddrcal will contain the values of the best
- * window RQDC.[RQFD] and RFDC.[RFFD].
- */
-
- /*
- * Call PPC4xx SDRAM DDR autocalibration methodA or methodB.
- * Default is methodB.
- * Defined the autocalibration method in the board specific
- * header file.
- * Please see include/configs/kilauea.h for an example for
- * a board specific implementation.
- */
-#if defined(CONFIG_PPC4xx_DDR_METHOD_A)
- result = program_DQS_calibration_methodA(&ddrcal);
-#else
- result = program_DQS_calibration_methodB(&ddrcal);
-#endif
-
- sync();
-
- /*
- * Clear potential errors resulting from auto-calibration.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- val = ddrcal.rdcc; /* RDCC from the best passing window */
-
- udelay(100);
-
- if (verbose_lvl > 1) {
- char *tstr;
- switch ((val >> 30)) {
- case 0:
- if (result != 0)
- tstr = "T1";
- else
- tstr = "N/A";
- break;
- case 1:
- tstr = "T2";
- break;
- case 2:
- tstr = "T3";
- break;
- case 3:
- tstr = "T4";
- break;
- default:
- tstr = "unknown";
- break;
- }
- printf("** WRDTR(%d) CLKTR(%d), Wind (%d), best (%d), "
- "max-min(0x%04x)(0x%04x), RDCC: %s\n",
- wdtr, clkp, result, best_result,
- ddrcal.rffd_min, ddrcal.rffd_max, tstr);
- }
-
- /*
- * The DQS calibration "result" is either "0"
- * if no passing window was found, or is the
- * size of the RFFD passing window.
- */
- /*
- * want the lowest Read Sample Cycle Select
- */
- val = SDRAM_RDCC_RDSS_DECODE(val);
- debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
- val, best_rdcc);
-
- if ((result != 0) &&
- (val >= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2))) {
- if (((result == best_result) && (val < best_rdcc)) ||
- ((result > best_result) && (val <= best_rdcc))) {
- tcal.autocal.flags = 1;
- debug("*** (%d)(%d) result passed window "
- "size: 0x%08x, rqfd = 0x%08x, "
- "rffd = 0x%08x, rdcc = 0x%08x\n",
- wdtr, clkp, result, ddrcal.rqfd,
- ddrcal.rffd, ddrcal.rdcc);
-
- /*
- * Save the SDRAM_WRDTR and SDRAM_CLKTR
- * settings for the largest returned
- * RFFD passing window size.
- */
- best_rdcc = val;
- tcal.clocks.wrdtr = wdtr;
- tcal.clocks.clktr = clkp;
- tcal.clocks.rdcc = SDRAM_RDCC_RDSS_ENCODE(val);
- tcal.autocal.rqfd = ddrcal.rqfd;
- tcal.autocal.rffd = ddrcal.rffd;
- best_result = result;
-
- if (verbose_lvl > 2) {
- printf("** (%d)(%d) "
- "best result: 0x%04x\n",
- wdtr, clkp,
- best_result);
- printf("** (%d)(%d) "
- "best WRDTR: 0x%04x\n",
- wdtr, clkp,
- tcal.clocks.wrdtr);
- printf("** (%d)(%d) "
- "best CLKTR: 0x%04x\n",
- wdtr, clkp,
- tcal.clocks.clktr);
- printf("** (%d)(%d) "
- "best RQDC: 0x%04x\n",
- wdtr, clkp,
- tcal.autocal.rqfd);
- printf("** (%d)(%d) "
- "best RFDC: 0x%04x\n",
- wdtr, clkp,
- tcal.autocal.rffd);
- printf("** (%d)(%d) "
- "best RDCC: 0x%08x\n",
- wdtr, clkp,
- (u32)tcal.clocks.rdcc);
- mfsdram(SDRAM_RTSR, val);
- printf("** (%d)(%d) best "
- "loop RTSR: 0x%08x\n",
- wdtr, clkp, val);
- mfsdram(SDRAM_FCSR, val);
- printf("** (%d)(%d) best "
- "loop FCSR: 0x%08x\n",
- wdtr, clkp, val);
- }
- }
- } /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */
- scan_list++;
- } /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */
-
- if (tcal.autocal.flags == 1) {
- if (verbose_lvl > 0) {
- printf("*** --------------\n");
- printf("*** best_result window size: %d\n",
- best_result);
- printf("*** best_result WRDTR: 0x%04x\n",
- tcal.clocks.wrdtr);
- printf("*** best_result CLKTR: 0x%04x\n",
- tcal.clocks.clktr);
- printf("*** best_result RQFD: 0x%04x\n",
- tcal.autocal.rqfd);
- printf("*** best_result RFFD: 0x%04x\n",
- tcal.autocal.rffd);
- printf("*** best_result RDCC: 0x%04x\n",
- tcal.clocks.rdcc);
- printf("*** --------------\n");
- printf("\n");
- }
-
- /*
- * if got best passing result window, then lock in the
- * best CLKTR, WRDTR, RQFD, and RFFD values
- */
- mfsdram(SDRAM_WRDTR, val);
- mtsdram(SDRAM_WRDTR, (val &
- ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
- ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC |
- (tcal.clocks.wrdtr << 25)));
-
- mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
-
- relock_memory_DLL();
-
- mfsdram(SDRAM_RQDC, rqdc_reg);
- rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
- mtsdram(SDRAM_RQDC, rqdc_reg |
- SDRAM_RQDC_RQFD_ENCODE(tcal.autocal.rqfd));
-
- mfsdram(SDRAM_RQDC, rqdc_reg);
- debug("*** best_result: read value SDRAM_RQDC 0x%08lx\n",
- rqdc_reg);
-
-#if defined(CONFIG_DDR_RFDC_FIXED)
- mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
-#else /* CONFIG_DDR_RFDC_FIXED */
- mfsdram(SDRAM_RFDC, rfdc_reg);
- rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
- mtsdram(SDRAM_RFDC, rfdc_reg |
- SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd));
-#endif /* CONFIG_DDR_RFDC_FIXED */
-
- mfsdram(SDRAM_RFDC, rfdc_reg);
- debug("*** best_result: read value SDRAM_RFDC 0x%08lx\n",
- rfdc_reg);
- mfsdram(SDRAM_RDCC, val);
- debug("*** SDRAM_RDCC 0x%08x\n", val);
- } else {
- /*
- * no valid windows were found
- */
- printf("DQS memory calibration window can not be determined, "
- "terminating u-boot.\n");
- ppc4xx_ibm_ddr2_register_dump();
- spd_ddr_init_hang();
- }
-
- blank_string(strlen(str));
-
- return 0;
-}
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- *
- * File Name: 405gp_pci.c
- *
- * Function: Initialization code for the 405GP PCI Configuration regs.
- *
- * Author: Mark Game
- *
- * Change Activity-
- *
- * Date Description of Change BY
- * --------- --------------------- ---
- * 09-Sep-98 Created MCG
- * 02-Nov-98 Removed External arbiter selected message JWB
- * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
- * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
- * from (0 to n) to (1 to n).
- * 17-May-99 Port to Walnut JWB
- * 17-Jun-99 Updated for VGA support JWB
- * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
- * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
- * target latency timer values are not supported).
- * Should be fixed in pass 2.
- * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
- * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
- * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
- * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
- * really required after a reset since PMMxMAs are already
- * disabled but is a good practice nonetheless. JWB
- * 12-Jun-01 stefan.roese@esd-electronics.com
- * - PCI host/adapter handling reworked
- * 09-Jul-01 stefan.roese@esd-electronics.com
- * - PCI host now configures from device 0 (not 1) to max_dev,
- * (host configures itself)
- * - On CPCI-405 pci base address and size is generated from
- * SDRAM and FLASH size (CFG regs not used anymore)
- * - Some minor changes for CPCI-405-A (adapter version)
- * 14-Sep-01 stefan.roese@esd-electronics.com
- * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
- * 28-Sep-01 stefan.roese@esd-electronics.com
- * - Changed pci master configuration for linux compatibility
- * (no need for bios_fixup() anymore)
- * 26-Feb-02 stefan.roese@esd-electronics.com
- * - Bug fixed in pci configuration (Andrew May)
- * - Removed pci class code init for CPCI405 board
- * 15-May-02 stefan.roese@esd-electronics.com
- * - New vga device handling
- * 29-May-02 stefan.roese@esd-electronics.com
- * - PCI class code init added (if defined)
- *----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <command.h>
-#include <asm/4xx_pci.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <asm/ppc4xx.h>
-
-#ifdef CONFIG_PCI
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
-
-/*#define DEBUG*/
-
-/*
- * Board-specific pci initialization
- * Platform code can reimplement pci_pre_init() if needed
- */
-int __pci_pre_init(struct pci_controller *hose)
-{
-#if defined(CONFIG_405EP)
- /*
- * Enable the internal PCI arbiter by default.
- *
- * On 405EP CPUs the internal arbiter can be controlled
- * by the I2C strapping EEPROM. If you want to do so
- * or if you want to disable the arbiter pci_pre_init()
- * must be reimplemented without enabling the arbiter.
- * The arbiter is enabled in this place because of
- * compatibility reasons.
- */
- mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
-#endif /* CONFIG_405EP */
-
- return 1;
-}
-int pci_pre_init(struct pci_controller *hose)
- __attribute__((weak, alias("__pci_pre_init")));
-
-int __is_pci_host(struct pci_controller *hose)
-{
-#if defined(CONFIG_405GP)
- if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
- return 1;
-#elif defined (CONFIG_405EP)
- if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
- return 1;
-#endif
- return 0;
-}
-int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
-
-/*-----------------------------------------------------------------------------+
- * pci_init. Initializes the 405GP PCI Configuration regs.
- *-----------------------------------------------------------------------------*/
-void pci_405gp_init(struct pci_controller *hose)
-{
- int i, reg_num = 0;
- bd_t *bd = gd->bd;
-
- unsigned short temp_short;
- unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
-#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
- char *ptmla_str, *ptmms_str;
-#endif
- unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
- unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
-#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
- || defined(CONFIG_TARGET_MIP405T)
- unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
- unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
- unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
- unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
-#else
- unsigned long pmmla[3] = {0x80000000, 0,0};
- unsigned long pmmma[3] = {0xC0000001, 0,0};
- unsigned long pmmpcila[3] = {0x80000000, 0,0};
- unsigned long pmmpciha[3] = {0x00000000, 0,0};
-#endif
-#ifdef CONFIG_PCI_PNP
-#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
- char *s;
-#endif
-#endif
-
-#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
- ptmla_str = getenv("ptm1la");
- ptmms_str = getenv("ptm1ms");
- if(NULL != ptmla_str && NULL != ptmms_str ) {
- ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
- ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
- }
-
- ptmla_str = getenv("ptm2la");
- ptmms_str = getenv("ptm2ms");
- if(NULL != ptmla_str && NULL != ptmms_str ) {
- ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
- ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
- }
-#endif
-
- /*
- * Register the hose
- */
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* ISA/PCI I/O space */
- pci_set_region(hose->regions + reg_num++,
- MIN_PCI_PCI_IOADDR,
- MIN_PLB_PCI_IOADDR,
- 0x10000,
- PCI_REGION_IO);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + reg_num++,
- 0x00800000,
- 0xe8800000,
- 0x03800000,
- PCI_REGION_IO);
-
- reg_num = 2;
-
- /* Memory spaces */
- for (i=0; i<2; i++)
- if (ptmms[i] & 1)
- {
- if (!i) hose->pci_fb = hose->regions + reg_num;
-
- pci_set_region(hose->regions + reg_num++,
- ptmpcila[i], ptmla[i],
- ~(ptmms[i] & 0xfffff000) + 1,
- PCI_REGION_MEM |
- PCI_REGION_SYS_MEMORY);
- }
-
- /* PCI memory spaces */
- for (i=0; i<3; i++)
- if (pmmma[i] & 1)
- {
- pci_set_region(hose->regions + reg_num++,
- pmmpcila[i], pmmla[i],
- ~(pmmma[i] & 0xfffff000) + 1,
- PCI_REGION_MEM);
- }
-
- hose->region_count = reg_num;
-
- pci_setup_indirect(hose,
- PCICFGADR,
- PCICFGDATA);
-
- if (hose->pci_fb)
- pciauto_region_init(hose->pci_fb);
-
- /* Let board change/modify hose & do initial checks */
- if (pci_pre_init(hose) == 0) {
- printf("PCI: Board-specific initialization failed.\n");
- printf("PCI: Configuration aborted.\n");
- return;
- }
-
- pci_register_hose(hose);
-
- /*--------------------------------------------------------------------------+
- * 405GP PCI Master configuration.
- * Map one 512 MB range of PLB/processor addresses to PCI memory space.
- * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
- * Use byte reversed out routines to handle endianess.
- *--------------------------------------------------------------------------*/
- out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
- out32r(PMM0LA, pmmla[0]);
- out32r(PMM0PCILA, pmmpcila[0]);
- out32r(PMM0PCIHA, pmmpciha[0]);
- out32r(PMM0MA, pmmma[0]);
-
- /*--------------------------------------------------------------------------+
- * PMM1 is not used. Initialize them to zero.
- *--------------------------------------------------------------------------*/
- out32r(PMM1MA, (pmmma[1]&~0x1));
- out32r(PMM1LA, pmmla[1]);
- out32r(PMM1PCILA, pmmpcila[1]);
- out32r(PMM1PCIHA, pmmpciha[1]);
- out32r(PMM1MA, pmmma[1]);
-
- /*--------------------------------------------------------------------------+
- * PMM2 is not used. Initialize them to zero.
- *--------------------------------------------------------------------------*/
- out32r(PMM2MA, (pmmma[2]&~0x1));
- out32r(PMM2LA, pmmla[2]);
- out32r(PMM2PCILA, pmmpcila[2]);
- out32r(PMM2PCIHA, pmmpciha[2]);
- out32r(PMM2MA, pmmma[2]);
-
- /*--------------------------------------------------------------------------+
- * 405GP PCI Target configuration. (PTM1)
- * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
- *--------------------------------------------------------------------------*/
- out32r(PTM1LA, ptmla[0]); /* insert address */
- out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
- pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
-
- /*--------------------------------------------------------------------------+
- * 405GP PCI Target configuration. (PTM2)
- *--------------------------------------------------------------------------*/
- out32r(PTM2LA, ptmla[1]); /* insert address */
- pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
-
- if (ptmms[1] == 0)
- {
- out32r(PTM2MS, 0x00000001); /* set enable bit */
- pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
- out32r(PTM2MS, 0x00000000); /* disable */
- }
- else
- {
- out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
- }
-
- /*
- * Insert Subsystem Vendor and Device ID
- */
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-#ifdef CONFIG_CPCI405
- if (is_pci_host(hose))
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
- else
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
-#else
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-#endif
-
- /*
- * Insert Class-code
- */
-#ifdef CONFIG_SYS_PCI_CLASSCODE
- pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
-#endif /* CONFIG_SYS_PCI_CLASSCODE */
-
- /*--------------------------------------------------------------------------+
- * If PCI speed = 66MHz, set 66MHz capable bit.
- *--------------------------------------------------------------------------*/
- if (bd->bi_pci_busfreq >= 66000000) {
- pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
- pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
- }
-
-#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
-#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
- if (is_pci_host(hose) ||
- (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
-#endif
- {
- /*--------------------------------------------------------------------------+
- * Write the 405GP PCI Configuration regs.
- * Enable 405GP to be a master on the PCI bus (PMM).
- * Enable 405GP to act as a PCI memory target (PTM).
- *--------------------------------------------------------------------------*/
- pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
- pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- }
-#endif
-
-#if defined(CONFIG_405EP)
- /*
- * on ppc405ep vendor/device id is not set
- * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
- * are the correct values.
- */
- pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
- pci_write_config_word(PCIDEVID_405GP,
- PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
-#endif
-
- /*
- * Set HCE bit (Host Configuration Enabled)
- */
- pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
- pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
-
-#ifdef CONFIG_PCI_PNP
- /*--------------------------------------------------------------------------+
- * Scan the PCI bus and configure devices found.
- *--------------------------------------------------------------------------*/
-#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
- if (is_pci_host(hose) ||
- (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
-#endif
- {
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- hose->last_busno = pci_hose_scan(hose);
- }
-#endif /* CONFIG_PCI_PNP */
-
-}
-
-/*
- * drivers/pci/pci.c skips every host bridge but the 405GP since it could
- * be set as an Adapter.
- *
- * I (Andrew May) don't know what we should do here, but I don't want
- * the auto setup of a PCI device disabling what is done pci_405gp_init
- * as has happened before.
- */
-void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *entry)
-{
-#ifdef DEBUG
- printf("405gp_setup_bridge\n");
-#endif
-}
-
-/*
- *
- */
-
-void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char int_line = 0xff;
-
- /*
- * Write pci interrupt line register (cpci405 specific)
- */
- switch (PCI_DEV(dev) & 0x03)
- {
- case 0:
- int_line = 27 + 2;
- break;
- case 1:
- int_line = 27 + 3;
- break;
- case 2:
- int_line = 27 + 0;
- break;
- case 3:
- int_line = 27 + 1;
- break;
- }
-
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
-}
-
-void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *entry)
-{
- unsigned int cmdstat = 0;
-
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
-
- /* always enable io space on vga boards */
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
- cmdstat |= PCI_COMMAND_IO;
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
-}
-
-#if !(defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
- || defined(CONFIG_TARGET_MIP405T))
-
-/*
- *As is these functs get called out of flash Not a horrible
- *thing, but something to keep in mind. (no statics?)
- */
-static struct pci_config_table pci_405gp_config_table[] = {
-/*if VendID is 0 it terminates the table search (ie Walnut)*/
-#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
- {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
-#endif
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
-
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
-
- { }
-};
-
-static struct pci_controller hose = {
- fixup_irq: pci_405gp_fixup_irq,
- config_table: pci_405gp_config_table,
-};
-
-void pci_init_board(void)
-{
- /*we want the ptrs to RAM not flash (ie don't use init list)*/
- hose.fixup_irq = pci_405gp_fixup_irq;
- hose.config_table = pci_405gp_config_table;
- pci_405gp_init(&hose);
-}
-
-#endif
-
-#endif /* CONFIG_405GP */
-
-/*-----------------------------------------------------------------------------+
- * CONFIG_440
- *-----------------------------------------------------------------------------*/
-#if defined(CONFIG_440)
-
-#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
-static struct pci_controller ppc440_hose = {0};
-#endif
-
-/*
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- * Weak default implementation: "Normal" boards implement the PCI
- * host functionality. This can be overridden for PCI adapter boards.
- */
-int __is_pci_host(struct pci_controller *hose)
-{
- return 1;
-}
-int is_pci_host(struct pci_controller *hose)
- __attribute__((weak, alias("__is_pci_host")));
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRX)
-
-#if defined(CONFIG_SYS_PCI_TARGET_INIT)
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-void __pci_target_init(struct pci_controller *hose)
-{
- /*
- * Set up Direct MMIO registers
- */
-
- /*
- * PowerPC440 EP PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- /* PMM0 Mask/Attribute - disabled b4 setting */
- out_le32((void *)PCIL0_PMM0MA, 0x00000000);
- /* PMM0 Local Address */
- out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
- /* PMM0 PCI Low Address */
- out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
- /* PMM0 PCI High Address */
- out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
- /* 512M + No prefetching, and enable region */
- out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
-
- /* PMM1 Mask/Attribute - disabled b4 setting */
- out_le32((void *)PCIL0_PMM1MA, 0x00000000);
- /* PMM1 Local Address */
- out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
- /* PMM1 PCI Low Address */
- out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
- /* PMM1 PCI High Address */
- out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
- /* 512M + No prefetching, and enable region */
- out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
-
- out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-}
-#endif /* CONFIG_SYS_PCI_TARGET_INIT */
-
-/*
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- */
-int __pci_pre_init(struct pci_controller *hose)
-{
- u32 reg;
-
- /*
- * Set priority for all PLB3 devices to 0.
- * Set PLB3 arbiter to fair mode.
- */
- mfsdr(SDR0_AMP1, reg);
- mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
- reg = mfdcr(PLB3A0_ACR);
- mtdcr(PLB3A0_ACR, reg | 0x80000000);
-
- /*
- * Set priority for all PLB4 devices to 0.
- */
- mfsdr(SDR0_AMP0, reg);
- mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
- reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
- mtdcr(PLB4A0_ACR, reg);
-
- /*
- * Set Nebula PLB4 arbiter to fair mode.
- */
- /* Segment0 */
- reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
- reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
- reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
- reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
- mtdcr(PLB4A0_ACR, reg);
-
- /* Segment1 */
- reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
- reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
- reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
- reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
- mtdcr(PLB4A1_ACR, reg);
-
-#if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
- hose->fixup_irq = board_pci_fixup_irq;
-#endif
-
- return 1;
-}
-
-#else /* defined(CONFIG_440EP) ... */
-
-#if defined(CONFIG_SYS_PCI_TARGET_INIT)
-void __pci_target_init(struct pci_controller * hose)
-{
- /*
- * Disable everything
- */
- out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
- out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options do not support sizes such as 128/256 MB.
- */
- out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out_le32((void *)PCIL0_PIM0LAH, 0);
- out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out_le32((void *)PCIL0_BAR0, 0);
-
- /*
- * Program the board's subsystem id/vendor id
- */
- out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
- PCI_COMMAND_MEMORY);
-}
-#endif /* CONFIG_SYS_PCI_TARGET_INIT */
-
-int __pci_pre_init(struct pci_controller *hose)
-{
- /*
- * This board is always configured as the host & requires the
- * PCI arbiter to be enabled.
- */
- if (!pci_arbiter_enabled()) {
- printf("PCI: PCI Arbiter disabled!\n");
- return 0;
- }
-
- return 1;
-}
-
-#endif /* defined(CONFIG_440EP) ... */
-
-#if defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose)
- __attribute__((weak, alias("__pci_target_init")));
-#endif /* CONFIG_SYS_PCI_TARGET_INIT */
-
-int pci_pre_init(struct pci_controller *hose)
- __attribute__((weak, alias("__pci_pre_init")));
-
-#if defined(CONFIG_SYS_PCI_MASTER_INIT)
-void __pci_master_init(struct pci_controller *hose)
-{
- u16 reg;
-
- /*
- * Write the PowerPC440 EP PCI Configuration regs.
- * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- * Enable PowerPC440 EP to act as a PCI memory target (PTM).
- */
- pci_read_config_word(0, PCI_COMMAND, ®);
- pci_write_config_word(0, PCI_COMMAND, reg |
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-}
-void pci_master_init(struct pci_controller *hose)
- __attribute__((weak, alias("__pci_master_init")));
-#endif /* CONFIG_SYS_PCI_MASTER_INIT */
-
-#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
-static int pci_440_init (struct pci_controller *hose)
-{
- int reg_num = 0;
-
-#ifndef CONFIG_DISABLE_PISE_TEST
- /*--------------------------------------------------------------------------+
- * The PCI initialization sequence enable bit must be set ... if not abort
- * pci setup since updating the bit requires chip reset.
- *--------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
- unsigned long strap;
-
- mfsdr(SDR0_SDSTP1,strap);
- if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
- printf("PCI: SDR0_STRP1[PISE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return -1;
- }
-#elif defined(CONFIG_440GP)
- unsigned long strap;
-
- strap = mfdcr(CPC0_STRP1);
- if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
- printf("PCI: CPC0_STRP1[PISE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return -1;
- }
-#endif
-#endif /* CONFIG_DISABLE_PISE_TEST */
-
- /*--------------------------------------------------------------------------+
- * PCI controller init
- *--------------------------------------------------------------------------*/
- hose->first_busno = 0;
- hose->last_busno = 0;
-
- /* PCI I/O space */
- pci_set_region(hose->regions + reg_num++,
- 0x00000000,
- PCIL0_IOBASE,
- 0x10000,
- PCI_REGION_IO);
-
- /* PCI memory space */
- pci_set_region(hose->regions + reg_num++,
- CONFIG_SYS_PCI_TARGBASE,
- CONFIG_SYS_PCI_MEMBASE,
-#ifdef CONFIG_SYS_PCI_MEMSIZE
- CONFIG_SYS_PCI_MEMSIZE,
-#else
- 0x10000000,
-#endif
- PCI_REGION_MEM );
-
-#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
- defined(CONFIG_PCI_SYS_MEM_SIZE)
- /* System memory space */
- pci_set_region(hose->regions + reg_num++,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- CONFIG_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
-#endif
-
- hose->region_count = reg_num;
-
- pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
-
- /* Let board change/modify hose & do initial checks */
- if (pci_pre_init(hose) == 0) {
- printf("PCI: Board-specific initialization failed.\n");
- printf("PCI: Configuration aborted.\n");
- return -1;
- }
-
- pci_register_hose( hose );
-
- /*--------------------------------------------------------------------------+
- * PCI target init
- *--------------------------------------------------------------------------*/
-#if defined(CONFIG_SYS_PCI_TARGET_INIT)
- pci_target_init(hose); /* Let board setup pci target */
-#else
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
- out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
-#endif
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
- out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
-#elif defined(PCIL0_BRDGOPT1)
- out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
- out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */
-#endif
-
- /*--------------------------------------------------------------------------+
- * PCI master init: default is one 256MB region for PCI memory:
- * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
- *--------------------------------------------------------------------------*/
-#if defined(CONFIG_SYS_PCI_MASTER_INIT)
- pci_master_init(hose); /* Let board setup pci master */
-#else
- out32r( PCIL0_POM0SA, 0 ); /* disable */
- out32r( PCIL0_POM1SA, 0 ); /* disable */
- out32r( PCIL0_POM2SA, 0 ); /* disable */
-#if defined(CONFIG_440SPE)
- out32r( PCIL0_POM0LAL, 0x10000000 );
- out32r( PCIL0_POM0LAH, 0x0000000c );
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
- out32r( PCIL0_POM0LAL, 0x20000000 );
- out32r( PCIL0_POM0LAH, 0x0000000c );
-#else
- out32r( PCIL0_POM0LAL, 0x00000000 );
- out32r( PCIL0_POM0LAH, 0x00000003 );
-#endif
- out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
- out32r( PCIL0_POM0PCIAH, 0x00000000 );
- out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
- out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
-#endif
-
- /*--------------------------------------------------------------------------+
- * PCI host configuration -- we don't make any assumptions here ... the
- * _board_must_indicate_ what to do -- there's just too many runtime
- * scenarios in environments like cPCI, PPMC, etc. to make a determination
- * based on hard-coded values or state of arbiter enable.
- *--------------------------------------------------------------------------*/
- if (is_pci_host(hose)) {
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
-#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
- !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
- out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
-#endif
- hose->last_busno = pci_hose_scan(hose);
- }
- return hose->last_busno;
-}
-#endif
-
-void pci_init_board(void)
-{
- int busno = 0;
-
- /*
- * Only init PCI when either master or target functionality
- * is selected.
- */
-#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
- busno = pci_440_init(&ppc440_hose);
- if (busno < 0)
- return;
-#endif
-#if (defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
- !defined(CONFIG_PCI_DISABLE_PCIE)
- pcie_setup_hoses(busno + 1);
-#endif
-}
-
-#endif /* CONFIG_440 */
-
-#if defined(CONFIG_405EX)
-void pci_init_board(void)
-{
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- pcie_setup_hoses(0);
-}
-#endif /* CONFIG_405EX */
-
-#endif /* CONFIG_PCI */
+++ /dev/null
-/*
- * (C) Copyright 2006 - 2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (c) 2005 Cisco Systems. All rights reserved.
- * Roland Dreier <rolandd@cisco.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <pci.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-
-#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
- defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE)
-
-#include <asm/4xx_pcie.h>
-
-enum {
- PTYPE_ENDPOINT = 0x0,
- PTYPE_LEGACY_ENDPOINT = 0x1,
- PTYPE_ROOT_PORT = 0x4,
-
- LNKW_X1 = 0x1,
- LNKW_X4 = 0x4,
- LNKW_X8 = 0x8
-};
-
-static struct pci_controller pcie_hose[CONFIG_SYS_PCIE_NR_PORTS];
-
-/*
- * Per default, all cards are present, so we need to check if the
- * link comes up.
- */
-int __board_pcie_card_present(int port)
-{
- return 1;
-}
-int board_pcie_card_present(int port)
- __attribute__((weak, alias("__board_pcie_card_present")));
-
-/*
- * Some boards have runtime detection of the first and last PCIe
- * slot used, so let's provide weak default functions for the
- * common version.
- */
-int __board_pcie_first(void)
-{
- return 0;
-}
-int board_pcie_first(void)
- __attribute__((weak, alias("__board_pcie_first")));
-
-int __board_pcie_last(void)
-{
- return CONFIG_SYS_PCIE_NR_PORTS - 1;
-}
-int board_pcie_last(void)
- __attribute__((weak, alias("__board_pcie_last")));
-
-void __board_pcie_setup_port(int port, int rootpoint)
-{
- /* noting in this weak default implementation */
-}
-void board_pcie_setup_port(int port, int rootpoint)
- __attribute__((weak, alias("__board_pcie_setup_port")));
-
-void pcie_setup_hoses(int busno)
-{
- struct pci_controller *hose;
- int i, bus;
- int ret = 0;
- char *env;
- unsigned int delay;
- int first = board_pcie_first();
- int last = board_pcie_last();
-
- /*
- * Assume we're called after the PCI(X) hose(s) are initialized,
- * which takes bus ID 0... and therefore start numbering PCIe's
- * from the next number.
- */
- bus = busno;
-
- for (i = first; i <= last; i++) {
- /*
- * Some boards (e.g. Katmai) can detects via hardware
- * if a PCIe card is plugged, so let's check this.
- */
- if (!board_pcie_card_present(i))
- continue;
-
- if (is_end_point(i)) {
- board_pcie_setup_port(i, 0);
- ret = ppc4xx_init_pcie_endport(i);
- } else {
- board_pcie_setup_port(i, 1);
- ret = ppc4xx_init_pcie_rootport(i);
- }
- if (ret == -ENODEV)
- continue;
- if (ret) {
- printf("PCIE%d: initialization as %s failed\n", i,
- is_end_point(i) ? "endpoint" : "root-complex");
- continue;
- }
-
- hose = &pcie_hose[i];
- hose->first_busno = bus;
- hose->last_busno = bus;
- hose->current_busno = bus;
-
- /* setup mem resource */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMSIZE,
- PCI_REGION_MEM);
- hose->region_count = 1;
- pci_register_hose(hose);
-
- if (is_end_point(i)) {
- ppc4xx_setup_pcie_endpoint(hose, i);
- /*
- * Reson for no scanning is endpoint can not generate
- * upstream configuration accesses.
- */
- } else {
- ppc4xx_setup_pcie_rootpoint(hose, i);
- env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul(env, NULL, 10);
- if (delay > 5)
- printf("Warning, expect noticable delay before "
- "PCIe scan due to 'pciscandelay' value!\n");
- mdelay(delay * 1000);
- }
-
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
- }
- }
-}
-
-static int validate_endpoint(struct pci_controller *hose)
-{
- if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
- return (is_end_point(0));
- else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE)
- return (is_end_point(1));
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE)
- return (is_end_point(2));
-#endif
-
- return 0;
-}
-
-static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
-{
- u8 *base = (u8*)hose->cfg_data;
-
- /* use local configuration space for the first bus */
- if (PCI_BUS(devfn) == 0) {
- if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE)
- base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE;
- if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE)
- base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE)
- base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE;
-#endif
- }
-
- return base;
-}
-
-static void pcie_dmer_disable(void)
-{
- mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
- mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
-#endif
-}
-
-static void pcie_dmer_enable(void)
-{
- mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
- mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
-#endif
-}
-
-static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
- int offset, int len, u32 *val) {
-
- *val = 0;
-
- if (validate_endpoint(hose))
- return 0; /* No upstream config access */
-
- /*
- * Bus numbers are relative to hose->first_busno
- */
- devfn -= PCI_BDF(hose->first_busno, 0, 0);
-
- /*
- * NOTICE: configuration space ranges are currenlty mapped only for
- * the first 16 buses, so such limit must be imposed. In case more
- * buses are required the TLB settings in board/amcc/<board>/init.S
- * need to be altered accordingly (one bus takes 1 MB of memory space).
- */
- if (PCI_BUS(devfn) >= 16)
- return 0;
-
- /*
- * Only single device/single function is supported for the primary and
- * secondary buses of the 440SPe host bridge.
- */
- if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
- ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
- return 0;
-
- pcie_get_base(hose, devfn);
- offset += devfn << 4;
-
- /*
- * Reading from configuration space of non-existing device can
- * generate transaction errors. For the read duration we suppress
- * assertion of machine check exceptions to avoid those.
- */
- pcie_dmer_disable ();
-
- debug("%s: cfg_data=%p offset=%08x\n", __func__,
- hose->cfg_data, offset);
- switch (len) {
- case 1:
- *val = in_8(hose->cfg_data + offset);
- break;
- case 2:
- *val = in_le16((u16 *)(hose->cfg_data + offset));
- break;
- default:
- *val = in_le32((u32*)(hose->cfg_data + offset));
- break;
- }
-
- pcie_dmer_enable ();
-
- return 0;
-}
-
-static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
- int offset, int len, u32 val) {
-
- if (validate_endpoint(hose))
- return 0; /* No upstream config access */
-
- /*
- * Bus numbers are relative to hose->first_busno
- */
- devfn -= PCI_BDF(hose->first_busno, 0, 0);
-
- /*
- * Same constraints as in pcie_read_config().
- */
- if (PCI_BUS(devfn) >= 16)
- return 0;
-
- if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
- ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
- return 0;
-
- pcie_get_base(hose, devfn);
- offset += devfn << 4;
-
- /*
- * Suppress MCK exceptions, similar to pcie_read_config()
- */
- pcie_dmer_disable ();
-
- switch (len) {
- case 1:
- out_8(hose->cfg_data + offset, val);
- break;
- case 2:
- out_le16((u16 *)(hose->cfg_data + offset), val);
- break;
- default:
- out_le32((u32 *)(hose->cfg_data + offset), val);
- break;
- }
-
- pcie_dmer_enable ();
-
- return 0;
-}
-
-int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
-{
- u32 v;
- int rv;
-
- rv = pcie_read_config(hose, dev, offset, 1, &v);
- *val = (u8)v;
- return rv;
-}
-
-int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
-{
- u32 v;
- int rv;
-
- rv = pcie_read_config(hose, dev, offset, 2, &v);
- *val = (u16)v;
- return rv;
-}
-
-int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
-{
- u32 v;
- int rv;
-
- rv = pcie_read_config(hose, dev, offset, 3, &v);
- *val = (u32)v;
- return rv;
-}
-
-int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
-{
- return pcie_write_config(hose,(u32)dev,offset,1,val);
-}
-
-int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
-{
- return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
-}
-
-int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
-{
- return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
-}
-
-#if defined(CONFIG_440SPE)
-static void ppc4xx_setup_utl(u32 port) {
-
- volatile void *utl_base = NULL;
-
- /*
- * Map UTL registers
- */
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
- break;
-
- case 1:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
- break;
-
- case 2:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
- break;
- }
- utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
-
- /*
- * Set buffer allocations and then assert VRB and TXE.
- */
- out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
- out_be32(utl_base + PEUTL_INTR, 0x02000000);
- out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
- out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
- out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
- out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
- out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
- out_be32(utl_base + PEUTL_PCTL, 0x80800066);
-}
-
-static int check_error(void)
-{
- u32 valPE0, valPE1, valPE2;
- int err = 0;
-
- /* SDR0_PEGPLLLCT1 reset */
- if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000))
- printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
-
- valPE0 = SDR_READ(PESDR0_RCSSET);
- valPE1 = SDR_READ(PESDR1_RCSSET);
- valPE2 = SDR_READ(PESDR2_RCSSET);
-
- /* SDR0_PExRCSSET rstgu */
- if (!(valPE0 & 0x01000000) ||
- !(valPE1 & 0x01000000) ||
- !(valPE2 & 0x01000000)) {
- printf("PCIE: SDR0_PExRCSSET rstgu error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rstdl */
- if (!(valPE0 & 0x00010000) ||
- !(valPE1 & 0x00010000) ||
- !(valPE2 & 0x00010000)) {
- printf("PCIE: SDR0_PExRCSSET rstdl error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rstpyn */
- if ((valPE0 & 0x00001000) ||
- (valPE1 & 0x00001000) ||
- (valPE2 & 0x00001000)) {
- printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET hldplb */
- if ((valPE0 & 0x10000000) ||
- (valPE1 & 0x10000000) ||
- (valPE2 & 0x10000000)) {
- printf("PCIE: SDR0_PExRCSSET hldplb error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rdy */
- if ((valPE0 & 0x00100000) ||
- (valPE1 & 0x00100000) ||
- (valPE2 & 0x00100000)) {
- printf("PCIE: SDR0_PExRCSSET rdy error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET shutdown */
- if ((valPE0 & 0x00000100) ||
- (valPE1 & 0x00000100) ||
- (valPE2 & 0x00000100)) {
- printf("PCIE: SDR0_PExRCSSET shutdown error\n");
- err = -1;
- }
- return err;
-}
-
-/*
- * Initialize PCI Express core
- */
-int ppc4xx_init_pcie(void)
-{
- int time_out = 20;
-
- /* Set PLL clock receiver to LVPECL */
- SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
-
- if (check_error()) {
- printf("ERROR: failed to set PCIe reference clock receiver --"
- "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1));
-
- return -1;
- }
-
- /* Did resistance calibration work? */
- if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
- printf("ERROR: PCIe resistance calibration failed --"
- "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2));
-
- return -1;
- }
- /* De-assert reset of PCIe PLL, wait for lock */
- SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
- udelay(300); /* 300 uS is maximum time lock should take */
-
- while (time_out) {
- if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
- time_out--;
- udelay(20); /* Wait 20 uS more if needed */
- } else
- break;
- }
- if (!time_out) {
- printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
- "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3));
-
- return -1;
- }
- return 0;
-}
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-static void ppc4xx_setup_utl(u32 port)
-{
- volatile void *utl_base = NULL;
-
- /*
- * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK
- */
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
- mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE));
- mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
- break;
-
- case 1:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
- mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)
- + 0x1000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
- break;
- }
- utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
-
- /*
- * Set buffer allocations and then assert VRB and TXE.
- */
- out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */
- out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
- out_be32(utl_base + PEUTL_INTR, 0x02000000);
- out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */
- out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */
- out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000);
- out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */
- out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
- out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */
-}
-
-/*
- * TODO: double check PCI express SDR based on the latest user manual
- * Some registers specified here no longer exist.. has to be
- * updated based on the final EAS spec.
- */
-static int check_error(void)
-{
- u32 valPE0, valPE1;
- int err = 0;
-
- valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0));
- valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1));
-
- /* SDR0_PExRCSSET rstgu */
- if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) {
- printf("PCIE: SDR0_PExRCSSET rstgu error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rstdl */
- if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) {
- printf("PCIE: SDR0_PExRCSSET rstdl error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rstpyn */
- if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) {
- printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET hldplb */
- if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) {
- printf("PCIE: SDR0_PExRCSSET hldplb error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rdy */
- if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) {
- printf("PCIE: SDR0_PExRCSSET rdy error\n");
- err = -1;
- }
-
- return err;
-}
-
-/*
- * Initialize PCI Express core as described in User Manual
- * TODO: double check PE SDR PLL Register with the updated user manual.
- */
-int ppc4xx_init_pcie(void)
-{
- if (check_error())
- return -1;
-
- return 0;
-}
-#endif /* CONFIG_460EX */
-
-#if defined(CONFIG_405EX)
-static void ppc4xx_setup_utl(u32 port)
-{
- u32 utl_base;
-
- /*
- * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
- */
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
- break;
-
- case 1:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
-
- break;
- }
- utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE;
-
- /*
- * Set buffer allocations and then assert VRB and TXE.
- */
- out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000);
- out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000);
- out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
- out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
- out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
- out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
- out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
- out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
-
- out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
- out_be32((u32 *)(utl_base + PEUTL_RCSTA),
- in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
-}
-
-int ppc4xx_init_pcie(void)
-{
- /*
- * Nothing to do on 405EX
- */
- return 0;
-}
-#endif /* CONFIG_405EX */
-
-/*
- * Board-specific pcie initialization
- * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
- */
-
-/*
- * Initialize various parts of the PCI Express core for our port:
- *
- * - Set as a root port and enable max width
- * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
- * - Set up UTL configuration.
- * - Increase SERDES drive strength to levels suggested by AMCC.
- * - De-assert RSTPYN, RSTDL and RSTGU.
- *
- * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
- * with default setting 0x11310000. The register has new fields,
- * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
- * hang.
- */
-#if defined(CONFIG_440SPE)
-int __ppc4xx_init_pcie_port_hw(int port, int rootport)
-{
- u32 val = 1 << 24;
- u32 utlset1;
-
- if (rootport) {
- val = PTYPE_ROOT_PORT << 20;
- utlset1 = 0x21222222;
- } else {
- val = PTYPE_LEGACY_ENDPOINT << 20;
- utlset1 = 0x20222222;
- }
-
- if (port == 0)
- val |= LNKW_X8 << 12;
- else
- val |= LNKW_X4 << 12;
-
- SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
- SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
- if (!ppc440spe_revB())
- SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
- SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
- SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
- SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
- SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
- if (port == 0) {
- SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
- }
- SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
- ~(1 << 24 | 1 << 16)) | 1 << 12);
-
- return 0;
-}
-#endif /* CONFIG_440SPE */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-int __ppc4xx_init_pcie_port_hw(int port, int rootport)
-{
- u32 val;
- u32 utlset1;
-
- if (rootport)
- val = PTYPE_ROOT_PORT << 20;
- else
- val = PTYPE_LEGACY_ENDPOINT << 20;
-
- if (port == 0) {
- val |= LNKW_X1 << 12;
- utlset1 = 0x20000000;
- } else {
- val |= LNKW_X4 << 12;
- utlset1 = 0x20101101;
- }
-
- SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
- SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
- SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000);
-
- switch (port) {
- case 0:
- SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
- SDR_WRITE(PESDR0_L0DRV, 0x00000130);
- SDR_WRITE(PESDR0_L0CLK, 0x00000006);
-
- SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
- break;
-
- case 1:
- SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230);
- SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
- SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
- SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
- SDR_WRITE(PESDR1_L0DRV, 0x00000130);
- SDR_WRITE(PESDR1_L1DRV, 0x00000130);
- SDR_WRITE(PESDR1_L2DRV, 0x00000130);
- SDR_WRITE(PESDR1_L3DRV, 0x00000130);
- SDR_WRITE(PESDR1_L0CLK, 0x00000006);
- SDR_WRITE(PESDR1_L1CLK, 0x00000006);
- SDR_WRITE(PESDR1_L2CLK, 0x00000006);
- SDR_WRITE(PESDR1_L3CLK, 0x00000006);
-
- SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000);
- break;
- }
-
- SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) |
- (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
-
- /* Poll for PHY reset */
- switch (port) {
- case 0:
- while (!(SDR_READ(PESDR0_RSTSTA) & 0x1))
- udelay(10);
- break;
- case 1:
- while (!(SDR_READ(PESDR1_RSTSTA) & 0x1))
- udelay(10);
- break;
- }
-
- SDR_WRITE(SDRN_PESDR_RCSSET(port),
- (SDR_READ(SDRN_PESDR_RCSSET(port)) &
- ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
- PESDRx_RCSSET_RSTPYN);
-
- return 0;
-}
-#endif /* CONFIG_440SPE */
-
-#if defined(CONFIG_405EX)
-int __ppc4xx_init_pcie_port_hw(int port, int rootport)
-{
- u32 val;
-
- if (rootport)
- val = 0x00401000;
- else
- val = 0x00101000;
-
- SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
- SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
- SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
- SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
- SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
-
- /* Assert the PE0_PHY reset */
- SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
- udelay(1000);
-
- /* deassert the PE0_hotreset */
- if (is_end_point(port))
- SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
- else
- SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
-
- /* poll for phy !reset */
- while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
- ;
-
- /* deassert the PE0_gpl_utl_reset */
- SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
-
- if (port == 0)
- mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
- else
- mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
-
- return 0;
-}
-#endif /* CONFIG_405EX */
-
-int ppc4xx_init_pcie_port_hw(int port, int rootport)
-__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
-
-/*
- * We map PCI Express configuration access into the 512MB regions
- *
- * NOTICE: revB is very strict about PLB real addressess and ranges to
- * be mapped for config space; it seems to only work with d_nnnn_nnnn
- * range (hangs the core upon config transaction attempts when set
- * otherwise) while revA uses c_nnnn_nnnn.
- *
- * For 440SPe revA:
- * PCIE0: 0xc_4000_0000
- * PCIE1: 0xc_8000_0000
- * PCIE2: 0xc_c000_0000
- *
- * For 440SPe revB:
- * PCIE0: 0xd_0000_0000
- * PCIE1: 0xd_2000_0000
- * PCIE2: 0xd_4000_0000
- *
- * For 405EX:
- * PCIE0: 0xa000_0000
- * PCIE1: 0xc000_0000
- *
- * For 460EX/GT:
- * PCIE0: 0xd_0000_0000
- * PCIE1: 0xd_2000_0000
- */
-static inline u64 ppc4xx_get_cfgaddr(int port)
-{
-#if defined(CONFIG_405EX)
- if (port == 0)
- return (u64)CONFIG_SYS_PCIE0_CFGBASE;
- else
- return (u64)CONFIG_SYS_PCIE1_CFGBASE;
-#endif
-#if defined(CONFIG_440SPE)
- if (ppc440spe_revB()) {
- switch (port) {
- default: /* to satisfy compiler */
- case 0:
- return 0x0000000d00000000ULL;
- case 1:
- return 0x0000000d20000000ULL;
- case 2:
- return 0x0000000d40000000ULL;
- }
- } else {
- switch (port) {
- default: /* to satisfy compiler */
- case 0:
- return 0x0000000c40000000ULL;
- case 1:
- return 0x0000000c80000000ULL;
- case 2:
- return 0x0000000cc0000000ULL;
- }
- }
-#endif
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- if (port == 0)
- return 0x0000000d00000000ULL;
- else
- return 0x0000000d20000000ULL;
-#endif
-}
-
-/*
- * 4xx boards as endpoint and root point setup
- * and
- * testing inbound and out bound windows
- *
- * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
- * cable which can be used to setup loop back from one port to another port.
- * Please rememeber that unless there is a endpoint plugged in to root port it
- * will not initialize. It is the same in case of endpoint , unless there is
- * root port attached it will not initialize.
- *
- * In this release of software all the PCI-E ports are configured as either
- * endpoint or rootpoint.In future we will have support for selective ports
- * setup as endpoint and root point in single board.
- *
- * Once your board came up as root point , you can verify by reading
- * /proc/bus/pci/devices. Where you can see the configuration registers
- * of endpoint device attached to the port.
- *
- * Enpoint cofiguration can be verified by connecting 4xx board to any
- * host or another 4xx board. Then try to scan the device. In case of
- * linux use "lspci" or appripriate os command.
- *
- * How do I verify the inbound and out bound windows ? (4xx to 4xx)
- * in this configuration inbound and outbound windows are setup to access
- * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
- * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
- * This is waere your POM(PLB out bound memory window) mapped. then
- * read the data from other 4xx board's u-boot prompt at address
- * 0x9000 0000(SRAM). Data should match.
- * In case of inbound , write data to u-boot command prompt at 0xb000 0000
- * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
- * data at 0x9000 0000(SRAM).Data should match.
- */
-int ppc4xx_init_pcie_port(int port, int rootport)
-{
- static int core_init;
- volatile u32 val = 0;
- int attempts;
- u64 addr;
- u32 low, high;
-
- if (!core_init) {
- if (ppc4xx_init_pcie())
- return -1;
- ++core_init;
- }
-
- /*
- * Initialize various parts of the PCI Express core for our port
- */
- ppc4xx_init_pcie_port_hw(port, rootport);
-
- /*
- * Notice: the following delay has critical impact on device
- * initialization - if too short (<50ms) the link doesn't get up.
- */
- mdelay(100);
-
- val = SDR_READ(SDRN_PESDR_RCSSTS(port));
- if (val & (1 << 20)) {
- printf("PCIE%d: PGRST failed %08x\n", port, val);
- return -1;
- }
-
- /*
- * Verify link is up
- */
- val = SDR_READ(SDRN_PESDR_LOOP(port));
- if (!(val & 0x00001000)) {
- printf("PCIE%d: link is not up.\n", port);
- return -ENODEV;
- }
-
- /*
- * Setup UTL registers - but only on revA!
- * We use default settings for revB chip.
- */
- if (!ppc440spe_revB())
- ppc4xx_setup_utl(port);
-
- /*
- * We map PCI Express configuration access into the 512MB regions
- */
- addr = ppc4xx_get_cfgaddr(port);
- low = U64_TO_U32_LOW(addr);
- high = U64_TO_U32_HIGH(addr);
-
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
- break;
- case 1:
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
- break;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- case 2:
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
- break;
-#endif
- }
-
- /*
- * Check for VC0 active and assert RDY.
- */
- attempts = 10;
- while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
- if (!(attempts--)) {
- printf("PCIE%d: VC0 not active\n", port);
- return -1;
- }
- mdelay(1000);
- }
- SDR_WRITE(SDRN_PESDR_RCSSET(port),
- SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
- mdelay(100);
-
- return 0;
-}
-
-int ppc4xx_init_pcie_rootport(int port)
-{
- return ppc4xx_init_pcie_port(port, 1);
-}
-
-int ppc4xx_init_pcie_endport(int port)
-{
- return ppc4xx_init_pcie_port(port, 0);
-}
-
-void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
-{
- volatile void *mbase = NULL;
-
- pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
-
- switch (port) {
- case 0:
- mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
- break;
- case 1:
- mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
- break;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- case 2:
- mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
- break;
-#endif
- }
-
- /*
- * Set bus numbers on our root port
- */
- out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
- out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
- out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
-
- /*
- * Set up outbound translation to hose->mem_space from PLB
- * addresses at an offset of 0xd_0000_0000. We set the low
- * bits of the mask to 11 to turn off splitting into 8
- * subregions and to enable the outbound translation.
- */
- out_le32(mbase + PECFG_POM0LAH, 0x00000000);
- out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
- in_le32(mbase + PECFG_POM0LAL));
-
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
- mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
- mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
- mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
- mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
- break;
- case 1:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
- mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
- mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
- mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
- mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
- break;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- case 2:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
- mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
- mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
- mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
- mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
- break;
-#endif
- }
-
- /* Set up 4GB inbound memory window at 0 */
- out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
- out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
- out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff);
- out_le32(mbase + PECFG_BAR0LMPA, 0);
-
- out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
- out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
- out_le32(mbase + PECFG_PIM0LAL, 0);
- out_le32(mbase + PECFG_PIM0LAH, 0);
- out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
- out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
- out_le32(mbase + PECFG_PIMEN, 0x1);
-
- /* Enable I/O, Mem, and Busmaster cycles */
- out_le16((u16 *)(mbase + PCI_COMMAND),
- in_le16((u16 *)(mbase + PCI_COMMAND)) |
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Set Device and Vendor Id */
- out_le16(mbase + 0x200, 0xaaa0 + port);
- out_le16(mbase + 0x202, 0xbed0 + port);
-
- /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
- out_le32(mbase + 0x208, 0x06040001);
-
- printf("PCIE%d: successfully set as root-complex\n", port);
-}
-
-int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
-{
- volatile void *mbase = NULL;
- int attempts = 0;
-
- pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
-
- switch (port) {
- case 0:
- mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
- break;
- case 1:
- mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
- break;
-#if defined(CONFIG_SYS_PCIE2_CFGBASE)
- case 2:
- mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
- break;
-#endif
- }
-
- /*
- * Set up outbound translation to hose->mem_space from PLB
- * addresses at an offset of 0xd_0000_0000. We set the low
- * bits of the mask to 11 to turn off splitting into 8
- * subregions and to enable the outbound translation.
- */
- out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
- out_le32(mbase + PECFG_POM0LAL, 0x00001000);
-
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- break;
- case 1:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- break;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- case 2:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- break;
-#endif
- }
-
- /* Set up 64MB inbound memory window at 0 */
- out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
- out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
-
- out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
- out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
-
- /* Setup BAR0 */
- out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
- out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
-
- /* Disable BAR1 & BAR2 */
- out_le32(mbase + PECFG_BAR1MPA, 0);
- out_le32(mbase + PECFG_BAR2HMPA, 0);
- out_le32(mbase + PECFG_BAR2LMPA, 0);
-
- out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE));
- out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE));
- out_le32(mbase + PECFG_PIMEN, 0x1);
-
- /* Enable I/O, Mem, and Busmaster cycles */
- out_le16((u16 *)(mbase + PCI_COMMAND),
- in_le16((u16 *)(mbase + PCI_COMMAND)) |
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
- out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
-
- /* Set Class Code to Processor/PPC */
- out_le32(mbase + 0x208, 0x0b200001);
-
- attempts = 10;
- while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
- if (!(attempts--)) {
- printf("PCIE%d: BME not active\n", port);
- return -1;
- }
- mdelay(1000);
- }
-
- printf("PCIE%d: successfully set as endpoint\n", port);
-
- return 0;
-}
-#endif /* CONFIG_440SPE && CONFIG_PCI */
+++ /dev/null
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <watchdog.h>
-#include <asm/ppc4xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_405EX) || defined(CONFIG_440)
-
-#if defined(CONFIG_440)
-
-#if defined(CONFIG_440GP)
-#define CR0_MASK 0x3fff0000
-#define CR0_EXTCLK_ENA 0x00600000
-#define CR0_UDIV_POS 16
-#define UDIV_SUBTRACT 1
-#define UART0_SDR CPC0_CR0
-#define MFREG(a, d) d = mfdcr(a)
-#define MTREG(a, d) mtdcr(a, d)
-#else /* #if defined(CONFIG_440GP) */
-/* all other 440 PPC's access clock divider via sdr register */
-#define CR0_MASK 0xdfffffff
-#define CR0_EXTCLK_ENA 0x00800000
-#define CR0_UDIV_POS 0
-#define UDIV_SUBTRACT 0
-#define UART0_SDR SDR0_UART0
-#define UART1_SDR SDR0_UART1
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART2_SDR SDR0_UART2
-#endif
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART3_SDR SDR0_UART3
-#endif
-#define MFREG(a, d) mfsdr(a, d)
-#define MTREG(a, d) mtsdr(a, d)
-#endif /* #if defined(CONFIG_440GP) */
-#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
-#define UCR0_MASK 0x0000007f
-#define UCR1_MASK 0x00007f00
-#define UCR0_UDIV_POS 0
-#define UCR1_UDIV_POS 8
-#define UDIV_MAX 127
-#elif defined(CONFIG_405EX)
-#define MFREG(a, d) mfsdr(a, d)
-#define MTREG(a, d) mtsdr(a, d)
-#define CR0_MASK 0x000000ff
-#define CR0_EXTCLK_ENA 0x00800000
-#define CR0_UDIV_POS 0
-#define UDIV_SUBTRACT 0
-#define UART0_SDR SDR0_UART0
-#define UART1_SDR SDR0_UART1
-#else /* CONFIG_405GP */
-#define CR0_MASK 0x00001fff
-#define CR0_EXTCLK_ENA 0x000000c0
-#define CR0_UDIV_POS 1
-#define UDIV_MAX 32
-#endif
-
-#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
-#error "External serial clock not supported on AMCC PPC405EP!"
-#endif
-
-#if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \
- defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
-/*
- * For some SoC's, the cpu clock is on divider chain A, UART on
- * divider chain B ... so cpu clock is irrelevant. Get the
- * "optimized" values that are subject to the 1/2 opb clock
- * constraint.
- */
-static u16 serial_bdiv(int baudrate, u32 *udiv)
-{
- sys_info_t sysinfo;
- u32 div; /* total divisor udiv * bdiv */
- u32 umin; /* minimum udiv */
- u16 diff; /* smallest diff */
- u16 idiff; /* current diff */
- u16 ibdiv; /* current bdiv */
- u32 i;
- u32 est; /* current estimate */
- u32 max;
-#if defined(CONFIG_405EZ)
- u32 cpr_pllc;
- u32 plloutb;
- u32 reg;
-#endif
-
- get_sys_info(&sysinfo);
-
-#if defined(CONFIG_405EZ)
- /* check the pll feedback source */
- mfcpr(CPR0_PLLC, cpr_pllc);
- plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
- sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
- sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
- div = plloutb / (16 * baudrate); /* total divisor */
- umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
- max = 256; /* highest possible */
-#else /* 405EZ */
- div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
- umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
- max = 32; /* highest possible */
-#endif /* 405EZ */
-
- *udiv = diff = max;
-
- /*
- * i is the test udiv value -- start with the largest
- * possible (max) to minimize serial clock and constrain
- * search to umin.
- */
- for (i = max; i > umin; i--) {
- ibdiv = div / i;
- est = i * ibdiv;
- idiff = (est > div) ? (est - div) : (div - est);
- if (idiff == 0) {
- *udiv = i;
- break; /* can't do better */
- } else if (idiff < diff) {
- *udiv = i; /* best so far */
- diff = idiff; /* update lowest diff*/
- }
- }
-
-#if defined(CONFIG_405EZ)
- mfcpr(CPR0_PERD0, reg);
- reg &= ~0x0000ffff;
- reg |= ((*udiv - 0) << 8) | (*udiv - 0);
- mtcpr(CPR0_PERD0, reg);
-#endif
-
- return div / *udiv;
-}
-#endif /* #if (defined(CONFIG_405EP) ... */
-
-/*
- * This function returns the UART clock used by the common
- * NS16550 driver. Additionally the SoC internal divisors for
- * optimal UART baudrate are configured.
- */
-int get_serial_clock(void)
-{
- u32 clk;
- u32 udiv;
-#if !defined(CONFIG_405EZ)
- u32 reg;
-#endif
-#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
- PPC4xx_SYS_INFO sys_info;
-#endif
-
- /*
- * Programming of the internal divisors is SoC specific.
- * Let's handle this in some #ifdef's for the SoC's.
- */
-
-#if defined(CONFIG_405GP)
- reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
- clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
- udiv = 1;
- reg |= CR0_EXTCLK_ENA;
-#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
- clk = gd->cpu_clk;
-#ifdef CONFIG_SYS_405_UART_ERRATA_59
- udiv = 31; /* Errata 59: stuck at 31 */
-#else /* CONFIG_SYS_405_UART_ERRATA_59 */
- {
- u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
-
- udiv = (clk + tmp / 2) / tmp;
- }
- if (udiv > UDIV_MAX) /* max. n bits for udiv */
- udiv = UDIV_MAX;
-#endif /* CONFIG_SYS_405_UART_ERRATA_59 */
-#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
- reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
- mtdcr (CPC0_CR0, reg);
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
- clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
-#else
- clk = CONFIG_SYS_BASE_BAUD * 16;
-#endif
-#endif
-
-#if defined(CONFIG_405EP)
- {
- u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
-
- reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
- clk = gd->cpu_clk;
- udiv = (clk + tmp / 2) / tmp;
- if (udiv > UDIV_MAX) /* max. n bits for udiv */
- udiv = UDIV_MAX;
- }
- reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */
- reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */
- mtdcr(CPC0_UCR, reg);
- clk = CONFIG_SYS_BASE_BAUD * 16;
-#endif /* CONFIG_405EP */
-
-#if defined(CONFIG_405EX) || defined(CONFIG_440)
- MFREG(UART0_SDR, reg);
- reg &= ~CR0_MASK;
-
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
- reg |= CR0_EXTCLK_ENA;
- udiv = 1;
- clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
-#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
- clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
-#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
-
- reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
-
- /*
- * Configure input clock to baudrate generator for all
- * available serial ports here
- */
- MTREG(UART0_SDR, reg);
-#if defined(UART1_SDR)
- MTREG(UART1_SDR, reg);
-#endif
-#if defined(UART2_SDR)
- MTREG(UART2_SDR, reg);
-#endif
-#if defined(UART3_SDR)
- MTREG(UART3_SDR, reg);
-#endif
-#endif /* CONFIG_405EX ... */
-
-#if defined(CONFIG_405EZ)
- clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
-#endif /* CONFIG_405EZ */
-
- /*
- * Correct UART frequency in bd-info struct now that
- * the UART divisor is available
- */
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
- gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
-#else
- get_sys_info(&sys_info);
- gd->arch.uart_clk = sys_info.freqUART / udiv;
-#endif
-
- return clk;
-}
-#endif /* CONFIG_405GP */
+++ /dev/null
-menu "ppc4xx CPU"
- depends on 4xx
-
-config SYS_CPU
- default "ppc4xx"
-
-choice
- prompt "Target select"
- optional
-
-config TARGET_LWMON5
- bool "Support lwmon5"
-
-config TARGET_T3CORP
- bool "Support t3corp"
-
-config TARGET_ACADIA
- bool "Support acadia"
-
-config TARGET_BAMBOO
- bool "Support bamboo"
-
-config TARGET_BUBINGA
- bool "Support bubinga"
-
-config TARGET_CANYONLANDS
- bool "Support canyonlands"
- select DM
- select DM_SERIAL
-
-config TARGET_KATMAI
- bool "Support katmai"
- select PHYS_64BIT
-
-config TARGET_KILAUEA
- bool "Support kilauea"
-
-config TARGET_LUAN
- bool "Support luan"
-
-config TARGET_MAKALU
- bool "Support makalu"
-
-config TARGET_REDWOOD
- bool "Support redwood"
-
-config TARGET_SEQUOIA
- bool "Support sequoia"
-
-config TARGET_WALNUT
- bool "Support walnut"
-
-config TARGET_YOSEMITE
- bool "Support yosemite"
-
-config TARGET_YUCCA
- bool "Support yucca"
-
-config TARGET_CPCI2DP
- bool "Support CPCI2DP"
-
-config TARGET_CPCI4052
- bool "Support CPCI4052"
-
-config TARGET_PLU405
- bool "Support PLU405"
-
-config TARGET_PMC405DE
- bool "Support PMC405DE"
-
-config TARGET_PMC440
- bool "Support PMC440"
-
-config TARGET_VOM405
- bool "Support VOM405"
-
-config TARGET_DLVISION_10G
- bool "Support dlvision-10g"
-
-config TARGET_IO
- bool "Support io"
-
-config TARGET_IOCON
- bool "Support iocon"
-
-config TARGET_NEO
- bool "Support neo"
-
-config TARGET_IO64
- bool "Support io64"
-
-config TARGET_DLVISION
- bool "Support dlvision"
-
-config TARGET_GDPPC440ETX
- bool "Support gdppc440etx"
-
-config TARGET_INTIP
- bool "Support intip"
-
-config TARGET_ICON
- bool "Support icon"
-
-config TARGET_MIP405
- bool "Support MIP405"
-
-config TARGET_MIP405T
- bool "Support MIP405T"
-
-config TARGET_PIP405
- bool "Support PIP405"
-
-config TARGET_XPEDITE1000
- bool "Support xpedite1000"
-
-config TARGET_XILINX_PPC405_GENERIC
- bool "Support xilinx-ppc405-generic"
- select SUPPORT_SPL
- select OF_CONTROL
- select DM
- select DM_SERIAL
-
-config TARGET_XILINX_PPC440_GENERIC
- bool "Support xilinx-ppc440-generic"
- select SUPPORT_SPL
- select OF_CONTROL
- select DM
- select DM_SERIAL
-
-endchoice
-
-config CMD_CHIP_CONFIG
- bool "Enable the 'chip_config' command"
- help
- This command programs the I2C bootstrap EEPROM or shows a list of
- possible configurations. The configurations are board-specific
- and control the CPU and peripehrals clocks. The programmed
- configuration is then used when the board boots.
-
-config CMD_ECCTEST
- bool "Enable the 'ecctest' command"
- help
- This command tests memory ECC by single and double error bit
- injection.
-
-source "board/amcc/acadia/Kconfig"
-source "board/amcc/bamboo/Kconfig"
-source "board/amcc/bubinga/Kconfig"
-source "board/amcc/canyonlands/Kconfig"
-source "board/amcc/katmai/Kconfig"
-source "board/amcc/kilauea/Kconfig"
-source "board/amcc/luan/Kconfig"
-source "board/amcc/makalu/Kconfig"
-source "board/amcc/redwood/Kconfig"
-source "board/amcc/sequoia/Kconfig"
-source "board/amcc/walnut/Kconfig"
-source "board/amcc/yosemite/Kconfig"
-source "board/amcc/yucca/Kconfig"
-source "board/esd/cpci2dp/Kconfig"
-source "board/esd/cpci405/Kconfig"
-source "board/esd/plu405/Kconfig"
-source "board/esd/pmc405de/Kconfig"
-source "board/esd/pmc440/Kconfig"
-source "board/esd/vom405/Kconfig"
-source "board/gdsys/405ep/Kconfig"
-source "board/gdsys/405ex/Kconfig"
-source "board/gdsys/dlvision/Kconfig"
-source "board/gdsys/gdppc440etx/Kconfig"
-source "board/gdsys/intip/Kconfig"
-source "board/liebherr/lwmon5/Kconfig"
-source "board/mosaixtech/icon/Kconfig"
-source "board/mpl/mip405/Kconfig"
-source "board/mpl/pip405/Kconfig"
-source "board/t3corp/Kconfig"
-source "board/xes/xpedite1000/Kconfig"
-source "board/xilinx/ppc405-generic/Kconfig"
-source "board/xilinx/ppc440-generic/Kconfig"
-
-endmenu
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y := resetvec.o
-extra-y += start.o
-
-obj-y := cache.o
-obj-y += dcr.o
-obj-y += kgdb.o
-
-obj-y += 40x_spd_sdram.o
-
-obj-y += 44x_spd_ddr.o
-obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
-obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
-obj-y += 4xx_pci.o
-obj-y += 4xx_pcie.o
-obj-y += bedbug_405.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += cmd_chip_config.o
-obj-y += cpu.o
-obj-y += cpu_init.o
-obj-y += denali_data_eye.o
-obj-y += denali_spd_ddr2.o
-obj-y += ecc.o
-obj-$(CONFIG_CMD_ECCTEST) += cmd_ecctest.o
-obj-y += fdt.o
-obj-y += interrupts.o
-obj-$(CONFIG_CMD_REGINFO) += reginfo.o
-obj-y += sdram.o
-obj-y += speed.o
-obj-y += tlb.o
-obj-y += traps.o
-obj-y += usb.o
-obj-y += usb_ohci.o
-obj-$(CONFIG_XILINX_440) += xilinx_irq.o
-ifndef CONFIG_XILINX_440
-obj-y += 4xx_uart.o
-obj-y += gpio.o
-obj-y += miiphy.o
-obj-y += uic.o
-endif
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl_boot.o
-endif
+++ /dev/null
-/*
- * Bedbug Functions specific to the PPC405 chip
- */
-
-#include <common.h>
-#include <command.h>
-#include <linux/ctype.h>
-#include <bedbug/type.h>
-#include <bedbug/bedbug.h>
-#include <bedbug/regs.h>
-#include <bedbug/ppc.h>
-
-#if defined(CONFIG_CMD_BEDBUG) && defined(CONFIG_4xx)
-
-#define MAX_BREAK_POINTS 4
-
-extern CPU_DEBUG_CTX bug_ctx;
-
-void bedbug405_init __P ((void));
-void bedbug405_do_break __P ((cmd_tbl_t *, int, int, char * const []));
-void bedbug405_break_isr __P ((struct pt_regs *));
-int bedbug405_find_empty __P ((void));
-int bedbug405_set __P ((int, unsigned long));
-int bedbug405_clear __P ((int));
-\f
-
-/* ======================================================================
- * Initialize the global bug_ctx structure for the AMCC PPC405. Clear all
- * of the breakpoints.
- * ====================================================================== */
-
-void bedbug405_init (void)
-{
- int i;
-
- /* -------------------------------------------------- */
-
- bug_ctx.hw_debug_enabled = 0;
- bug_ctx.stopped = 0;
- bug_ctx.current_bp = 0;
- bug_ctx.regs = NULL;
-
- bug_ctx.do_break = bedbug405_do_break;
- bug_ctx.break_isr = bedbug405_break_isr;
- bug_ctx.find_empty = bedbug405_find_empty;
- bug_ctx.set = bedbug405_set;
- bug_ctx.clear = bedbug405_clear;
-
- for (i = 1; i <= MAX_BREAK_POINTS; ++i)
- (*bug_ctx.clear) (i);
-
- puts ("BEDBUG:ready\n");
- return;
-} /* bedbug_init_breakpoints */
-\f
-
-
-/* ======================================================================
- * Set/clear/show one of the hardware breakpoints for the 405. The "off"
- * string will disable a specific breakpoint. The "show" string will
- * display the current breakpoints. Otherwise an address will set a
- * breakpoint at that address. Setting a breakpoint uses the CPU-specific
- * set routine which will assign a breakpoint number.
- * ====================================================================== */
-
-void bedbug405_do_break (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- long addr = 0; /* Address to break at */
- int which_bp; /* Breakpoint number */
-
- /* -------------------------------------------------- */
-
- if (argc < 2) {
- cmd_usage(cmdtp);
- return;
- }
-
- /* Turn off a breakpoint */
-
- if (strcmp (argv[1], "off") == 0) {
- if (bug_ctx.hw_debug_enabled == 0) {
- printf ("No breakpoints enabled\n");
- return;
- }
-
- which_bp = simple_strtoul (argv[2], NULL, 10);
-
- if (bug_ctx.clear)
- (*bug_ctx.clear) (which_bp);
-
- printf ("Breakpoint %d removed\n", which_bp);
- return;
- }
-
- /* Show a list of breakpoints */
-
- if (strcmp (argv[1], "show") == 0) {
- for (which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp) {
-
- switch (which_bp) {
- case 1:
- addr = GET_IAC1 ();
- break;
- case 2:
- addr = GET_IAC2 ();
- break;
- case 3:
- addr = GET_IAC3 ();
- break;
- case 4:
- addr = GET_IAC4 ();
- break;
- }
-
- printf ("Breakpoint [%d]: ", which_bp);
- if (addr == 0)
- printf ("NOT SET\n");
- else
- disppc ((unsigned char *) addr, 0, 1, bedbug_puts,
- F_RADHEX);
- }
- return;
- }
-
- /* Set a breakpoint at the address */
-
- if (!isdigit (argv[1][0])) {
- cmd_usage(cmdtp);
- return;
- }
-
- addr = simple_strtoul (argv[1], NULL, 16) & 0xfffffffc;
-
- if ((bug_ctx.set) && (which_bp = (*bug_ctx.set) (0, addr)) > 0) {
- printf ("Breakpoint [%d]: ", which_bp);
- disppc ((unsigned char *) addr, 0, 1, bedbug_puts, F_RADHEX);
- }
-
- return;
-} /* bedbug405_do_break */
-\f
-
-
-/* ======================================================================
- * Handle a breakpoint. First determine which breakpoint was hit by
- * looking at the DeBug Status Register (DBSR), clear the breakpoint
- * and enter a mini main loop. Stay in the loop until the stopped flag
- * in the debug context is cleared.
- * ====================================================================== */
-
-void bedbug405_break_isr (struct pt_regs *regs)
-{
- unsigned long dbsr_val; /* Value of the DBSR */
- unsigned long addr = 0; /* Address stopped at */
-
- /* -------------------------------------------------- */
-
- dbsr_val = GET_DBSR ();
-
- if (dbsr_val & DBSR_IA1) {
- bug_ctx.current_bp = 1;
- addr = GET_IAC1 ();
- SET_DBSR (DBSR_IA1); /* Write a 1 to clear */
- } else if (dbsr_val & DBSR_IA2) {
- bug_ctx.current_bp = 2;
- addr = GET_IAC2 ();
- SET_DBSR (DBSR_IA2); /* Write a 1 to clear */
- } else if (dbsr_val & DBSR_IA3) {
- bug_ctx.current_bp = 3;
- addr = GET_IAC3 ();
- SET_DBSR (DBSR_IA3); /* Write a 1 to clear */
- } else if (dbsr_val & DBSR_IA4) {
- bug_ctx.current_bp = 4;
- addr = GET_IAC4 ();
- SET_DBSR (DBSR_IA4); /* Write a 1 to clear */
- }
-
- bedbug_main_loop (addr, regs);
- return;
-} /* bedbug405_break_isr */
-\f
-
-
-/* ======================================================================
- * Look through all of the hardware breakpoints available to see if one
- * is unused.
- * ====================================================================== */
-
-int bedbug405_find_empty (void)
-{
- /* -------------------------------------------------- */
-
- if (GET_IAC1 () == 0)
- return 1;
-
- if (GET_IAC2 () == 0)
- return 2;
-
- if (GET_IAC3 () == 0)
- return 3;
-
- if (GET_IAC4 () == 0)
- return 4;
-
- return 0;
-} /* bedbug405_find_empty */
-\f
-
-
-/* ======================================================================
- * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint
- * number, otherwise reassign the given breakpoint. If hardware debugging
- * is not enabled, then turn it on via the MSR and DBCR0. Set the break
- * address in the appropriate IACx register and enable proper address
- * beakpoint in DBCR0.
- * ====================================================================== */
-
-int bedbug405_set (int which_bp, unsigned long addr)
-{
- /* -------------------------------------------------- */
-
- /* Only look if which_bp == 0, else use which_bp */
- if ((bug_ctx.find_empty) && (!which_bp) &&
- (which_bp = (*bug_ctx.find_empty) ()) == 0) {
- printf ("All breakpoints in use\n");
- return 0;
- }
-
- if (which_bp < 1 || which_bp > MAX_BREAK_POINTS) {
- printf ("Invalid break point # %d\n", which_bp);
- return 0;
- }
-
- if (!bug_ctx.hw_debug_enabled) {
- SET_MSR (GET_MSR () | 0x200); /* set MSR[ DE ] */
- SET_DBCR0 (GET_DBCR0 () | DBCR0_IDM);
- bug_ctx.hw_debug_enabled = 1;
- }
-
- switch (which_bp) {
- case 1:
- SET_IAC1 (addr);
- SET_DBCR0 (GET_DBCR0 () | DBCR0_IA1);
- break;
-
- case 2:
- SET_IAC2 (addr);
- SET_DBCR0 (GET_DBCR0 () | DBCR0_IA2);
- break;
-
- case 3:
- SET_IAC3 (addr);
- SET_DBCR0 (GET_DBCR0 () | DBCR0_IA3);
- break;
-
- case 4:
- SET_IAC4 (addr);
- SET_DBCR0 (GET_DBCR0 () | DBCR0_IA4);
- break;
- }
-
- return which_bp;
-} /* bedbug405_set */
-\f
-
-
-/* ======================================================================
- * Disable a specific breakoint by setting the appropriate IACx register
- * to zero and claring the instruction address breakpoint in DBCR0.
- * ====================================================================== */
-
-int bedbug405_clear (int which_bp)
-{
- /* -------------------------------------------------- */
-
- if (which_bp < 1 || which_bp > MAX_BREAK_POINTS) {
- printf ("Invalid break point # (%d)\n", which_bp);
- return -1;
- }
-
- switch (which_bp) {
- case 1:
- SET_IAC1 (0);
- SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA1);
- break;
-
- case 2:
- SET_IAC2 (0);
- SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA2);
- break;
-
- case 3:
- SET_IAC3 (0);
- SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA3);
- break;
-
- case 4:
- SET_IAC4 (0);
- SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA4);
- break;
- }
-
- return 0;
-} /* bedbug405_clear */
-
-
-/* ====================================================================== */
-#endif
+++ /dev/null
-/*
- * This file contains miscellaneous low-level functions.
- * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
- *
- * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
- * and Paul Mackerras.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <config.h>
-#include <asm/ppc4xx.h>
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-/*
- * Flush instruction cache.
- */
-_GLOBAL(invalidate_icache)
- iccci r0,r0
- isync
- blr
-
-/*
- * Write any modified data cache blocks out to memory
- * and invalidate the corresponding instruction cache blocks.
- *
- * flush_icache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(flush_icache_range)
- li r5,L1_CACHE_BYTES-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,L1_CACHE_SHIFT
- beqlr
- mtctr r4
- mr r6,r3
-1: dcbst 0,r3
- addi r3,r3,L1_CACHE_BYTES
- bdnz 1b
- sync /* wait for dcbst's to get to ram */
- mtctr r4
-2: icbi 0,r6
- addi r6,r6,L1_CACHE_BYTES
- bdnz 2b
- sync /* additional sync needed on g4 */
- isync
- blr
-
-/*
- * Write any modified data cache blocks out to memory.
- * Does not invalidate the corresponding cache lines (especially for
- * any corresponding instruction cache).
- *
- * clean_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(clean_dcache_range)
- li r5,L1_CACHE_BYTES-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,L1_CACHE_SHIFT
- beqlr
- mtctr r4
-
-1: dcbst 0,r3
- addi r3,r3,L1_CACHE_BYTES
- bdnz 1b
- sync /* wait for dcbst's to get to ram */
- blr
-
-/*
- * 40x cores have 8K or 16K dcache and 32 byte line size.
- * 44x has a 32K dcache and 32 byte line size.
- * 8xx has 1, 2, 4, 8K variants.
- * For now, cover the worst case of the 44x.
- * Must be called with external interrupts disabled.
- */
-#define CACHE_NWAYS 64
-#define CACHE_NLINES 32
-
-_GLOBAL(flush_dcache)
- li r4,(2 * CACHE_NWAYS * CACHE_NLINES)
- mtctr r4
- lis r5,0
-1: lwz r3,0(r5) /* Load one word from every line */
- addi r5,r5,L1_CACHE_BYTES
- bdnz 1b
- sync
- blr
-
-_GLOBAL(invalidate_dcache)
- addi r6,0,0x0000 /* clear GPR 6 */
- /* Do loop for # of dcache congruence classes. */
- lis r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */
- ori r7,r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
- /* NOTE: dccci invalidates both */
- mtctr r7 /* ways in the D cache */
-..dcloop:
- dccci 0,r6 /* invalidate line */
- addi r6,r6,L1_CACHE_BYTES /* bump to next line */
- bdnz ..dcloop
- sync
- blr
-
-/*
- * Cache functions.
- *
- * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
- * although for some cache-ralated calls stubs have to be provided to satisfy
- * symbols resolution.
- * Icache-related functions are used in POST framework.
- *
- */
-#ifdef CONFIG_440
-
- .globl dcache_disable
- .globl dcache_enable
- .globl icache_disable
- .globl icache_enable
-dcache_disable:
-dcache_enable:
-icache_disable:
-icache_enable:
- blr
-
- .globl dcache_status
- .globl icache_status
-dcache_status:
-icache_status:
- mr r3, 0
- blr
-
-#else /* CONFIG_440 */
-
- .globl icache_enable
-icache_enable:
- mflr r8
- bl invalidate_icache
- mtlr r8
- isync
- addis r3,r0, 0xc000 /* set bit 0 */
- mticcr r3
- blr
-
- .globl icache_disable
-icache_disable:
- addis r3,r0, 0x0000 /* clear bit 0 */
- mticcr r3
- isync
- blr
-
- .globl icache_status
-icache_status:
- mficcr r3
- srwi r3, r3, 31 /* >>31 => select bit 0 */
- blr
-
- .globl dcache_enable
-dcache_enable:
- mflr r8
- bl invalidate_dcache
- mtlr r8
- isync
- addis r3,r0, 0x8000 /* set bit 0 */
- mtdccr r3
- blr
-
- .globl dcache_disable
-dcache_disable:
- mflr r8
- bl flush_dcache
- mtlr r8
- addis r3,r0, 0x0000 /* clear bit 0 */
- mtdccr r3
- blr
-
- .globl dcache_status
-dcache_status:
- mfdccr r3
- srwi r3, r3, 31 /* >>31 => select bit 0 */
- blr
-
-#endif /* CONFIG_440 */
+++ /dev/null
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2009
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <asm/ppc4xx_config.h>
-#include <asm/io.h>
-
-static void print_configs(int cur_config_nr)
-{
- int i;
-
- for (i = 0; i < ppc4xx_config_count; i++) {
- printf("%-16s - %s", ppc4xx_config_val[i].label,
- ppc4xx_config_val[i].description);
- if (i == cur_config_nr)
- printf(" ***");
- printf("\n");
- }
-
-}
-
-static int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
- int ret;
- int cur_config_nr = -1;
- u8 cur_config[CONFIG_4xx_CONFIG_BLOCKSIZE];
-
- /*
- * First switch to correct I2C bus. This is I2C bus 0
- * for all currently available 4xx derivats.
- */
- i2c_set_bus_num(0);
-
-#ifdef CONFIG_CMD_EEPROM
- ret = eeprom_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
- CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
- cur_config, CONFIG_4xx_CONFIG_BLOCKSIZE);
-#else
- ret = i2c_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
- CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
- 1, cur_config, CONFIG_4xx_CONFIG_BLOCKSIZE);
-#endif
- if (ret) {
- printf("Error reading EEPROM at addr 0x%x\n",
- CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
- return -1;
- }
-
- /*
- * Search the current configuration
- */
- for (i = 0; i < ppc4xx_config_count; i++) {
- if (memcmp(cur_config, ppc4xx_config_val[i].val,
- CONFIG_4xx_CONFIG_BLOCKSIZE) == 0)
- cur_config_nr = i;
- }
-
- if (cur_config_nr == -1) {
- printf("Warning: The I2C bootstrap values don't match any"
- " of the available options!\n");
- printf("I2C bootstrap EEPROM values are (I2C address 0x%02x):\n",
- CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
- for (i = 0; i < CONFIG_4xx_CONFIG_BLOCKSIZE; i++) {
- printf("%02x ", cur_config[i]);
- }
- printf("\n");
- }
-
- if (argc < 2) {
- printf("Available configurations (I2C address 0x%02x):\n",
- CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
- print_configs(cur_config_nr);
- return 0;
- }
-
- for (i = 0; i < ppc4xx_config_count; i++) {
- /*
- * Search for configuration name/label
- */
- if (strcmp(argv[1], ppc4xx_config_val[i].label) == 0) {
- printf("Using configuration:\n%-16s - %s\n",
- ppc4xx_config_val[i].label,
- ppc4xx_config_val[i].description);
-
-#ifdef CONFIG_CMD_EEPROM
- ret = eeprom_write(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
- CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
- ppc4xx_config_val[i].val,
- CONFIG_4xx_CONFIG_BLOCKSIZE);
-#else
- ret = i2c_write(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
- CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
- 1, ppc4xx_config_val[i].val,
- CONFIG_4xx_CONFIG_BLOCKSIZE);
-#endif
- udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
- if (ret) {
- printf("Error updating EEPROM at addr 0x%x\n",
- CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
- return -1;
- }
-
- printf("done (dump via 'i2c md %x 0.1 %x')\n",
- CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
- CONFIG_4xx_CONFIG_BLOCKSIZE);
- printf("Reset the board for the changes to"
- " take effect\n");
- return 0;
- }
- }
-
- printf("Configuration %s not found!\n", argv[1]);
- print_configs(cur_config_nr);
- return -1;
-}
-
-U_BOOT_CMD(
- chip_config, 2, 0, do_chip_config,
- "program the I2C bootstrap EEPROM",
- "[config-label]"
-);
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
- defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
-#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
-
-#if defined(CONFIG_405EX)
-/*
- * Currently only 405EX uses 16bit data bus width as an alternative
- * option to 32bit data width (SDRAM0_MCOPT1_WDTH)
- */
-#define SDRAM_DATA_ALT_WIDTH 2
-#else
-#define SDRAM_DATA_ALT_WIDTH 8
-#endif
-
-#if defined(CONFIG_SYS_OCM_BASE)
-#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_OCM_BASE
-#endif
-
-#if defined(CONFIG_SYS_ISRAM_BASE)
-#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_ISRAM_BASE
-#endif
-
-#if !defined(CONFIG_FUNC_ISRAM_ADDR)
-#error "No internal SRAM/OCM provided!"
-#endif
-
-#define force_inline inline __attribute__ ((always_inline))
-
-static inline void machine_check_disable(void)
-{
- mtmsr(mfmsr() & ~MSR_ME);
-}
-
-static inline void machine_check_enable(void)
-{
- mtmsr(mfmsr() | MSR_ME);
-}
-
-/*
- * These helper functions need to be inlined, since they
- * are called from the functions running from internal SRAM.
- * SDRAM operation is forbidden at that time, so calling
- * functions in SDRAM has to be avoided.
- */
-static force_inline void wait_ddr_idle(void)
-{
- u32 val;
-
- do {
- mfsdram(SDRAM_MCSTAT, val);
- } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
-}
-
-static force_inline void recalibrate_ddr(void)
-{
- u32 val;
-
- /*
- * Rewrite RQDC & RFDC to calibrate again. If this is not
- * done, the SDRAM controller is working correctly after
- * changing the MCOPT1_MCHK bits.
- */
- mfsdram(SDRAM_RQDC, val);
- mtsdram(SDRAM_RQDC, val);
- mfsdram(SDRAM_RFDC, val);
- mtsdram(SDRAM_RFDC, val);
-}
-
-static force_inline void set_mcopt1_mchk(u32 bits)
-{
- u32 val;
-
- wait_ddr_idle();
- mfsdram(SDRAM_MCOPT1, val);
- mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | bits);
- recalibrate_ddr();
-}
-
-/*
- * The next 2 functions are copied to internal SRAM/OCM and run
- * there. No function calls allowed here. No SDRAM acitivity should
- * be done here.
- */
-static void inject_ecc_error(void *ptr, int par)
-{
- /*
- * Taken from PPC460EX/EXr/GT users manual (Rev 1.21)
- * 22.2.17.13 ECC Diagnostics
- *
- * Items 1 ... 5 are already done by now, running from RAM
- * with ECC enabled
- */
-
- out_be32(ptr, 0x00000000);
- in_be32(ptr);
-
- /* 6. Set memory controller to no error checking */
- set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON);
-
- /* 7. Modify one or two bits for error simulation */
- if (par == 1)
- out_be32(ptr, in_be32(ptr) ^ 0x00000001);
- else
- out_be32(ptr, in_be32(ptr) ^ 0x00000003);
-
- /* 8. Wait for SDRAM idle */
- in_be32(ptr);
- set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
-
- /* Wait for SDRAM idle */
- wait_ddr_idle();
-
- /* Continue with 9. in calling function... */
-}
-
-static void rewrite_ecc_parity(void *ptr, int par)
-{
- u32 current_address = (u32)ptr;
- u32 end_address;
- u32 address_increment;
- u32 mcopt1;
-
- /*
- * Fill ECC parity byte again. Otherwise further accesses to
- * the failure address will result in exceptions.
- */
-
- /* Wait for SDRAM idle */
- in_be32(0x00000000);
- set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN);
-
- /* ECC bit set method for non-cached memory */
- mfsdram(SDRAM_MCOPT1, mcopt1);
- if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
- address_increment = 4;
- else
- address_increment = SDRAM_DATA_ALT_WIDTH;
- end_address = current_address + CONFIG_SYS_CACHELINE_SIZE;
-
- while (current_address < end_address) {
- *((unsigned long *)current_address) = 0;
- current_address += address_increment;
- }
-
- set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
-
- /* Wait for SDRAM idle */
- wait_ddr_idle();
-}
-
-static int do_ecctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 old_val;
- u32 val;
- u32 *ptr;
- void (*sram_func)(u32 *, int);
- int error;
-
- if (argc < 3) {
- return cmd_usage(cmdtp);
- }
-
- ptr = (u32 *)simple_strtoul(argv[1], NULL, 16);
- error = simple_strtoul(argv[2], NULL, 16);
- if ((error < 1) || (error > 2)) {
- return cmd_usage(cmdtp);
- }
-
- printf("Using address %p for %d bit ECC error injection\n",
- ptr, error);
-
- /*
- * Save value to restore it later on
- */
- old_val = in_be32(ptr);
-
- /*
- * Copy ECC injection function into internal SRAM/OCM
- */
- sram_func = (void *)CONFIG_FUNC_ISRAM_ADDR;
- memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, inject_ecc_error, 0x10000);
-
- /*
- * Disable interrupts and exceptions before calling this
- * function in internal SRAM/OCM
- */
- disable_interrupts();
- machine_check_disable();
- eieio();
-
- /*
- * Jump to ECC simulation function in internal SRAM/OCM
- */
- (*sram_func)(ptr, error);
-
- /* 10. Read the corresponding address */
- val = in_be32(ptr);
-
- /*
- * Read and print ECC status register/info:
- * The faulting address is only known upon uncorrectable ECC
- * errors.
- */
- mfsdram(SDRAM_ECCES, val);
- if (val & SDRAM_ECCES_CE)
- printf("ECC: Correctable error\n");
- if (val & SDRAM_ECCES_UE) {
- printf("ECC: Uncorrectable error at 0x%02x%08x\n",
- mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
- }
-
- /*
- * Clear pending interrupts/exceptions
- */
- mtsdram(SDRAM_ECCES, 0xffffffff);
- mtdcr(SDRAM_ERRSTATLL, 0xff000000);
- set_mcsr(get_mcsr());
-
- /* Now enable interrupts and exceptions again */
- eieio();
- machine_check_enable();
- enable_interrupts();
-
- /*
- * The ECC parity byte need to be re-written for the
- * corresponding address. Otherwise future accesses to it
- * will result in exceptions.
- *
- * Jump to ECC parity generation function
- */
- memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, rewrite_ecc_parity, 0x10000);
- (*sram_func)(ptr, 0);
-
- /*
- * Restore value in corresponding address
- */
- out_be32(ptr, old_val);
-
- return 0;
-}
-
-U_BOOT_CMD(
- ecctest, 3, 0, do_ecctest,
- "Test ECC by single and double error bit injection",
- "address 1/2"
-);
-
-#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
-#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
+++ /dev/null
-#
-# (C) Copyright 2000-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mstring -msoft-float
-
-ifneq (,$(CONFIG_440))
-PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440
-else
-PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405
-endif
+++ /dev/null
-/*
- * (C) Copyright 2000-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * CPU specific code
- *
- * written or collected and sometimes rewritten by
- * Magnus Damm <damm@bitsmart.com>
- *
- * minor modifications by
- * Wolfgang Denk <wd@denx.de>
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <asm/cache.h>
-#include <asm/ppc4xx.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_reset(void);
-
-/*
- * To provide an interface to detect CPU number for boards that support
- * more then one CPU, we implement the "weak" default functions here.
- *
- * Returns CPU number
- */
-int __get_cpu_num(void)
-{
- return NA_OR_UNKNOWN_CPU;
-}
-int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
-
-#if defined(CONFIG_PCI)
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-#define PCI_ASYNC
-
-static int pci_async_enabled(void)
-{
-#if defined(CONFIG_405GP)
- return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
-#endif
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- unsigned long val;
-
- mfsdr(SDR0_SDSTP1, val);
- return (val & SDR0_SDSTP1_PAME_MASK);
-#endif
-}
-#endif
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_PCI) && \
- !defined(CONFIG_405) && !defined(CONFIG_405EX)
-int pci_arbiter_enabled(void)
-{
-#if defined(CONFIG_405GP)
- return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
-#endif
-
-#if defined(CONFIG_405EP)
- return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
-#endif
-
-#if defined(CONFIG_440GP)
- return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
-#endif
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
- unsigned long val;
-
- mfsdr(SDR0_XCR0, val);
- return (val & SDR0_XCR0_PAE_MASK);
-#endif
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- unsigned long val;
-
- mfsdr(SDR0_PCI0, val);
- return (val & SDR0_PCI0_PAE_MASK);
-#endif
-}
-#endif
-
-#if defined(CONFIG_405EP)
-#define I2C_BOOTROM
-
-static int i2c_bootrom_enabled(void)
-{
-#if defined(CONFIG_405EP)
- return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
-#else
- unsigned long val;
-
- mfsdr(SDR0_SDCS0, val);
- return (val & SDR0_SDCS_SDD);
-#endif
-}
-#endif
-
-#if defined(CONFIG_440GX)
-#define SDR0_PINSTP_SHIFT 29
-static char *bootstrap_str[] = {
- "EBC (16 bits)",
- "EBC (8 bits)",
- "EBC (32 bits)",
- "EBC (8 bits)",
- "PCI",
- "I2C (Addr 0x54)",
- "Reserved",
- "I2C (Addr 0x50)",
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
-#endif
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define SDR0_PINSTP_SHIFT 30
-static char *bootstrap_str[] = {
- "EBC (8 bits)",
- "PCI",
- "I2C (Addr 0x54)",
- "I2C (Addr 0x50)",
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
-#endif
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define SDR0_PINSTP_SHIFT 29
-static char *bootstrap_str[] = {
- "EBC (8 bits)",
- "PCI",
- "NAND (8 bits)",
- "EBC (16 bits)",
- "EBC (16 bits)",
- "I2C (Addr 0x54)",
- "PCI",
- "I2C (Addr 0x52)",
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
-#endif
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define SDR0_PINSTP_SHIFT 29
-static char *bootstrap_str[] = {
- "EBC (8 bits)",
- "EBC (16 bits)",
- "EBC (16 bits)",
- "NAND (8 bits)",
- "PCI",
- "I2C (Addr 0x54)",
- "PCI",
- "I2C (Addr 0x52)",
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define SDR0_PINSTP_SHIFT 29
-static char *bootstrap_str[] = {
- "EBC (8 bits)",
- "EBC (16 bits)",
- "PCI",
- "PCI",
- "EBC (16 bits)",
- "NAND (8 bits)",
- "I2C (Addr 0x54)", /* A8 */
- "I2C (Addr 0x52)", /* A4 */
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
-#endif
-
-#if defined(CONFIG_460SX)
-#define SDR0_PINSTP_SHIFT 29
-static char *bootstrap_str[] = {
- "EBC (8 bits)",
- "EBC (16 bits)",
- "EBC (32 bits)",
- "NAND (8 bits)",
- "I2C (Addr 0x54)", /* A8 */
- "I2C (Addr 0x52)", /* A4 */
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
-#endif
-
-#if defined(CONFIG_405EZ)
-#define SDR0_PINSTP_SHIFT 28
-static char *bootstrap_str[] = {
- "EBC (8 bits)",
- "SPI (fast)",
- "NAND (512 page, 4 addr cycle)",
- "I2C (Addr 0x50)",
- "EBC (32 bits)",
- "I2C (Addr 0x50)",
- "NAND (2K page, 5 addr cycle)",
- "I2C (Addr 0x50)",
- "EBC (16 bits)",
- "Reserved",
- "NAND (2K page, 4 addr cycle)",
- "I2C (Addr 0x50)",
- "NAND (512 page, 3 addr cycle)",
- "I2C (Addr 0x50)",
- "SPI (slow)",
- "I2C (Addr 0x50)",
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
- 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
-#endif
-
-#if defined(CONFIG_405EX)
-#define SDR0_PINSTP_SHIFT 29
-static char *bootstrap_str[] = {
- "EBC (8 bits)",
- "EBC (16 bits)",
- "EBC (16 bits)",
- "NAND (8 bits)",
- "NAND (8 bits)",
- "I2C (Addr 0x54)",
- "EBC (8 bits)",
- "I2C (Addr 0x52)",
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
-#endif
-
-#if defined(SDR0_PINSTP_SHIFT)
-static int bootstrap_option(void)
-{
- unsigned long val;
-
- mfsdr(SDR0_PINSTP, val);
- return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
-}
-#endif /* SDR0_PINSTP_SHIFT */
-
-
-#if defined(CONFIG_440GP)
-static int do_chip_reset (unsigned long sys0, unsigned long sys1)
-{
- /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
- * reset.
- */
- mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */
- mtdcr (CPC0_SYS0, sys0);
- mtdcr (CPC0_SYS1, sys1);
- mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
- mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
-
- return 1;
-}
-#endif /* CONFIG_440GP */
-
-
-int checkcpu (void)
-{
-#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
- uint pvr = get_pvr();
- ulong clock = gd->cpu_clk;
- char buf[32];
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- u32 reg;
-#endif
-
- char addstr[64] = "";
- sys_info_t sys_info;
- int cpu_num;
-
- cpu_num = get_cpu_num();
- if (cpu_num >= 0)
- printf("CPU%d: ", cpu_num);
- else
- puts("CPU: ");
-
- get_sys_info(&sys_info);
-
-#if defined(CONFIG_XILINX_440)
- puts("IBM PowerPC ");
-#else
- puts("AMCC PowerPC ");
-#endif
-
- switch (pvr) {
-
-#if !defined(CONFIG_440)
- case PVR_405GP_RB:
- puts("405GP Rev. B");
- break;
-
- case PVR_405GP_RC:
- puts("405GP Rev. C");
- break;
-
- case PVR_405GP_RD:
- puts("405GP Rev. D");
- break;
-
- case PVR_405GP_RE:
- puts("405GP Rev. E");
- break;
-
- case PVR_405GPR_RB:
- puts("405GPr Rev. B");
- break;
-
- case PVR_405EP_RB:
- puts("405EP Rev. B");
- break;
-
- case PVR_405EZ_RA:
- puts("405EZ Rev. A");
- break;
-
- case PVR_405EX1_RA:
- puts("405EX Rev. A");
- strcpy(addstr, "Security support");
- break;
-
- case PVR_405EXR2_RA:
- puts("405EXr Rev. A");
- strcpy(addstr, "No Security support");
- break;
-
- case PVR_405EX1_RC:
- puts("405EX Rev. C");
- strcpy(addstr, "Security support");
- break;
-
- case PVR_405EX2_RC:
- puts("405EX Rev. C");
- strcpy(addstr, "No Security support");
- break;
-
- case PVR_405EXR1_RC:
- puts("405EXr Rev. C");
- strcpy(addstr, "Security support");
- break;
-
- case PVR_405EXR2_RC:
- puts("405EXr Rev. C");
- strcpy(addstr, "No Security support");
- break;
-
- case PVR_405EX1_RD:
- puts("405EX Rev. D");
- strcpy(addstr, "Security support");
- break;
-
- case PVR_405EX2_RD:
- puts("405EX Rev. D");
- strcpy(addstr, "No Security support");
- break;
-
- case PVR_405EXR1_RD:
- puts("405EXr Rev. D");
- strcpy(addstr, "Security support");
- break;
-
- case PVR_405EXR2_RD:
- puts("405EXr Rev. D");
- strcpy(addstr, "No Security support");
- break;
-
-#else /* CONFIG_440 */
-
-#if defined(CONFIG_440GP)
- case PVR_440GP_RB:
- puts("440GP Rev. B");
- /* See errata 1.12: CHIP_4 */
- if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
- (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
- puts ( "\n\t CPC0_SYSx DCRs corrupted. "
- "Resetting chip ...\n");
- udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
- do_chip_reset ( mfdcr(CPC0_STRP0),
- mfdcr(CPC0_STRP1) );
- }
- break;
-
- case PVR_440GP_RC:
- puts("440GP Rev. C");
- break;
-#endif /* CONFIG_440GP */
-
- case PVR_440GX_RA:
- puts("440GX Rev. A");
- break;
-
- case PVR_440GX_RB:
- puts("440GX Rev. B");
- break;
-
- case PVR_440GX_RC:
- puts("440GX Rev. C");
- break;
-
- case PVR_440GX_RF:
- puts("440GX Rev. F");
- break;
-
- case PVR_440EP_RA:
- puts("440EP Rev. A");
- break;
-
-#ifdef CONFIG_440EP
- case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
- puts("440EP Rev. B");
- break;
-
- case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
- puts("440EP Rev. C");
- break;
-#endif /* CONFIG_440EP */
-
-#ifdef CONFIG_440GR
- case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
- puts("440GR Rev. A");
- break;
-
- case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
- puts("440GR Rev. B");
- break;
-#endif /* CONFIG_440GR */
-
-#ifdef CONFIG_440EPX
- case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
- puts("440EPx Rev. A");
- strcpy(addstr, "Security/Kasumi support");
- break;
-
- case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
- puts("440EPx Rev. A");
- strcpy(addstr, "No Security/Kasumi support");
- break;
-#endif /* CONFIG_440EPX */
-
-#ifdef CONFIG_440GRX
- case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
- puts("440GRx Rev. A");
- strcpy(addstr, "Security/Kasumi support");
- break;
-
- case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
- puts("440GRx Rev. A");
- strcpy(addstr, "No Security/Kasumi support");
- break;
-#endif /* CONFIG_440GRX */
-
- case PVR_440SP_6_RAB:
- puts("440SP Rev. A/B");
- strcpy(addstr, "RAID 6 support");
- break;
-
- case PVR_440SP_RAB:
- puts("440SP Rev. A/B");
- strcpy(addstr, "No RAID 6 support");
- break;
-
- case PVR_440SP_6_RC:
- puts("440SP Rev. C");
- strcpy(addstr, "RAID 6 support");
- break;
-
- case PVR_440SP_RC:
- puts("440SP Rev. C");
- strcpy(addstr, "No RAID 6 support");
- break;
-
- case PVR_440SPe_6_RA:
- puts("440SPe Rev. A");
- strcpy(addstr, "RAID 6 support");
- break;
-
- case PVR_440SPe_RA:
- puts("440SPe Rev. A");
- strcpy(addstr, "No RAID 6 support");
- break;
-
- case PVR_440SPe_6_RB:
- puts("440SPe Rev. B");
- strcpy(addstr, "RAID 6 support");
- break;
-
- case PVR_440SPe_RB:
- puts("440SPe Rev. B");
- strcpy(addstr, "No RAID 6 support");
- break;
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- case PVR_460EX_RA:
- puts("460EX Rev. A");
- strcpy(addstr, "No Security/Kasumi support");
- break;
-
- case PVR_460EX_SE_RA:
- puts("460EX Rev. A");
- strcpy(addstr, "Security/Kasumi support");
- break;
-
- case PVR_460EX_RB:
- puts("460EX Rev. B");
- mfsdr(SDR0_ECID3, reg);
- if (reg & 0x00100000)
- strcpy(addstr, "No Security/Kasumi support");
- else
- strcpy(addstr, "Security/Kasumi support");
- break;
-
- case PVR_460GT_RA:
- puts("460GT Rev. A");
- strcpy(addstr, "No Security/Kasumi support");
- break;
-
- case PVR_460GT_SE_RA:
- puts("460GT Rev. A");
- strcpy(addstr, "Security/Kasumi support");
- break;
-
- case PVR_460GT_RB:
- puts("460GT Rev. B");
- mfsdr(SDR0_ECID3, reg);
- if (reg & 0x00100000)
- strcpy(addstr, "No Security/Kasumi support");
- else
- strcpy(addstr, "Security/Kasumi support");
- break;
-#endif
-
- case PVR_460SX_RA:
- puts("460SX Rev. A");
- strcpy(addstr, "Security support");
- break;
-
- case PVR_460SX_RA_V1:
- puts("460SX Rev. A");
- strcpy(addstr, "No Security support");
- break;
-
- case PVR_460GX_RA:
- puts("460GX Rev. A");
- strcpy(addstr, "Security support");
- break;
-
- case PVR_460GX_RA_V1:
- puts("460GX Rev. A");
- strcpy(addstr, "No Security support");
- break;
-
- case PVR_APM821XX_RA:
- puts("APM821XX Rev. A");
- strcpy(addstr, "Security support");
- break;
-
- case PVR_VIRTEX5:
- puts("440x5 VIRTEX5");
- break;
-#endif /* CONFIG_440 */
-
- default:
- printf (" UNKNOWN (PVR=%08x)", pvr);
- break;
- }
-
- printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
- strmhz(buf, clock),
- sys_info.freqPLB / 1000000,
- get_OPB_freq() / 1000000,
- sys_info.freqEBC / 1000000);
-#if defined(CONFIG_PCI) && \
- (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRX))
- printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
-#endif
- printf(")\n");
-
- if (addstr[0] != 0)
- printf(" %s\n", addstr);
-
-#if defined(I2C_BOOTROM)
- printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
-#endif /* I2C_BOOTROM */
-#if defined(SDR0_PINSTP_SHIFT)
- printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
- printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
- putc('\n');
-#endif /* SDR0_PINSTP_SHIFT */
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
- printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
-#endif
-
-#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
- if (pci_async_enabled()) {
- printf (", PCI async ext clock used");
- } else {
- printf (", PCI sync clock at %lu MHz",
- sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
- }
-#endif
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
- putc('\n');
-#endif
-
-#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
- printf(" 16 KiB I-Cache 16 KiB D-Cache");
-#elif defined(CONFIG_440)
- printf(" 32 KiB I-Cache 32 KiB D-Cache");
-#else
- printf(" 16 KiB I-Cache %d KiB D-Cache",
- ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
-#endif
-
-#endif /* !defined(CONFIG_405) */
-
- putc ('\n');
-
- return 0;
-}
-
-int ppc440spe_revB() {
- unsigned int pvr;
-
- pvr = get_pvr();
- if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
- return 1;
- else
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if defined(CONFIG_BOARD_RESET)
- board_reset();
-#else
-#if defined(CONFIG_SYS_4xx_RESET_TYPE)
- mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
-#else
- /*
- * Initiate system reset in debug control register DBCR
- */
- mtspr(SPRN_DBCR0, 0x30000000);
-#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
-#endif /* defined(CONFIG_BOARD_RESET) */
-
- return 1;
-}
-
-
-/*
- * Get timebase clock frequency
- */
-unsigned long get_tbclk (void)
-{
- sys_info_t sys_info;
-
- get_sys_info(&sys_info);
- return (sys_info.freqProcessor);
-}
-
-
-#if defined(CONFIG_WATCHDOG)
-void watchdog_reset(void)
-{
- int re_enable = disable_interrupts();
- reset_4xx_watchdog();
- if (re_enable) enable_interrupts();
-}
-
-void reset_4xx_watchdog(void)
-{
- /*
- * Clear TSR(WIS) bit
- */
- mtspr(SPRN_TSR, 0x40000000);
-}
-#endif /* CONFIG_WATCHDOG */
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_PPC4xx_EMAC)
- ppc_4xx_eth_initialize(bis);
-#endif
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <asm/ppc4xx-emac.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/ppc4xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_PLL_RECONFIG
-#define CONFIG_SYS_PLL_RECONFIG 0
-#endif
-
-#if defined(CONFIG_440EPX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-static void reset_with_rli(void)
-{
- u32 reg;
-
- /*
- * Set reload inhibit so configuration will persist across
- * processor resets
- */
- mfcpr(CPR0_ICFG, reg);
- reg |= CPR0_ICFG_RLI_MASK;
- mtcpr(CPR0_ICFG, reg);
-
- /* Reset processor if configuration changed */
- __asm__ __volatile__ ("sync; isync");
- mtspr(SPRN_DBCR0, 0x20000000);
-}
-#endif
-
-void reconfigure_pll(u32 new_cpu_freq)
-{
-#if defined(CONFIG_440EPX)
- int reset_needed = 0;
- u32 reg, temp;
- u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
- fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
- fbdv, target_fbdv, lfbdv, target_lfbdv,
- perdv0, target_perdv0, /* CLK_PERD */
- spcid0, target_spcid0; /* CLK_SPCID */
-
- /* Reconfigure clocks if necessary.
- * See PPC440EPx User's Manual, sections 8.2 and 14 */
- if (new_cpu_freq == 667) {
- target_prbdv0 = 2;
- target_fwdva = 2;
- target_fwdvb = 4;
- target_fbdv = 20;
- target_lfbdv = 1;
- target_perdv0 = 4;
- target_spcid0 = 4;
-
- mfcpr(CPR0_PRIMBD0, reg);
- temp = (reg & PRBDV_MASK) >> 24;
- prbdv0 = temp ? temp : 8;
- if (prbdv0 != target_prbdv0) {
- reg &= ~PRBDV_MASK;
- reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
- mtcpr(CPR0_PRIMBD0, reg);
- reset_needed = 1;
- }
-
- mfcpr(CPR0_PLLD, reg);
-
- temp = (reg & PLLD_FWDVA_MASK) >> 16;
- fwdva = temp ? temp : 16;
-
- temp = (reg & PLLD_FWDVB_MASK) >> 8;
- fwdvb = temp ? temp : 8;
-
- temp = (reg & PLLD_FBDV_MASK) >> 24;
- fbdv = temp ? temp : 32;
-
- temp = (reg & PLLD_LFBDV_MASK);
- lfbdv = temp ? temp : 64;
-
- if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
- reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
- PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
- reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
- ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
- ((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
- (target_lfbdv == 64 ? 0 : target_lfbdv);
- mtcpr(CPR0_PLLD, reg);
- reset_needed = 1;
- }
-
- mfcpr(CPR0_PERD, reg);
- perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
- if (perdv0 != target_perdv0) {
- reg &= ~CPR0_PERD_PERDV0_MASK;
- reg |= (target_perdv0 << 24);
- mtcpr(CPR0_PERD, reg);
- reset_needed = 1;
- }
-
- mfcpr(CPR0_SPCID, reg);
- temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
- spcid0 = temp ? temp : 4;
- if (spcid0 != target_spcid0) {
- reg &= ~CPR0_SPCID_SPCIDV0_MASK;
- reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
- mtcpr(CPR0_SPCID, reg);
- reset_needed = 1;
- }
- }
-
- /* Get current value of FWDVA.*/
- mfcpr(CPR0_PLLD, reg);
- temp = (reg & PLLD_FWDVA_MASK) >> 16;
-
- /*
- * Check to see if FWDVA has been set to value of 1. if it has we must
- * modify it.
- */
- if (temp == 1) {
- /*
- * Load register that contains current boot strapping option.
- */
- mfcpr(CPR0_ICFG, reg);
- /*
- * Strapping option bits (ICS) are already in correct position,
- * only masking needed.
- */
- reg &= CPR0_ICFG_ICS_MASK;
-
- if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
- (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
- mfcpr(CPR0_PLLD, reg);
-
- /* Get current value of fbdv. */
- temp = (reg & PLLD_FBDV_MASK) >> 24;
- fbdv = temp ? temp : 32;
-
- /* Get current value of lfbdv. */
- temp = (reg & PLLD_LFBDV_MASK);
- lfbdv = temp ? temp : 64;
-
- /*
- * Get current value of FWDVA. Assign current FWDVA to
- * new FWDVB.
- */
- mfcpr(CPR0_PLLD, reg);
- target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
- fwdvb = target_fwdvb ? target_fwdvb : 8;
-
- /*
- * Get current value of FWDVB. Assign current FWDVB to
- * new FWDVA.
- */
- target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
- fwdva = target_fwdva ? target_fwdva : 16;
-
- /*
- * Update CPR0_PLLD with switched FWDVA and FWDVB.
- */
- reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
- PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
- reg |= ((fwdva == 16 ? 0 : fwdva) << 16) |
- ((fwdvb == 8 ? 0 : fwdvb) << 8) |
- ((fbdv == 32 ? 0 : fbdv) << 24) |
- (lfbdv == 64 ? 0 : lfbdv);
- mtcpr(CPR0_PLLD, reg);
-
- /* Acknowledge that a reset is required. */
- reset_needed = 1;
- }
- }
-
- /* Now reset the CPU if needed */
- if (reset_needed)
- reset_with_rli();
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- u32 reg;
-
- /*
- * See "9.2.1.1 Booting with Option E" in the 460EX/GT
- * users manual
- */
- mfcpr(CPR0_PLLC, reg);
- if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
- /*
- * Set engage bit
- */
- reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG;
- mtcpr(CPR0_PLLC, reg);
-
- /* Now reset the CPU */
- reset_with_rli();
- }
-#endif
-}
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
-void
-chip_21_errata(void)
-{
- /*
- * See rev 1.09 of the 405EX/405EXr errata. CHIP_21 says that
- * sometimes reading the PVR and/or SDR0_ECID results in incorrect
- * values. Since the rev-D chip uses the SDR0_ECID bits to control
- * internal features, that means the second PCIe or ethernet of an EX
- * variant could fail to work. Also, security features of both EX and
- * EXr might be incorrectly disabled.
- *
- * The suggested workaround is as follows (covering rev-C and rev-D):
- *
- * 1.Read the PVR and SDR0_ECID3.
- *
- * 2.If the PVR matches an expected Revision C PVR value AND if
- * SDR0_ECID3[12:15] is different from PVR[28:31], then processor is
- * Revision C: continue executing the initialization code (no reset
- * required). else go to step 3.
- *
- * 3.If the PVR matches an expected Revision D PVR value AND if
- * SDR0_ECID3[10:11] matches its expected value, then continue
- * executing initialization code, no reset required. else write
- * DBCR0[RST] = 0b11 to generate a SysReset.
- */
-
- u32 pvr;
- u32 pvr_28_31;
- u32 ecid3;
- u32 ecid3_10_11;
- u32 ecid3_12_15;
-
- /* Step 1: */
- pvr = get_pvr();
- mfsdr(SDR0_ECID3, ecid3);
-
- /* Step 2: */
- pvr_28_31 = pvr & 0xf;
- ecid3_10_11 = (ecid3 >> 20) & 0x3;
- ecid3_12_15 = (ecid3 >> 16) & 0xf;
- if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_C) &&
- (pvr_28_31 != ecid3_12_15)) {
- /* No reset required. */
- return;
- }
-
- /* Step 3: */
- if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_D) &&
- (ecid3_10_11 == CONFIG_405EX_CHIP21_ECID3_REV_D)) {
- /* No reset required. */
- return;
- }
-
- /* Reset required. */
- __asm__ __volatile__ ("sync; isync");
- mtspr(SPRN_DBCR0, 0x30000000);
-}
-#endif
-
-/*
- * Breath some life into the CPU...
- *
- * Reconfigure PLL if necessary,
- * set up the memory map,
- * initialize a bunch of registers
- */
-void
-cpu_init_f (void)
-{
-#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
- u32 val;
-#endif
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
- chip_21_errata();
-#endif
-
- reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
-
-#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
- !defined(CONFIG_SYS_4xx_GPIO_TABLE)
- /*
- * GPIO0 setup (select GPIO or alternate function)
- */
-#if defined(CONFIG_SYS_GPIO0_OR)
- out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */
-#endif
-#if defined(CONFIG_SYS_GPIO0_ODR)
- out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */
-#endif
- out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
- out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
- out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
- out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
- out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
- out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
-#if defined(CONFIG_SYS_GPIO0_ISR2H)
- out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
- out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
-#endif
-#if defined (CONFIG_SYS_GPIO0_TCR)
- out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
-#endif
-#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
-
-#if defined (CONFIG_405EP)
- /*
- * Set EMAC noise filter bits
- */
- mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE);
-#endif /* CONFIG_405EP */
-
-#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
- gpio_set_chip_configuration();
-#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
-
- /*
- * External Bus Controller (EBC) Setup
- */
-#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
-#if (defined(CONFIG_405GP) || \
- defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_405EX) || defined(CONFIG_405))
- /*
- * Move the next instructions into icache, since these modify the flash
- * we are running from!
- */
- asm volatile(" bl 0f" ::: "lr");
- asm volatile("0: mflr 3" ::: "r3");
- asm volatile(" addi 4, 0, 14" ::: "r4");
- asm volatile(" mtctr 4" ::: "ctr");
- asm volatile("1: icbt 0, 3");
- asm volatile(" addi 3, 3, 32" ::: "r3");
- asm volatile(" bdnz 1b" ::: "ctr", "cr0");
- asm volatile(" addis 3, 0, 0x0" ::: "r3");
- asm volatile(" ori 3, 3, 0xA000" ::: "r3");
- asm volatile(" mtctr 3" ::: "ctr");
- asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
-#endif
-
- mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
- mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
-#endif
-
-#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
- mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
- mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
-#endif
-
-#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
- mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
- mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
-#endif
-
-#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
- mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
- mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
-#endif
-
-#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
- mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
- mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
-#endif
-
-#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
- mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
- mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
-#endif
-
-#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
- mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
- mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
-#endif
-
-#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
- mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
- mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
-#endif
-
-#if defined (CONFIG_SYS_EBC_CFG)
- mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
-#endif
-
-#if defined(CONFIG_WATCHDOG)
- val = mfspr(SPRN_TCR);
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- val |= 0xb8000000; /* generate system reset after 1.34 seconds */
-#elif defined(CONFIG_440EPX)
- val |= 0xb0000000; /* generate system reset after 1.34 seconds */
-#else
- val |= 0xf0000000; /* generate system reset after 2.684 seconds */
-#endif
-#if defined(CONFIG_SYS_4xx_RESET_TYPE)
- val &= ~0x30000000; /* clear WRC bits */
- val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
-#endif
- mtspr(SPRN_TCR, val);
-
- val = mfspr(SPRN_TSR);
- val |= 0x80000000; /* enable watchdog timer */
- mtspr(SPRN_TSR, val);
-
- reset_4xx_watchdog();
-#endif /* CONFIG_WATCHDOG */
-
-#if defined(CONFIG_440GX)
- /* Take the GX out of compatibility mode
- * Travis Sawyer, 9 Mar 2004
- * NOTE: 440gx user manual inconsistency here
- * Compatibility mode and Ethernet Clock select are not
- * correct in the manual
- */
- mfsdr(SDR0_MFR, val);
- val &= ~0x10000000;
- mtsdr(SDR0_MFR,val);
-#endif /* CONFIG_440GX */
-
-#if defined(CONFIG_460EX)
- /*
- * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
- * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
- * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
- */
- mfsdr(SDR0_AHB_CFG, val);
- val |= 0x80;
- val &= ~0x40;
- mtsdr(SDR0_AHB_CFG, val);
- mfsdr(SDR0_USB2HOST_CFG, val);
- val &= ~0xf00;
- val |= 0x400;
- mtsdr(SDR0_USB2HOST_CFG, val);
-#endif /* CONFIG_460EX */
-
-#if defined(CONFIG_405EX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
- /*
- * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
- */
- mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
- PLB4Ax_ACR_RDP_4DEEP);
- mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
- PLB4Ax_ACR_RDP_4DEEP);
-#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
-}
-
-/*
- * initialize higher level parts of CPU like time base and timers
- */
-int cpu_init_r (void)
-{
-#if defined(CONFIG_405GP)
- uint pvr = get_pvr();
-
- /*
- * Set edge conditioning circuitry on PPC405GPr
- * for compatibility to existing PPC405GP designs.
- */
- if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
- mtdcr(CPC0_ECR, 0x60606000);
- }
-#endif /* defined(CONFIG_405GP) */
-
- return 0;
-}
-
-#if defined(CONFIG_PCI) && \
- (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRX))
-/*
- * 440EP(x)/GR(x) PCI async/sync clocking restriction:
- *
- * In asynchronous PCI mode, the synchronous PCI clock must meet
- * certain requirements. The following equation describes the
- * relationship that must be maintained between the asynchronous PCI
- * clock and synchronous PCI clock. Select an appropriate PCI:PLB
- * ratio to maintain the relationship:
- *
- * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
- */
-static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
-{
- if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000)))
- return 0;
- else
- return 1;
-}
-
-int ppc4xx_pci_sync_clock_config(u32 async)
-{
- sys_info_t sys_info;
- u32 sync;
- int div;
- u32 reg;
- u32 spcid_val[] = {
- CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
- CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };
-
- get_sys_info(&sys_info);
- sync = sys_info.freqPCI;
-
- /*
- * First check if the equation above is met
- */
- if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
- /*
- * Reconfigure PCI sync clock to meet the equation.
- * Start with highest possible PCI sync frequency
- * (divider 1).
- */
- for (div = 1; div <= 4; div++) {
- sync = sys_info.freqPLB / div;
- if (ppc4xx_pci_sync_clock_ok(sync, async))
- break;
- }
-
- if (div <= 4) {
- mtcpr(CPR0_SPCID, spcid_val[div]);
-
- mfcpr(CPR0_ICFG, reg);
- reg |= CPR0_ICFG_RLI_MASK;
- mtcpr(CPR0_ICFG, reg);
-
- /* do chip reset */
- mtspr(SPRN_DBCR0, 0x20000000);
- } else {
- /* Impossible to configure the PCI sync clock */
- return -1;
- }
- }
-
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-
-#if defined(CONFIG_4xx) && defined(CONFIG_CMD_SETGETDCR)
-
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#define _ASMLANGUAGE
-
-/*****************************************************************************
- *
- * XXX - DANGER
- * These routines make use of self modifying code. DO NOT CALL THEM
- * UNTIL THEY ARE RELOCATED TO RAM. Additionally, I do not
- * recommend them for use in anything other than an interactive
- * debugging environment. This is mainly due to performance reasons.
- *
- ****************************************************************************/
-
-/*
- * static void _create_MFDCR(unsigned short dcrn)
- *
- * Builds a 'mfdcr' instruction for get_dcr
- * function.
- */
- .section ".text"
- .align 2
- .type _create_MFDCR,@function
-_create_MFDCR:
- /*
- * Build up a 'mfdcr' instruction formatted as follows:
- *
- * OPCD | RT | DCRF | XO | CR |
- * ---------------|--------------|--------------|----|
- * 0 5 | 6 10 | 11 20 | 21 30 | 31 |
- * | | DCRN | | |
- * 31 | %r3 | (5..9|0..4) | 323 | 0 |
- *
- * Where:
- * OPCD = opcode - 31
- * RT = destination register - %r3 return register
- * DCRF = DCRN # with upper and lower halves swapped
- * XO = extended opcode - 323
- * CR = CR[CR0] NOT undefined - 0
- */
- rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */
- rlwinm r3, r3, 5, 22, 26
- or r3, r3, r0
- slwi r3, r3, 10
- oris r3, r3, 0x3e30 /* RT = %r3 */
- ori r3, r3, 323 /* XO = 323 */
- slwi r3, r3, 1 /* CR = 0 */
-
- mflr r4
- stw r3, 0(r4) /* Store instr in get_dcr() */
- dcbst r0, r4 /* Make sure val is written out */
- sync /* Wait for write to complete */
- icbi r0, r4 /* Make sure old instr is dumped */
- isync /* Wait for icbi to complete */
-
- blr
-.Lfe1: .size _create_MFDCR,.Lfe1-_create_MFDCR
-/* end _create_MFDCR() */
-
-/*
- * static void _create_MTDCR(unsigned short dcrn, unsigned long value)
- *
- * Builds a 'mtdcr' instruction for set_dcr
- * function.
- */
- .section ".text"
- .align 2
- .type _create_MTDCR,@function
-_create_MTDCR:
- /*
- * Build up a 'mtdcr' instruction formatted as follows:
- *
- * OPCD | RS | DCRF | XO | CR |
- * ---------------|--------------|--------------|----|
- * 0 5 | 6 10 | 11 20 | 21 30 | 31 |
- * | | DCRN | | |
- * 31 | %r3 | (5..9|0..4) | 451 | 0 |
- *
- * Where:
- * OPCD = opcode - 31
- * RS = source register - %r4
- * DCRF = dest. DCRN # with upper and lower halves swapped
- * XO = extended opcode - 451
- * CR = CR[CR0] NOT undefined - 0
- */
- rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */
- rlwinm r3, r3, 5, 22, 26
- or r3, r3, r0
- slwi r3, r3, 10
- oris r3, r3, 0x3e40 /* RS = %r4 */
- ori r3, r3, 451 /* XO = 451 */
- slwi r3, r3, 1 /* CR = 0 */
-
- mflr r5
- stw r3, 0(r5) /* Store instr in set_dcr() */
- dcbst r0, r5 /* Make sure val is written out */
- sync /* Wait for write to complete */
- icbi r0, r5 /* Make sure old instr is dumped */
- isync /* Wait for icbi to complete */
-
- blr
-.Lfe2: .size _create_MTDCR,.Lfe2-_create_MTDCR
-/* end _create_MTDCR() */
-
-
-/*
- * unsigned long get_dcr(unsigned short dcrn)
- *
- * Return a given DCR's value.
- */
- /* */
- /* XXX - This is self modifying code, hence */
- /* it is in the data section. */
- /* */
- .section ".data"
- .align 2
- .globl get_dcr
- .type get_dcr,@function
-get_dcr:
- mflr r0 /* Get link register */
- stwu r1, -32(r1) /* Save back chain and move SP */
- stw r0, +36(r1) /* Save link register */
-
- bl _create_MFDCR /* Build following instruction */
- /* XXX - we build this instuction up on the fly. */
- .long 0 /* Get DCR's value */
-
- lwz r0, +36(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- addi r1, r1, +32 /* Remove frame from stack */
- blr /* Return to calling function */
-.Lfe3: .size get_dcr,.Lfe3-get_dcr
-/* end get_dcr() */
-
-
-/*
- * unsigned void set_dcr(unsigned short dcrn, unsigned long value)
- *
- * Return a given DCR's value.
- */
- /*
- * XXX - This is self modifying code, hence
- * it is in the data section.
- */
- .section ".data"
- .align 2
- .globl set_dcr
- .type set_dcr,@function
-set_dcr:
- mflr r0 /* Get link register */
- stwu r1, -32(r1) /* Save back chain and move SP */
- stw r0, +36(r1) /* Save link register */
-
- bl _create_MTDCR /* Build following instruction */
- /* XXX - we build this instuction up on the fly. */
- .long 0 /* Set DCR's value */
-
- lwz r0, +36(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- addi r1, r1, +32 /* Remove frame from stack */
- blr /* Return to calling function */
-.Lfe4: .size set_dcr,.Lfe4-set_dcr
-/* end set_dcr() */
-#endif
+++ /dev/null
-/*
- * arch/powerpc/cpu/ppc4xx/denali_data_eye.c
- * Extracted from board/amcc/sequoia/sdram.c by Larry Johnson <lrj@acm.org>.
- *
- * (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx.h>
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-/*-----------------------------------------------------------------------------+
- * denali_wait_for_dlllock.
- +----------------------------------------------------------------------------*/
-int denali_wait_for_dlllock(void)
-{
- u32 val;
- int wait;
-
- /* -----------------------------------------------------------+
- * Wait for the DCC master delay line to finish calibration
- * ----------------------------------------------------------*/
- for (wait = 0; wait != 0xffff; ++wait) {
- mfsdram(DDR0_17, val);
- if (DDR0_17_DLLLOCKREG_DECODE(val)) {
- /* dlllockreg bit on */
- return 0;
- }
- }
- debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
- debug("Waiting for dlllockreg bit to raise\n");
- return -1;
-}
-
-#if defined(CONFIG_DDR_DATA_EYE)
-#define DDR_DCR_BASE 0x10
-#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
-#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
-
-/*-----------------------------------------------------------------------------+
- * wait_for_dram_init_complete.
- +----------------------------------------------------------------------------*/
-static int wait_for_dram_init_complete(void)
-{
- unsigned long val;
- int wait = 0;
-
- /* --------------------------------------------------------------+
- * Wait for 'DRAM initialization complete' bit in status register
- * -------------------------------------------------------------*/
- mtdcr(ddrcfga, DDR0_00);
-
- while (wait != 0xffff) {
- val = mfdcr(ddrcfgd);
- if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
- /* 'DRAM initialization complete' bit */
- return 0;
- else
- wait++;
- }
- debug("DRAM initialization complete bit in status register did not "
- "rise\n");
- return -1;
-}
-
-#define NUM_TRIES 64
-#define NUM_READS 10
-
-/*-----------------------------------------------------------------------------+
- * denali_core_search_data_eye.
- +----------------------------------------------------------------------------*/
-void denali_core_search_data_eye(void)
-{
- int k, j;
- u32 val;
- u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
- u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
- u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
- u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
- volatile u32 *ram_pointer;
- u32 test[NUM_TRIES] = {
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55
- };
-
- ram_pointer = (volatile u32 *)(CONFIG_SYS_SDRAM_BASE);
-
- for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
- /* for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) { */
-
- /* -----------------------------------------------------------+
- * De-assert 'start' parameter.
- * ----------------------------------------------------------*/
- mtdcr(ddrcfga, DDR0_02);
- val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) |
- DDR0_02_START_OFF;
- mtdcr(ddrcfgd, val);
-
- /* -----------------------------------------------------------+
- * Set 'wr_dqs_shift'
- * ----------------------------------------------------------*/
- mtdcr(ddrcfga, DDR0_09);
- val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) |
- DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
- mtdcr(ddrcfgd, val);
-
- /* -----------------------------------------------------------+
- * Set 'dqs_out_shift' = wr_dqs_shift + 32
- * ----------------------------------------------------------*/
- dqs_out_shift = wr_dqs_shift + 32;
- mtdcr(ddrcfga, DDR0_22);
- val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) |
- DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
- mtdcr(ddrcfgd, val);
-
- passing_cases = 0;
-
- for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64;
- dll_dqs_delay_X++) {
- /* for (dll_dqs_delay_X=1; dll_dqs_delay_X<128;
- dll_dqs_delay_X++) { */
- /* -----------------------------------------------------------+
- * Set 'dll_dqs_delay_X'.
- * ----------------------------------------------------------*/
- /* dll_dqs_delay_0 */
- mtdcr(ddrcfga, DDR0_17);
- val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
- | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
- mtdcr(ddrcfgd, val);
- /* dll_dqs_delay_1 to dll_dqs_delay_4 */
- mtdcr(ddrcfga, DDR0_18);
- val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
- | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
- | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
- | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
- | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
- mtdcr(ddrcfgd, val);
- /* dll_dqs_delay_5 to dll_dqs_delay_8 */
- mtdcr(ddrcfga, DDR0_19);
- val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
- | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
- | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
- | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
- | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
- mtdcr(ddrcfgd, val);
- /* clear any ECC errors */
- mtdcr(ddrcfga, DDR0_00);
- mtdcr(ddrcfgd,
- mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C));
-
- sync();
- eieio();
-
- /* -----------------------------------------------------------+
- * Assert 'start' parameter.
- * ----------------------------------------------------------*/
- mtdcr(ddrcfga, DDR0_02);
- val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) |
- DDR0_02_START_ON;
- mtdcr(ddrcfgd, val);
-
- sync();
- eieio();
-
- /* -----------------------------------------------------------+
- * Wait for the DCC master delay line to finish calibration
- * ----------------------------------------------------------*/
- if (denali_wait_for_dlllock() != 0) {
- printf("dll lock did not occur !!!\n");
- printf("denali_core_search_data_eye!!!\n");
- printf("wr_dqs_shift = %d - dll_dqs_delay_X = "
- "%d\n", wr_dqs_shift, dll_dqs_delay_X);
- hang();
- }
- sync();
- eieio();
-
- if (wait_for_dram_init_complete() != 0) {
- printf("dram init complete did not occur!!!\n");
- printf("denali_core_search_data_eye!!!\n");
- printf("wr_dqs_shift = %d - dll_dqs_delay_X = "
- "%d\n", wr_dqs_shift, dll_dqs_delay_X);
- hang();
- }
- udelay(100); /* wait 100us to ensure init is really completed !!! */
-
- /* write values */
- for (j = 0; j < NUM_TRIES; j++) {
- ram_pointer[j] = test[j];
-
- /* clear any cache at ram location */
- __asm__("dcbf 0,%0": :"r"(&ram_pointer[j]));
- }
-
- /* read values back */
- for (j = 0; j < NUM_TRIES; j++) {
- for (k = 0; k < NUM_READS; k++) {
- /* clear any cache at ram location */
- __asm__("dcbf 0,%0": :"r"(&ram_pointer
- [j]));
-
- if (ram_pointer[j] != test[j])
- break;
- }
-
- /* read error */
- if (k != NUM_READS)
- break;
- }
-
- /* See if the dll_dqs_delay_X value passed. */
- mtdcr(ddrcfga, DDR0_00);
- if (j < NUM_TRIES
- || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) &
- 0x3F)) {
- /* Failed */
- passing_cases = 0;
- /* break; */
- } else {
- /* Passed */
- if (passing_cases == 0)
- dll_dqs_delay_X_sw_val =
- dll_dqs_delay_X;
- passing_cases++;
- if (passing_cases >= max_passing_cases) {
- max_passing_cases = passing_cases;
- wr_dqs_shift_with_max_passing_cases =
- wr_dqs_shift;
- dll_dqs_delay_X_start_window =
- dll_dqs_delay_X_sw_val;
- dll_dqs_delay_X_end_window =
- dll_dqs_delay_X;
- }
- }
-
- /* -----------------------------------------------------------+
- * De-assert 'start' parameter.
- * ----------------------------------------------------------*/
- mtdcr(ddrcfga, DDR0_02);
- val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) |
- DDR0_02_START_OFF;
- mtdcr(ddrcfgd, val);
- } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
- } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
-
- /* -----------------------------------------------------------+
- * Largest passing window is now detected.
- * ----------------------------------------------------------*/
-
- /* Compute dll_dqs_delay_X value */
- dll_dqs_delay_X = (dll_dqs_delay_X_end_window +
- dll_dqs_delay_X_start_window) / 2;
- wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
-
- debug("DQS calibration - Window detected:\n");
- debug("max_passing_cases = %d\n", max_passing_cases);
- debug("wr_dqs_shift = %d\n", wr_dqs_shift);
- debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
- debug("dll_dqs_delay_X window = %d - %d\n",
- dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
-
- /* -----------------------------------------------------------+
- * De-assert 'start' parameter.
- * ----------------------------------------------------------*/
- mtdcr(ddrcfga, DDR0_02);
- val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
- mtdcr(ddrcfgd, val);
-
- /* -----------------------------------------------------------+
- * Set 'wr_dqs_shift'
- * ----------------------------------------------------------*/
- mtdcr(ddrcfga, DDR0_09);
- val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
- | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
- mtdcr(ddrcfgd, val);
- debug("DDR0_09=0x%08x\n", val);
-
- /* -----------------------------------------------------------+
- * Set 'dqs_out_shift' = wr_dqs_shift + 32
- * ----------------------------------------------------------*/
- dqs_out_shift = wr_dqs_shift + 32;
- mtdcr(ddrcfga, DDR0_22);
- val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
- | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
- mtdcr(ddrcfgd, val);
- debug("DDR0_22=0x%08x\n", val);
-
- /* -----------------------------------------------------------+
- * Set 'dll_dqs_delay_X'.
- * ----------------------------------------------------------*/
- /* dll_dqs_delay_0 */
- mtdcr(ddrcfga, DDR0_17);
- val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
- | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
- mtdcr(ddrcfgd, val);
- debug("DDR0_17=0x%08x\n", val);
-
- /* dll_dqs_delay_1 to dll_dqs_delay_4 */
- mtdcr(ddrcfga, DDR0_18);
- val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
- | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
- | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
- | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
- | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
- mtdcr(ddrcfgd, val);
- debug("DDR0_18=0x%08x\n", val);
-
- /* dll_dqs_delay_5 to dll_dqs_delay_8 */
- mtdcr(ddrcfga, DDR0_19);
- val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
- | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
- | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
- | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
- | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
- mtdcr(ddrcfgd, val);
- debug("DDR0_19=0x%08x\n", val);
-
- /* -----------------------------------------------------------+
- * Assert 'start' parameter.
- * ----------------------------------------------------------*/
- mtdcr(ddrcfga, DDR0_02);
- val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
- mtdcr(ddrcfgd, val);
-
- sync();
- eieio();
-
- /* -----------------------------------------------------------+
- * Wait for the DCC master delay line to finish calibration
- * ----------------------------------------------------------*/
- if (denali_wait_for_dlllock() != 0) {
- printf("dll lock did not occur !!!\n");
- hang();
- }
- sync();
- eieio();
-
- if (wait_for_dram_init_complete() != 0) {
- printf("dram init complete did not occur !!!\n");
- hang();
- }
- udelay(100); /* wait 100us to ensure init is really completed !!! */
-}
-#endif /* defined(CONFIG_DDR_DATA_EYE) */
-#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
+++ /dev/null
-/*
- * arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
- * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
- * DDR2 controller, specifically the 440EPx/GRx.
- *
- * (C) Copyright 2007-2008
- * Larry Johnson, lrj@acm.org.
- *
- * Based primarily on arch/powerpc/cpu/ppc4xx/4xx_spd_ddr2.c, which is...
- *
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * COPYRIGHT AMCC CORPORATION 2004
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc4xx.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_SPD_EEPROM) && \
- (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
-
-/*-----------------------------------------------------------------------------+
- * Defines
- *-----------------------------------------------------------------------------*/
-#define MAXDIMMS 2
-#define MAXRANKS 2
-
-#define ONE_BILLION 1000000000
-
-#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
-
-#define DLL_DQS_DELAY 0x19
-#define DLL_DQS_BYPASS 0x0B
-#define DQS_OUT_SHIFT 0x7F
-
-/*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
- * region. Right now the cache should still be disabled in U-Boot because of the
- * EMAC driver, that need it's buffer descriptor to be located in non cached
- * memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#if defined(CONFIG_4xx_DCACHE)
-#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
-#else
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Prototypes
- *-----------------------------------------------------------------------------*/
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-extern void dcbz_area(u32 start_address, u32 num_bytes);
-
-/*
- * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
- */
-void __spd_ddr_init_hang(void)
-{
- hang();
-}
-void spd_ddr_init_hang(void)
- __attribute__ ((weak, alias("__spd_ddr_init_hang")));
-
-#if defined(DEBUG)
-static void print_mcsr(void)
-{
- printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR));
-}
-
-static void denali_sdram_register_dump(void)
-{
- unsigned int sdram_data;
-
- printf("\n Register Dump:\n");
- mfsdram(DDR0_00, sdram_data);
- printf(" DDR0_00 = 0x%08X", sdram_data);
- mfsdram(DDR0_01, sdram_data);
- printf(" DDR0_01 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_02, sdram_data);
- printf(" DDR0_02 = 0x%08X", sdram_data);
- mfsdram(DDR0_03, sdram_data);
- printf(" DDR0_03 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_04, sdram_data);
- printf(" DDR0_04 = 0x%08X", sdram_data);
- mfsdram(DDR0_05, sdram_data);
- printf(" DDR0_05 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_06, sdram_data);
- printf(" DDR0_06 = 0x%08X", sdram_data);
- mfsdram(DDR0_07, sdram_data);
- printf(" DDR0_07 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_08, sdram_data);
- printf(" DDR0_08 = 0x%08X", sdram_data);
- mfsdram(DDR0_09, sdram_data);
- printf(" DDR0_09 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_10, sdram_data);
- printf(" DDR0_10 = 0x%08X", sdram_data);
- mfsdram(DDR0_11, sdram_data);
- printf(" DDR0_11 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_12, sdram_data);
- printf(" DDR0_12 = 0x%08X", sdram_data);
- mfsdram(DDR0_14, sdram_data);
- printf(" DDR0_14 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_17, sdram_data);
- printf(" DDR0_17 = 0x%08X", sdram_data);
- mfsdram(DDR0_18, sdram_data);
- printf(" DDR0_18 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_19, sdram_data);
- printf(" DDR0_19 = 0x%08X", sdram_data);
- mfsdram(DDR0_20, sdram_data);
- printf(" DDR0_20 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_21, sdram_data);
- printf(" DDR0_21 = 0x%08X", sdram_data);
- mfsdram(DDR0_22, sdram_data);
- printf(" DDR0_22 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_23, sdram_data);
- printf(" DDR0_23 = 0x%08X", sdram_data);
- mfsdram(DDR0_24, sdram_data);
- printf(" DDR0_24 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_25, sdram_data);
- printf(" DDR0_25 = 0x%08X", sdram_data);
- mfsdram(DDR0_26, sdram_data);
- printf(" DDR0_26 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_27, sdram_data);
- printf(" DDR0_27 = 0x%08X", sdram_data);
- mfsdram(DDR0_28, sdram_data);
- printf(" DDR0_28 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_31, sdram_data);
- printf(" DDR0_31 = 0x%08X", sdram_data);
- mfsdram(DDR0_32, sdram_data);
- printf(" DDR0_32 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_33, sdram_data);
- printf(" DDR0_33 = 0x%08X", sdram_data);
- mfsdram(DDR0_34, sdram_data);
- printf(" DDR0_34 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_35, sdram_data);
- printf(" DDR0_35 = 0x%08X", sdram_data);
- mfsdram(DDR0_36, sdram_data);
- printf(" DDR0_36 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_37, sdram_data);
- printf(" DDR0_37 = 0x%08X", sdram_data);
- mfsdram(DDR0_38, sdram_data);
- printf(" DDR0_38 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_39, sdram_data);
- printf(" DDR0_39 = 0x%08X", sdram_data);
- mfsdram(DDR0_40, sdram_data);
- printf(" DDR0_40 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_41, sdram_data);
- printf(" DDR0_41 = 0x%08X", sdram_data);
- mfsdram(DDR0_42, sdram_data);
- printf(" DDR0_42 = 0x%08X\n", sdram_data);
- mfsdram(DDR0_43, sdram_data);
- printf(" DDR0_43 = 0x%08X", sdram_data);
- mfsdram(DDR0_44, sdram_data);
- printf(" DDR0_44 = 0x%08X\n", sdram_data);
-}
-#else
-static inline void denali_sdram_register_dump(void)
-{
-}
-
-inline static void print_mcsr(void)
-{
-}
-#endif /* defined(DEBUG) */
-
-static int is_ecc_enabled(void)
-{
- u32 val;
-
- mfsdram(DDR0_22, val);
- return 0x3 == DDR0_22_CTRL_RAW_DECODE(val);
-}
-
-static unsigned char spd_read(u8 chip, unsigned int addr)
-{
- u8 data[2];
-
- if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) {
- debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr);
- return 0;
- }
- debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n",
- chip, addr, data[0]);
- return data[0];
-}
-
-static unsigned long get_tcyc(unsigned char reg)
-{
- /*
- * Byte 9, et al: Cycle time for CAS Latency=X, is split into two
- * nibbles: the higher order nibble (bits 4-7) designates the cycle time
- * to a granularity of 1ns; the value presented by the lower order
- * nibble (bits 0-3) has a granularity of .1ns and is added to the value
- * designated by the higher nibble. In addition, four lines of the lower
- * order nibble are assigned to support +.25, +.33, +.66, and +.75.
- */
-
- unsigned char subfield_b = reg & 0x0F;
-
- switch (subfield_b & 0x0F) {
- case 0x0:
- case 0x1:
- case 0x2:
- case 0x3:
- case 0x4:
- case 0x5:
- case 0x6:
- case 0x7:
- case 0x8:
- case 0x9:
- return 1000 * (reg >> 4) + 100 * subfield_b;
- case 0xA:
- return 1000 * (reg >> 4) + 250;
- case 0xB:
- return 1000 * (reg >> 4) + 333;
- case 0xC:
- return 1000 * (reg >> 4) + 667;
- case 0xD:
- return 1000 * (reg >> 4) + 750;
- }
- return 0;
-}
-
-/*------------------------------------------------------------------
- * Find the installed DIMMs, make sure that the are DDR2, and fill
- * in the dimm_ranks array. Then dimm_ranks[dimm_num] > 0 iff the
- * DIMM and dimm_num is present.
- * Note: Because there are only two chip-select lines, it is assumed
- * that a board with a single socket can support two ranks on that
- * socket, while a board with two sockets can support only one rank
- * on each socket.
- *-----------------------------------------------------------------*/
-static void get_spd_info(unsigned long dimm_ranks[],
- unsigned long *ranks,
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long dimm_found = false;
- unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
- unsigned char num_of_bytes;
- unsigned char total_size;
-
- *ranks = 0;
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- num_of_bytes = 0;
- total_size = 0;
-
- num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
- total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
- if ((num_of_bytes != 0) && (total_size != 0)) {
- unsigned char const dimm_type =
- spd_read(iic0_dimm_addr[dimm_num], 2);
-
- unsigned long ranks_on_dimm =
- (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1;
-
- if (8 != dimm_type) {
- switch (dimm_type) {
- case 1:
- printf("ERROR: Standard Fast Page Mode "
- "DRAM DIMM");
- break;
- case 2:
- printf("ERROR: EDO DIMM");
- break;
- case 3:
- printf("ERROR: Pipelined Nibble DIMM");
- break;
- case 4:
- printf("ERROR: SDRAM DIMM");
- break;
- case 5:
- printf("ERROR: Multiplexed ROM DIMM");
- break;
- case 6:
- printf("ERROR: SGRAM DIMM");
- break;
- case 7:
- printf("ERROR: DDR1 DIMM");
- break;
- default:
- printf("ERROR: Unknown DIMM (type %d)",
- (unsigned int)dimm_type);
- break;
- }
- printf(" detected in slot %lu.\n", dimm_num);
- printf("Only DDR2 SDRAM DIMMs are supported."
- "\n");
- printf("Replace the module with a DDR2 DIMM."
- "\n\n");
- spd_ddr_init_hang();
- }
- dimm_found = true;
- debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
- "\n", dimm_num, ranks_on_dimm);
- if (ranks_on_dimm > max_ranks_per_dimm) {
- printf("WARNING: DRAM DIMM in slot %lu has %lu "
- "ranks.\n", dimm_num, ranks_on_dimm);
- if (1 == max_ranks_per_dimm) {
- printf("Only one rank will be used.\n");
- } else {
- printf
- ("Only two ranks will be used.\n");
- }
- ranks_on_dimm = max_ranks_per_dimm;
- }
- dimm_ranks[dimm_num] = ranks_on_dimm;
- *ranks += ranks_on_dimm;
- } else {
- dimm_ranks[dimm_num] = 0;
- debug("DIMM slot %lu: Not populated\n", dimm_num);
- }
- }
- if (dimm_found == false) {
- printf("ERROR: No memory installed.\n");
- printf("Install at least one DDR2 DIMM.\n\n");
- spd_ddr_init_hang();
- }
- debug("Total number of ranks = %ld\n", *ranks);
-}
-
-/*------------------------------------------------------------------
- * For the memory DIMMs installed, this routine verifies that
- * frequency previously calculated is supported.
- *-----------------------------------------------------------------*/
-static void check_frequency(unsigned long *dimm_ranks,
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks,
- unsigned long sdram_freq)
-{
- unsigned long dimm_num;
- unsigned long cycle_time;
- unsigned long calc_cycle_time;
-
- /*
- * calc_cycle_time is calculated from DDR frequency set by board/chip
- * and is expressed in picoseconds to match the way DIMM cycle time is
- * calculated below.
- */
- calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq);
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_ranks[dimm_num]) {
- cycle_time =
- get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9));
- debug("cycle_time=%ld ps\n", cycle_time);
-
- if (cycle_time > (calc_cycle_time + 10)) {
- /*
- * the provided sdram cycle_time is too small
- * for the available DIMM cycle_time. The
- * additionnal 10ps is here to accept a small
- * incertainty.
- */
- printf
- ("ERROR: DRAM DIMM detected with cycle_time %d ps in "
- "slot %d \n while calculated cycle time is %d ps.\n",
- (unsigned int)cycle_time,
- (unsigned int)dimm_num,
- (unsigned int)calc_cycle_time);
- printf
- ("Replace the DIMM, or change DDR frequency via "
- "strapping bits.\n\n");
- spd_ddr_init_hang();
- }
- }
- }
-}
-
-/*------------------------------------------------------------------
- * This routine gets size information for the installed memory
- * DIMMs.
- *-----------------------------------------------------------------*/
-static void get_dimm_size(unsigned long dimm_ranks[],
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks,
- unsigned long *const rows,
- unsigned long *const banks,
- unsigned long *const cols, unsigned long *const width)
-{
- unsigned long dimm_num;
-
- *rows = 0;
- *banks = 0;
- *cols = 0;
- *width = 0;
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_ranks[dimm_num]) {
- unsigned long t;
-
- /* Rows */
- t = spd_read(iic0_dimm_addr[dimm_num], 3);
- if (0 == *rows) {
- *rows = t;
- } else if (t != *rows) {
- printf("ERROR: DRAM DIMM modules do not all "
- "have the same number of rows.\n\n");
- spd_ddr_init_hang();
- }
- /* Banks */
- t = spd_read(iic0_dimm_addr[dimm_num], 17);
- if (0 == *banks) {
- *banks = t;
- } else if (t != *banks) {
- printf("ERROR: DRAM DIMM modules do not all "
- "have the same number of banks.\n\n");
- spd_ddr_init_hang();
- }
- /* Columns */
- t = spd_read(iic0_dimm_addr[dimm_num], 4);
- if (0 == *cols) {
- *cols = t;
- } else if (t != *cols) {
- printf("ERROR: DRAM DIMM modules do not all "
- "have the same number of columns.\n\n");
- spd_ddr_init_hang();
- }
- /* Data width */
- t = spd_read(iic0_dimm_addr[dimm_num], 6);
- if (0 == *width) {
- *width = t;
- } else if (t != *width) {
- printf("ERROR: DRAM DIMM modules do not all "
- "have the same data width.\n\n");
- spd_ddr_init_hang();
- }
- }
- }
- debug("Number of rows = %ld\n", *rows);
- debug("Number of columns = %ld\n", *cols);
- debug("Number of banks = %ld\n", *banks);
- debug("Data width = %ld\n", *width);
- if (*rows > 14) {
- printf("ERROR: DRAM DIMM modules have %lu address rows.\n",
- *rows);
- printf("Only modules with 14 or fewer rows are supported.\n\n");
- spd_ddr_init_hang();
- }
- if (4 != *banks && 8 != *banks) {
- printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks);
- printf("Only modules with 4 or 8 banks are supported.\n\n");
- spd_ddr_init_hang();
- }
- if (*cols > 12) {
- printf("ERROR: DRAM DIMM modules have %lu address columns.\n",
- *cols);
- printf("Only modules with 12 or fewer columns are "
- "supported.\n\n");
- spd_ddr_init_hang();
- }
- if (32 != *width && 40 != *width && 64 != *width && 72 != *width) {
- printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n",
- *width);
- printf("Only modules with widths of 32, 40, 64, and 72 bits "
- "are supported.\n\n");
- spd_ddr_init_hang();
- }
-}
-
-/*------------------------------------------------------------------
- * Only 1.8V modules are supported. This routine verifies this.
- *-----------------------------------------------------------------*/
-static void check_voltage_type(unsigned long dimm_ranks[],
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks)
-{
- unsigned long dimm_num;
- unsigned long voltage_type;
-
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_ranks[dimm_num]) {
- voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
- if (0x05 != voltage_type) { /* 1.8V for DDR2 */
- printf("ERROR: Slot %lu provides 1.8V for DDR2 "
- "DIMMs.\n", dimm_num);
- switch (voltage_type) {
- case 0x00:
- printf("This DIMM is 5.0 Volt/TTL.\n");
- break;
- case 0x01:
- printf("This DIMM is LVTTL.\n");
- break;
- case 0x02:
- printf("This DIMM is 1.5 Volt.\n");
- break;
- case 0x03:
- printf("This DIMM is 3.3 Volt/TTL.\n");
- break;
- case 0x04:
- printf("This DIMM is 2.5 Volt.\n");
- break;
- default:
- printf("This DIMM is an unknown "
- "voltage.\n");
- break;
- }
- printf("Replace it with a 1.8V DDR2 DIMM.\n\n");
- spd_ddr_init_hang();
- }
- }
- }
-}
-
-static void program_ddr0_03(unsigned long dimm_ranks[],
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks,
- unsigned long sdram_freq,
- unsigned long rows, unsigned long *cas_latency)
-{
- unsigned long dimm_num;
- unsigned long cas_index;
- unsigned long cycle_2_0_clk;
- unsigned long cycle_3_0_clk;
- unsigned long cycle_4_0_clk;
- unsigned long cycle_5_0_clk;
- unsigned long max_2_0_tcyc_ps = 100;
- unsigned long max_3_0_tcyc_ps = 100;
- unsigned long max_4_0_tcyc_ps = 100;
- unsigned long max_5_0_tcyc_ps = 100;
- unsigned char cas_available = 0x3C; /* value for DDR2 */
- u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2);
- unsigned int const tcyc_addr[3] = { 9, 23, 25 };
-
- /*------------------------------------------------------------------
- * Get the board configuration info.
- *-----------------------------------------------------------------*/
- debug("sdram_freq = %ld\n", sdram_freq);
-
- /*------------------------------------------------------------------
- * Handle the timing. We need to find the worst case timing of all
- * the dimm modules installed.
- *-----------------------------------------------------------------*/
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_ranks[dimm_num]) {
- unsigned char const cas_bit =
- spd_read(iic0_dimm_addr[dimm_num], 18);
- unsigned char cas_mask;
-
- cas_available &= cas_bit;
- for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) {
- if (cas_bit & cas_mask)
- break;
- }
- debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n",
- cas_bit, cas_mask);
-
- for (cas_index = 0; cas_index < 3;
- cas_mask >>= 1, cas_index++) {
- unsigned long cycle_time_ps;
-
- if (!(cas_available & cas_mask)) {
- continue;
- }
- cycle_time_ps =
- get_tcyc(spd_read(iic0_dimm_addr[dimm_num],
- tcyc_addr[cas_index]));
-
- debug("cas_index = %ld: cycle_time_ps = %ld\n",
- cas_index, cycle_time_ps);
- /*
- * DDR2 devices use the following bitmask for CAS latency:
- * Bit 7 6 5 4 3 2 1 0
- * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
- */
- switch (cas_mask) {
- case 0x20:
- max_5_0_tcyc_ps =
- max(max_5_0_tcyc_ps, cycle_time_ps);
- break;
- case 0x10:
- max_4_0_tcyc_ps =
- max(max_4_0_tcyc_ps, cycle_time_ps);
- break;
- case 0x08:
- max_3_0_tcyc_ps =
- max(max_3_0_tcyc_ps, cycle_time_ps);
- break;
- case 0x04:
- max_2_0_tcyc_ps =
- max(max_2_0_tcyc_ps, cycle_time_ps);
- break;
- }
- }
- }
- }
- debug("cas_available (bit map) = 0x%02X\n", cas_available);
-
- /*------------------------------------------------------------------
- * Set the SDRAM mode, SDRAM_MMODE
- *-----------------------------------------------------------------*/
-
- /* add 10 here because of rounding problems */
- cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10;
- cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10;
- cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10;
- cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10;
- debug("cycle_2_0_clk = %ld\n", cycle_2_0_clk);
- debug("cycle_3_0_clk = %ld\n", cycle_3_0_clk);
- debug("cycle_4_0_clk = %ld\n", cycle_4_0_clk);
- debug("cycle_5_0_clk = %ld\n", cycle_5_0_clk);
-
- if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) {
- *cas_latency = 2;
- ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) |
- DDR0_03_CASLAT_LIN_ENCODE(0x4);
- } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) {
- *cas_latency = 3;
- ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) |
- DDR0_03_CASLAT_LIN_ENCODE(0x6);
- } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) {
- *cas_latency = 4;
- ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) |
- DDR0_03_CASLAT_LIN_ENCODE(0x8);
- } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) {
- *cas_latency = 5;
- ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) |
- DDR0_03_CASLAT_LIN_ENCODE(0xA);
- } else {
- printf("ERROR: Cannot find a supported CAS latency with the "
- "installed DIMMs.\n");
- printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, "
- "and 5.0 are supported.\n");
- printf("Make sure the PLB speed is within the supported range "
- "of the DIMMs.\n");
- printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld "
- "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk,
- cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
- spd_ddr_init_hang();
- }
- debug("CAS latency = %ld\n", *cas_latency);
- mtsdram(DDR0_03, ddr0_03);
-}
-
-static void program_ddr0_04(unsigned long dimm_ranks[],
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks,
- unsigned long sdram_freq)
-{
- unsigned long dimm_num;
- unsigned long t_rc_ps = 0;
- unsigned long t_rrd_ps = 0;
- unsigned long t_rtp_ps = 0;
- unsigned long t_rc_clk;
- unsigned long t_rrd_clk;
- unsigned long t_rtp_clk;
-
- /*------------------------------------------------------------------
- * Handle the timing. We need to find the worst case timing of all
- * the dimm modules installed.
- *-----------------------------------------------------------------*/
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_ranks[dimm_num]) {
- unsigned long ps;
-
- /* tRC */
- ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41);
- switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) {
- case 0x1:
- ps += 250;
- break;
- case 0x2:
- ps += 333;
- break;
- case 0x3:
- ps += 500;
- break;
- case 0x4:
- ps += 667;
- break;
- case 0x5:
- ps += 750;
- break;
- }
- t_rc_ps = max(t_rc_ps, ps);
- /* tRRD */
- ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28);
- t_rrd_ps = max(t_rrd_ps, ps);
- /* tRTP */
- ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38);
- t_rtp_ps = max(t_rtp_ps, ps);
- }
- }
- debug("t_rc_ps = %ld\n", t_rc_ps);
- t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000;
- debug("t_rrd_ps = %ld\n", t_rrd_ps);
- t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000;
- debug("t_rtp_ps = %ld\n", t_rtp_ps);
- t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000;
- mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) |
- DDR0_04_TRRD_ENCODE(t_rrd_clk) |
- DDR0_04_TRTP_ENCODE(t_rtp_clk));
-}
-
-static void program_ddr0_05(unsigned long dimm_ranks[],
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks,
- unsigned long sdram_freq)
-{
- unsigned long dimm_num;
- unsigned long t_rp_ps = 0;
- unsigned long t_ras_ps = 0;
- unsigned long t_rp_clk;
- unsigned long t_ras_clk;
- u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2);
-
- /*------------------------------------------------------------------
- * Handle the timing. We need to find the worst case timing of all
- * the dimm modules installed.
- *-----------------------------------------------------------------*/
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_ranks[dimm_num]) {
- unsigned long ps;
-
- /* tRP */
- ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27);
- t_rp_ps = max(t_rp_ps, ps);
- /* tRAS */
- ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30);
- t_ras_ps = max(t_ras_ps, ps);
- }
- }
- debug("t_rp_ps = %ld\n", t_rp_ps);
- t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000;
- debug("t_ras_ps = %ld\n", t_ras_ps);
- t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000;
- mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) |
- DDR0_05_TRAS_MIN_ENCODE(t_ras_clk));
-}
-
-static void program_ddr0_06(unsigned long dimm_ranks[],
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks,
- unsigned long sdram_freq)
-{
- unsigned long dimm_num;
- unsigned char spd_40;
- unsigned long t_wtr_ps = 0;
- unsigned long t_rfc_ps = 0;
- unsigned long t_wtr_clk;
- unsigned long t_rfc_clk;
- u32 ddr0_06 =
- DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200);
-
- /*------------------------------------------------------------------
- * Handle the timing. We need to find the worst case timing of all
- * the dimm modules installed.
- *-----------------------------------------------------------------*/
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_ranks[dimm_num]) {
- unsigned long ps;
-
- /* tWTR */
- ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37);
- t_wtr_ps = max(t_wtr_ps, ps);
- /* tRFC */
- ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42);
- spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40);
- ps += 256000 * (spd_40 & 0x01);
- switch ((spd_40 & 0x0E) >> 1) {
- case 0x1:
- ps += 250;
- break;
- case 0x2:
- ps += 333;
- break;
- case 0x3:
- ps += 500;
- break;
- case 0x4:
- ps += 667;
- break;
- case 0x5:
- ps += 750;
- break;
- }
- t_rfc_ps = max(t_rfc_ps, ps);
- }
- }
- debug("t_wtr_ps = %ld\n", t_wtr_ps);
- t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000;
- debug("t_rfc_ps = %ld\n", t_rfc_ps);
- t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000;
- mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) |
- DDR0_06_TRFC_ENCODE(t_rfc_clk));
-}
-
-static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks)
-{
- unsigned long csmap;
-
- if (2 == ranks) {
- /* Both chip selects in use */
- csmap = 0x03;
- } else {
- /* One chip select in use */
- csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2;
- }
- mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) |
- DDR0_10_CS_MAP_ENCODE(csmap) |
- DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0));
-}
-
-static void program_ddr0_11(unsigned long sdram_freq)
-{
- unsigned long const t_xsnr_ps = 200000; /* 200 ns */
- unsigned long t_xsnr_clk;
-
- debug("t_xsnr_ps = %ld\n", t_xsnr_ps);
- t_xsnr_clk =
- (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000;
- mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) |
- DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200));
-}
-
-static void program_ddr0_22(unsigned long dimm_ranks[],
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks, unsigned long width)
-{
-#if defined(CONFIG_DDR_ECC)
- unsigned long dimm_num;
- unsigned long ecc_available = width >= 64;
- u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
- DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
- DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS);
-
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_ranks[dimm_num]) {
- /* Check for ECC */
- if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
- 0x02)) {
- ecc_available = false;
- }
- }
- }
- if (ecc_available) {
- debug("ECC found on all DIMMs present\n");
- mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3));
- } else {
- debug("ECC not found on some or all DIMMs present\n");
- mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0));
- }
-#else
- mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) |
- DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
- DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
- DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS));
-#endif /* defined(CONFIG_DDR_ECC) */
-}
-
-static void program_ddr0_24(unsigned long ranks)
-{
- u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */
- DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0);
-
- if (2 == ranks) {
- /* Both chip selects in use */
- ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) |
- DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2);
- } else {
- /* One chip select in use */
- /* One of the two fields added to ddr0_24 is a "don't care" */
- ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) |
- DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1);
- }
- mtsdram(DDR0_24, ddr0_24);
-}
-
-static void program_ddr0_26(unsigned long sdram_freq)
-{
- unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */
- /* TODO: check definition of tRAS_MAX */
- unsigned long const t_ras_max_ps = 9 * t_ref_ps;
- unsigned long t_ras_max_clk;
- unsigned long t_ref_clk;
-
- /* Round down t_ras_max_clk and t_ref_clk */
- debug("t_ras_max_ps = %ld\n", t_ras_max_ps);
- t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000;
- debug("t_ref_ps = %ld\n", t_ref_ps);
- t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000;
- mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) |
- DDR0_26_TREF_ENCODE(t_ref_clk));
-}
-
-static void program_ddr0_27(unsigned long sdram_freq)
-{
- unsigned long const t_init_ps = 200000000; /* 200 us. init */
- unsigned long t_init_clk;
-
- debug("t_init_ps = %ld\n", t_init_ps);
- t_init_clk =
- (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000;
- mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) |
- DDR0_27_TINIT_ENCODE(t_init_clk));
-}
-
-static void program_ddr0_43(unsigned long dimm_ranks[],
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks,
- unsigned long sdram_freq,
- unsigned long cols, unsigned long banks)
-{
- unsigned long dimm_num;
- unsigned long t_wr_ps = 0;
- unsigned long t_wr_clk;
- u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) |
- DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) |
- DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0);
-
- /*------------------------------------------------------------------
- * Handle the timing. We need to find the worst case timing of all
- * the dimm modules installed.
- *-----------------------------------------------------------------*/
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_ranks[dimm_num]) {
- unsigned long ps;
-
- ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36);
- t_wr_ps = max(t_wr_ps, ps);
- }
- }
- debug("t_wr_ps = %ld\n", t_wr_ps);
- t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000;
- mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk));
-}
-
-static void program_ddr0_44(unsigned long dimm_ranks[],
- unsigned char const iic0_dimm_addr[],
- unsigned long num_dimm_banks,
- unsigned long sdram_freq)
-{
- unsigned long dimm_num;
- unsigned long t_rcd_ps = 0;
- unsigned long t_rcd_clk;
-
- /*------------------------------------------------------------------
- * Handle the timing. We need to find the worst case timing of all
- * the dimm modules installed.
- *-----------------------------------------------------------------*/
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- /* If a dimm is installed in a particular slot ... */
- if (dimm_ranks[dimm_num]) {
- unsigned long ps;
-
- ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29);
- t_rcd_ps = max(t_rcd_ps, ps);
- }
- }
- debug("t_rcd_ps = %ld\n", t_rcd_ps);
- t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000;
- mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk));
-}
-
-/*-----------------------------------------------------------------------------+
- * dram_init. Initializes the 440EPx/GPx DDR SDRAM controller.
- * Note: This routine runs from flash with a stack set up in the chip's
- * sram space. It is important that the routine does not require .sbss, .bss or
- * .data sections. It also cannot call routines that require these sections.
- *-----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------
- * Function: dram_init
- * Description: Configures SDRAM memory banks for DDR operation.
- * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
- * via the IIC bus and then configures the DDR SDRAM memory
- * banks appropriately. If Auto Memory Configuration is
- * not used, it is assumed that no DIMM is plugged
- *-----------------------------------------------------------------------------*/
-int dram_init(void)
-{
- unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
- unsigned long dimm_ranks[MAXDIMMS];
- unsigned long ranks;
- unsigned long rows;
- unsigned long banks;
- unsigned long cols;
- unsigned long width;
- unsigned long const sdram_freq = get_bus_freq(0);
- unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */
- unsigned long cas_latency = 0; /* to quiet initialization warning */
- unsigned long dram_size;
-
- debug("\nEntering dram_init()\n");
-
- /*------------------------------------------------------------------
- * Stop the DDR-SDRAM controller.
- *-----------------------------------------------------------------*/
- mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));
-
- /*
- * Make sure I2C controller is initialized
- * before continuing.
- */
- /* switch to correct I2C bus */
- i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
-
- /*------------------------------------------------------------------
- * Clear out the serial presence detect buffers.
- * Perform IIC reads from the dimm. Fill in the spds.
- * Check to see if the dimm slots are populated
- *-----------------------------------------------------------------*/
- get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Check the frequency supported for the dimms plugged.
- *-----------------------------------------------------------------*/
- check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
-
- /*------------------------------------------------------------------
- * Check and get size information.
- *-----------------------------------------------------------------*/
- get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
- &cols, &width);
-
- /*------------------------------------------------------------------
- * Check the voltage type for the dimms plugged.
- *-----------------------------------------------------------------*/
- check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);
-
- /*------------------------------------------------------------------
- * Program registers for SDRAM controller.
- *-----------------------------------------------------------------*/
- mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
- DDR0_00_DLL_START_POINT_DECODE(0x0A));
-
- mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
- DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
- DDR0_01_INT_MASK_ENCODE(0xFF));
-
- program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
- rows, &cas_latency);
-
- program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
-
- program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
-
- program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
-
- /*
- * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia
- * board SDRAM, but may be overly conservative.
- */
- mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
- DDR0_07_TFAW_ENCODE(13) |
- DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
- DDR0_07_AREFRESH_ENCODE(0));
-
- mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
- DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
- DDR0_08_DDRII_ENCODE(1));
-
- mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
- DDR0_09_RTT_0_ENCODE(0x1) |
- DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
- DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));
-
- program_ddr0_10(dimm_ranks, ranks);
-
- program_ddr0_11(sdram_freq);
-
- mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));
-
- mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
- DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
- DDR0_14_REG_DIMM_ENABLE_ENCODE(0));
-
- mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));
-
- mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
- DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
- DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
- DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));
-
- mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
- DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
- DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
- DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));
-
- mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
- DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
- DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
- DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));
-
- mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
- DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
- DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
- DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));
-
- program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);
-
- mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
- DDR0_23_FWC_ENCODE(0));
-
- program_ddr0_24(ranks);
-
- program_ddr0_26(sdram_freq);
-
- program_ddr0_27(sdram_freq);
-
- mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
- DDR0_28_EMRS2_DATA_ENCODE(0x0000));
-
- mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
-
- mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) |
- DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
-
- program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
- cols, banks);
-
- program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
-
- denali_sdram_register_dump();
-
- dram_size = (width >= 64) ? 8 : 4;
- dram_size *= 1 << cols;
- dram_size *= banks;
- dram_size *= 1 << rows;
- dram_size *= ranks;
- debug("dram_size = %lu\n", dram_size);
-
- /* Start the SDRAM controller */
- mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
- denali_wait_for_dlllock();
-
-#if defined(CONFIG_DDR_DATA_EYE)
- /*
- * Map the first 1 MiB of memory in the TLB, and perform the data eye
- * search.
- */
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
- denali_core_search_data_eye();
- denali_sdram_register_dump();
- remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
-#endif
-
-#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
- sync();
- /* Zero the memory */
- debug("Zeroing SDRAM...");
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
-#else
-#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
-#endif
- /* Write modified dcache lines back to memory */
- clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
- debug("Completed\n");
- sync();
- remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
-
-#if defined(CONFIG_DDR_ECC)
- /*
- * If ECC is enabled, clear and enable interrupts
- */
- if (is_ecc_enabled()) {
- u32 val;
-
- sync();
- /* Clear error status */
- mfsdram(DDR0_00, val);
- mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
- /* Set 'int_mask' parameter to functionnal value */
- mfsdram(DDR0_01, val);
- mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
- DDR0_01_INT_MASK_ALL_OFF);
-#if defined(CONFIG_DDR_DATA_EYE)
- /*
- * Running denali_core_search_data_eye() when ECC is enabled
- * causes non-ECC machine checks. This clears them.
- */
- print_mcsr();
- mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
- print_mcsr();
-#endif
- sync();
- }
-#endif /* defined(CONFIG_DDR_ECC) */
-#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
-
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
- gd->ram_size = dram_size;
-
- return 0;
-}
-
-void board_add_ram_info(int use_default)
-{
- u32 val;
-
- printf(" (ECC");
- if (!is_ecc_enabled()) {
- printf(" not");
- }
- printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000);
-
- mfsdram(DDR0_03, val);
- printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
-}
-#endif /* CONFIG_SPD_EEPROM */
+++ /dev/null
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- * Grant Erickson <gerickson@nuovations.com>
- *
- * (C) Copyright 2005-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Jun Gu, Artesyn Technology, jung@artesyncp.com
- *
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Description:
- * This file implements generic DRAM ECC initialization for
- * PowerPC processors using a SDRAM DDR/DDR2 controller,
- * including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and
- * 460EX/GT.
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-
-#include "ecc.h"
-
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
- defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
-#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
-
-#if defined(CONFIG_405EX)
-/*
- * Currently only 405EX uses 16bit data bus width as an alternative
- * option to 32bit data width (SDRAM0_MCOPT1_WDTH)
- */
-#define SDRAM_DATA_ALT_WIDTH 2
-#else
-#define SDRAM_DATA_ALT_WIDTH 8
-#endif
-
-static void wait_ddr_idle(void)
-{
- u32 val;
-
- do {
- mfsdram(SDRAM_MCSTAT, val);
- } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
-}
-
-static void program_ecc_addr(unsigned long start_address,
- unsigned long num_bytes,
- unsigned long tlb_word2_i_value)
-{
- unsigned long current_address;
- unsigned long end_address;
- unsigned long address_increment;
- unsigned long mcopt1;
- char str[] = "ECC generation -";
- char slash[] = "\\|/-\\|/-";
- int loop = 0;
- int loopi = 0;
-
- current_address = start_address;
- mfsdram(SDRAM_MCOPT1, mcopt1);
- if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
- mtsdram(SDRAM_MCOPT1,
- (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
- sync();
- eieio();
- wait_ddr_idle();
-
- puts(str);
-
-#ifdef CONFIG_440
- if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
-#endif
- /* ECC bit set method for non-cached memory */
- if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
- address_increment = 4;
- else
- address_increment = SDRAM_DATA_ALT_WIDTH;
- end_address = current_address + num_bytes;
-
- while (current_address < end_address) {
- *((unsigned long *)current_address) = 0;
- current_address += address_increment;
-
- if ((loop++ % (2 << 20)) == 0) {
- putc('\b');
- putc(slash[loopi++ % 8]);
- }
- }
-#ifdef CONFIG_440
- } else {
- /* ECC bit set method for cached memory */
- dcbz_area(start_address, num_bytes);
- /* Write modified dcache lines back to memory */
- clean_dcache_range(start_address, start_address + num_bytes);
- }
-#endif /* CONFIG_440 */
-
- blank_string(strlen(str));
-
- sync();
- eieio();
- wait_ddr_idle();
-
- /* clear ECC error repoting registers */
- mtsdram(SDRAM_ECCES, 0xffffffff);
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
- /*
- * IBM DDR(1) core (440GX):
- * Clear Mx bits in SDRAM0_BESR0/1
- */
- mtsdram(SDRAM0_BESR0, 0xffffffff);
- mtsdram(SDRAM0_BESR1, 0xffffffff);
-#elif defined(CONFIG_440)
- /*
- * 440/460 DDR2 core:
- * Clear EMID (Error PLB Master ID) in MQ0_ESL
- */
- mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
-#else
- /*
- * 405EX(r) DDR2 core:
- * Clear M0ID (Error PLB Master ID) in SDRAM_BESR
- */
- mtsdram(SDRAM_BESR, 0xf0000000);
-#endif
-
- mtsdram(SDRAM_MCOPT1,
- (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
- sync();
- eieio();
- wait_ddr_idle();
- }
-}
-
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
-void ecc_init(unsigned long * const start, unsigned long size)
-{
- /*
- * Init ECC with cache disabled (on PPC's with IBM DDR
- * controller (non DDR2), not tested with cache enabled yet
- */
- program_ecc_addr((u32)start, size, TLB_WORD2_I_ENABLE);
-}
-#endif
-
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
-void do_program_ecc(unsigned long tlb_word2_i_value)
-{
- unsigned long mcopt1;
- unsigned long mcopt2;
- unsigned long mcstat;
- phys_size_t memsize = sdram_memsize();
-
- if (memsize > CONFIG_MAX_MEM_MAPPED) {
- printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
- return;
- }
-
- mfsdram(SDRAM_MCOPT1, mcopt1);
- mfsdram(SDRAM_MCOPT2, mcopt2);
-
- if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
- /* DDR controller must be enabled and not in self-refresh. */
- mfsdram(SDRAM_MCSTAT, mcstat);
- if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
- && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
- && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
- == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
-
- program_ecc_addr(0, memsize, tlb_word2_i_value);
- }
- }
-}
-#endif
-
-#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
-#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
+++ /dev/null
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- * Grant Erickson <gerickson@nuovations.com>
- *
- * Copyright (c) 2007-2009 DENX Software Engineering, GmbH
- * Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Description:
- * This file implements ECC initialization for PowerPC processors
- * using the IBM SDRAM DDR1 & DDR2 controller.
- */
-
-#ifndef _ECC_H_
-#define _ECC_H_
-
-/*
- * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
- * compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
- * we need to make some processor dependant defines used later on by the
- * driver.
- */
-
-/* For 440GP/GX/EP/GR */
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
-#define SDRAM_MCOPT1 SDRAM_CFG0
-#define SDRAM_MCOPT1_MCHK_MASK SDRAM_CFG0_MCHK_MASK
-#define SDRAM_MCOPT1_MCHK_NON SDRAM_CFG0_MCHK_NON
-#define SDRAM_MCOPT1_MCHK_GEN SDRAM_CFG0_MCHK_GEN
-#define SDRAM_MCOPT1_MCHK_CHK SDRAM_CFG0_MCHK_CHK
-#define SDRAM_MCOPT1_MCHK_CHK_REP SDRAM_CFG0_MCHK_CHK
-#define SDRAM_MCOPT1_DMWD_MASK SDRAM_CFG0_DMWD_MASK
-#define SDRAM_MCOPT1_DMWD_32 SDRAM_CFG0_DMWD_32
-
-#define SDRAM_MCSTAT SDRAM0_MCSTS
-#define SDRAM_MCSTAT_IDLE_MASK SDRAM_MCSTS_CIS
-#define SDRAM_MCSTAT_IDLE_NOT SDRAM_MCSTS_IDLE_NOT
-
-#define SDRAM_ECCES SDRAM0_ECCESR
-#endif
-
-void ecc_init(unsigned long * const start, unsigned long size);
-void do_program_ecc(unsigned long tlb_word2_i_value);
-
-static void inline blank_string(int size)
-{
- int i;
-
- for (i = 0; i < size; i++)
- putc('\b');
- for (i = 0; i < size; i++)
- putc(' ');
- for (i = 0; i < size; i++)
- putc('\b');
-}
-
-#endif /* _ECC_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <asm/cache.h>
-#include <asm/ppc4xx.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/4xx_pcie.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int __ft_board_setup(void *blob, bd_t *bd)
-{
- int rc;
- int i;
- u32 bxcr;
- u32 ranges[EBC_NUM_BANKS * 4];
- u32 *p = ranges;
- char ebc_path[] = "/plb/opb/ebc";
-
- ft_cpu_setup(blob, bd);
-
- /*
- * Read 4xx EBC bus bridge registers to get mappings of the
- * peripheral banks into the OPB/PLB address space
- */
- for (i = 0; i < EBC_NUM_BANKS; i++) {
- mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
- bxcr = mfdcr(EBC0_CFGDATA);
-
- if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
- *p++ = i;
- *p++ = 0;
- *p++ = bxcr & EBC_BXCR_BAS_MASK;
- *p++ = EBC_BXCR_BANK_SIZE(bxcr);
- }
- }
-
-
-#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
- /* Update reg property in all nor flash nodes too */
- fdt_fixup_nor_flash_size(blob);
-#endif
-
- /* Some 405 PPC's have EBC as direct PLB child in the dts */
- if (fdt_path_offset(blob, ebc_path) < 0)
- strcpy(ebc_path, "/plb/ebc");
- rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
- (p - ranges) * sizeof(u32), 1);
- if (rc) {
- printf("Unable to update property EBC mappings, err=%s\n",
- fdt_strerror(rc));
- }
-
- return 0;
-}
-int ft_board_setup(void *blob, bd_t *bd)
- __attribute__((weak, alias("__ft_board_setup")));
-
-/*
- * Fixup all PCIe nodes by setting the device_type property
- * to "pci-endpoint" instead is "pci" for endpoint ports.
- * This property will get checked later by the Linux driver
- * to properly configure the PCIe port in Linux (again).
- */
-void fdt_pcie_setup(void *blob)
-{
- const char *compat = "ibm,plb-pciex";
- const char *prop = "device_type";
- const char *prop_val = "pci-endpoint";
- const u32 *port;
- int no;
- int rc;
-
- /* Search first PCIe node */
- no = fdt_node_offset_by_compatible(blob, -1, compat);
- while (no != -FDT_ERR_NOTFOUND) {
- port = fdt_getprop(blob, no, "port", NULL);
- if (port == NULL) {
- printf("WARNING: could not find port property\n");
- } else {
- if (is_end_point(*port)) {
- rc = fdt_setprop(blob, no, prop, prop_val,
- strlen(prop_val) + 1);
- if (rc < 0)
- printf("WARNING: could not set %s for %s: %s.\n",
- prop, compat, fdt_strerror(rc));
- }
- }
-
- /* Jump to next PCIe node */
- no = fdt_node_offset_by_compatible(blob, no, compat);
- }
-}
-
-void ft_cpu_setup(void *blob, bd_t *bd)
-{
- sys_info_t sys_info;
- int off, ndepth = 0;
-
- get_sys_info(&sys_info);
-
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency",
- bd->bi_intfreq, 1);
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency",
- bd->bi_intfreq, 1);
- do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
- do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
-
- if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
- do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
- sys_info.freqEBC, 1);
- else
- do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
- sys_info.freqEBC, 1);
-
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-
- /*
- * Fixup all UART clocks for CPU internal UARTs
- * (only these UARTs are definitely clocked by gd->arch.uart_clk)
- *
- * These UARTs are direct childs of /plb/opb. This code
- * does not touch any UARTs that are connected to the ebc.
- */
- off = fdt_path_offset(blob, "/plb/opb");
- while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
- /*
- * process all sub nodes and stop when we are back
- * at the starting depth
- */
- if (ndepth <= 0)
- break;
-
- /* only update direct childs */
- if ((ndepth == 1) &&
- (fdt_node_check_compatible(blob, off, "ns16550") == 0))
- fdt_setprop(blob, off,
- "clock-frequency",
- (void *)&gd->arch.uart_clk, 4);
- }
-
- /*
- * Fixup all available PCIe nodes by setting the device_type property
- */
- fdt_pcie_setup(blob);
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-/* Only compile this file for boards with GPIO support */
-#if defined(GPIO0_BASE)
-
-#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
-gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
-#endif
-
-#if defined(GPIO0_OSRL)
-/* Only some 4xx variants support alternate funtions on the GPIO's */
-void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
-{
- u32 mask;
- u32 mask2;
- u32 val;
- u32 offs = 0;
- u32 offs2 = 0;
- int pin2 = pin << 1;
-
- if (pin >= GPIO_MAX) {
- offs = 0x100;
- pin -= GPIO_MAX;
- }
-
- if (pin >= GPIO_MAX/2) {
- offs2 = 0x4;
- pin2 = (pin - GPIO_MAX/2) << 1;
- }
-
- mask = 0x80000000 >> pin;
- mask2 = 0xc0000000 >> pin2;
-
- /* first set TCR to 0 */
- out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask);
-
- if (in_out == GPIO_OUT) {
- val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2;
- switch (gpio_alt) {
- case GPIO_ALT1:
- val |= GPIO_ALT1_SEL >> pin2;
- break;
- case GPIO_ALT2:
- val |= GPIO_ALT2_SEL >> pin2;
- break;
- case GPIO_ALT3:
- val |= GPIO_ALT3_SEL >> pin2;
- break;
- }
- out_be32((void *)GPIO0_OSRL + offs + offs2, val);
-
- /* setup requested output value */
- if (out_val == GPIO_OUT_0)
- out_be32((void *)GPIO0_OR + offs,
- in_be32((void *)GPIO0_OR + offs) & ~mask);
- else if (out_val == GPIO_OUT_1)
- out_be32((void *)GPIO0_OR + offs,
- in_be32((void *)GPIO0_OR + offs) | mask);
-
- /* now configure TCR to drive output if selected */
- out_be32((void *)GPIO0_TCR + offs,
- in_be32((void *)GPIO0_TCR + offs) | mask);
- } else {
- val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2;
- val |= GPIO_IN_SEL >> pin2;
- out_be32((void *)GPIO0_ISR1L + offs + offs2, val);
- }
-}
-#endif /* GPIO_OSRL */
-
-void gpio_write_bit(int pin, int val)
-{
- u32 offs = 0;
-
- if (pin >= GPIO_MAX) {
- offs = 0x100;
- pin -= GPIO_MAX;
- }
-
- if (val)
- out_be32((void *)GPIO0_OR + offs,
- in_be32((void *)GPIO0_OR + offs) | GPIO_VAL(pin));
- else
- out_be32((void *)GPIO0_OR + offs,
- in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin));
-}
-
-int gpio_read_out_bit(int pin)
-{
- u32 offs = 0;
-
- if (pin >= GPIO_MAX) {
- offs = 0x100;
- pin -= GPIO_MAX;
- }
-
- return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
-}
-
-int gpio_read_in_bit(int pin)
-{
- u32 offs = 0;
-
- if (pin >= GPIO_MAX) {
- offs = 0x100;
- pin -= GPIO_MAX;
- }
-
- return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
-}
-
-#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
-void gpio_set_chip_configuration(void)
-{
- unsigned char i=0, j=0, offs=0, gpio_core;
- unsigned long reg, core_add;
-
- for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
- j = 0;
- offs = 0;
- /* GPIO config of the GPIOs 0 to 31 */
- for (i=0; i<GPIO_MAX; i++, j++) {
- if (i == GPIO_MAX/2) {
- offs = 4;
- j = i-16;
- }
-
- core_add = gpio_tab[gpio_core][i].add;
-
- if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
- (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
-
- switch (gpio_tab[gpio_core][i].alt_nb) {
- case GPIO_SEL:
- break;
-
- case GPIO_ALT1:
- reg = in_be32((void *)GPIO_IS1(core_add+offs))
- & ~(GPIO_MASK >> (j*2));
- reg = reg | (GPIO_IN_SEL >> (j*2));
- out_be32((void *)GPIO_IS1(core_add+offs), reg);
- break;
-
- case GPIO_ALT2:
- reg = in_be32((void *)GPIO_IS2(core_add+offs))
- & ~(GPIO_MASK >> (j*2));
- reg = reg | (GPIO_IN_SEL >> (j*2));
- out_be32((void *)GPIO_IS2(core_add+offs), reg);
- break;
-
- case GPIO_ALT3:
- reg = in_be32((void *)GPIO_IS3(core_add+offs))
- & ~(GPIO_MASK >> (j*2));
- reg = reg | (GPIO_IN_SEL >> (j*2));
- out_be32((void *)GPIO_IS3(core_add+offs), reg);
- break;
- }
- }
-
- if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
- (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
-
- u32 gpio_alt_sel = 0;
-
- switch (gpio_tab[gpio_core][i].alt_nb) {
- case GPIO_SEL:
- /*
- * Setup output value
- * 1 -> high level
- * 0 -> low level
- * else -> don't touch
- */
- reg = in_be32((void *)GPIO_OR(core_add));
- if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
- reg |= (0x80000000 >> (i));
- else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
- reg &= ~(0x80000000 >> (i));
- out_be32((void *)GPIO_OR(core_add), reg);
-
- reg = in_be32((void *)GPIO_TCR(core_add)) |
- (0x80000000 >> (i));
- out_be32((void *)GPIO_TCR(core_add), reg);
-
- reg = in_be32((void *)GPIO_OS(core_add+offs))
- & ~(GPIO_MASK >> (j*2));
- out_be32((void *)GPIO_OS(core_add+offs), reg);
- reg = in_be32((void *)GPIO_TS(core_add+offs))
- & ~(GPIO_MASK >> (j*2));
- out_be32((void *)GPIO_TS(core_add+offs), reg);
- break;
-
- case GPIO_ALT1:
- gpio_alt_sel = GPIO_ALT1_SEL;
- break;
-
- case GPIO_ALT2:
- gpio_alt_sel = GPIO_ALT2_SEL;
- break;
-
- case GPIO_ALT3:
- gpio_alt_sel = GPIO_ALT3_SEL;
- break;
- }
-
- if (0 != gpio_alt_sel) {
- reg = in_be32((void *)GPIO_OS(core_add+offs))
- & ~(GPIO_MASK >> (j*2));
- reg = reg | (gpio_alt_sel >> (j*2));
- out_be32((void *)GPIO_OS(core_add+offs), reg);
-
- if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) {
- reg = in_be32((void *)GPIO_TCR(core_add))
- | (0x80000000 >> (i));
- out_be32((void *)GPIO_TCR(core_add), reg);
- reg = in_be32((void *)GPIO_TS(core_add+offs))
- & ~(GPIO_MASK >> (j*2));
- out_be32((void *)GPIO_TS(core_add+offs), reg);
- } else {
- reg = in_be32((void *)GPIO_TCR(core_add))
- & ~(0x80000000 >> (i));
- out_be32((void *)GPIO_TCR(core_add), reg);
- reg = in_be32((void *)GPIO_TS(core_add+offs))
- & ~(GPIO_MASK >> (j*2));
- reg = reg | (gpio_alt_sel >> (j*2));
- out_be32((void *)GPIO_TS(core_add+offs), reg);
- }
- }
- }
- }
- }
-}
-
-#endif /* GPIO0_BASE */
-#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
+++ /dev/null
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 (440 port)
- * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
- *
- * (C) Copyright 2003 (440GX port)
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
- * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * Work supported by Qtechnology (htpp://qtec.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/interrupt.h>
-#include <asm/ppc4xx.h>
-#include <ppc_asm.tmpl>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * CPM interrupt vector functions.
- */
-struct irq_action {
- interrupt_handler_t *handler;
- void *arg;
- int count;
-};
-static struct irq_action irq_vecs[IRQ_MAX];
-
-#if defined(CONFIG_440)
-
-/* SPRN changed in 440 */
-static __inline__ void set_evpr(unsigned long val)
-{
- asm volatile("mtspr 0x03f,%0" : : "r" (val));
-}
-
-#else /* !defined(CONFIG_440) */
-
-static __inline__ void set_pit(unsigned long val)
-{
- asm volatile("mtpit %0" : : "r" (val));
-}
-
-static __inline__ void set_evpr(unsigned long val)
-{
- asm volatile("mtevpr %0" : : "r" (val));
-}
-#endif /* defined(CONFIG_440 */
-
-int interrupt_init_cpu (unsigned *decrementer_count)
-{
- int vec;
- unsigned long val;
-
- /* decrementer is automatically reloaded */
- *decrementer_count = 0;
-
- /*
- * Mark all irqs as free
- */
- for (vec = 0; vec < IRQ_MAX; vec++) {
- irq_vecs[vec].handler = NULL;
- irq_vecs[vec].arg = NULL;
- irq_vecs[vec].count = 0;
- }
-
-#ifdef CONFIG_4xx
- /*
- * Init PIT
- */
-#if defined(CONFIG_440)
- val = mfspr( SPRN_TCR );
- val &= (~0x04400000); /* clear DIS & ARE */
- mtspr( SPRN_TCR, val );
- mtspr( SPRN_DEC, 0 ); /* Prevent exception after TSR clear*/
- mtspr( SPRN_DECAR, 0 ); /* clear reload */
- mtspr( SPRN_TSR, 0x08000000 ); /* clear DEC status */
- val = gd->bd->bi_intfreq/1000; /* 1 msec */
- mtspr( SPRN_DECAR, val ); /* Set auto-reload value */
- mtspr( SPRN_DEC, val ); /* Set inital val */
-#else
- set_pit(gd->bd->bi_intfreq / 1000);
-#endif
-#endif /* CONFIG_4xx */
-
-#ifdef CONFIG_ADCIOP
- /*
- * Init PIT
- */
- set_pit(66000);
-#endif
-
- /*
- * Enable PIT
- */
- val = mfspr(SPRN_TCR);
- val |= 0x04400000;
- mtspr(SPRN_TCR, val);
-
- /*
- * Set EVPR to 0
- */
- set_evpr(0x00000000);
-
- /*
- * Call uic or xilinx_irq pic_enable
- */
- pic_enable();
-
- return (0);
-}
-
-void timer_interrupt_cpu(struct pt_regs *regs)
-{
- /* nothing to do here */
- return;
-}
-
-void interrupt_run_handler(int vec)
-{
- irq_vecs[vec].count++;
-
- if (irq_vecs[vec].handler != NULL) {
- /* call isr */
- (*irq_vecs[vec].handler) (irq_vecs[vec].arg);
- } else {
- pic_irq_disable(vec);
- printf("Masking bogus interrupt vector %d\n", vec);
- }
-
- pic_irq_ack(vec);
- return;
-}
-
-void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
-{
- /*
- * Print warning when replacing with a different irq vector
- */
- if ((irq_vecs[vec].handler != NULL) && (irq_vecs[vec].handler != handler)) {
- printf("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
- vec, (uint) handler, (uint) irq_vecs[vec].handler);
- }
- irq_vecs[vec].handler = handler;
- irq_vecs[vec].arg = arg;
-
- pic_irq_enable(vec);
- return;
-}
-
-void irq_free_handler(int vec)
-{
- debug("Free interrupt for vector %d ==> %p\n",
- vec, irq_vecs[vec].handler);
-
- pic_irq_disable(vec);
-
- irq_vecs[vec].handler = NULL;
- irq_vecs[vec].arg = NULL;
- return;
-}
-
-#if defined(CONFIG_CMD_IRQ)
-int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int vec;
-
- printf ("Interrupt-Information:\n");
- printf ("Nr Routine Arg Count\n");
-
- for (vec = 0; vec < IRQ_MAX; vec++) {
- if (irq_vecs[vec].handler != NULL) {
- printf ("%02d %08lx %08lx %d\n",
- vec,
- (ulong)irq_vecs[vec].handler,
- (ulong)irq_vecs[vec].arg,
- irq_vecs[vec].count);
- }
- }
-
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <command.h>
-#include <asm/ppc4xx.h>
-
-#define CONFIG_405GP 1 /* needed for Linux kernel header files */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#if defined(CONFIG_CMD_KGDB)
- /*
- * cache flushing routines for kgdb
- */
-
- .globl kgdb_flush_cache_all
-kgdb_flush_cache_all:
- /* icache */
- iccci r0,r0 /* iccci invalidates the entire I cache */
- /* dcache */
- addi r6,0,0x0000 /* clear GPR 6 */
- addi r7,r0, 128 /* do loop for # of dcache lines */
- /* NOTE: dccci invalidates both */
- mtctr r7 /* ways in the D cache */
-..dcloop:
- dccci 0,r6 /* invalidate line */
- addi r6,r6, 32 /* bump to next line */
- bdnz ..dcloop
- blr
-
- .globl kgdb_flush_cache_range
-kgdb_flush_cache_range:
- li r5,L1_CACHE_BYTES-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,L1_CACHE_SHIFT
- beqlr
- mtctr r4
- mr r6,r3
-1: dcbst 0,r3
- addi r3,r3,L1_CACHE_BYTES
- bdnz 1b
- sync /* wait for dcbst's to get to ram */
- mtctr r4
-2: icbi 0,r6
- addi r6,r6,L1_CACHE_BYTES
- bdnz 2b
- SYNC
- blr
-
-#endif
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*-----------------------------------------------------------------------------+
- |
- | File Name: miiphy.c
- |
- | Function: This module has utilities for accessing the MII PHY through
- | the EMAC3 macro.
- |
- | Author: Mark Wisner
- |
- +-----------------------------------------------------------------------------*/
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <ppc_asm.tmpl>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-emac.h>
-#include <asm/ppc4xx-mal.h>
-#include <miiphy.h>
-
-#if !defined(CONFIG_PHY_CLK_FREQ)
-#define CONFIG_PHY_CLK_FREQ 0
-#endif
-
-/***********************************************************/
-/* Dump out to the screen PHY regs */
-/***********************************************************/
-
-void miiphy_dump (char *devname, unsigned char addr)
-{
- unsigned long i;
- unsigned short data;
-
- for (i = 0; i < 0x1A; i++) {
- if (miiphy_read (devname, addr, i, &data)) {
- printf ("read error for reg %lx\n", i);
- return;
- }
- printf ("Phy reg %lx ==> %4x\n", i, data);
-
- /* jump to the next set of regs */
- if (i == 0x07)
- i = 0x0f;
-
- } /* end for loop */
-} /* end dump */
-
-/***********************************************************/
-/* (Re)start autonegotiation */
-/***********************************************************/
-int phy_setup_aneg (char *devname, unsigned char addr)
-{
- u16 bmcr;
-
-#if defined(CONFIG_PHY_DYNAMIC_ANEG)
- /*
- * Set up advertisement based on capablilities reported by the PHY.
- * This should work for both copper and fiber.
- */
- u16 bmsr;
-#if defined(CONFIG_PHY_GIGE)
- u16 exsr = 0x0000;
-#endif
-
- miiphy_read (devname, addr, MII_BMSR, &bmsr);
-
-#if defined(CONFIG_PHY_GIGE)
- if (bmsr & BMSR_ESTATEN)
- miiphy_read (devname, addr, MII_ESTATUS, &exsr);
-
- if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) {
- /* 1000BASE-X */
- u16 anar = 0x0000;
-
- if (exsr & ESTATUS_1000XF)
- anar |= ADVERTISE_1000XFULL;
-
- if (exsr & ESTATUS_1000XH)
- anar |= ADVERTISE_1000XHALF;
-
- miiphy_write (devname, addr, MII_ADVERTISE, anar);
- } else
-#endif
- {
- u16 anar, btcr;
-
- miiphy_read (devname, addr, MII_ADVERTISE, &anar);
- anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL |
- LPA_100HALF | LPA_10FULL | LPA_10HALF);
-
- miiphy_read (devname, addr, MII_CTRL1000, &btcr);
- btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD);
-
- if (bmsr & BMSR_100BASE4)
- anar |= LPA_100BASE4;
-
- if (bmsr & BMSR_100FULL)
- anar |= LPA_100FULL;
-
- if (bmsr & BMSR_100HALF)
- anar |= LPA_100HALF;
-
- if (bmsr & BMSR_10FULL)
- anar |= LPA_10FULL;
-
- if (bmsr & BMSR_10HALF)
- anar |= LPA_10HALF;
-
- miiphy_write (devname, addr, MII_ADVERTISE, anar);
-
-#if defined(CONFIG_PHY_GIGE)
- if (exsr & ESTATUS_1000_TFULL)
- btcr |= PHY_1000BTCR_1000FD;
-
- if (exsr & ESTATUS_1000_THALF)
- btcr |= PHY_1000BTCR_1000HD;
-
- miiphy_write (devname, addr, MII_CTRL1000, btcr);
-#endif
- }
-
-#else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
- /*
- * Set up standard advertisement
- */
- u16 adv;
-
- miiphy_read (devname, addr, MII_ADVERTISE, &adv);
- adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF |
- LPA_10FULL | LPA_10HALF);
- miiphy_write (devname, addr, MII_ADVERTISE, adv);
-
- miiphy_read (devname, addr, MII_CTRL1000, &adv);
- adv |= (0x0300);
- miiphy_write (devname, addr, MII_CTRL1000, adv);
-
-#endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
-
- /* Start/Restart aneg */
- miiphy_read (devname, addr, MII_BMCR, &bmcr);
- bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
- miiphy_write (devname, addr, MII_BMCR, bmcr);
-
- return 0;
-}
-
-/***********************************************************/
-/* read a phy reg and return the value with a rc */
-/***********************************************************/
-/* AMCC_TODO:
- * Find out of the choice for the emac for MDIO is from the bridges,
- * i.e. ZMII or RGMII as approporiate. If the bridges are not used
- * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL]
- * used? If so, then this routine below does not apply to the 460EX/GT.
- *
- * sr: Currently on 460EX only EMAC0 works with MDIO, so we always
- * return EMAC0 offset here
- * vg: For 460EX/460GT if internal GPCS PHY address is specified
- * return appropriate EMAC offset
- */
-unsigned int miiphy_getemac_offset(u8 addr)
-{
-#if defined(CONFIG_440) && \
- !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
- !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
- unsigned long zmii;
- unsigned long eoffset;
-
- /* Need to find out which mdi port we're using */
- zmii = in_be32((void *)ZMII0_FER);
-
- if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0)))
- /* using port 0 */
- eoffset = 0;
-
- else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1)))
- /* using port 1 */
- eoffset = 0x100;
-
- else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2)))
- /* using port 2 */
- eoffset = 0x400;
-
- else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3)))
- /* using port 3 */
- eoffset = 0x600;
-
- else {
- /* None of the mdi ports are enabled! */
- /* enable port 0 */
- zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
- out_be32((void *)ZMII0_FER, zmii);
- eoffset = 0;
- /* need to soft reset port 0 */
- zmii = in_be32((void *)EMAC0_MR0);
- zmii |= EMAC_MR0_SRST;
- out_be32((void *)EMAC0_MR0, zmii);
- }
-
- return (eoffset);
-#else
-
-#if defined(CONFIG_405EX)
- unsigned long rgmii;
- int devnum = 1;
-
- rgmii = in_be32((void *)RGMII_FER);
- if (rgmii & (1 << (19 - devnum)))
- return 0x100;
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- u32 eoffset = 0;
-
- switch (addr) {
-#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
- case CONFIG_GPCS_PHY1_ADDR:
- if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100)))
- eoffset = 0x100;
- break;
-#endif
-#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
- case CONFIG_GPCS_PHY2_ADDR:
- if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300)))
- eoffset = 0x300;
- break;
-#endif
-#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
- case CONFIG_GPCS_PHY3_ADDR:
- if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400)))
- eoffset = 0x400;
- break;
-#endif
- default:
- eoffset = 0;
- break;
- }
- return eoffset;
-#endif
-
- return 0;
-#endif
-}
-
-static int emac_miiphy_wait(u32 emac_reg)
-{
- u32 sta_reg;
- int i;
-
- /* wait for completion */
- i = 0;
- do {
- sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
- if (i++ > 5) {
- debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__,
- __LINE__, sta_reg);
- return -1;
- }
- udelay(10);
- } while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK);
-
- return 0;
-}
-
-static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
-{
- u32 emac_reg;
- u32 sta_reg;
-
- emac_reg = miiphy_getemac_offset(addr);
-
- /* wait for completion */
- if (emac_miiphy_wait(emac_reg) != 0)
- return -1;
-
- sta_reg = reg; /* reg address */
-
- /* set clock (50MHz) and read flags */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
-#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
- sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd;
-#else
- sta_reg |= cmd;
-#endif
-#else
- sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ;
-#endif
-
- /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */
- sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
- sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */
- sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
- if (cmd == EMAC_STACR_WRITE)
- memcpy(&sta_reg, &value, 2); /* put in data */
-
- out_be32((void *)EMAC0_STACR + emac_reg, sta_reg);
- debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
-
- /* wait for completion */
- if (emac_miiphy_wait(emac_reg) != 0)
- return -1;
-
- debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
- if ((sta_reg & EMAC_STACR_PHYE) != 0)
- return -1;
-
- return 0;
-}
-
-int emac4xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- unsigned long sta_reg;
- unsigned long emac_reg;
-
- emac_reg = miiphy_getemac_offset(addr);
-
- if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
- return -1;
-
- sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
- return sta_reg >> 16;
-}
-
-/***********************************************************/
-/* write a phy reg and return the value with a rc */
-/***********************************************************/
-
-int emac4xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 value)
-{
- return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value);
-}
+++ /dev/null
-/*
- *(C) Copyright 2005-2009 Netstal Maschinen AG
- * Bruno Hars (Bruno.Hars@netstal.com)
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * reginfo.c - register dump of HW-configuratin register for PPC4xx based board
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-uic.h>
-#include <asm/ppc4xx-emac.h>
-
-enum REGISTER_TYPE {
- IDCR1, /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */
- IDCR2, /* Indirectly Accessed DCR via EBC0_CFGADDR/EBC0_CFGDATA */
- IDCR3, /* Indirectly Accessed DCR via EBM0_CFGADDR/EBM0_CFGDATA */
- IDCR4, /* Indirectly Accessed DCR via PPM0_CFGADDR/PPM0_CFGDATA */
- IDCR5, /* Indirectly Accessed DCR via CPR0_CFGADDR/CPR0_CFGDATA */
- IDCR6, /* Indirectly Accessed DCR via SDR0_CFGADDR/SDR0_CFGDATA */
- MM /* Directly Accessed MMIO Register */
-};
-
-struct cpu_register {
- char *name;
- enum REGISTER_TYPE type;
- u32 address;
-};
-
-/*
- * PPC440EPx registers ordered for output
- * name type addr size
- * -------------------------------------------
- */
-
-const struct cpu_register ppc4xx_reg[] = {
- {"PB0CR", IDCR2, PB0CR},
- {"PB0AP", IDCR2, PB0AP},
- {"PB1CR", IDCR2, PB1CR},
- {"PB1AP", IDCR2, PB1AP},
- {"PB2CR", IDCR2, PB2CR},
- {"PB2AP", IDCR2, PB2AP},
- {"PB3CR", IDCR2, PB3CR},
- {"PB3AP", IDCR2, PB3AP},
-
- {"PB4CR", IDCR2, PB4CR},
- {"PB4AP", IDCR2, PB4AP},
-#if !defined(CONFIG_405EP)
- {"PB5CR", IDCR2, PB5CR},
- {"PB5AP", IDCR2, PB5AP},
- {"PB6CR", IDCR2, PB6CR},
- {"PB6AP", IDCR2, PB6AP},
- {"PB7CR", IDCR2, PB7CR},
- {"PB7AP", IDCR2, PB7AP},
-#endif
-
- {"PBEAR", IDCR2, PBEAR},
-#if defined(CONFIG_405EP) || defined (CONFIG_405GP)
- {"PBESR0", IDCR2, PBESR0},
- {"PBESR1", IDCR2, PBESR1},
-#endif
- {"EBC0_CFG", IDCR2, EBC0_CFG},
-
-#ifdef CONFIG_405GP
- {"SDRAM0_BESR0", IDCR1, SDRAM0_BESR0},
- {"SDRAM0_BESRS0", IDCR1, SDRAM0_BESRS0},
- {"SDRAM0_BESR1", IDCR1, SDRAM0_BESR1},
- {"SDRAM0_BESRS1", IDCR1, SDRAM0_BESRS1},
- {"SDRAM0_BEAR", IDCR1, SDRAM0_BEAR},
- {"SDRAM0_CFG", IDCR1, SDRAM0_CFG},
- {"SDRAM0_RTR", IDCR1, SDRAM0_RTR},
- {"SDRAM0_PMIT", IDCR1, SDRAM0_PMIT},
-
- {"SDRAM0_B0CR", IDCR1, SDRAM0_B0CR},
- {"SDRAM0_B1CR", IDCR1, SDRAM0_B1CR},
- {"SDRAM0_B2CR", IDCR1, SDRAM0_B2CR},
- {"SDRAM0_B3CR", IDCR1, SDRAM0_B1CR},
- {"SDRAM0_TR", IDCR1, SDRAM0_TR},
- {"SDRAM0_ECCCFG", IDCR1, SDRAM0_B1CR},
- {"SDRAM0_ECCESR", IDCR1, SDRAM0_ECCESR},
-
-
-#endif
-
-#ifdef CONFIG_440EPX
- {"SDR0_SDSTP0", IDCR6, SDR0_SDSTP0},
- {"SDR0_SDSTP1", IDCR6, SDR0_SDSTP1},
- {"SDR0_SDSTP2", IDCR6, SDR0_SDSTP2},
- {"SDR0_SDSTP3", IDCR6, SDR0_SDSTP3},
- {"SDR0_CUST0", IDCR6, SDR0_CUST0},
- {"SDR0_CUST1", IDCR6, SDR0_CUST1},
- {"SDR0_EBC", IDCR6, SDR0_EBC},
- {"SDR0_AMP0", IDCR6, SDR0_AMP0},
- {"SDR0_AMP1", IDCR6, SDR0_AMP1},
- {"SDR0_CP440", IDCR6, SDR0_CP440},
- {"SDR0_CRYP0", IDCR6, SDR0_CRYP0},
- {"SDR0_DDRCFG", IDCR6, SDR0_DDRCFG},
- {"SDR0_EMAC0RXST", IDCR6, SDR0_EMAC0RXST},
- {"SDR0_EMAC0TXST", IDCR6, SDR0_EMAC0TXST},
- {"SDR0_MFR", IDCR6, SDR0_MFR},
- {"SDR0_PCI0", IDCR6, SDR0_PCI0},
- {"SDR0_PFC0", IDCR6, SDR0_PFC0},
- {"SDR0_PFC1", IDCR6, SDR0_PFC1},
- {"SDR0_PFC2", IDCR6, SDR0_PFC2},
- {"SDR0_PFC4", IDCR6, SDR0_PFC4},
- {"SDR0_UART0", IDCR6, SDR0_UART0},
- {"SDR0_UART1", IDCR6, SDR0_UART1},
- {"SDR0_UART2", IDCR6, SDR0_UART2},
- {"SDR0_UART3", IDCR6, SDR0_UART3},
- {"DDR0_02", IDCR1, DDR0_02},
- {"DDR0_00", IDCR1, DDR0_00},
- {"DDR0_01", IDCR1, DDR0_01},
- {"DDR0_03", IDCR1, DDR0_03},
- {"DDR0_04", IDCR1, DDR0_04},
- {"DDR0_05", IDCR1, DDR0_05},
- {"DDR0_06", IDCR1, DDR0_06},
- {"DDR0_07", IDCR1, DDR0_07},
- {"DDR0_08", IDCR1, DDR0_08},
- {"DDR0_09", IDCR1, DDR0_09},
- {"DDR0_10", IDCR1, DDR0_10},
- {"DDR0_11", IDCR1, DDR0_11},
- {"DDR0_12", IDCR1, DDR0_12},
- {"DDR0_14", IDCR1, DDR0_14},
- {"DDR0_17", IDCR1, DDR0_17},
- {"DDR0_18", IDCR1, DDR0_18},
- {"DDR0_19", IDCR1, DDR0_19},
- {"DDR0_20", IDCR1, DDR0_20},
- {"DDR0_21", IDCR1, DDR0_21},
- {"DDR0_22", IDCR1, DDR0_22},
- {"DDR0_23", IDCR1, DDR0_23},
- {"DDR0_24", IDCR1, DDR0_24},
- {"DDR0_25", IDCR1, DDR0_25},
- {"DDR0_26", IDCR1, DDR0_26},
- {"DDR0_27", IDCR1, DDR0_27},
- {"DDR0_28", IDCR1, DDR0_28},
- {"DDR0_31", IDCR1, DDR0_31},
- {"DDR0_32", IDCR1, DDR0_32},
- {"DDR0_33", IDCR1, DDR0_33},
- {"DDR0_34", IDCR1, DDR0_34},
- {"DDR0_35", IDCR1, DDR0_35},
- {"DDR0_36", IDCR1, DDR0_36},
- {"DDR0_37", IDCR1, DDR0_37},
- {"DDR0_38", IDCR1, DDR0_38},
- {"DDR0_39", IDCR1, DDR0_39},
- {"DDR0_40", IDCR1, DDR0_40},
- {"DDR0_41", IDCR1, DDR0_41},
- {"DDR0_42", IDCR1, DDR0_42},
- {"DDR0_43", IDCR1, DDR0_43},
- {"DDR0_44", IDCR1, DDR0_44},
- {"CPR0_ICFG", IDCR5, CPR0_ICFG},
- {"CPR0_MALD", IDCR5, CPR0_MALD},
- {"CPR0_OPBD00", IDCR5, CPR0_OPBD0},
- {"CPR0_PERD0", IDCR5, CPR0_PERD},
- {"CPR0_PLLC0", IDCR5, CPR0_PLLC},
- {"CPR0_PLLD0", IDCR5, CPR0_PLLD},
- {"CPR0_PRIMAD0", IDCR5, CPR0_PRIMAD0},
- {"CPR0_PRIMBD0", IDCR5, CPR0_PRIMBD0},
- {"CPR0_SPCID", IDCR5, CPR0_SPCID},
- {"SPI0_MODE", MM, SPI0_MODE},
- {"IIC0_CLKDIV", MM, PCIL0_PMM1MA},
- {"PCIL0_PMM0MA", MM, PCIL0_PMM0MA},
- {"PCIL0_PMM1MA", MM, PCIL0_PMM1MA},
- {"PCIL0_PTM1LA", MM, PCIL0_PMM1MA},
- {"PCIL0_PTM1MS", MM, PCIL0_PTM1MS},
- {"PCIL0_PTM2LA", MM, PCIL0_PMM1MA},
- {"PCIL0_PTM2MS", MM, PCIL0_PTM2MS},
- {"ZMII0_FER", MM, ZMII0_FER},
- {"ZMII0_SSR", MM, ZMII0_SSR},
- {"EMAC0_IPGVR", MM, EMAC0_IPGVR},
- {"EMAC0_MR1", MM, EMAC0_MR1},
- {"EMAC0_PTR", MM, EMAC0_PTR},
- {"EMAC0_RWMR", MM, EMAC0_RWMR},
- {"EMAC0_STACR", MM, EMAC0_STACR},
- {"EMAC0_TMR0", MM, EMAC0_TMR0},
- {"EMAC0_TMR1", MM, EMAC0_TMR1},
- {"EMAC0_TRTR", MM, EMAC0_TRTR},
- {"EMAC1_MR1", MM, EMAC1_MR1},
- {"GPIO0_OR", MM, GPIO0_OR},
- {"GPIO1_OR", MM, GPIO1_OR},
- {"GPIO0_TCR", MM, GPIO0_TCR},
- {"GPIO1_TCR", MM, GPIO1_TCR},
- {"GPIO0_ODR", MM, GPIO0_ODR},
- {"GPIO1_ODR", MM, GPIO1_ODR},
- {"GPIO0_OSRL", MM, GPIO0_OSRL},
- {"GPIO0_OSRH", MM, GPIO0_OSRH},
- {"GPIO1_OSRL", MM, GPIO1_OSRL},
- {"GPIO1_OSRH", MM, GPIO1_OSRH},
- {"GPIO0_TSRL", MM, GPIO0_TSRL},
- {"GPIO0_TSRH", MM, GPIO0_TSRH},
- {"GPIO1_TSRL", MM, GPIO1_TSRL},
- {"GPIO1_TSRH", MM, GPIO1_TSRH},
- {"GPIO0_IR", MM, GPIO0_IR},
- {"GPIO1_IR", MM, GPIO1_IR},
- {"GPIO0_ISR1L", MM, GPIO0_ISR1L},
- {"GPIO0_ISR1H", MM, GPIO0_ISR1H},
- {"GPIO1_ISR1L", MM, GPIO1_ISR1L},
- {"GPIO1_ISR1H", MM, GPIO1_ISR1H},
- {"GPIO0_ISR2L", MM, GPIO0_ISR2L},
- {"GPIO0_ISR2H", MM, GPIO0_ISR2H},
- {"GPIO1_ISR2L", MM, GPIO1_ISR2L},
- {"GPIO1_ISR2H", MM, GPIO1_ISR2H},
- {"GPIO0_ISR3L", MM, GPIO0_ISR3L},
- {"GPIO0_ISR3H", MM, GPIO0_ISR3H},
- {"GPIO1_ISR3L", MM, GPIO1_ISR3L},
- {"GPIO1_ISR3H", MM, GPIO1_ISR3H},
- {"SDR0_USB2PHY0CR", IDCR6, SDR0_USB2PHY0CR},
- {"SDR0_USB2H0CR", IDCR6, SDR0_USB2H0CR},
- {"SDR0_USB2D0CR", IDCR6, SDR0_USB2D0CR},
-#endif
-};
-
-/*
- * CPU Register dump of PPC4xx HW configuration registers
- * Output: first all DCR-registers, then in order of struct ppc4xx_reg
- */
-#define PRINT_DCR(dcr) printf("0x%08x %-16s: 0x%08x\n", dcr,#dcr, mfdcr(dcr));
-
-void ppc4xx_reginfo(void)
-{
- unsigned int i;
- unsigned int n;
- u32 value;
- enum REGISTER_TYPE type;
-#if defined (CONFIG_405EP)
- printf("Dump PPC405EP HW configuration registers\n\n");
-#elif CONFIG_405GP
- printf ("Dump 405GP HW configuration registers\n\n");
-#elif CONFIG_440EPX
- printf("Dump PPC440EPx HW configuration registers\n\n");
-#endif
- printf("MSR: 0x%08x\n", mfmsr());
-
- printf ("\nUniversal Interrupt Controller Regs\n");
- PRINT_DCR(UIC0SR);
- PRINT_DCR(UIC0ER);
- PRINT_DCR(UIC0CR);
- PRINT_DCR(UIC0PR);
- PRINT_DCR(UIC0TR);
- PRINT_DCR(UIC0MSR);
- PRINT_DCR(UIC0VR);
- PRINT_DCR(UIC0VCR);
-
-#if (UIC_MAX > 1)
- PRINT_DCR(UIC2SR);
- PRINT_DCR(UIC2ER);
- PRINT_DCR(UIC2CR);
- PRINT_DCR(UIC2PR);
- PRINT_DCR(UIC2TR);
- PRINT_DCR(UIC2MSR);
- PRINT_DCR(UIC2VR);
- PRINT_DCR(UIC2VCR);
-#endif
-
-#if (UIC_MAX > 2)
- PRINT_DCR(UIC2SR);
- PRINT_DCR(UIC2ER);
- PRINT_DCR(UIC2CR);
- PRINT_DCR(UIC2PR);
- PRINT_DCR(UIC2TR);
- PRINT_DCR(UIC2MSR);
- PRINT_DCR(UIC2VR);
- PRINT_DCR(UIC2VCR);
-#endif
-
-#if (UIC_MAX > 3)
- PRINT_DCR(UIC3SR);
- PRINT_DCR(UIC3ER);
- PRINT_DCR(UIC3CR);
- PRINT_DCR(UIC3PR);
- PRINT_DCR(UIC3TR);
- PRINT_DCR(UIC3MSR);
- PRINT_DCR(UIC3VR);
- PRINT_DCR(UIC3VCR);
-#endif
-
-#if defined (CONFIG_405EP) || defined (CONFIG_405GP)
- printf ("\n\nDMA Channels\n");
- PRINT_DCR(DMASR);
- PRINT_DCR(DMASGC);
- PRINT_DCR(DMAADR);
-
- PRINT_DCR(DMACR0);
- PRINT_DCR(DMACT0);
- PRINT_DCR(DMADA0);
- PRINT_DCR(DMASA0);
- PRINT_DCR(DMASB0);
-
- PRINT_DCR(DMACR1);
- PRINT_DCR(DMACT1);
- PRINT_DCR(DMADA1);
- PRINT_DCR(DMASA1);
- PRINT_DCR(DMASB1);
-
- PRINT_DCR(DMACR2);
- PRINT_DCR(DMACT2);
- PRINT_DCR(DMADA2);
- PRINT_DCR(DMASA2);
- PRINT_DCR(DMASB2);
-
- PRINT_DCR(DMACR3);
- PRINT_DCR(DMACT3);
- PRINT_DCR(DMADA3);
- PRINT_DCR(DMASA3);
- PRINT_DCR(DMASB3);
-#endif
-
- printf ("\n\nVarious HW-Configuration registers\n");
-#if defined (CONFIG_440EPX)
- PRINT_DCR(MAL0_CFG);
- PRINT_DCR(CPM0_ER);
- PRINT_DCR(CPM1_ER);
- PRINT_DCR(PLB4A0_ACR);
- PRINT_DCR(PLB4A1_ACR);
- PRINT_DCR(PLB3A0_ACR);
- PRINT_DCR(OPB2PLB40_BCTRL);
- PRINT_DCR(P4P3BO0_CFG);
-#endif
- n = ARRAY_SIZE(ppc4xx_reg);
- for (i = 0; i < n; i++) {
- value = 0;
- type = ppc4xx_reg[i].type;
- switch (type) {
- case IDCR1: /* Indirect via SDRAM0_CFGADDR/DDR0_CFGDATA */
- mtdcr(SDRAM0_CFGADDR, ppc4xx_reg[i].address);
- value = mfdcr(SDRAM0_CFGDATA);
- break;
- case IDCR2: /* Indirect via EBC0_CFGADDR/EBC0_CFGDATA */
- mtdcr(EBC0_CFGADDR, ppc4xx_reg[i].address);
- value = mfdcr(EBC0_CFGDATA);
- break;
- case IDCR5: /* Indirect via CPR0_CFGADDR/CPR0_CFGDATA */
- mtdcr(CPR0_CFGADDR, ppc4xx_reg[i].address);
- value = mfdcr(CPR0_CFGDATA);
- break;
- case IDCR6: /* Indirect via SDR0_CFGADDR/SDR0_CFGDATA */
- mtdcr(SDR0_CFGADDR, ppc4xx_reg[i].address);
- value = mfdcr(SDR0_CFGDATA);
- break;
- case MM: /* Directly Accessed MMIO Register */
- value = in_be32((const volatile unsigned __iomem *)
- ppc4xx_reg[i].address);
- break;
- default:
- printf("\nERROR: struct entry %d: unknown register"
- "type\n", i);
- break;
- }
- printf("0x%08x %-16s: 0x%08x\n",ppc4xx_reg[i].address,
- ppc4xx_reg[i].name, value);
- }
-}
+++ /dev/null
-/* Copyright MontaVista Software Incorporated, 2000 */
-#include <config.h>
- .section .resetvec,"ax"
-#if defined(CONFIG_440)
- b _start_440
-#else
-#if defined(CONFIG_BOOT_PCI) && (defined(CONFIG_TARGET_MIP405) \
- || defined(CONFIG_TARGET_MIP405T))
- b _start_pci
-#else
- b _start
-#endif
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * DAVE Srl <www.dave-tech.it>
- *
- * (C) Copyright 2002-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include "sdram.h"
-#include "ecc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SDRAM_BANK0
-
-#ifndef CONFIG_440
-
-#ifndef CONFIG_SYS_SDRAM_TABLE
-sdram_conf_t mb0cf[] = {
- {(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
- {(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
- {(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */
- {(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
- {(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
-};
-#else
-sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
-#endif
-
-#define N_MB0CF (ARRAY_SIZE(mb0cf))
-
-#ifdef CONFIG_SYS_SDRAM_CASL
-static ulong ns2clks(ulong ns)
-{
- ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
-
- return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
-}
-#endif /* CONFIG_SYS_SDRAM_CASL */
-
-static ulong compute_sdtr1(ulong speed)
-{
-#ifdef CONFIG_SYS_SDRAM_CASL
- ulong tmp;
- ulong sdtr1 = 0;
-
- /* CASL */
- if (CONFIG_SYS_SDRAM_CASL < 2)
- sdtr1 |= (1 << SDRAM0_TR_CASL);
- else
- if (CONFIG_SYS_SDRAM_CASL > 4)
- sdtr1 |= (3 << SDRAM0_TR_CASL);
- else
- sdtr1 |= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL);
-
- /* PTA */
- tmp = ns2clks(CONFIG_SYS_SDRAM_PTA);
- if ((tmp >= 2) && (tmp <= 4))
- sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
- else
- sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
-
- /* CTP */
- tmp = ns2clks(CONFIG_SYS_SDRAM_CTP);
- if ((tmp >= 2) && (tmp <= 4))
- sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
- else
- sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
-
- /* LDF */
- tmp = ns2clks(CONFIG_SYS_SDRAM_LDF);
- if ((tmp >= 2) && (tmp <= 4))
- sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
- else
- sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
-
- /* RFTA */
- tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA);
- if ((tmp >= 4) && (tmp <= 10))
- sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
- else
- sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
-
- /* RCD */
- tmp = ns2clks(CONFIG_SYS_SDRAM_RCD);
- if ((tmp >= 2) && (tmp <= 4))
- sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
- else
- sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
-
- return sdtr1;
-#else /* CONFIG_SYS_SDRAM_CASL */
- /*
- * If no values are configured in the board config file
- * use the default values, which seem to be ok for most
- * boards.
- *
- * REMARK:
- * For new board ports we strongly recommend to define the
- * correct values for the used SDRAM chips in your board
- * config file (see PPChameleonEVB.h)
- */
- if (speed > 100000000) {
- /*
- * 133 MHz SDRAM
- */
- return 0x01074015;
- } else {
- /*
- * default: 100 MHz SDRAM
- */
- return 0x0086400d;
- }
-#endif /* CONFIG_SYS_SDRAM_CASL */
-}
-
-/* refresh is expressed in ms */
-static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
-{
-#ifdef CONFIG_SYS_SDRAM_CASL
- ulong tmp;
-
- tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
- tmp /= 1000000;
-
- return ((tmp & 0x00003FF8) << 16);
-#else /* CONFIG_SYS_SDRAM_CASL */
- if (speed > 100000000) {
- /*
- * 133 MHz SDRAM
- */
- return 0x07f00000;
- } else {
- /*
- * default: 100 MHz SDRAM
- */
- return 0x05f00000;
- }
-#endif /* CONFIG_SYS_SDRAM_CASL */
-}
-
-/*
- * Autodetect onboard SDRAM on 405 platforms
- */
-int dram_init(void)
-{
- ulong speed;
- ulong sdtr1;
- int i;
-
- /*
- * Determine SDRAM speed
- */
- speed = get_bus_freq(0); /* parameter not used on ppc4xx */
-
- /*
- * sdtr1 (register SDRAM0_TR) must take into account timings listed
- * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
- * account actual SDRAM size. So we can set up sdtr1 according to what
- * is specified in board configuration file while rtr dependds on SDRAM
- * size we are assuming before detection.
- */
- sdtr1 = compute_sdtr1(speed);
-
- for (i=0; i<N_MB0CF; i++) {
- /*
- * Disable memory controller.
- */
- mtsdram(SDRAM0_CFG, 0x00000000);
-
- /*
- * Set MB0CF for bank 0.
- */
- mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
- mtsdram(SDRAM0_TR, sdtr1);
- mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));
-
- udelay(200);
-
- /*
- * Set memory controller options reg, MCOPT1.
- * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
- * read/prefetch.
- */
- mtsdram(SDRAM0_CFG, 0x80800000);
-
- udelay(10000);
-
- if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
- phys_size_t size = mb0cf[i].size;
-
- /*
- * OK, size detected. Enable second bank if
- * defined (assumes same type as bank 0)
- */
-#ifdef CONFIG_SDRAM_BANK1
- mtsdram(SDRAM0_CFG, 0x00000000);
- mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
- mtsdram(SDRAM0_CFG, 0x80800000);
- udelay(10000);
-
- /*
- * Check if 2nd bank is really available.
- * If the size not equal to the size of the first
- * bank, then disable the 2nd bank completely.
- */
- if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
- mb0cf[i].size) {
- mtsdram(SDRAM0_B1CR, 0);
- mtsdram(SDRAM0_CFG, 0);
- } else {
- /*
- * We have two identical banks, so the size
- * is twice the bank size
- */
- size = 2 * size;
- }
-#endif
-
- /*
- * OK, size detected -> all done
- */
- gd->ram_size = size;
-
- return 0;
- }
- }
-
- return -ENXIO;
-}
-
-#else /* CONFIG_440 */
-
-/*
- * Define some default values. Those can be overwritten in the
- * board config file.
- */
-
-#ifndef CONFIG_SYS_SDRAM_TABLE
-sdram_conf_t mb0cf[] = {
- {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
- {(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4) */
- {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
-};
-#else
-sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
-#endif
-
-#ifndef CONFIG_SYS_SDRAM0_TR0
-#define CONFIG_SYS_SDRAM0_TR0 0x41094012
-#endif
-
-#ifndef CONFIG_SYS_SDRAM0_WDDCTR
-#define CONFIG_SYS_SDRAM0_WDDCTR 0x00000000 /* wrcp=0 dcd=0 */
-#endif
-
-#ifndef CONFIG_SYS_SDRAM0_RTR
-#define CONFIG_SYS_SDRAM0_RTR 0x04100000 /* 7.8us @ 133MHz PLB */
-#endif
-
-#ifndef CONFIG_SYS_SDRAM0_CFG0
-#define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */
-#endif
-
-#define N_MB0CF (ARRAY_SIZE(mb0cf))
-
-#define NUM_TRIES 64
-#define NUM_READS 10
-
-static void sdram_tr1_set(int ram_address, int* tr1_value)
-{
- int i;
- int j, k;
- volatile unsigned int* ram_pointer = (unsigned int *)ram_address;
- int first_good = -1, last_bad = 0x1ff;
-
- unsigned long test[NUM_TRIES] = {
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
-
- /* go through all possible SDRAM0_TR1[RDCT] values */
- for (i=0; i<=0x1ff; i++) {
- /* set the current value for TR1 */
- mtsdram(SDRAM0_TR1, (0x80800800 | i));
-
- /* write values */
- for (j=0; j<NUM_TRIES; j++) {
- ram_pointer[j] = test[j];
-
- /* clear any cache at ram location */
- __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
- }
-
- /* read values back */
- for (j=0; j<NUM_TRIES; j++) {
- for (k=0; k<NUM_READS; k++) {
- /* clear any cache at ram location */
- __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-
- if (ram_pointer[j] != test[j])
- break;
- }
-
- /* read error */
- if (k != NUM_READS)
- break;
- }
-
- /* we have a SDRAM0_TR1[RDCT] that is part of the window */
- if (j == NUM_TRIES) {
- if (first_good == -1)
- first_good = i; /* found beginning of window */
- } else { /* bad read */
- /* if we have not had a good read then don't care */
- if (first_good != -1) {
- /* first failure after a good read */
- last_bad = i-1;
- break;
- }
- }
- }
-
- /* return the current value for TR1 */
- *tr1_value = (first_good + last_bad) / 2;
-}
-
-/*
- * Autodetect onboard DDR SDRAM on 440 platforms
- *
- * NOTE: Some of the hardcoded values are hardware dependant,
- * so this should be extended for other future boards
- * using this routine!
- */
-int dram_init(void)
-{
- int i;
- int tr1_bank1;
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
- defined(CONFIG_440GR) || defined(CONFIG_440SP)
- /*
- * Soft-reset SDRAM controller.
- */
- mtsdr(SDR0_SRST, SDR0_SRST_DMC);
- mtsdr(SDR0_SRST, 0x00000000);
-#endif
-
- for (i=0; i<N_MB0CF; i++) {
- /*
- * Disable memory controller.
- */
- mtsdram(SDRAM0_CFG0, 0x00000000);
-
- /*
- * Setup some default
- */
- mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
- mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR);
- mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
-
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
- mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0);
- mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
- mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR);
- mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
- udelay(400); /* Delay 200 usecs (min) */
-
- /*
- * Enable the controller, then wait for DCEN to complete
- */
- mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
- udelay(10000);
-
- if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
- phys_size_t size = mb0cf[i].size;
- /*
- * Optimize TR1 to current hardware environment
- */
- sdram_tr1_set(0x00000000, &tr1_bank1);
- mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800));
-
-
- /*
- * OK, size detected. Enable second bank if
- * defined (assumes same type as bank 0)
- */
-#ifdef CONFIG_SDRAM_BANK1
- mtsdram(SDRAM0_CFG0, 0);
- mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
- mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
- udelay(10000);
-
- /*
- * Check if 2nd bank is really available.
- * If the size not equal to the size of the first
- * bank, then disable the 2nd bank completely.
- */
- if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
- != mb0cf[i].size) {
- mtsdram(SDRAM0_CFG0, 0);
- mtsdram(SDRAM0_B1CR, 0);
- mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
- udelay(10000);
- } else {
- /*
- * We have two identical banks, so the size
- * is twice the bank size
- */
- size = 2 * size;
- }
-#endif
-
-#ifdef CONFIG_SDRAM_ECC
- ecc_init(0, size);
-#endif
-
- /*
- * OK, size detected -> all done
- */
- gd->ram_size = size;
-
- return 0;
- }
- }
-
- return -ENXIO; /* nothing found ! */
-}
-
-#endif /* CONFIG_440 */
-
-#endif /* CONFIG_SDRAM_BANK0 */
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * DAVE Srl <www.dave-tech.it>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SDRAM_H_
-#define _SDRAM_H_
-
-#include <config.h>
-
-#define ONE_BILLION 1000000000
-
-struct sdram_conf_s {
- unsigned long size;
- int rows;
- unsigned long reg;
-};
-
-typedef struct sdram_conf_s sdram_conf_t;
-
-/* Bitfields offsets */
-#define SDRAM0_TR_CASL (31 - 8)
-#define SDRAM0_TR_PTA (31 - 13)
-#define SDRAM0_TR_CTP (31 - 15)
-#define SDRAM0_TR_LDF (31 - 17)
-#define SDRAM0_TR_RFTA (31 - 29)
-#define SDRAM0_TR_RCD (31 - 31)
-
-#ifdef CONFIG_SYS_SDRAM_CL
-/* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */
-#define CONFIG_SYS_SDRAM_CASL CONFIG_SYS_SDRAM_CL
-#define CONFIG_SYS_SDRAM_PTA CONFIG_SYS_SDRAM_tRP
-#define CONFIG_SYS_SDRAM_CTP (CONFIG_SYS_SDRAM_tRC - CONFIG_SYS_SDRAM_tRCD - CONFIG_SYS_SDRAM_tRP)
-#define CONFIG_SYS_SDRAM_LDF 0
-#ifdef CONFIG_SYS_SDRAM_tRFC
-#define CONFIG_SYS_SDRAM_RFTA CONFIG_SYS_SDRAM_tRFC
-#else
-#define CONFIG_SYS_SDRAM_RFTA CONFIG_SYS_SDRAM_tRC
-#endif
-#define CONFIG_SYS_SDRAM_RCD CONFIG_SYS_SDRAM_tRCD
-#endif /* #ifdef CONFIG_SYS_SDRAM_CL */
-
-/*
- * Some defines for the 440 DDR controller
- */
-#define SDRAM_CFG0_DC_EN 0x80000000 /* SDRAM Controller Enable */
-#define SDRAM_CFG0_MEMCHK 0x30000000 /* Memory data error checking mask*/
-#define SDRAM_CFG0_MEMCHK_NON 0x00000000 /* No ECC generation */
-#define SDRAM_CFG0_MEMCHK_GEN 0x20000000 /* ECC generation */
-#define SDRAM_CFG0_MEMCHK_CHK 0x30000000 /* ECC generation and checking */
-#define SDRAM_CFG0_DRAMWDTH 0x02000000 /* DRAM width mask */
-#define SDRAM_CFG0_DRAMWDTH_32 0x00000000 /* 32 bits */
-#define SDRAM_CFG0_DRAMWDTH_64 0x02000000 /* 64 bits */
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000-2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ppc_asm.tmpl>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define ONE_BILLION 1000000000
-#ifdef DEBUG
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-
-#if defined(CONFIG_405GP)
-
-void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
-{
- unsigned long pllmr;
- unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
- uint pvr = get_pvr();
- unsigned long psr;
- unsigned long m;
-
- /*
- * Read PLL Mode register
- */
- pllmr = mfdcr (CPC0_PLLMR);
-
- /*
- * Read Pin Strapping register
- */
- psr = mfdcr (CPC0_PSR);
-
- /*
- * Determine FWD_DIV.
- */
- sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);
-
- /*
- * Determine FBK_DIV.
- */
- sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
- if (sysInfo->pllFbkDiv == 0) {
- sysInfo->pllFbkDiv = 16;
- }
-
- /*
- * Determine PLB_DIV.
- */
- sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;
-
- /*
- * Determine PCI_DIV.
- */
- sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;
-
- /*
- * Determine EXTBUS_DIV.
- */
- sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;
-
- /*
- * Determine OPB_DIV.
- */
- sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;
-
- /*
- * Check if PPC405GPr used (mask minor revision field)
- */
- if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
- /*
- * Determine FWD_DIV B (only PPC405GPr with new mode strapping).
- */
- sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);
-
- /*
- * Determine factor m depending on PLL feedback clock source
- */
- if (!(psr & PSR_PCI_ASYNC_EN)) {
- if (psr & PSR_NEW_MODE_EN) {
- /*
- * sync pci clock used as feedback (new mode)
- */
- m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
- } else {
- /*
- * sync pci clock used as feedback (legacy mode)
- */
- m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
- }
- } else if (psr & PSR_NEW_MODE_EN) {
- if (psr & PSR_PERCLK_SYNC_MODE_EN) {
- /*
- * PerClk used as feedback (new mode)
- */
- m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
- } else {
- /*
- * CPU clock used as feedback (new mode)
- */
- m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
- }
- } else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
- /*
- * PerClk used as feedback (legacy mode)
- */
- m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
- } else {
- /*
- * PLB clock used as feedback (legacy mode)
- */
- m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
- }
-
- sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
- (unsigned long long)sysClkPeriodPs;
- sysInfo->freqProcessor = sysInfo->freqVCOHz / sysInfo->pllFwdDiv;
- sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
- } else {
- /*
- * Check pllFwdDiv to see if running in bypass mode where the CPU speed
- * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
- * to make sure it is within the proper range.
- * spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
- * Note freqVCO is calculated in MHz to avoid errors introduced by rounding.
- */
- if (sysInfo->pllFwdDiv == 1) {
- sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
- sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
- } else {
- sysInfo->freqVCOHz = ( 1000000000000LL *
- (unsigned long long)sysInfo->pllFwdDiv *
- (unsigned long long)sysInfo->pllFbkDiv *
- (unsigned long long)sysInfo->pllPlbDiv
- ) / (unsigned long long)sysClkPeriodPs;
- sysInfo->freqPLB = (ONE_BILLION / ((sysClkPeriodPs * 10) /
- sysInfo->pllFbkDiv)) * 10000;
- sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
- }
- }
-
- sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
- sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv;
- sysInfo->freqUART = sysInfo->freqProcessor;
-}
-
-
-/********************************************
- * get_PCI_freq
- * return PCI bus freq in Hz
- *********************************************/
-ulong get_PCI_freq (void)
-{
- ulong val;
- PPC4xx_SYS_INFO sys_info;
-
- get_sys_info (&sys_info);
- val = sys_info.freqPLB / sys_info.pllPciDiv;
- return val;
-}
-
-
-#elif defined(CONFIG_440)
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
-static u8 pll_fwdv_multi_bits[] = {
- /* values for: 1 - 16 */
- 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
- 0x05, 0x08, 0x07, 0x02, 0x0b, 0x06
-};
-
-u32 get_cpr0_fwdv(unsigned long cpr_reg_fwdv)
-{
- u32 index;
-
- for (index = 0; index < ARRAY_SIZE(pll_fwdv_multi_bits); index++)
- if (cpr_reg_fwdv == (u32)pll_fwdv_multi_bits[index])
- return index + 1;
-
- return 0;
-}
-
-static u8 pll_fbdv_multi_bits[] = {
- /* values for: 1 - 100 */
- 0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
- 0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
- 0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
- 0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
- 0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
- 0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
- 0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
- 0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
- 0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
- 0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
- /* values for: 101 - 200 */
- 0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
- 0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
- 0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
- 0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
- 0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
- 0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
- 0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
- 0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
- 0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
- 0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
- /* values for: 201 - 255 */
- 0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
- 0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
- 0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
- 0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
- 0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
- 0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */
-};
-
-u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv)
-{
- u32 index;
-
- for (index = 0; index < ARRAY_SIZE(pll_fbdv_multi_bits); index++)
- if (cpr_reg_fbdv == (u32)pll_fbdv_multi_bits[index])
- return index + 1;
-
- return 0;
-}
-
-/*
- * AMCC_TODO: verify this routine against latest EAS, cause stuff changed
- * with latest EAS
- */
-void get_sys_info (sys_info_t * sysInfo)
-{
- unsigned long strp0;
- unsigned long strp1;
- unsigned long temp;
- unsigned long m;
- unsigned long plbedv0;
-
- /* Extract configured divisors */
- mfsdr(SDR0_SDSTP0, strp0);
- mfsdr(SDR0_SDSTP1, strp1);
-
- temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4);
- sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
-
- temp = (strp0 & PLLSYS0_FWD_DIV_B_MASK);
- sysInfo->pllFwdDivB = get_cpr0_fwdv(temp);
-
- temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 8;
- sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
-
- temp = (strp1 & PLLSYS0_OPB_DIV_MASK) >> 26;
- sysInfo->pllOpbDiv = temp ? temp : 4;
-
- /* AMCC_TODO: verify the SDR0_SDSTP1.PERDV0 value sysInfo->pllExtBusDiv */
- temp = (strp1 & PLLSYS0_PERCLK_DIV_MASK) >> 24;
- sysInfo->pllExtBusDiv = temp ? temp : 4;
-
- temp = (strp1 & PLLSYS0_PLBEDV0_DIV_MASK) >> 29;
- plbedv0 = temp ? temp: 8;
-
- /* Calculate 'M' based on feedback source */
- temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
- if (temp == 0) {
- /* PLL internal feedback */
- m = sysInfo->pllFbkDiv;
- } else {
- /* PLL PerClk feedback */
- m = sysInfo->pllFwdDivA * plbedv0 * sysInfo->pllOpbDiv *
- sysInfo->pllExtBusDiv;
- }
-
- /* Now calculate the individual clocks */
- sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m >> 1);
- sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
- sysInfo->freqPLB = sysInfo->freqVCOMhz / sysInfo->pllFwdDivA / plbedv0;
- sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
- sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
- sysInfo->freqDDR = sysInfo->freqPLB;
- sysInfo->freqUART = sysInfo->freqPLB;
-
- return;
-}
-
-#elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-void get_sys_info (sys_info_t *sysInfo)
-{
- unsigned long temp;
- unsigned long reg;
- unsigned long lfdiv;
- unsigned long m;
- unsigned long prbdv0;
- /*
- WARNING: ASSUMES the following:
- ENG=1
- PRADV0=1
- PRBDV0=1
- */
-
- /* Decode CPR0_PLLD0 for divisors */
- mfcpr(CPR0_PLLD, reg);
- temp = (reg & PLLD_FWDVA_MASK) >> 16;
- sysInfo->pllFwdDivA = temp ? temp : 16;
- temp = (reg & PLLD_FWDVB_MASK) >> 8;
- sysInfo->pllFwdDivB = temp ? temp: 8 ;
- temp = (reg & PLLD_FBDV_MASK) >> 24;
- sysInfo->pllFbkDiv = temp ? temp : 32;
- lfdiv = reg & PLLD_LFBDV_MASK;
-
- mfcpr(CPR0_OPBD0, reg);
- temp = (reg & OPBDDV_MASK) >> 24;
- sysInfo->pllOpbDiv = temp ? temp : 4;
-
- mfcpr(CPR0_PERD, reg);
- temp = (reg & PERDV_MASK) >> 24;
- sysInfo->pllExtBusDiv = temp ? temp : 8;
-
- mfcpr(CPR0_PRIMBD0, reg);
- temp = (reg & PRBDV_MASK) >> 24;
- prbdv0 = temp ? temp : 8;
-
- mfcpr(CPR0_SPCID, reg);
- temp = (reg & SPCID_MASK) >> 24;
- sysInfo->pllPciDiv = temp ? temp : 4;
-
- /* Calculate 'M' based on feedback source */
- mfsdr(SDR0_SDSTP0, reg);
- temp = (reg & PLLSYS0_SEL_MASK) >> 27;
- if (temp == 0) { /* PLL output */
- /* Figure which pll to use */
- mfcpr(CPR0_PLLC, reg);
- temp = (reg & PLLC_SRC_MASK) >> 29;
- if (!temp) /* PLLOUTA */
- m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
- else /* PLLOUTB */
- m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
- }
- else if (temp == 1) /* CPU output */
- m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
- else /* PerClk */
- m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
-
- /* Now calculate the individual clocks */
- sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
- sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
- sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
- sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
- sysInfo->freqEBC = sysInfo->freqPLB/sysInfo->pllExtBusDiv;
- sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv;
- sysInfo->freqUART = sysInfo->freqPLB;
-
- /* Figure which timer source to use */
- if (mfspr(SPRN_CCR1) & 0x0080) {
- /* External Clock, assume same as SYS_CLK */
- temp = sysInfo->freqProcessor / 2; /* Max extern clock speed */
- if (CONFIG_SYS_CLK_FREQ > temp)
- sysInfo->freqTmrClk = temp;
- else
- sysInfo->freqTmrClk = CONFIG_SYS_CLK_FREQ;
- }
- else /* Internal clock */
- sysInfo->freqTmrClk = sysInfo->freqProcessor;
-}
-
-/********************************************
- * get_PCI_freq
- * return PCI bus freq in Hz
- *********************************************/
-ulong get_PCI_freq (void)
-{
- sys_info_t sys_info;
- get_sys_info (&sys_info);
- return sys_info.freqPCI;
-}
-
-#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) \
- && !defined(CONFIG_XILINX_440)
-void get_sys_info (sys_info_t * sysInfo)
-{
- unsigned long strp0;
- unsigned long temp;
- unsigned long m;
-
- /* Extract configured divisors */
- strp0 = mfdcr( CPC0_STRP0 );
- sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
- sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
- temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
- sysInfo->pllFbkDiv = temp ? temp : 16;
- sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
- sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);
-
- /* Calculate 'M' based on feedback source */
- if( strp0 & PLLSYS0_EXTSL_MASK )
- m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
- else
- m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
-
- /* Now calculate the individual clocks */
- sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
- sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
- sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
- if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
- sysInfo->freqPLB >>= 1;
- sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
- sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
- sysInfo->freqUART = sysInfo->freqPLB;
-}
-#else
-
-#if !defined(CONFIG_XILINX_440)
-void get_sys_info (sys_info_t * sysInfo)
-{
- unsigned long strp0;
- unsigned long strp1;
- unsigned long temp;
- unsigned long temp1;
- unsigned long lfdiv;
- unsigned long m;
- unsigned long prbdv0;
-
-#if defined(CONFIG_YUCCA)
- unsigned long sys_freq;
- unsigned long sys_per=0;
- unsigned long msr;
- unsigned long pci_clock_per;
- unsigned long sdr_ddrpll;
-
- /*-------------------------------------------------------------------------+
- | Get the system clock period.
- +-------------------------------------------------------------------------*/
- sys_per = determine_sysper();
-
- msr = (mfmsr () & ~(MSR_EE)); /* disable interrupts */
-
- /*-------------------------------------------------------------------------+
- | Calculate the system clock speed from the period.
- +-------------------------------------------------------------------------*/
- sys_freq = (ONE_BILLION / sys_per) * 1000;
-#endif
-
- /* Extract configured divisors */
- mfsdr( SDR0_SDSTP0,strp0 );
- mfsdr( SDR0_SDSTP1,strp1 );
-
- temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
- sysInfo->pllFwdDivA = temp ? temp : 16 ;
- temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
- sysInfo->pllFwdDivB = temp ? temp: 8 ;
- temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
- sysInfo->pllFbkDiv = temp ? temp : 32;
- temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
- sysInfo->pllOpbDiv = temp ? temp : 4;
- temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
- sysInfo->pllExtBusDiv = temp ? temp : 4;
- prbdv0 = (strp0 >> 2) & 0x7;
-
- /* Calculate 'M' based on feedback source */
- temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
- temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
- lfdiv = temp1 ? temp1 : 64;
- if (temp == 0) { /* PLL output */
- /* Figure which pll to use */
- temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
- if (!temp)
- m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
- else
- m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
- }
- else if (temp == 1) /* CPU output */
- m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
- else /* PerClk */
- m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
-
- /* Now calculate the individual clocks */
-#if defined(CONFIG_YUCCA)
- sysInfo->freqVCOMhz = (m * sys_freq) ;
-#else
- sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m >> 1);
-#endif
- sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
- sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
- sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
- sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
-
-#if defined(CONFIG_YUCCA)
- /* Determine PCI Clock Period */
- pci_clock_per = determine_pci_clock_per();
- sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
- mfsdr(SDR0_DDR0, sdr_ddrpll);
- sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
-#endif
-
- sysInfo->freqUART = sysInfo->freqPLB;
-}
-
-#endif
-#endif /* CONFIG_XILINX_440 */
-
-#if defined(CONFIG_YUCCA)
-unsigned long determine_sysper(void)
-{
- unsigned int fpga_clocking_reg;
- unsigned int master_clock_selection;
- unsigned long master_clock_per = 0;
- unsigned long fb_div_selection;
- unsigned int vco_div_reg_value;
- unsigned long vco_div_selection;
- unsigned long sys_per = 0;
- int extClkVal;
-
- /*-------------------------------------------------------------------------+
- | Read FPGA reg 0 and reg 1 to get FPGA reg information
- +-------------------------------------------------------------------------*/
- fpga_clocking_reg = in16(FPGA_REG16);
-
-
- /* Determine Master Clock Source Selection */
- master_clock_selection = fpga_clocking_reg & FPGA_REG16_MASTER_CLK_MASK;
-
- switch(master_clock_selection) {
- case FPGA_REG16_MASTER_CLK_66_66:
- master_clock_per = PERIOD_66_66MHZ;
- break;
- case FPGA_REG16_MASTER_CLK_50:
- master_clock_per = PERIOD_50_00MHZ;
- break;
- case FPGA_REG16_MASTER_CLK_33_33:
- master_clock_per = PERIOD_33_33MHZ;
- break;
- case FPGA_REG16_MASTER_CLK_25:
- master_clock_per = PERIOD_25_00MHZ;
- break;
- case FPGA_REG16_MASTER_CLK_EXT:
- if ((extClkVal==EXTCLK_33_33)
- && (extClkVal==EXTCLK_50)
- && (extClkVal==EXTCLK_66_66)
- && (extClkVal==EXTCLK_83)) {
- /* calculate master clock period from external clock value */
- master_clock_per=(ONE_BILLION/extClkVal) * 1000;
- } else {
- /* Unsupported */
- DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
- hang();
- }
- break;
- default:
- /* Unsupported */
- DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
- hang();
- break;
- }
-
- /* Determine FB divisors values */
- if ((fpga_clocking_reg & FPGA_REG16_FB1_DIV_MASK) == FPGA_REG16_FB1_DIV_LOW) {
- if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
- fb_div_selection = FPGA_FB_DIV_6;
- else
- fb_div_selection = FPGA_FB_DIV_12;
- } else {
- if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
- fb_div_selection = FPGA_FB_DIV_10;
- else
- fb_div_selection = FPGA_FB_DIV_20;
- }
-
- /* Determine VCO divisors values */
- vco_div_reg_value = fpga_clocking_reg & FPGA_REG16_VCO_DIV_MASK;
-
- switch(vco_div_reg_value) {
- case FPGA_REG16_VCO_DIV_4:
- vco_div_selection = FPGA_VCO_DIV_4;
- break;
- case FPGA_REG16_VCO_DIV_6:
- vco_div_selection = FPGA_VCO_DIV_6;
- break;
- case FPGA_REG16_VCO_DIV_8:
- vco_div_selection = FPGA_VCO_DIV_8;
- break;
- case FPGA_REG16_VCO_DIV_10:
- default:
- vco_div_selection = FPGA_VCO_DIV_10;
- break;
- }
-
- if (master_clock_selection == FPGA_REG16_MASTER_CLK_EXT) {
- switch(master_clock_per) {
- case PERIOD_25_00MHZ:
- if (fb_div_selection == FPGA_FB_DIV_12) {
- if (vco_div_selection == FPGA_VCO_DIV_4)
- sys_per = PERIOD_75_00MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_6)
- sys_per = PERIOD_50_00MHZ;
- }
- break;
- case PERIOD_33_33MHZ:
- if (fb_div_selection == FPGA_FB_DIV_6) {
- if (vco_div_selection == FPGA_VCO_DIV_4)
- sys_per = PERIOD_50_00MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_6)
- sys_per = PERIOD_33_33MHZ;
- }
- if (fb_div_selection == FPGA_FB_DIV_10) {
- if (vco_div_selection == FPGA_VCO_DIV_4)
- sys_per = PERIOD_83_33MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_10)
- sys_per = PERIOD_33_33MHZ;
- }
- if (fb_div_selection == FPGA_FB_DIV_12) {
- if (vco_div_selection == FPGA_VCO_DIV_4)
- sys_per = PERIOD_100_00MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_6)
- sys_per = PERIOD_66_66MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_8)
- sys_per = PERIOD_50_00MHZ;
- }
- break;
- case PERIOD_50_00MHZ:
- if (fb_div_selection == FPGA_FB_DIV_6) {
- if (vco_div_selection == FPGA_VCO_DIV_4)
- sys_per = PERIOD_75_00MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_6)
- sys_per = PERIOD_50_00MHZ;
- }
- if (fb_div_selection == FPGA_FB_DIV_10) {
- if (vco_div_selection == FPGA_VCO_DIV_6)
- sys_per = PERIOD_83_33MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_10)
- sys_per = PERIOD_50_00MHZ;
- }
- if (fb_div_selection == FPGA_FB_DIV_12) {
- if (vco_div_selection == FPGA_VCO_DIV_6)
- sys_per = PERIOD_100_00MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_8)
- sys_per = PERIOD_75_00MHZ;
- }
- break;
- case PERIOD_66_66MHZ:
- if (fb_div_selection == FPGA_FB_DIV_6) {
- if (vco_div_selection == FPGA_VCO_DIV_4)
- sys_per = PERIOD_100_00MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_6)
- sys_per = PERIOD_66_66MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_8)
- sys_per = PERIOD_50_00MHZ;
- }
- if (fb_div_selection == FPGA_FB_DIV_10) {
- if (vco_div_selection == FPGA_VCO_DIV_8)
- sys_per = PERIOD_83_33MHZ;
- if (vco_div_selection == FPGA_VCO_DIV_10)
- sys_per = PERIOD_66_66MHZ;
- }
- if (fb_div_selection == FPGA_FB_DIV_12) {
- if (vco_div_selection == FPGA_VCO_DIV_8)
- sys_per = PERIOD_100_00MHZ;
- }
- break;
- default:
- break;
- }
-
- if (sys_per == 0) {
- /* Other combinations are not supported */
- DEBUGF ("%s[%d] *** sys period compute failed ***\n", __FUNCTION__,__LINE__);
- hang();
- }
- } else {
- /* calcul system clock without cheking */
- /* if engineering option clock no check is selected */
- /* sys_per = master_clock_per * vco_div_selection / fb_div_selection */
- sys_per = (master_clock_per/fb_div_selection) * vco_div_selection;
- }
-
- return(sys_per);
-}
-
-/*-------------------------------------------------------------------------+
-| determine_pci_clock_per.
-+-------------------------------------------------------------------------*/
-unsigned long determine_pci_clock_per(void)
-{
- unsigned long pci_clock_selection, pci_period;
-
- /*-------------------------------------------------------------------------+
- | Read FPGA reg 6 to get PCI 0 FPGA reg information
- +-------------------------------------------------------------------------*/
- pci_clock_selection = in16(FPGA_REG16); /* was reg6 averifier */
-
-
- pci_clock_selection = pci_clock_selection & FPGA_REG16_PCI0_CLK_MASK;
-
- switch (pci_clock_selection) {
- case FPGA_REG16_PCI0_CLK_133_33:
- pci_period = PERIOD_133_33MHZ;
- break;
- case FPGA_REG16_PCI0_CLK_100:
- pci_period = PERIOD_100_00MHZ;
- break;
- case FPGA_REG16_PCI0_CLK_66_66:
- pci_period = PERIOD_66_66MHZ;
- break;
- default:
- pci_period = PERIOD_33_33MHZ;
- break;
- }
-
- return(pci_period);
-}
-#endif
-
-#elif defined(CONFIG_XILINX_405)
-extern void get_sys_info (sys_info_t * sysInfo);
-extern ulong get_PCI_freq (void);
-
-#elif defined(CONFIG_405)
-
-void get_sys_info (sys_info_t * sysInfo)
-{
- sysInfo->freqVCOMhz=3125000;
- sysInfo->freqProcessor=12*1000*1000;
- sysInfo->freqPLB=50*1000*1000;
- sysInfo->freqPCI=66*1000*1000;
-}
-
-#elif defined(CONFIG_405EP)
-void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
-{
- unsigned long pllmr0;
- unsigned long pllmr1;
- unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
- unsigned long m;
- unsigned long pllmr0_ccdv;
-
- /*
- * Read PLL Mode registers
- */
- pllmr0 = mfdcr (CPC0_PLLMR0);
- pllmr1 = mfdcr (CPC0_PLLMR1);
-
- /*
- * Determine forward divider A
- */
- sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16);
-
- /*
- * Determine forward divider B (should be equal to A)
- */
- sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12);
-
- /*
- * Determine FBK_DIV.
- */
- sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
- if (sysInfo->pllFbkDiv == 0)
- sysInfo->pllFbkDiv = 16;
-
- /*
- * Determine PLB_DIV.
- */
- sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
-
- /*
- * Determine PCI_DIV.
- */
- sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1;
-
- /*
- * Determine EXTBUS_DIV.
- */
- sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2;
-
- /*
- * Determine OPB_DIV.
- */
- sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1;
-
- /*
- * Determine the M factor
- */
- m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
-
- /*
- * Determine VCO clock frequency
- */
- sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
- (unsigned long long)sysClkPeriodPs;
-
- /*
- * Determine CPU clock frequency
- */
- pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
- if (pllmr1 & PLLMR1_SSCS_MASK) {
- /*
- * This is true if FWDVA == FWDVB:
- * sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
- * / pllmr0_ccdv;
- */
- sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB)
- / sysInfo->pllFwdDiv / pllmr0_ccdv;
- } else {
- sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
- }
-
- /*
- * Determine PLB clock frequency
- */
- sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
-
- sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv;
-
- sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
-
- sysInfo->freqUART = sysInfo->freqProcessor * pllmr0_ccdv;
-}
-
-
-/********************************************
- * get_PCI_freq
- * return PCI bus freq in Hz
- *********************************************/
-ulong get_PCI_freq (void)
-{
- ulong val;
- PPC4xx_SYS_INFO sys_info;
-
- get_sys_info (&sys_info);
- val = sys_info.freqPLB / sys_info.pllPciDiv;
- return val;
-}
-
-#elif defined(CONFIG_405EZ)
-void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
-{
- unsigned long cpr_plld;
- unsigned long cpr_pllc;
- unsigned long cpr_primad;
- unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
- unsigned long primad_cpudv;
- unsigned long m;
- unsigned long plloutb;
-
- /*
- * Read PLL Mode registers
- */
- mfcpr(CPR0_PLLD, cpr_plld);
- mfcpr(CPR0_PLLC, cpr_pllc);
-
- /*
- * Determine forward divider A
- */
- sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
-
- /*
- * Determine forward divider B
- */
- sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
- if (sysInfo->pllFwdDivB == 0)
- sysInfo->pllFwdDivB = 8;
-
- /*
- * Determine FBK_DIV.
- */
- sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
- if (sysInfo->pllFbkDiv == 0)
- sysInfo->pllFbkDiv = 256;
-
- /*
- * Read CPR_PRIMAD register
- */
- mfcpr(CPR0_PRIMAD, cpr_primad);
-
- /*
- * Determine PLB_DIV.
- */
- sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
- if (sysInfo->pllPlbDiv == 0)
- sysInfo->pllPlbDiv = 16;
-
- /*
- * Determine EXTBUS_DIV.
- */
- sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
- if (sysInfo->pllExtBusDiv == 0)
- sysInfo->pllExtBusDiv = 16;
-
- /*
- * Determine OPB_DIV.
- */
- sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
- if (sysInfo->pllOpbDiv == 0)
- sysInfo->pllOpbDiv = 16;
-
- /*
- * Determine the M factor
- */
- if (cpr_pllc & PLLC_SRC_MASK)
- m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
- else
- m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
-
- /*
- * Determine VCO clock frequency
- */
- sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
- (unsigned long long)sysClkPeriodPs;
-
- /*
- * Determine CPU clock frequency
- */
- primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
- if (primad_cpudv == 0)
- primad_cpudv = 16;
-
- sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * m) /
- sysInfo->pllFwdDiv / primad_cpudv;
-
- /*
- * Determine PLB clock frequency
- */
- sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) /
- sysInfo->pllFwdDiv / sysInfo->pllPlbDiv;
-
- sysInfo->freqOPB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) /
- sysInfo->pllOpbDiv;
-
- sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) /
- sysInfo->pllExtBusDiv;
-
- plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
- sysInfo->pllFwdDivB : sysInfo->pllFwdDiv) * sysInfo->pllFbkDiv) /
- sysInfo->pllFwdDivB);
- sysInfo->freqUART = plloutb;
-}
-
-#elif defined(CONFIG_405EX)
-
-/*
- * TODO: We need to get the CPR registers and calculate these values correctly!!!!
- * We need the specs!!!!
- */
-static unsigned char get_fbdv(unsigned char index)
-{
- unsigned char ret = 0;
- /* This is table should be 256 bytes.
- * Only take first 52 values.
- */
- unsigned char fbdv_tb[] = {
- 0x00, 0xff, 0x7f, 0xfd,
- 0x7a, 0xf5, 0x6a, 0xd5,
- 0x2a, 0xd4, 0x29, 0xd3,
- 0x26, 0xcc, 0x19, 0xb3,
- 0x67, 0xce, 0x1d, 0xbb,
- 0x77, 0xee, 0x5d, 0xba,
- 0x74, 0xe9, 0x52, 0xa5,
- 0x4b, 0x96, 0x2c, 0xd8,
- 0x31, 0xe3, 0x46, 0x8d,
- 0x1b, 0xb7, 0x6f, 0xde,
- 0x3d, 0xfb, 0x76, 0xed,
- 0x5a, 0xb5, 0x6b, 0xd6,
- 0x2d, 0xdb, 0x36, 0xec,
-
- };
-
- if ((index & 0x7f) == 0)
- return 1;
- while (ret < sizeof (fbdv_tb)) {
- if (fbdv_tb[ret] == index)
- break;
- ret++;
- }
- ret++;
-
- return ret;
-}
-
-#define PLL_FBK_PLL_LOCAL 0
-#define PLL_FBK_CPU 1
-#define PLL_FBK_PERCLK 5
-
-void get_sys_info (sys_info_t * sysInfo)
-{
- unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
- unsigned long m = 1;
- unsigned int tmp;
- unsigned char fwdva[16] = {
- 1, 2, 14, 9, 4, 11, 16, 13,
- 12, 5, 6, 15, 10, 7, 8, 3,
- };
- unsigned char sel, cpudv0, plb2xDiv;
-
- mfcpr(CPR0_PLLD, tmp);
-
- /*
- * Determine forward divider A
- */
- sysInfo->pllFwdDiv = fwdva[((tmp >> 16) & 0x0f)]; /* FWDVA */
-
- /*
- * Determine FBK_DIV.
- */
- sysInfo->pllFbkDiv = get_fbdv(((tmp >> 24) & 0x0ff)); /* FBDV */
-
- /*
- * Determine PLBDV0
- */
- sysInfo->pllPlbDiv = 2;
-
- /*
- * Determine PERDV0
- */
- mfcpr(CPR0_PERD, tmp);
- tmp = (tmp >> 24) & 0x03;
- sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp;
-
- /*
- * Determine OPBDV0
- */
- mfcpr(CPR0_OPBD0, tmp);
- tmp = (tmp >> 24) & 0x03;
- sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp;
-
- /* Determine PLB2XDV0 */
- mfcpr(CPR0_PLBD, tmp);
- tmp = (tmp >> 16) & 0x07;
- plb2xDiv = (tmp == 0) ? 8 : tmp;
-
- /* Determine CPUDV0 */
- mfcpr(CPR0_CPUD, tmp);
- tmp = (tmp >> 24) & 0x07;
- cpudv0 = (tmp == 0) ? 8 : tmp;
-
- /* Determine SEL(5:7) in CPR0_PLLC */
- mfcpr(CPR0_PLLC, tmp);
- sel = (tmp >> 24) & 0x07;
-
- /*
- * Determine the M factor
- * PLL local: M = FBDV
- * CPU clock: M = FBDV * FWDVA * CPUDV0
- * PerClk : M = FBDV * FWDVA * PLB2XDV0 * PLBDV0(2) * OPBDV0 * PERDV0
- *
- */
- switch (sel) {
- case PLL_FBK_CPU:
- m = sysInfo->pllFwdDiv * cpudv0;
- break;
- case PLL_FBK_PERCLK:
- m = sysInfo->pllFwdDiv * plb2xDiv * 2
- * sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv;
- break;
- case PLL_FBK_PLL_LOCAL:
- break;
- default:
- printf("%s unknown m\n", __FUNCTION__);
- return;
-
- }
- m *= sysInfo->pllFbkDiv;
-
- /*
- * Determine VCO clock frequency
- */
- sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
- (unsigned long long)sysClkPeriodPs;
-
- /*
- * Determine CPU clock frequency
- */
- sysInfo->freqProcessor = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * cpudv0);
-
- /*
- * Determine PLB clock frequency, ddr1x should be the same
- */
- sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * plb2xDiv * 2);
- sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
- sysInfo->freqDDR = sysInfo->freqPLB;
- sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
- sysInfo->freqUART = sysInfo->freqPLB;
-}
-
-#endif
-
-int get_clocks (void)
-{
- sys_info_t sys_info;
-
- get_sys_info (&sys_info);
- gd->cpu_clk = sys_info.freqProcessor;
- gd->bus_clk = sys_info.freqPLB;
-
- return (0);
-}
-
-
-/********************************************
- * get_bus_freq
- * return PLB bus freq in Hz
- *********************************************/
-ulong get_bus_freq (ulong dummy)
-{
- ulong val;
-
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_405EX) || defined(CONFIG_405) || \
- defined(CONFIG_440)
- sys_info_t sys_info;
-
- get_sys_info (&sys_info);
- val = sys_info.freqPLB;
-#else
-# error get_bus_freq() not implemented
-#endif
-
- return val;
-}
-
-ulong get_OPB_freq (void)
-{
- PPC4xx_SYS_INFO sys_info;
-
- get_sys_info (&sys_info);
-
- return sys_info.freqOPB;
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Return selected boot device. On PPC4xx its only NOR flash right now.
- */
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_NOR;
-}
-
-/*
- * SPL version of board_init_f()
- */
-void board_init_f(ulong bootflag)
-{
- /*
- * First we need to initialize the SDRAM, so that the real
- * U-Boot or the OS (Linux) can be loaded
- */
- dram_init();
-
- /* Clear bss */
- memset(__bss_start, '\0', __bss_end - __bss_start);
-
- /*
- * Init global_data pointer. Has to be done before calling
- * get_clocks(), as it stores some clock values into gd needed
- * later on in the serial driver.
- */
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
- /* Clear initial global data */
- memset((void *)gd, 0, sizeof(gd_t));
-
- /*
- * get_clocks() needs to be called so that the serial driver
- * works correctly
- */
- get_clocks();
-
- /*
- * Do rudimental console / serial setup
- */
- preloader_console_init();
-
- /*
- * Call board_init_r() (SPL framework version) to load and boot
- * real U-Boot or OS
- */
- board_init_r(NULL, 0);
- /* Does not return!!! */
-}
+++ /dev/null
-/*
- * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
- * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
- * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
- * Copyright (c) 2008 Nuovation System Designs, LLC
- * Grant Erickson <gerickson@nuovations.com>
- *
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-
-/*
- * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
- *
- * The following description only applies to the NOR flash style booting.
- * NAND booting is different. For more details about NAND booting on 4xx
- * take a look at doc/README.nand-boot-ppc440.
- *
- * The CPU starts at address 0xfffffffc (last word in the address space).
- * The U-Boot image therefore has to be located in the "upper" area of the
- * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
- * the boot chip-select (CS0) is quite big and covers this area. On the
- * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
- * reconfigure this CS0 (and other chip-selects as well when configured
- * this way) in the boot process to the "correct" values matching the
- * board layout.
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/ppc4xx.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx-isram.h>
-
-#ifdef CONFIG_SYS_INIT_DCACHE_CS
-# if (CONFIG_SYS_INIT_DCACHE_CS == 0)
-# define PBxAP PB1AP
-# define PBxCR PB0CR
-# if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
-# define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
-# define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
-# endif
-# endif
-# if (CONFIG_SYS_INIT_DCACHE_CS == 1)
-# define PBxAP PB1AP
-# define PBxCR PB1CR
-# if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
-# define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
-# define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
-# endif
-# endif
-# if (CONFIG_SYS_INIT_DCACHE_CS == 2)
-# define PBxAP PB2AP
-# define PBxCR PB2CR
-# if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
-# define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
-# define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
-# endif
-# endif
-# if (CONFIG_SYS_INIT_DCACHE_CS == 3)
-# define PBxAP PB3AP
-# define PBxCR PB3CR
-# if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
-# define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
-# define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
-# endif
-# endif
-# if (CONFIG_SYS_INIT_DCACHE_CS == 4)
-# define PBxAP PB4AP
-# define PBxCR PB4CR
-# if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
-# define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
-# define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
-# endif
-# endif
-# if (CONFIG_SYS_INIT_DCACHE_CS == 5)
-# define PBxAP PB5AP
-# define PBxCR PB5CR
-# if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
-# define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
-# define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
-# endif
-# endif
-# if (CONFIG_SYS_INIT_DCACHE_CS == 6)
-# define PBxAP PB6AP
-# define PBxCR PB6CR
-# if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
-# define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
-# define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
-# endif
-# endif
-# if (CONFIG_SYS_INIT_DCACHE_CS == 7)
-# define PBxAP PB7AP
-# define PBxCR PB7CR
-# if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
-# define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
-# define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
-# endif
-# endif
-# ifndef PBxAP_VAL
-# define PBxAP_VAL 0
-# endif
-# ifndef PBxCR_VAL
-# define PBxCR_VAL 0
-# endif
-/*
- * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
- * used as temporary stack pointer for the primordial stack
- */
-# ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
-# define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(7) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(0) | \
- EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(2) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-# endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
-# ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
-# define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
- EBC_BXCR_BS_64MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-# endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
-# ifndef CONFIG_SYS_INIT_RAM_PATTERN
-# define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
-# endif
-#endif /* CONFIG_SYS_INIT_DCACHE_CS */
-
-#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
-#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
-#endif
-
-/*
- * Unless otherwise overridden, enable two 128MB cachable instruction regions
- * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
- * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
- */
-#if !defined(CONFIG_SYS_FLASH_BASE)
-/* If not already defined, set it to the "last" 128MByte region */
-# define CONFIG_SYS_FLASH_BASE 0xf8000000
-#endif
-#if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
-# define CONFIG_SYS_ICACHE_SACR_VALUE \
- (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
- PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
- PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
-#endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
-
-#if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
-# define CONFIG_SYS_DCACHE_SACR_VALUE \
- (0x00000000)
-#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
-
-#if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
-#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
-#endif
-
-#define function_prolog(func_name) .text; \
- .align 2; \
- .globl func_name; \
- func_name:
-#define function_epilog(func_name) .type func_name,@function; \
- .size func_name,.-func_name
-
-/* We don't want the MMU yet.
-*/
-#undef MSR_KERNEL
-#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
-
-
- .extern ext_bus_cntlr_init
-
-/*
- * Set up GOT: Global Offset Table
- *
- * Use r12 to access the GOT
- */
-#if !defined(CONFIG_SPL_BUILD)
- START_GOT
- GOT_ENTRY(_GOT2_TABLE_)
- GOT_ENTRY(_FIXUP_TABLE_)
-
- GOT_ENTRY(_start)
- GOT_ENTRY(_start_of_vectors)
- GOT_ENTRY(_end_of_vectors)
- GOT_ENTRY(transfer_to_handler)
-
- GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end)
- GOT_ENTRY(__bss_start)
- END_GOT
-#endif /* CONFIG_SPL_BUILD */
-
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
- /*
- * 4xx RAM-booting U-Boot image is started from offset 0
- */
- .text
- bl _start_440
-#endif
-
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- /*
- * This is the entry of the real U-Boot from a board port
- * that supports SPL booting on the PPC4xx. We only need
- * to call board_init_f() here. Everything else has already
- * been done in the SPL u-boot version.
- */
- GET_GOT /* initialize GOT access */
- bl board_init_f /* run 1st part of board init code (in Flash)*/
- /* NOTREACHED - board_init_f() does not return */
-#endif
-
-/*
- * 440 Startup -- on reset only the top 4k of the effective
- * address space is mapped in by an entry in the instruction
- * and data shadow TLB. The .bootpg section is located in the
- * top 4k & does only what's necessary to map in the the rest
- * of the boot rom. Once the boot rom is mapped in we can
- * proceed with normal startup.
- *
- * NOTE: CS0 only covers the top 2MB of the effective address
- * space after reset.
- */
-
-#if defined(CONFIG_440)
- .section .bootpg,"ax"
- .globl _start_440
-
-/**************************************************************************/
-_start_440:
- /*--------------------------------------------------------------------+
- | 440EPX BUP Change - Hardware team request
- +--------------------------------------------------------------------*/
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
- sync
- nop
- nop
-#endif
- /*----------------------------------------------------------------+
- | Core bug fix. Clear the esr
- +-----------------------------------------------------------------*/
- li r0,0
- mtspr SPRN_ESR,r0
- /*----------------------------------------------------------------*/
- /* Clear and set up some registers. */
- /*----------------------------------------------------------------*/
- iccci r0,r0 /* NOTE: operands not used for 440 */
- dccci r0,r0 /* NOTE: operands not used for 440 */
- sync
- li r0,0
- mtspr SPRN_SRR0,r0
- mtspr SPRN_SRR1,r0
- mtspr SPRN_CSRR0,r0
- mtspr SPRN_CSRR1,r0
- /* NOTE: 440GX adds machine check status regs */
-#if defined(CONFIG_440) && !defined(CONFIG_440GP)
- mtspr SPRN_MCSRR0,r0
- mtspr SPRN_MCSRR1,r0
- mfspr r1,SPRN_MCSR
- mtspr SPRN_MCSR,r1
-#endif
-
- /*----------------------------------------------------------------*/
- /* CCR0 init */
- /*----------------------------------------------------------------*/
- /* Disable store gathering & broadcast, guarantee inst/data
- * cache block touch, force load/store alignment
- * (see errata 1.12: 440_33)
- */
- lis r1,0x0030 /* store gathering & broadcast disable */
- ori r1,r1,0x6000 /* cache touch */
- mtspr SPRN_CCR0,r1
-
- /*----------------------------------------------------------------*/
- /* Initialize debug */
- /*----------------------------------------------------------------*/
- mfspr r1,SPRN_DBCR0
- andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
- bne skip_debug_init /* if set, don't clear debug register */
- mfspr r1,SPRN_CCR0
- ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
- mtspr SPRN_CCR0,r1
- mtspr SPRN_DBCR0,r0
- mtspr SPRN_DBCR1,r0
- mtspr SPRN_DBCR2,r0
- mtspr SPRN_IAC1,r0
- mtspr SPRN_IAC2,r0
- mtspr SPRN_IAC3,r0
- mtspr SPRN_DAC1,r0
- mtspr SPRN_DAC2,r0
- mtspr SPRN_DVC1,r0
- mtspr SPRN_DVC2,r0
-
- mfspr r1,SPRN_DBSR
- mtspr SPRN_DBSR,r1 /* Clear all valid bits */
-skip_debug_init:
-
-#if defined (CONFIG_440SPE)
- /*----------------------------------------------------------------+
- | Initialize Core Configuration Reg1.
- | a. ICDPEI: Record even parity. Normal operation.
- | b. ICTPEI: Record even parity. Normal operation.
- | c. DCTPEI: Record even parity. Normal operation.
- | d. DCDPEI: Record even parity. Normal operation.
- | e. DCUPEI: Record even parity. Normal operation.
- | f. DCMPEI: Record even parity. Normal operation.
- | g. FCOM: Normal operation
- | h. MMUPEI: Record even parity. Normal operation.
- | i. FFF: Flush only as much data as necessary.
- | j. TCS: Timebase increments from CPU clock.
- +-----------------------------------------------------------------*/
- li r0,0
- mtspr SPRN_CCR1, r0
-
- /*----------------------------------------------------------------+
- | Reset the timebase.
- | The previous write to CCR1 sets the timebase source.
- +-----------------------------------------------------------------*/
- mtspr SPRN_TBWL, r0
- mtspr SPRN_TBWU, r0
-#endif
-
- /*----------------------------------------------------------------*/
- /* Setup interrupt vectors */
- /*----------------------------------------------------------------*/
- mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
- li r1,0x0100
- mtspr SPRN_IVOR0,r1 /* Critical input */
- li r1,0x0200
- mtspr SPRN_IVOR1,r1 /* Machine check */
- li r1,0x0300
- mtspr SPRN_IVOR2,r1 /* Data storage */
- li r1,0x0400
- mtspr SPRN_IVOR3,r1 /* Instruction storage */
- li r1,0x0500
- mtspr SPRN_IVOR4,r1 /* External interrupt */
- li r1,0x0600
- mtspr SPRN_IVOR5,r1 /* Alignment */
- li r1,0x0700
- mtspr SPRN_IVOR6,r1 /* Program check */
- li r1,0x0800
- mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
- li r1,0x0c00
- mtspr SPRN_IVOR8,r1 /* System call */
- li r1,0x0a00
- mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
- li r1,0x0900
- mtspr SPRN_IVOR10,r1 /* Decrementer */
- li r1,0x1300
- mtspr SPRN_IVOR13,r1 /* Data TLB error */
- li r1,0x1400
- mtspr SPRN_IVOR14,r1 /* Instr TLB error */
- li r1,0x2000
- mtspr SPRN_IVOR15,r1 /* Debug */
-
- /*----------------------------------------------------------------*/
- /* Configure cache regions */
- /*----------------------------------------------------------------*/
- mtspr SPRN_INV0,r0
- mtspr SPRN_INV1,r0
- mtspr SPRN_INV2,r0
- mtspr SPRN_INV3,r0
- mtspr SPRN_DNV0,r0
- mtspr SPRN_DNV1,r0
- mtspr SPRN_DNV2,r0
- mtspr SPRN_DNV3,r0
- mtspr SPRN_ITV0,r0
- mtspr SPRN_ITV1,r0
- mtspr SPRN_ITV2,r0
- mtspr SPRN_ITV3,r0
- mtspr SPRN_DTV0,r0
- mtspr SPRN_DTV1,r0
- mtspr SPRN_DTV2,r0
- mtspr SPRN_DTV3,r0
-
- /*----------------------------------------------------------------*/
- /* Cache victim limits */
- /*----------------------------------------------------------------*/
- /* floors 0, ceiling max to use the entire cache -- nothing locked
- */
- lis r1,0x0001
- ori r1,r1,0xf800
- mtspr SPRN_IVLIM,r1
- mtspr SPRN_DVLIM,r1
-
- /*----------------------------------------------------------------+
- |Initialize MMUCR[STID] = 0.
- +-----------------------------------------------------------------*/
- mfspr r0,SPRN_MMUCR
- addis r1,0,0xFFFF
- ori r1,r1,0xFF00
- and r0,r0,r1
- mtspr SPRN_MMUCR,r0
-
- /*----------------------------------------------------------------*/
- /* Clear all TLB entries -- TID = 0, TS = 0 */
- /*----------------------------------------------------------------*/
- addis r0,0,0x0000
-#ifdef CONFIG_SYS_RAMBOOT
- li r4,0 /* Start with TLB #0 */
-#else
- li r4,1 /* Start with TLB #1 */
-#endif
- li r1,64 /* 64 TLB entries */
- sub r1,r1,r4 /* calculate last TLB # */
- mtctr r1
-rsttlb:
-#ifdef CONFIG_SYS_RAMBOOT
- tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
- rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
- beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
-#endif
- tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
- tlbwe r0,r4,1
- tlbwe r0,r4,2
-tlbnxt: addi r4,r4,1 /* Next TLB */
- bdnz rsttlb
-
- /*----------------------------------------------------------------*/
- /* TLB entry setup -- step thru tlbtab */
- /*----------------------------------------------------------------*/
-#if defined(CONFIG_440SPE_REVA)
- /*----------------------------------------------------------------*/
- /* We have different TLB tables for revA and rev B of 440SPe */
- /*----------------------------------------------------------------*/
- mfspr r1, PVR
- lis r0,0x5342
- ori r0,r0,0x1891
- cmpw r7,r1,r0
- bne r7,..revA
- bl tlbtabB
- b ..goon
-..revA:
- bl tlbtabA
-..goon:
-#else
- bl tlbtab /* Get tlbtab pointer */
-#endif
- mr r5,r0
- li r1,0x003f /* 64 TLB entries max */
- mtctr r1
- li r4,0 /* TLB # */
-
- addi r5,r5,-4
-1:
-#ifdef CONFIG_SYS_RAMBOOT
- tlbre r3,r4,0 /* Read contents from TLB word #0 */
- rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
- bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
-#endif
- lwzu r0,4(r5)
- cmpwi r0,0
- beq 2f /* 0 marks end */
- lwzu r1,4(r5)
- lwzu r2,4(r5)
- tlbwe r0,r4,0 /* TLB Word 0 */
- tlbwe r1,r4,1 /* TLB Word 1 */
- tlbwe r2,r4,2 /* TLB Word 2 */
-tlbnx2: addi r4,r4,1 /* Next TLB */
- bdnz 1b
-
- /*----------------------------------------------------------------*/
- /* Continue from 'normal' start */
- /*----------------------------------------------------------------*/
-2:
- bl 3f
- b _start
-
-3: li r0,0
- mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
- mflr r1
- mtspr SPRN_SRR0,r1
- rfi
-#endif /* CONFIG_440 */
-
-/*
- * r3 - 1st arg to board_init(): IMMP pointer
- * r4 - 2nd arg to board_init(): boot flag
- */
-#if !defined(CONFIG_SPL_BUILD)
- .text
- .long 0x27051956 /* U-Boot Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION_STRING, "\0"
-
- . = EXC_OFF_SYS_RESET
- .globl _start_of_vectors
-_start_of_vectors:
-
-/* Critical input. */
- CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
-
-#ifdef CONFIG_440
-/* Machine check */
- MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
-#else
- CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
-#endif /* CONFIG_440 */
-
-/* Data Storage exception. */
- STD_EXCEPTION(0x300, DataStorage, UnknownException)
-
-/* Instruction Storage exception. */
- STD_EXCEPTION(0x400, InstStorage, UnknownException)
-
-/* External Interrupt exception. */
- STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
-
-/* Alignment exception. */
- . = 0x600
-Alignment:
- EXCEPTION_PROLOG(SRR0, SRR1)
- mfspr r4,DAR
- stw r4,_DAR(r21)
- mfspr r5,DSISR
- stw r5,_DSISR(r21)
- addi r3,r1,STACK_FRAME_OVERHEAD
- EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-
-/* Program check exception */
- . = 0x700
-ProgramCheck:
- EXCEPTION_PROLOG(SRR0, SRR1)
- addi r3,r1,STACK_FRAME_OVERHEAD
- EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
- MSR_KERNEL, COPY_EE)
-
-#ifdef CONFIG_440
- STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
- STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
- STD_EXCEPTION(0xa00, APU, UnknownException)
-#endif
- STD_EXCEPTION(0xc00, SystemCall, UnknownException)
-
-#ifdef CONFIG_440
- STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
- STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
-#else
- STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
- STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
- STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
-#endif
- CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
-
- .globl _end_of_vectors
-_end_of_vectors:
- . = _START_OFFSET
-#endif
- .globl _start
-_start:
-
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- /*
- * This is the entry of the real U-Boot from a board port
- * that supports SPL booting on the PPC4xx. We only need
- * to call board_init_f() here. Everything else has already
- * been done in the SPL u-boot version.
- */
- GET_GOT /* initialize GOT access */
- bl board_init_f /* run 1st part of board init code (in Flash)*/
- /* NOTREACHED - board_init_f() does not return */
-#endif
-
-/*****************************************************************************/
-#if defined(CONFIG_440)
-
- /*----------------------------------------------------------------*/
- /* Clear and set up some registers. */
- /*----------------------------------------------------------------*/
- li r0,0x0000
- lis r1,0xffff
- mtspr SPRN_DEC,r0 /* prevent dec exceptions */
- mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
- mtspr SPRN_TBWU,r0
- mtspr SPRN_TSR,r1 /* clear all timer exception status */
- mtspr SPRN_TCR,r0 /* disable all */
- mtspr SPRN_ESR,r0 /* clear exception syndrome register */
- mtxer r0 /* clear integer exception register */
-
- /*----------------------------------------------------------------*/
- /* Debug setup -- some (not very good) ice's need an event*/
- /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
- /* value you need in this case 0x8cff 0000 should do the trick */
- /*----------------------------------------------------------------*/
-#if defined(CONFIG_SYS_INIT_DBCR)
- lis r1,0xffff
- ori r1,r1,0xffff
- mtspr SPRN_DBSR,r1 /* Clear all status bits */
- lis r0,CONFIG_SYS_INIT_DBCR@h
- ori r0,r0,CONFIG_SYS_INIT_DBCR@l
- mtspr SPRN_DBCR0,r0
- isync
-#endif
-
- /*----------------------------------------------------------------*/
- /* Setup the internal SRAM */
- /*----------------------------------------------------------------*/
- li r0,0
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* Clear Dcache to use as RAM */
- addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
- ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
- addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
- ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
- rlwinm. r5,r4,0,27,31
- rlwinm r5,r4,27,5,31
- beq ..d_ran
- addi r5,r5,0x0001
-..d_ran:
- mtctr r5
-..d_ag:
- dcbz r0,r3
- addi r3,r3,32
- bdnz ..d_ag
-
- /*
- * Lock the init-ram/stack in d-cache, so that other regions
- * may use d-cache as well
- * Note, that this current implementation locks exactly 4k
- * of d-cache, so please make sure that you don't define a
- * bigger init-ram area. Take a look at the lwmon5 440EPx
- * implementation as a reference.
- */
- msync
- isync
- /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
- lis r1,0x0201
- ori r1,r1,0xf808
- mtspr SPRN_DVLIM,r1
- lis r1,0x0808
- ori r1,r1,0x0808
- mtspr SPRN_DNV0,r1
- mtspr SPRN_DNV1,r1
- mtspr SPRN_DNV2,r1
- mtspr SPRN_DNV3,r1
- mtspr SPRN_DTV0,r1
- mtspr SPRN_DTV1,r1
- mtspr SPRN_DTV2,r1
- mtspr SPRN_DTV3,r1
- msync
- isync
-#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
-
- /* 440EP & 440GR are only 440er PPC's without internal SRAM */
-#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
- /* not all PPC's have internal SRAM usable as L2-cache */
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460SX)
- mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
- lis r1, 0x0000
- ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
- mtdcr L2_CACHE_CFG,r1
-#endif
-
- lis r2,0x7fff
- ori r2,r2,0xffff
- mfdcr r1,ISRAM0_DPC
- and r1,r1,r2 /* Disable parity check */
- mtdcr ISRAM0_DPC,r1
- mfdcr r1,ISRAM0_PMEG
- and r1,r1,r2 /* Disable pwr mgmt */
- mtdcr ISRAM0_PMEG,r1
-
- lis r1,0x8000 /* BAS = 8000_0000 */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
- ori r1,r1,0x0980 /* first 64k */
- mtdcr ISRAM0_SB0CR,r1
- lis r1,0x8001
- ori r1,r1,0x0980 /* second 64k */
- mtdcr ISRAM0_SB1CR,r1
- lis r1, 0x8002
- ori r1,r1, 0x0980 /* third 64k */
- mtdcr ISRAM0_SB2CR,r1
- lis r1, 0x8003
- ori r1,r1, 0x0980 /* fourth 64k */
- mtdcr ISRAM0_SB3CR,r1
-#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
- defined(CONFIG_460GT)
- lis r1,0x0000 /* BAS = X_0000_0000 */
- ori r1,r1,0x0984 /* first 64k */
- mtdcr ISRAM0_SB0CR,r1
- lis r1,0x0001
- ori r1,r1,0x0984 /* second 64k */
- mtdcr ISRAM0_SB1CR,r1
- lis r1, 0x0002
- ori r1,r1, 0x0984 /* third 64k */
- mtdcr ISRAM0_SB2CR,r1
- lis r1, 0x0003
- ori r1,r1, 0x0984 /* fourth 64k */
- mtdcr ISRAM0_SB3CR,r1
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- lis r2,0x7fff
- ori r2,r2,0xffff
- mfdcr r1,ISRAM1_DPC
- and r1,r1,r2 /* Disable parity check */
- mtdcr ISRAM1_DPC,r1
- mfdcr r1,ISRAM1_PMEG
- and r1,r1,r2 /* Disable pwr mgmt */
- mtdcr ISRAM1_PMEG,r1
-
- lis r1,0x0004 /* BAS = 4_0004_0000 */
- ori r1,r1,ISRAM1_SIZE /* ocm size */
- mtdcr ISRAM1_SB0CR,r1
-#endif
-#elif defined(CONFIG_460SX)
- lis r1,0x0000 /* BAS = 0000_0000 */
- ori r1,r1,0x0B84 /* first 128k */
- mtdcr ISRAM0_SB0CR,r1
- lis r1,0x0001
- ori r1,r1,0x0B84 /* second 128k */
- mtdcr ISRAM0_SB1CR,r1
- lis r1, 0x0002
- ori r1,r1, 0x0B84 /* third 128k */
- mtdcr ISRAM0_SB2CR,r1
- lis r1, 0x0003
- ori r1,r1, 0x0B84 /* fourth 128k */
- mtdcr ISRAM0_SB3CR,r1
-#elif defined(CONFIG_440GP)
- ori r1,r1,0x0380 /* 8k rw */
- mtdcr ISRAM0_SB0CR,r1
- mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
-#endif
-#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
-
- /*----------------------------------------------------------------*/
- /* Setup the stack in internal SRAM */
- /*----------------------------------------------------------------*/
- lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
- ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
- /*
- * Reserve space for globals and store address for initialization
- * with board_init_f_init_reserve() in r14
- */
- mr r3, r1
- bl board_init_f_alloc_reserve
- mr r1, r3
- mr r14, r3
- li r0,0
- stwu r0,-4(r1)
- stwu r0,-4(r1) /* Terminate call chain */
-
- stwu r1,-8(r1) /* Save back chain and move SP */
- lis r0,RESET_VECTOR@h /* Address of reset vector */
- ori r0,r0, RESET_VECTOR@l
- stwu r1,-8(r1) /* Save back chain and move SP */
- stw r0,+12(r1) /* Save return addr (underflow vect) */
-
-#ifndef CONFIG_SPL_BUILD
- GET_GOT
-#endif
-
- bl cpu_init_f /* run low-level CPU init code (from Flash) */
- /* address for globals was stored in r14 */
- mr r3, r14
- bl board_init_f_init_reserve
- li r3, 0
- bl board_init_f
- /* NOTREACHED - board_init_f() does not return */
-
-#endif /* CONFIG_440 */
-
-/*****************************************************************************/
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_405EX) || defined(CONFIG_405)
- /*----------------------------------------------------------------------- */
- /* Clear and set up some registers. */
- /*----------------------------------------------------------------------- */
- addi r4,r0,0x0000
-#if !defined(CONFIG_405EX)
- mtspr SPRN_SGR,r4
-#else
- /*
- * On 405EX, completely clearing the SGR leads to PPC hangup
- * upon PCIe configuration access. The PCIe memory regions
- * need to be guarded!
- */
- lis r3,0x0000
- ori r3,r3,0x7FFC
- mtspr SPRN_SGR,r3
-#endif
- mtspr SPRN_DCWR,r4
- mtesr r4 /* clear Exception Syndrome Reg */
- mttcr r4 /* clear Timer Control Reg */
- mtxer r4 /* clear Fixed-Point Exception Reg */
- mtevpr r4 /* clear Exception Vector Prefix Reg */
- addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
- /* dbsr is cleared by setting bits to 1) */
- mtdbsr r4 /* clear/reset the dbsr */
-
- /* Invalidate the i- and d-caches. */
- bl invalidate_icache
- bl invalidate_dcache
-
- /* Set-up icache cacheability. */
- lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
- ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
- mticcr r4
- isync
-
- /* Set-up dcache cacheability. */
- lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
- ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
- mtdccr r4
-
-#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
- && !defined (CONFIG_XILINX_405)
- /*----------------------------------------------------------------------- */
- /* Tune the speed and size for flash CS0 */
- /*----------------------------------------------------------------------- */
- bl ext_bus_cntlr_init
-#endif
-
-#if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
- /*
- * For boards that don't have OCM and can't use the data cache
- * for their primordial stack, setup stack here directly after the
- * SDRAM is initialized in ext_bus_cntlr_init.
- */
- lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
- ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
- /*
- * Reserve space for globals and store address for initialization
- * with board_init_f_init_reserve() in r14
- */
- mr r3, r1
- bl board_init_f_alloc_reserve
- mr r1, r3
- mr r14, r3
-
- li r0, 0 /* Make room for stack frame header and */
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
- /*
- * Set up a dummy frame to store reset vector as return address.
- * this causes stack underflow to reset board.
- */
- stwu r1, -8(r1) /* Save back chain and move SP */
- lis r0, RESET_VECTOR@h /* Address of reset vector */
- ori r0, r0, RESET_VECTOR@l
- stwu r1, -8(r1) /* Save back chain and move SP */
- stw r0, +12(r1) /* Save return addr (underflow vect) */
-#endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
-
-#if defined(CONFIG_405EP)
- /*----------------------------------------------------------------------- */
- /* DMA Status, clear to come up clean */
- /*----------------------------------------------------------------------- */
- addis r3,r0, 0xFFFF /* Clear all existing DMA status */
- ori r3,r3, 0xFFFF
- mtdcr DMASR, r3
-
- bl ppc405ep_init /* do ppc405ep specific init */
-#endif /* CONFIG_405EP */
-
-#if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
-#if defined(CONFIG_405EZ)
- /********************************************************************
- * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
- *******************************************************************/
- /*
- * We can map the OCM on the PLB3, so map it at
- * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
- */
- lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
- ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
- ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
- mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
- ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
- mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
- isync
-
- lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
- ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
- ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
- mtdcr OCM0_DSRC1, r3 /* Set Data Side */
- mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
- ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
- mtdcr OCM0_DSRC2, r3 /* Set Data Side */
- mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
- addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
- mtdcr OCM0_DISDPC,r3
-
- isync
-#else /* CONFIG_405EZ */
- /********************************************************************
- * Setup OCM - On Chip Memory
- *******************************************************************/
- /* Setup OCM */
- lis r0, 0x7FFF
- ori r0, r0, 0xFFFF
- mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
- mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
- and r3, r3, r0 /* disable data-side IRAM */
- and r4, r4, r0 /* disable data-side IRAM */
- mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
- mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
- isync
-
- lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
- ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
- mtdcr OCM0_DSARC, r3
- addis r4, 0, 0xC000 /* OCM data area enabled */
- mtdcr OCM0_DSCNTL, r4
- isync
-#endif /* CONFIG_405EZ */
-#endif
-
- /*----------------------------------------------------------------------- */
- /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
- /*----------------------------------------------------------------------- */
-#ifdef CONFIG_SYS_INIT_DCACHE_CS
- li r4, PBxAP
- mtdcr EBC0_CFGADDR, r4
- lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
- ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
- mtdcr EBC0_CFGDATA, r4
-
- addi r4, 0, PBxCR
- mtdcr EBC0_CFGADDR, r4
- lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
- ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
- mtdcr EBC0_CFGDATA, r4
-
- /*
- * Enable the data cache for the 128MB storage access control region
- * at CONFIG_SYS_INIT_RAM_ADDR.
- */
- mfdccr r4
- oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
- ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
- mtdccr r4
-
- /*
- * Preallocate data cache lines to be used to avoid a subsequent
- * cache miss and an ensuing machine check exception when exceptions
- * are enabled.
- */
- li r0, 0
-
- lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
- ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
-
- lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
- ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
-
- /*
- * Convert the size, in bytes, to the number of cache lines/blocks
- * to preallocate.
- */
- clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
- srwi r5, r4, L1_CACHE_SHIFT
- beq ..load_counter
- addi r5, r5, 0x0001
-..load_counter:
- mtctr r5
-
- /* Preallocate the computed number of cache blocks. */
-..alloc_dcache_block:
- dcba r0, r3
- addi r3, r3, L1_CACHE_BYTES
- bdnz ..alloc_dcache_block
- sync
-
- /*
- * Load the initial stack pointer and data area and convert the size,
- * in bytes, to the number of words to initialize to a known value.
- */
- lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
- ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
- /*
- * Reserve space for globals and store address for initialization
- * with board_init_f_init_reserve() in r14
- */
- mr r3, r1
- bl board_init_f_alloc_reserve
- mr r1, r3
- mr r14, r3
-
- lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
- ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
- mtctr r4
-
- lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
- ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
-
- lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
- ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
-
-..stackloop:
- stwu r4, -4(r2)
- bdnz ..stackloop
-
- /*
- * Make room for stack frame header and clear final stack frame so
- * that stack backtraces terminate cleanly.
- */
- li r0, 0
- stwu r0, -4(r1)
- stwu r0, -4(r1)
-
- /*
- * Set up a dummy frame to store reset vector as return address.
- * this causes stack underflow to reset board.
- */
- stwu r1, -8(r1) /* Save back chain and move SP */
- addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
- ori r0, r0, RESET_VECTOR@l
- stwu r1, -8(r1) /* Save back chain and move SP */
- stw r0, +12(r1) /* Save return addr (underflow vect) */
-
-#elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
- (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
- /*
- * Stack in OCM.
- */
- lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
- ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
- /*
- * Reserve space for globals and store address for initialization
- * with board_init_f_init_reserve() in r14
- */
- mr r3, r1
- bl board_init_f_alloc_reserve
- mr r1, r3
- mr r14, r3
-
- /* Set up a zeroized stack frame so that backtrace works right */
- li r0, 0
- stwu r0, -4(r1)
- stwu r0, -4(r1)
-
- /*
- * Set up a dummy frame to store reset vector as return address.
- * this causes stack underflow to reset board.
- */
- stwu r1, -8(r1) /* Save back chain and move SP */
- lis r0, RESET_VECTOR@h /* Address of reset vector */
- ori r0, r0, RESET_VECTOR@l
- stwu r1, -8(r1) /* Save back chain and move SP */
- stw r0, +12(r1) /* Save return addr (underflow vect) */
-#endif /* CONFIG_SYS_INIT_DCACHE_CS */
-
- GET_GOT /* initialize GOT access */
-
- bl cpu_init_f /* run low-level CPU init code (from Flash) */
- /* address for globals was stored in r14 */
- mr r3, r14
- bl board_init_f_init_reserve
- li r3, 0
- bl board_init_f /* run first part of init code (from Flash) */
- /* NOTREACHED - board_init_f() does not return */
-
-#endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
- /*----------------------------------------------------------------------- */
-
-
-#if !defined(CONFIG_SPL_BUILD)
-/*
- * This code finishes saving the registers to the exception frame
- * and jumps to the appropriate handler for the exception.
- * Register r21 is pointer into trap frame, r1 has new stack pointer.
- */
- .globl transfer_to_handler
-transfer_to_handler:
- stw r22,_NIP(r21)
- lis r22,MSR_POW@h
- andc r23,r23,r22
- stw r23,_MSR(r21)
- SAVE_GPR(7, r21)
- SAVE_4GPRS(8, r21)
- SAVE_8GPRS(12, r21)
- SAVE_8GPRS(24, r21)
- mflr r23
- andi. r24,r23,0x3f00 /* get vector offset */
- stw r24,TRAP(r21)
- li r22,0
- stw r22,RESULT(r21)
- mtspr SPRG2,r22 /* r1 is now kernel sp */
- lwz r24,0(r23) /* virtual address of handler */
- lwz r23,4(r23) /* where to go when done */
- mtspr SRR0,r24
- mtspr SRR1,r20
- mtlr r23
- SYNC
- rfi /* jump to handler, enable MMU */
-
-int_return:
- mfmsr r28 /* Disable interrupts */
- li r4,0
- ori r4,r4,MSR_EE
- andc r28,r28,r4
- SYNC /* Some chip revs need this... */
- mtmsr r28
- SYNC
- lwz r2,_CTR(r1)
- lwz r0,_LINK(r1)
- mtctr r2
- mtlr r0
- lwz r2,_XER(r1)
- lwz r0,_CCR(r1)
- mtspr XER,r2
- mtcrf 0xFF,r0
- REST_10GPRS(3, r1)
- REST_10GPRS(13, r1)
- REST_8GPRS(23, r1)
- REST_GPR(31, r1)
- lwz r2,_NIP(r1) /* Restore environment */
- lwz r0,_MSR(r1)
- mtspr SRR0,r2
- mtspr SRR1,r0
- lwz r0,GPR0(r1)
- lwz r2,GPR2(r1)
- lwz r1,GPR1(r1)
- SYNC
- rfi
-
-crit_return:
- mfmsr r28 /* Disable interrupts */
- li r4,0
- ori r4,r4,MSR_EE
- andc r28,r28,r4
- SYNC /* Some chip revs need this... */
- mtmsr r28
- SYNC
- lwz r2,_CTR(r1)
- lwz r0,_LINK(r1)
- mtctr r2
- mtlr r0
- lwz r2,_XER(r1)
- lwz r0,_CCR(r1)
- mtspr XER,r2
- mtcrf 0xFF,r0
- REST_10GPRS(3, r1)
- REST_10GPRS(13, r1)
- REST_8GPRS(23, r1)
- REST_GPR(31, r1)
- lwz r2,_NIP(r1) /* Restore environment */
- lwz r0,_MSR(r1)
- mtspr SPRN_CSRR0,r2
- mtspr SPRN_CSRR1,r0
- lwz r0,GPR0(r1)
- lwz r2,GPR2(r1)
- lwz r1,GPR1(r1)
- SYNC
- rfci
-
-#ifdef CONFIG_440
-mck_return:
- mfmsr r28 /* Disable interrupts */
- li r4,0
- ori r4,r4,MSR_EE
- andc r28,r28,r4
- SYNC /* Some chip revs need this... */
- mtmsr r28
- SYNC
- lwz r2,_CTR(r1)
- lwz r0,_LINK(r1)
- mtctr r2
- mtlr r0
- lwz r2,_XER(r1)
- lwz r0,_CCR(r1)
- mtspr XER,r2
- mtcrf 0xFF,r0
- REST_10GPRS(3, r1)
- REST_10GPRS(13, r1)
- REST_8GPRS(23, r1)
- REST_GPR(31, r1)
- lwz r2,_NIP(r1) /* Restore environment */
- lwz r0,_MSR(r1)
- mtspr SPRN_MCSRR0,r2
- mtspr SPRN_MCSRR1,r0
- lwz r0,GPR0(r1)
- lwz r2,GPR2(r1)
- lwz r1,GPR1(r1)
- SYNC
- rfmci
-#endif /* CONFIG_440 */
-
-
- .globl get_pvr
-get_pvr:
- mfspr r3, PVR
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: out16 */
-/* Description: Output 16 bits */
-/*------------------------------------------------------------------------------- */
- .globl out16
-out16:
- sth r4,0x0000(r3)
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: out16r */
-/* Description: Byte reverse and output 16 bits */
-/*------------------------------------------------------------------------------- */
- .globl out16r
-out16r:
- sthbrx r4,r0,r3
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: out32r */
-/* Description: Byte reverse and output 32 bits */
-/*------------------------------------------------------------------------------- */
- .globl out32r
-out32r:
- stwbrx r4,r0,r3
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: in16 */
-/* Description: Input 16 bits */
-/*------------------------------------------------------------------------------- */
- .globl in16
-in16:
- lhz r3,0x0000(r3)
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: in16r */
-/* Description: Input 16 bits and byte reverse */
-/*------------------------------------------------------------------------------- */
- .globl in16r
-in16r:
- lhbrx r3,r0,r3
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: in32r */
-/* Description: Input 32 bits and byte reverse */
-/*------------------------------------------------------------------------------- */
- .globl in32r
-in32r:
- lwbrx r3,r0,r3
- blr
-
-#if !defined(CONFIG_SPL_BUILD)
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r3 = Relocated stack pointer
- * r4 = Relocated global data pointer
- * r5 = Relocated text pointer
- */
- .globl relocate_code
-relocate_code:
-#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
- /*
- * We need to flush the initial global data (gd_t) and bd_info
- * before the dcache will be invalidated.
- */
-
- /* Save registers */
- mr r9, r3
- mr r10, r4
- mr r11, r5
-
- /*
- * Flush complete dcache, this is faster than flushing the
- * ranges for global_data and bd_info instead.
- */
- bl flush_dcache
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
- /*
- * Undo the earlier data cache set-up for the primordial stack and
- * data area. First, invalidate the data cache and then disable data
- * cacheability for that area. Finally, restore the EBC values, if
- * any.
- */
-
- /* Invalidate the primordial stack and data area in cache */
- lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
- ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
-
- lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
- ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
- add r4, r4, r3
-
- bl invalidate_dcache_range
-
- /* Disable cacheability for the region */
- mfdccr r3
- lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
- ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
- and r3, r3, r4
- mtdccr r3
-
- /* Restore the EBC parameters */
- li r3, PBxAP
- mtdcr EBC0_CFGADDR, r3
- lis r3, PBxAP_VAL@h
- ori r3, r3, PBxAP_VAL@l
- mtdcr EBC0_CFGDATA, r3
-
- li r3, PBxCR
- mtdcr EBC0_CFGADDR, r3
- lis r3, PBxCR_VAL@h
- ori r3, r3, PBxCR_VAL@l
- mtdcr EBC0_CFGDATA, r3
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
- /* Restore registers */
- mr r3, r9
- mr r4, r10
- mr r5, r11
-#endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /*
- * Unlock the previously locked d-cache
- */
- msync
- isync
- /* set TFLOOR/NFLOOR to 0 again */
- lis r6,0x0001
- ori r6,r6,0xf800
- mtspr SPRN_DVLIM,r6
- lis r6,0x0000
- ori r6,r6,0x0000
- mtspr SPRN_DNV0,r6
- mtspr SPRN_DNV1,r6
- mtspr SPRN_DNV2,r6
- mtspr SPRN_DNV3,r6
- mtspr SPRN_DTV0,r6
- mtspr SPRN_DTV1,r6
- mtspr SPRN_DTV2,r6
- mtspr SPRN_DTV3,r6
- msync
- isync
-
- /* Invalidate data cache, now no longer our stack */
- dccci 0,0
- sync
- isync
-#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
-
- /*
- * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
- * to speed up the boot process. Now this cache needs to be disabled.
- */
-#if defined(CONFIG_440)
- /* Clear all potential pending exceptions */
- mfspr r1,SPRN_MCSR
- mtspr SPRN_MCSR,r1
- addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
- tlbre r0,r1,0x0002 /* Read contents */
- ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
- tlbwe r0,r1,0x0002 /* Save it out */
- sync
- isync
-#endif /* defined(CONFIG_440) */
- mr r1, r3 /* Set new stack pointer */
- mr r9, r4 /* Save copy of Init Data pointer */
- mr r10, r5 /* Save copy of Destination Address */
-
- GET_GOT
- mr r3, r5 /* Destination Address */
- lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
- lwz r5, GOT(__init_end)
- sub r5, r5, r4
- li r6, L1_CACHE_BYTES /* Cache Line Size */
-
- /*
- * Fix GOT pointer:
- *
- * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
- *
- * Offset:
- */
- sub r15, r10, r4
-
- /* First our own GOT */
- add r12, r12, r15
- /* then the one used by the C code */
- add r30, r30, r15
-
- /*
- * Now relocate code
- */
-
- cmplw cr1,r3,r4
- addi r0,r5,3
- srwi. r0,r0,2
- beq cr1,4f /* In place copy is not necessary */
- beq 7f /* Protect against 0 count */
- mtctr r0
- bge cr1,2f
-
- la r8,-4(r4)
- la r7,-4(r3)
-1: lwzu r0,4(r8)
- stwu r0,4(r7)
- bdnz 1b
- b 4f
-
-2: slwi r0,r0,2
- add r8,r4,r0
- add r7,r3,r0
-3: lwzu r0,-4(r8)
- stwu r0,-4(r7)
- bdnz 3b
-
-/*
- * Now flush the cache: note that we must start from a cache aligned
- * address. Otherwise we might miss one cache line.
- */
-4: cmpwi r6,0
- add r5,r3,r5
- beq 7f /* Always flush prefetch queue in any case */
- subi r0,r6,1
- andc r3,r3,r0
- mr r4,r3
-5: dcbst 0,r4
- add r4,r4,r6
- cmplw r4,r5
- blt 5b
- sync /* Wait for all dcbst to complete on bus */
- mr r4,r3
-6: icbi 0,r4
- add r4,r4,r6
- cmplw r4,r5
- blt 6b
-7: sync /* Wait for all icbi to complete on bus */
- isync
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-
- addi r0, r10, in_ram - _start + _START_OFFSET
- mtlr r0
- blr /* NEVER RETURNS! */
-
-in_ram:
-
- /*
- * Relocation Function, r12 point to got2+0x8000
- *
- * Adjust got2 pointers, no need to check for 0, this code
- * already puts a few entries in the table.
- */
- li r0,__got2_entries@sectoff@l
- la r3,GOT(_GOT2_TABLE_)
- lwz r11,GOT(_GOT2_TABLE_)
- mtctr r0
- sub r11,r3,r11
- addi r3,r3,-4
-1: lwzu r0,4(r3)
- cmpwi r0,0
- beq- 2f
- add r0,r0,r11
- stw r0,0(r3)
-2: bdnz 1b
-
- /*
- * Now adjust the fixups and the pointers to the fixups
- * in case we need to move ourselves again.
- */
- li r0,__fixup_entries@sectoff@l
- lwz r3,GOT(_FIXUP_TABLE_)
- cmpwi r0,0
- mtctr r0
- addi r3,r3,-4
- beq 4f
-3: lwzu r4,4(r3)
- lwzux r0,r4,r11
- cmpwi r0,0
- add r0,r0,r11
- stw r4,0(r3)
- beq- 5f
- stw r0,0(r4)
-5: bdnz 3b
-4:
-clear_bss:
- /*
- * Now clear BSS segment
- */
- lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end)
-
- cmplw 0, r3, r4
- beq 7f
-
- li r0, 0
-
- andi. r5, r4, 3
- beq 6f
- sub r4, r4, r5
- mtctr r5
- mr r5, r4
-5: stb r0, 0(r5)
- addi r5, r5, 1
- bdnz 5b
-6:
- stw r0, 0(r3)
- addi r3, r3, 4
- cmplw 0, r3, r4
- bne 6b
-
-7:
- mr r3, r9 /* Init Data pointer */
- mr r4, r10 /* Destination Address */
- bl board_init_r
-
- /*
- * Copy exception vector code to low memory
- *
- * r3: dest_addr
- * r7: source address, r8: end address, r9: target address
- */
- .globl trap_init
-trap_init:
- mflr r4 /* save link register */
- GET_GOT
- lwz r7, GOT(_start_of_vectors)
- lwz r8, GOT(_end_of_vectors)
-
- li r9, 0x100 /* reset vector always at 0x100 */
-
- cmplw 0, r7, r8
- bgelr /* return if r7>=r8 - just in case */
-1:
- lwz r0, 0(r7)
- stw r0, 0(r9)
- addi r7, r7, 4
- addi r9, r9, 4
- cmplw 0, r7, r8
- bne 1b
-
- /*
- * relocate `hdlr' and `int_return' entries
- */
- li r7, .L_MachineCheck - _start + _START_OFFSET
- li r8, Alignment - _start + _START_OFFSET
-2:
- bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
- blt 2b
-
- li r7, .L_Alignment - _start + _START_OFFSET
- bl trap_reloc
-
- li r7, .L_ProgramCheck - _start + _START_OFFSET
- bl trap_reloc
-
-#ifdef CONFIG_440
- li r7, .L_FPUnavailable - _start + _START_OFFSET
- bl trap_reloc
-
- li r7, .L_Decrementer - _start + _START_OFFSET
- bl trap_reloc
-
- li r7, .L_APU - _start + _START_OFFSET
- bl trap_reloc
-
- li r7, .L_InstructionTLBError - _start + _START_OFFSET
- bl trap_reloc
-
- li r7, .L_DataTLBError - _start + _START_OFFSET
- bl trap_reloc
-#else /* CONFIG_440 */
- li r7, .L_PIT - _start + _START_OFFSET
- bl trap_reloc
-
- li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
- bl trap_reloc
-
- li r7, .L_DataTLBMiss - _start + _START_OFFSET
- bl trap_reloc
-#endif /* CONFIG_440 */
-
- li r7, .L_DebugBreakpoint - _start + _START_OFFSET
- bl trap_reloc
-
-#if !defined(CONFIG_440)
- addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
- oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
- mtmsr r7 /* change MSR */
-#else
- bl __440_msr_set
- b __440_msr_continue
-
-__440_msr_set:
- addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
- oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
- mtspr SPRN_SRR1,r7
- mflr r7
- mtspr SPRN_SRR0,r7
- rfi
-__440_msr_continue:
-#endif
-
- mtlr r4 /* restore link register */
- blr
-#endif /* CONFIG_SPL_BUILD */
-
-#if defined(CONFIG_440)
-/*----------------------------------------------------------------------------+
-| dcbz_area.
-+----------------------------------------------------------------------------*/
- function_prolog(dcbz_area)
- rlwinm. r5,r4,0,27,31
- rlwinm r5,r4,27,5,31
- beq ..d_ra2
- addi r5,r5,0x0001
-..d_ra2:mtctr r5
-..d_ag2:dcbz r0,r3
- addi r3,r3,32
- bdnz ..d_ag2
- sync
- blr
- function_epilog(dcbz_area)
-#endif /* CONFIG_440 */
-#endif /* CONFIG_SPL_BUILD */
-
-/*------------------------------------------------------------------------------- */
-/* Function: in8 */
-/* Description: Input 8 bits */
-/*------------------------------------------------------------------------------- */
- .globl in8
-in8:
- lbz r3,0x0000(r3)
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: out8 */
-/* Description: Output 8 bits */
-/*------------------------------------------------------------------------------- */
- .globl out8
-out8:
- stb r4,0x0000(r3)
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: out32 */
-/* Description: Output 32 bits */
-/*------------------------------------------------------------------------------- */
- .globl out32
-out32:
- stw r4,0x0000(r3)
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: in32 */
-/* Description: Input 32 bits */
-/*------------------------------------------------------------------------------- */
- .globl in32
-in32:
- lwz 3,0x0000(3)
- blr
-
-/**************************************************************************/
-/* PPC405EP specific stuff */
-/**************************************************************************/
-#ifdef CONFIG_405EP
-ppc405ep_init:
-
-#ifdef CONFIG_BUBINGA
- /*
- * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
- * function) to support FPGA and NVRAM accesses below.
- */
-
- lis r3,GPIO0_OSRH@h /* config GPIO output select */
- ori r3,r3,GPIO0_OSRH@l
- lis r4,CONFIG_SYS_GPIO0_OSRH@h
- ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
- stw r4,0(r3)
- lis r3,GPIO0_OSRL@h
- ori r3,r3,GPIO0_OSRL@l
- lis r4,CONFIG_SYS_GPIO0_OSRL@h
- ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
- stw r4,0(r3)
-
- lis r3,GPIO0_ISR1H@h /* config GPIO input select */
- ori r3,r3,GPIO0_ISR1H@l
- lis r4,CONFIG_SYS_GPIO0_ISR1H@h
- ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
- stw r4,0(r3)
- lis r3,GPIO0_ISR1L@h
- ori r3,r3,GPIO0_ISR1L@l
- lis r4,CONFIG_SYS_GPIO0_ISR1L@h
- ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
- stw r4,0(r3)
-
- lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
- ori r3,r3,GPIO0_TSRH@l
- lis r4,CONFIG_SYS_GPIO0_TSRH@h
- ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
- stw r4,0(r3)
- lis r3,GPIO0_TSRL@h
- ori r3,r3,GPIO0_TSRL@l
- lis r4,CONFIG_SYS_GPIO0_TSRL@h
- ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
- stw r4,0(r3)
-
- lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
- ori r3,r3,GPIO0_TCR@l
- lis r4,CONFIG_SYS_GPIO0_TCR@h
- ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
- stw r4,0(r3)
-
- li r3,PB1AP /* program EBC bank 1 for RTC access */
- mtdcr EBC0_CFGADDR,r3
- lis r3,CONFIG_SYS_EBC_PB1AP@h
- ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
- mtdcr EBC0_CFGDATA,r3
- li r3,PB1CR
- mtdcr EBC0_CFGADDR,r3
- lis r3,CONFIG_SYS_EBC_PB1CR@h
- ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
- mtdcr EBC0_CFGDATA,r3
-
- li r3,PB1AP /* program EBC bank 1 for RTC access */
- mtdcr EBC0_CFGADDR,r3
- lis r3,CONFIG_SYS_EBC_PB1AP@h
- ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
- mtdcr EBC0_CFGDATA,r3
- li r3,PB1CR
- mtdcr EBC0_CFGADDR,r3
- lis r3,CONFIG_SYS_EBC_PB1CR@h
- ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
- mtdcr EBC0_CFGDATA,r3
-
- li r3,PB4AP /* program EBC bank 4 for FPGA access */
- mtdcr EBC0_CFGADDR,r3
- lis r3,CONFIG_SYS_EBC_PB4AP@h
- ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
- mtdcr EBC0_CFGDATA,r3
- li r3,PB4CR
- mtdcr EBC0_CFGADDR,r3
- lis r3,CONFIG_SYS_EBC_PB4CR@h
- ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
- mtdcr EBC0_CFGDATA,r3
-#endif
-
- /*
- !-----------------------------------------------------------------------
- ! Check to see if chip is in bypass mode.
- ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
- ! CPU reset Otherwise, skip this step and keep going.
- ! Note: Running BIOS in bypass mode is not supported since PLB speed
- ! will not be fast enough for the SDRAM (min 66MHz)
- !-----------------------------------------------------------------------
- */
- mfdcr r5, CPC0_PLLMR1
- rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
- cmpi cr0,0,r4,0x1
-
- beq pll_done /* if SSCS =b'1' then PLL has */
- /* already been set */
- /* and CPU has been reset */
- /* so skip to next section */
-
-#ifdef CONFIG_BUBINGA
- /*
- !-----------------------------------------------------------------------
- ! Read NVRAM to get value to write in PLLMR.
- ! If value has not been correctly saved, write default value
- ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
- ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
- !
- ! WARNING: This code assumes the first three words in the nvram_t
- ! structure in openbios.h. Changing the beginning of
- ! the structure will break this code.
- !
- !-----------------------------------------------------------------------
- */
- addis r3,0,NVRAM_BASE@h
- addi r3,r3,NVRAM_BASE@l
-
- lwz r4, 0(r3)
- addis r5,0,NVRVFY1@h
- addi r5,r5,NVRVFY1@l
- cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
- bne ..no_pllset
- addi r3,r3,4
- lwz r4, 0(r3)
- addis r5,0,NVRVFY2@h
- addi r5,r5,NVRVFY2@l
- cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
- bne ..no_pllset
- addi r3,r3,8 /* Skip over conf_size */
- lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
- lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
- rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
- cmpi cr0,0,r5,1 /* See if PLL is locked */
- beq pll_write
-..no_pllset:
-#endif /* CONFIG_BUBINGA */
-
- addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
- ori r3,r3,PLLMR0_DEFAULT@l /* */
- addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
- ori r4,r4,PLLMR1_DEFAULT@l /* */
-
-1:
- b pll_write /* Write the CPC0_PLLMR with new value */
-
-pll_done:
- /*
- !-----------------------------------------------------------------------
- ! Clear Soft Reset Register
- ! This is needed to enable PCI if not booting from serial EPROM
- !-----------------------------------------------------------------------
- */
- addi r3, 0, 0x0
- mtdcr CPC0_SRR, r3
-
- addis r3,0,0x0010
- mtctr r3
-pci_wait:
- bdnz pci_wait
-
- blr /* return to main code */
-
-/*
-!-----------------------------------------------------------------------------
-! Function: pll_write
-! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
-! That is:
-! 1. Pll is first disabled (de-activated by putting in bypass mode)
-! 2. PLL is reset
-! 3. Clock dividers are set while PLL is held in reset and bypassed
-! 4. PLL Reset is cleared
-! 5. Wait 100us for PLL to lock
-! 6. A core reset is performed
-! Input: r3 = Value to write to CPC0_PLLMR0
-! Input: r4 = Value to write to CPC0_PLLMR1
-! Output r3 = none
-!-----------------------------------------------------------------------------
-*/
- .globl pll_write
-pll_write:
- mfdcr r5, CPC0_UCR
- andis. r5,r5,0xFFFF
- ori r5,r5,0x0101 /* Stop the UART clocks */
- mtdcr CPC0_UCR,r5 /* Before changing PLL */
-
- mfdcr r5, CPC0_PLLMR1
- rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
- mtdcr CPC0_PLLMR1,r5
- oris r5,r5,0x4000 /* Set PLL Reset */
- mtdcr CPC0_PLLMR1,r5
-
- mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
- rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
- oris r5,r5,0x4000 /* Set PLL Reset */
- mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
- rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
- mtdcr CPC0_PLLMR1,r5
-
- /*
- ! Wait min of 100us for PLL to lock.
- ! See CMOS 27E databook for more info.
- ! At 200MHz, that means waiting 20,000 instructions
- */
- addi r3,0,20000 /* 2000 = 0x4e20 */
- mtctr r3
-pll_wait:
- bdnz pll_wait
-
- oris r5,r5,0x8000 /* Enable PLL */
- mtdcr CPC0_PLLMR1,r5 /* Engage */
-
- /*
- * Reset CPU to guarantee timings are OK
- * Not sure if this is needed...
- */
- addis r3,0,0x1000
- mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
- /* execution will continue from the poweron */
- /* vector of 0xfffffffc */
-#endif /* CONFIG_405EP */
-
-#if defined(CONFIG_440)
-/*----------------------------------------------------------------------------+
-| mttlb3.
-+----------------------------------------------------------------------------*/
- function_prolog(mttlb3)
- TLBWE(4,3,2)
- blr
- function_epilog(mttlb3)
-
-/*----------------------------------------------------------------------------+
-| mftlb3.
-+----------------------------------------------------------------------------*/
- function_prolog(mftlb3)
- TLBRE(3,3,2)
- blr
- function_epilog(mftlb3)
-
-/*----------------------------------------------------------------------------+
-| mttlb2.
-+----------------------------------------------------------------------------*/
- function_prolog(mttlb2)
- TLBWE(4,3,1)
- blr
- function_epilog(mttlb2)
-
-/*----------------------------------------------------------------------------+
-| mftlb2.
-+----------------------------------------------------------------------------*/
- function_prolog(mftlb2)
- TLBRE(3,3,1)
- blr
- function_epilog(mftlb2)
-
-/*----------------------------------------------------------------------------+
-| mttlb1.
-+----------------------------------------------------------------------------*/
- function_prolog(mttlb1)
- TLBWE(4,3,0)
- blr
- function_epilog(mttlb1)
-
-/*----------------------------------------------------------------------------+
-| mftlb1.
-+----------------------------------------------------------------------------*/
- function_prolog(mftlb1)
- TLBRE(3,3,0)
- blr
- function_epilog(mftlb1)
-#endif /* CONFIG_440 */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_440)
-
-#include <asm/ppc440.h>
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-
-typedef struct region {
- u64 base;
- u32 size;
- u32 tlb_word2_i_value;
-} region_t;
-
-void remove_tlb(u32 vaddr, u32 size)
-{
- int i;
- u32 tlb_word0_value;
- u32 tlb_vaddr;
- u32 tlb_size = 0;
-
- for (i=0; i<PPC4XX_TLB_SIZE; i++) {
- tlb_word0_value = mftlb1(i);
- tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
- if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
- (tlb_vaddr >= vaddr)) {
- /*
- * TLB is enabled and start address is lower or equal
- * than the area we are looking for. Now we only have
- * to check the size/end address for a match.
- */
- switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
- case TLB_WORD0_SIZE_1KB:
- tlb_size = 1 << 10;
- break;
- case TLB_WORD0_SIZE_4KB:
- tlb_size = 4 << 10;
- break;
- case TLB_WORD0_SIZE_16KB:
- tlb_size = 16 << 10;
- break;
- case TLB_WORD0_SIZE_64KB:
- tlb_size = 64 << 10;
- break;
- case TLB_WORD0_SIZE_256KB:
- tlb_size = 256 << 10;
- break;
- case TLB_WORD0_SIZE_1MB:
- tlb_size = 1 << 20;
- break;
- case TLB_WORD0_SIZE_16MB:
- tlb_size = 16 << 20;
- break;
- case TLB_WORD0_SIZE_256MB:
- tlb_size = 256 << 20;
- break;
- }
-
- /*
- * Now check the end-address if it's in the range
- */
- if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1))
- /*
- * Found a TLB in the range.
- * Disable it by writing 0 to tlb0 word.
- */
- mttlb1(i, 0);
- }
- }
-
- /* Execute an ISYNC instruction so that the new TLB entry takes effect */
- asm("isync");
-}
-
-/*
- * Change the I attribute (cache inhibited) of a TLB or multiple TLB's.
- * This function is used to either turn cache on or off in a specific
- * memory area.
- */
-void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
-{
- int i;
- u32 tlb_word0_value;
- u32 tlb_word2_value;
- u32 tlb_vaddr;
- u32 tlb_size = 0;
-
- for (i=0; i<PPC4XX_TLB_SIZE; i++) {
- tlb_word0_value = mftlb1(i);
- tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
- if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
- (tlb_vaddr >= vaddr)) {
- /*
- * TLB is enabled and start address is lower or equal
- * than the area we are looking for. Now we only have
- * to check the size/end address for a match.
- */
- switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
- case TLB_WORD0_SIZE_1KB:
- tlb_size = 1 << 10;
- break;
- case TLB_WORD0_SIZE_4KB:
- tlb_size = 4 << 10;
- break;
- case TLB_WORD0_SIZE_16KB:
- tlb_size = 16 << 10;
- break;
- case TLB_WORD0_SIZE_64KB:
- tlb_size = 64 << 10;
- break;
- case TLB_WORD0_SIZE_256KB:
- tlb_size = 256 << 10;
- break;
- case TLB_WORD0_SIZE_1MB:
- tlb_size = 1 << 20;
- break;
- case TLB_WORD0_SIZE_16MB:
- tlb_size = 16 << 20;
- break;
- case TLB_WORD0_SIZE_256MB:
- tlb_size = 256 << 20;
- break;
- }
-
- /*
- * Now check the end-address if it's in the range
- */
- if (((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) ||
- ((tlb_vaddr < (vaddr + size - 1)) &&
- ((tlb_vaddr + tlb_size - 1) > (vaddr + size - 1)))) {
- /*
- * Found a TLB in the range.
- * Change cache attribute in tlb2 word.
- */
- tlb_word2_value =
- TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
- TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
- TLB_WORD2_W_DISABLE | tlb_word2_i_value |
- TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
- TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
- TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
- TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
- TLB_WORD2_SR_ENABLE;
-
- /*
- * Now either flush or invalidate the dcache
- */
- if (tlb_word2_i_value)
- flush_dcache();
- else
- invalidate_dcache();
-
- mttlb3(i, tlb_word2_value);
- asm("iccci 0,0");
- }
- }
- }
-
- /* Execute an ISYNC instruction so that the new TLB entry takes effect */
- asm("isync");
-}
-
-static int add_tlb_entry(u64 phys_addr,
- u32 virt_addr,
- u32 tlb_word0_size_value,
- u32 tlb_word2_i_value)
-{
- int i;
- unsigned long tlb_word0_value;
- unsigned long tlb_word1_value;
- unsigned long tlb_word2_value;
-
- /* First, find the index of a TLB entry not being used */
- for (i=0; i<PPC4XX_TLB_SIZE; i++) {
- tlb_word0_value = mftlb1(i);
- if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
- break;
- }
- if (i >= PPC4XX_TLB_SIZE)
- return -1;
-
- /* Second, create the TLB entry */
- tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
- TLB_WORD0_TS_0 | tlb_word0_size_value;
- tlb_word1_value = TLB_WORD1_RPN_ENCODE((u32)phys_addr) |
- TLB_WORD1_ERPN_ENCODE(phys_addr >> 32);
- tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
- TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
- TLB_WORD2_W_DISABLE | tlb_word2_i_value |
- TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
- TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
- TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
- TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
- TLB_WORD2_SR_ENABLE;
-
- /* Wait for all memory accesses to complete */
- sync();
-
- /* Third, add the TLB entries */
- mttlb1(i, tlb_word0_value);
- mttlb2(i, tlb_word1_value);
- mttlb3(i, tlb_word2_value);
-
- /* Execute an ISYNC instruction so that the new TLB entry takes effect */
- asm("isync");
-
- return 0;
-}
-
-static void program_tlb_addr(u64 phys_addr,
- u32 virt_addr,
- u32 mem_size,
- u32 tlb_word2_i_value)
-{
- int rc;
- int tlb_i;
-
- tlb_i = tlb_word2_i_value;
- while (mem_size != 0) {
- rc = 0;
- /* Add the TLB entries in to map the region. */
- if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
- (mem_size >= TLB_256MB_SIZE)) {
- /* Add a 256MB TLB entry */
- if ((rc = add_tlb_entry(phys_addr, virt_addr,
- TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
- mem_size -= TLB_256MB_SIZE;
- phys_addr += TLB_256MB_SIZE;
- virt_addr += TLB_256MB_SIZE;
- }
- } else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
- (mem_size >= TLB_16MB_SIZE)) {
- /* Add a 16MB TLB entry */
- if ((rc = add_tlb_entry(phys_addr, virt_addr,
- TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
- mem_size -= TLB_16MB_SIZE;
- phys_addr += TLB_16MB_SIZE;
- virt_addr += TLB_16MB_SIZE;
- }
- } else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
- (mem_size >= TLB_1MB_SIZE)) {
- /* Add a 1MB TLB entry */
- if ((rc = add_tlb_entry(phys_addr, virt_addr,
- TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
- mem_size -= TLB_1MB_SIZE;
- phys_addr += TLB_1MB_SIZE;
- virt_addr += TLB_1MB_SIZE;
- }
- } else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
- (mem_size >= TLB_256KB_SIZE)) {
- /* Add a 256KB TLB entry */
- if ((rc = add_tlb_entry(phys_addr, virt_addr,
- TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
- mem_size -= TLB_256KB_SIZE;
- phys_addr += TLB_256KB_SIZE;
- virt_addr += TLB_256KB_SIZE;
- }
- } else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
- (mem_size >= TLB_64KB_SIZE)) {
- /* Add a 64KB TLB entry */
- if ((rc = add_tlb_entry(phys_addr, virt_addr,
- TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
- mem_size -= TLB_64KB_SIZE;
- phys_addr += TLB_64KB_SIZE;
- virt_addr += TLB_64KB_SIZE;
- }
- } else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
- (mem_size >= TLB_16KB_SIZE)) {
- /* Add a 16KB TLB entry */
- if ((rc = add_tlb_entry(phys_addr, virt_addr,
- TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
- mem_size -= TLB_16KB_SIZE;
- phys_addr += TLB_16KB_SIZE;
- virt_addr += TLB_16KB_SIZE;
- }
- } else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
- (mem_size >= TLB_4KB_SIZE)) {
- /* Add a 4KB TLB entry */
- if ((rc = add_tlb_entry(phys_addr, virt_addr,
- TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
- mem_size -= TLB_4KB_SIZE;
- phys_addr += TLB_4KB_SIZE;
- virt_addr += TLB_4KB_SIZE;
- }
- } else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
- (mem_size >= TLB_1KB_SIZE)) {
- /* Add a 1KB TLB entry */
- if ((rc = add_tlb_entry(phys_addr, virt_addr,
- TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
- mem_size -= TLB_1KB_SIZE;
- phys_addr += TLB_1KB_SIZE;
- virt_addr += TLB_1KB_SIZE;
- }
- } else {
- printf("ERROR: no TLB size exists for the base address 0x%llx.\n",
- phys_addr);
- }
-
- if (rc != 0)
- printf("ERROR: no TLB entries available for the base addr 0x%llx.\n",
- phys_addr);
- }
-
- return;
-}
-
-/*
- * Program one (or multiple) TLB entries for one memory region
- *
- * Common usage for boards with SDRAM DIMM modules to dynamically
- * configure the TLB's for the SDRAM
- */
-void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
-{
- region_t region_array;
-
- region_array.base = phys_addr;
- region_array.size = size;
- region_array.tlb_word2_i_value = tlb_word2_i_value; /* en-/disable cache */
-
- /* Call the routine to add in the tlb entries for the memory regions */
- program_tlb_addr(region_array.base, virt_addr, region_array.size,
- region_array.tlb_word2_i_value);
-
- return;
-}
-
-#endif /* CONFIG_440 */
+++ /dev/null
-/*
- * linux/arch/powerpc/kernel/traps.c
- *
- * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
- *
- * Modified by Cort Dougan (cort@cs.nmt.edu)
- * and Paul Mackerras (paulus@cs.anu.edu.au)
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * This file handles the architecture-dependent parts of hardware exceptions
- */
-
-#include <common.h>
-#include <command.h>
-#include <kgdb.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Returns 0 if exception not found and fixup otherwise. */
-extern unsigned long search_exception_table(unsigned long);
-
-/* THIS NEEDS CHANGING to use the board info structure.
- */
-#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
-
-static __inline__ unsigned long get_esr(void)
-{
- unsigned long val;
-
-#if defined(CONFIG_440)
- asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
-#else
- asm volatile("mfesr %0" : "=r" (val) :);
-#endif
- return val;
-}
-
-#define ESR_MCI 0x80000000
-#define ESR_PIL 0x08000000
-#define ESR_PPR 0x04000000
-#define ESR_PTR 0x02000000
-#define ESR_DST 0x00800000
-#define ESR_DIZ 0x00400000
-#define ESR_U0F 0x00008000
-
-#if defined(CONFIG_CMD_BEDBUG)
-extern void do_bedbug_breakpoint(struct pt_regs *);
-#endif
-
-/*
- * Trap & Exception support
- */
-
-static void print_backtrace(unsigned long *sp)
-{
- int cnt = 0;
- unsigned long i;
-
- printf("Call backtrace: ");
- while (sp) {
- if ((uint)sp > END_OF_MEM)
- break;
-
- i = sp[1];
- if (cnt++ % 7 == 0)
- printf("\n");
- printf("%08lX ", i);
- if (cnt > 32) break;
- sp = (unsigned long *)*sp;
- }
- printf("\n");
-}
-
-void show_regs(struct pt_regs *regs)
-{
- int i;
-
- printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
- regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
- printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
- regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
- regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
- regs->msr&MSR_IR ? 1 : 0,
- regs->msr&MSR_DR ? 1 : 0);
-
- printf("\n");
- for (i = 0; i < 32; i++) {
- if ((i % 8) == 0) {
- printf("GPR%02d: ", i);
- }
-
- printf("%08lX ", regs->gpr[i]);
- if ((i % 8) == 7) {
- printf("\n");
- }
- }
-}
-
-
-static void _exception(int signr, struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Exception");
-}
-
-void MachineCheckException(struct pt_regs *regs)
-{
- unsigned long fixup, val;
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
- u32 value2;
- int corr_ecc = 0;
- int uncorr_ecc = 0;
-#endif
-
- if ((fixup = search_exception_table(regs->nip)) != 0) {
- regs->nip = fixup;
- val = mfspr(MCSR);
- /* Clear MCSR */
- mtspr(SPRN_MCSR, val);
- return;
- }
-
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- return;
-#endif
-
- printf("Machine Check Exception.\n");
- printf("Caused by (from msr): ");
- printf("regs %p ", regs);
-
- val = get_esr();
-
-#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
- if (val& ESR_IMCP) {
- printf("Instruction");
- mtspr(ESR, val & ~ESR_IMCP);
- } else {
- printf("Data");
- }
- printf(" machine check.\n");
-
-#elif defined(CONFIG_440) || defined(CONFIG_405EX)
- if (val& ESR_IMCP){
- printf("Instruction Synchronous Machine Check exception\n");
- mtspr(SPRN_ESR, val & ~ESR_IMCP);
- } else {
- val = mfspr(MCSR);
- if (val & MCSR_IB)
- printf("Instruction Read PLB Error\n");
-#if defined(CONFIG_440)
- if (val & MCSR_DRB)
- printf("Data Read PLB Error\n");
- if (val & MCSR_DWB)
- printf("Data Write PLB Error\n");
-#else
- if (val & MCSR_DB)
- printf("Data PLB Error\n");
-#endif
- if (val & MCSR_TLBP)
- printf("TLB Parity Error\n");
- if (val & MCSR_ICP){
- /*flush_instruction_cache(); */
- printf("I-Cache Parity Error\n");
- }
- if (val & MCSR_DCSP)
- printf("D-Cache Search Parity Error\n");
- if (val & MCSR_DCFP)
- printf("D-Cache Flush Parity Error\n");
- if (val & MCSR_IMPE)
- printf("Machine Check exception is imprecise\n");
-
- /* Clear MCSR */
- mtspr(SPRN_MCSR, val);
- }
-
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
- /*
- * Read and print ECC status register/info:
- * The faulting address is only known upon uncorrectable ECC
- * errors.
- */
- mfsdram(SDRAM_ECCES, val);
- if (val & SDRAM_ECCES_CE)
- printf("ECC: Correctable error\n");
- if (val & SDRAM_ECCES_UE) {
- printf("ECC: Uncorrectable error at 0x%02x%08x\n",
- mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
- }
-#endif /* CONFIG_DDR_ECC ... */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
- mfsdram(DDR0_00, val) ;
- printf("DDR0: DDR0_00 %lx\n", val);
- val = (val >> 16) & 0xff;
- if (val & 0x80)
- printf("DDR0: At least one interrupt active\n");
- if (val & 0x40)
- printf("DDR0: DRAM initialization complete.\n");
- if (val & 0x20) {
- printf("DDR0: Multiple uncorrectable ECC events.\n");
- uncorr_ecc = 1;
- }
- if (val & 0x10) {
- printf("DDR0: Single uncorrectable ECC event.\n");
- uncorr_ecc = 1;
- }
- if (val & 0x08) {
- printf("DDR0: Multiple correctable ECC events.\n");
- corr_ecc = 1;
- }
- if (val & 0x04) {
- printf("DDR0: Single correctable ECC event.\n");
- corr_ecc = 1;
- }
- if (val & 0x02)
- printf("Multiple accesses outside the defined"
- " physical memory space detected\n");
- if (val & 0x01)
- printf("DDR0: Single access outside the defined"
- " physical memory space detected.\n");
-
- mfsdram(DDR0_01, val);
- val = (val >> 8) & 0x7;
- switch (val ) {
- case 0:
- printf("DDR0: Write Out-of-Range command\n");
- break;
- case 1:
- printf("DDR0: Read Out-of-Range command\n");
- break;
- case 2:
- printf("DDR0: Masked write Out-of-Range command\n");
- break;
- case 4:
- printf("DDR0: Wrap write Out-of-Range command\n");
- break;
- case 5:
- printf("DDR0: Wrap read Out-of-Range command\n");
- break;
- default:
- mfsdram(DDR0_01, value2);
- printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2);
- }
- mfsdram(DDR0_23, val);
- if (((val >> 16) & 0xff) && corr_ecc)
- printf("DDR0: Syndrome for correctable ECC event 0x%lx\n",
- (val >> 16) & 0xff);
- mfsdram(DDR0_23, val);
- if (((val >> 8) & 0xff) && uncorr_ecc)
- printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n",
- (val >> 8) & 0xff);
- mfsdram(DDR0_33, val);
- if (val)
- printf("DDR0: Address of command that caused an "
- "Out-of-Range interrupt %lx\n", val);
- mfsdram(DDR0_34, val);
- if (val && uncorr_ecc)
- printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
- mfsdram(DDR0_35, val);
- if (val && uncorr_ecc)
- printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
- mfsdram(DDR0_36, val);
- if (val && uncorr_ecc)
- printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
- mfsdram(DDR0_37, val);
- if (val && uncorr_ecc)
- printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
- mfsdram(DDR0_38, val);
- if (val && corr_ecc)
- printf("DDR0: Address of correctable ECC event %lx\n", val);
- mfsdram(DDR0_39, val);
- if (val && corr_ecc)
- printf("DDR0: Address of correctable ECC event %lx\n", val);
- mfsdram(DDR0_40, val);
- if (val && corr_ecc)
- printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
- mfsdram(DDR0_41, val);
- if (val && corr_ecc)
- printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
-#endif /* CONFIG_440EPX */
-#endif /* CONFIG_440 */
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("machine check");
-}
-
-void AlignmentException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- return;
-#endif
-
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Alignment Exception");
-}
-
-void ProgramCheckException(struct pt_regs *regs)
-{
- long esr_val;
-
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- return;
-#endif
-
- show_regs(regs);
-
- esr_val = get_esr();
- if( esr_val & ESR_PIL )
- printf( "** Illegal Instruction **\n" );
- else if( esr_val & ESR_PPR )
- printf( "** Privileged Instruction **\n" );
- else if( esr_val & ESR_PTR )
- printf( "** Trap Instruction **\n" );
-
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Program Check Exception");
-}
-
-void DecrementerPITException(struct pt_regs *regs)
-{
- /*
- * Reset PIT interrupt
- */
- mtspr(SPRN_TSR, 0x08000000);
-
- /*
- * Call timer_interrupt routine in interrupts.c
- */
- timer_interrupt(NULL);
-}
-
-
-void UnknownException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- return;
-#endif
-
- printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
- regs->nip, regs->msr, regs->trap);
- _exception(0, regs);
-}
-
-void DebugException(struct pt_regs *regs)
-{
- printf("Debugger trap at @ %lx\n", regs->nip );
- show_regs(regs);
-#if defined(CONFIG_CMD_BEDBUG)
- do_bedbug_breakpoint( regs );
-#endif
-}
-
-/* Probe an address by reading. If not present, return -1, otherwise
- * return 0.
- */
-int
-addr_probe(uint *addr)
-{
-#if 0
- int retval;
-
- __asm__ __volatile__( \
- "1: lwz %0,0(%1)\n" \
- " eieio\n" \
- " li %0,0\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- "3: li %0,-1\n" \
- " b 2b\n" \
- ".section __ex_table,\"a\"\n" \
- " .align 2\n" \
- " .long 1b,3b\n" \
- ".text" \
- : "=r" (retval) : "r"(addr));
-
- return (retval);
-#endif
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2012-2013 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-MEMORY
-{
- sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
- LENGTH = CONFIG_SPL_BSS_MAX_SIZE
- flash : ORIGIN = CONFIG_SPL_TEXT_BASE,
- LENGTH = CONFIG_SYS_SPL_MAX_LEN
-}
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start)
-SECTIONS
-{
-#ifdef CONFIG_440
- .bootpg 0xfffff000 :
- {
- arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
-
- /*
- * PPC440 board need a board specific object with the
- * TLB definitions. This needs to get included right after
- * start.o, since the first shadow TLB only covers 4k
- * of address space.
- */
- CONFIG_BOARDDIR/init.o (.bootpg)
- } > flash
-#endif
-
- .resetvec 0xFFFFFFFC :
- {
- KEEP(*(.resetvec))
- } > flash
-
- .text :
- {
- __start = .;
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- CONFIG_BOARDDIR/init.o (.text)
- *(.text*)
- } > flash
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } > flash
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > flash
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } > sdram
-}
+++ /dev/null
-/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "config.h" /* CONFIG_BOARDDIR */
-
-#ifndef RESET_VECTOR_ADDRESS
-#ifdef CONFIG_RESET_VECTOR_ADDRESS
-#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
-#else
-#define RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-#endif
-
-OUTPUT_ARCH(powerpc)
-
-PHDRS
-{
- text PT_LOAD;
- bss PT_LOAD;
-}
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- *(.text*)
- } :text
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- } :text
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : {
- *(.data.init)
- . = ALIGN(256);
- LONG(0) LONG(0) /* Extend u-boot.bin to here */
- }
- __init_end = .;
- _end = .;
-
-#ifndef CONFIG_SPL
-#ifdef CONFIG_440
- .bootpg RESET_VECTOR_ADDRESS - 0xffc :
- {
- arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
-
- /*
- * PPC440 board need a board specific object with the
- * TLB definitions. This needs to get included right after
- * start.o, since the first shadow TLB only covers 4k
- * of address space.
- */
-#ifdef CONFIG_INIT_TLB
- CONFIG_INIT_TLB (.bootpg)
-#else
- CONFIG_BOARDDIR/init.o (.bootpg)
-#endif
- } :text = 0xffff
-#endif
-
- .resetvec RESET_VECTOR_ADDRESS :
- {
- KEEP(*(.resetvec))
- } :text = 0xffff
-
- . = RESET_VECTOR_ADDRESS + 0x4;
-
- /*
- * Make sure that the bss segment isn't linked at 0x0, otherwise its
- * address won't be updated during relocation fixups. Note that
- * this is a temporary fix. Code to dynamically the fixup the bss
- * location will be added in the future. When the bss relocation
- * fixup code is present this workaround should be removed.
- */
-#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
- . |= 0x10;
-#endif
-#endif /* CONFIG_SPL */
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- } :bss
-
- . = ALIGN(4);
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 (440 port)
- * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
- *
- * (C) Copyright 2003 (440GX port)
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
- * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * Work supported by Qtechnology (htpp://qtec.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/interrupt.h>
-#include <asm/ppc4xx.h>
-#include <ppc_asm.tmpl>
-
-#if (UIC_MAX > 3)
-#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
- UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
- UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
-#elif (UIC_MAX > 2)
-#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
- UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
-#elif (UIC_MAX > 1)
-#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
-#else
-#define UICB0_ALL 0
-#endif
-
-u32 get_dcr(u16);
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void pic_enable(void)
-{
-#if (UIC_MAX > 1)
- /* Install the UIC1 handlers */
- irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
- irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
-#endif
-#if (UIC_MAX > 2)
- irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
- irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
-#endif
-#if (UIC_MAX > 3)
- irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
- irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
-#endif
-}
-
-/* Handler for UIC interrupt */
-static void uic_interrupt(u32 uic_base, int vec_base)
-{
- u32 uic_msr;
- u32 msr_shift;
- int vec;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- uic_msr = get_dcr(uic_base + UIC_MSR);
- msr_shift = uic_msr;
- vec = vec_base;
-
- while (msr_shift != 0) {
- if (msr_shift & 0x80000000)
- interrupt_run_handler(vec);
- /*
- * Shift msr to next position and increment vector
- */
- msr_shift <<= 1;
- vec++;
- }
-}
-
-/*
- * Handle external interrupts
- */
-void external_interrupt(struct pt_regs *regs)
-{
- u32 uic_msr;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- uic_msr = mfdcr(UIC0MSR);
-
-#if (UIC_MAX > 1)
- if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
- (UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
- uic_interrupt(UIC1_DCR_BASE, 32);
-#endif
-
-#if (UIC_MAX > 2)
- if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
- (UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
- uic_interrupt(UIC2_DCR_BASE, 64);
-#endif
-
-#if (UIC_MAX > 3)
- if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
- (UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
- uic_interrupt(UIC3_DCR_BASE, 96);
-#endif
-
- mtdcr(UIC0SR, (uic_msr & UICB0_ALL));
-
- if (uic_msr & ~(UICB0_ALL))
- uic_interrupt(UIC0_DCR_BASE, 0);
-
- return;
-}
-
-void pic_irq_ack(unsigned int vec)
-{
- if ((vec >= 0) && (vec < 32))
- mtdcr(UIC0SR, UIC_MASK(vec));
- else if ((vec >= 32) && (vec < 64))
- mtdcr(UIC1SR, UIC_MASK(vec));
- else if ((vec >= 64) && (vec < 96))
- mtdcr(UIC2SR, UIC_MASK(vec));
- else if (vec >= 96)
- mtdcr(UIC3SR, UIC_MASK(vec));
-}
-
-/*
- * Install and free a interrupt handler.
- */
-void pic_irq_enable(unsigned int vec)
-{
-
- if ((vec >= 0) && (vec < 32))
- mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec));
- else if ((vec >= 32) && (vec < 64))
- mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec));
- else if ((vec >= 64) && (vec < 96))
- mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec));
- else if (vec >= 96)
- mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec));
-
- debug("Install interrupt vector %d\n", vec);
-}
-
-void pic_irq_disable(unsigned int vec)
-{
- if ((vec >= 0) && (vec < 32))
- mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec));
- else if ((vec >= 32) && (vec < 64))
- mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec));
- else if ((vec >= 64) && (vec < 96))
- mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec));
- else if (vec >= 96)
- mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec));
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-
-#ifdef CONFIG_4xx_DCACHE
-#include <asm/mmu.h>
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-int usb_cpu_init(void)
-{
-#ifdef CONFIG_4xx_DCACHE
- /* disable cache */
- change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
-#endif
-
- return 0;
-}
-
-int usb_cpu_stop(void)
-{
-#ifdef CONFIG_4xx_DCACHE
- /* enable cache */
- change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
-#endif
- return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-#ifdef CONFIG_4xx_DCACHE
- /* enable cache */
- change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
-#endif
- return 0;
-}
-
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
+++ /dev/null
-/*
- * URB OHCI HCD (Host Controller Driver) for USB on the PPC440EP.
- *
- * (C) Copyright 2003-2004
- * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
- *
- * Note: Much of this code has been derived from Linux 2.4
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * IMPORTANT NOTES
- * 1 - this driver is intended for use with USB Mass Storage Devices
- * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
- */
-
-#include <common.h>
-
-#ifdef CONFIG_USB_OHCI
-
-#include <malloc.h>
-#include <usb.h>
-#include "usb_ohci.h"
-
-#define OHCI_USE_NPS /* force NoPowerSwitching mode */
-#undef OHCI_VERBOSE_DEBUG /* not always helpful */
-#undef DEBUG
-#undef SHOW_INFO
-#undef OHCI_FILL_TRACE
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define OHCI_CONTROL_INIT \
- (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-
-#define readl(a) (*((volatile u32 *)(a)))
-#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-
-#ifdef DEBUG
-#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
-#else
-#define dbg(format, arg...) do {} while(0)
-#endif /* DEBUG */
-#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
-#ifdef SHOW_INFO
-#define info(format, arg...) printf("INFO: " format "\n", ## arg)
-#else
-#define info(format, arg...) do {} while(0)
-#endif
-
-#define m16_swap(x) swap_16(x)
-#define m32_swap(x) swap_32(x)
-
-#if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX)
-#define ohci_cpu_to_le16(x) (x)
-#define ohci_cpu_to_le32(x) (x)
-#else
-#define ohci_cpu_to_le16(x) swap_16(x)
-#define ohci_cpu_to_le32(x) swap_32(x)
-#endif
-
-/* global ohci_t */
-static ohci_t gohci;
-/* this must be aligned to a 256 byte boundary */
-struct ohci_hcca ghcca[1];
-/* a pointer to the aligned storage */
-struct ohci_hcca *phcca;
-/* this allocates EDs for all possible endpoints */
-struct ohci_device ohci_dev;
-/* urb_priv */
-urb_priv_t urb_priv;
-/* RHSC flag */
-int got_rhsc;
-/* device which was disconnected */
-struct usb_device *devgone;
-/* flag guarding URB transation */
-int urb_finished = 0;
-
-/*-------------------------------------------------------------------------*/
-
-/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
- * The erratum (#4) description is incorrect. AMD's workaround waits
- * till some bits (mostly reserved) are clear; ok for all revs.
- */
-#define OHCI_QUIRK_AMD756 0xabcd
-#define read_roothub(hc, register, mask) ({ \
- u32 temp = readl (&hc->regs->roothub.register); \
- if (hc->flags & OHCI_QUIRK_AMD756) \
- while (temp & mask) \
- temp = readl (&hc->regs->roothub.register); \
- temp; })
-
-static u32 roothub_a (struct ohci *hc)
- { return read_roothub (hc, a, 0xfc0fe000); }
-static inline u32 roothub_b (struct ohci *hc)
- { return readl (&hc->regs->roothub.b); }
-static inline u32 roothub_status (struct ohci *hc)
- { return readl (&hc->regs->roothub.status); }
-static u32 roothub_portstatus (struct ohci *hc, int i)
- { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
-
-
-/* forward declaration */
-static int hc_interrupt (void);
-static void
-td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
- int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
-
-/*-------------------------------------------------------------------------*
- * URB support functions
- *-------------------------------------------------------------------------*/
-
-/* free HCD-private data associated with this URB */
-
-static void urb_free_priv (urb_priv_t * urb)
-{
- int i;
- int last;
- struct td * td;
-
- last = urb->length - 1;
- if (last >= 0) {
- for (i = 0; i <= last; i++) {
- td = urb->td[i];
- if (td) {
- td->usb_dev = NULL;
- urb->td[i] = NULL;
- }
- }
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-static int sohci_get_current_frame_number (struct usb_device * dev);
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header */
-
-static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
- int transfer_len, struct devrequest * setup, char * str, int small)
-{
- urb_priv_t * purb = &urb_priv;
-
- dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
- str,
- sohci_get_current_frame_number (dev),
- usb_pipedevice (pipe),
- usb_pipeendpoint (pipe),
- usb_pipeout (pipe)? 'O': 'I',
- usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
- (usb_pipecontrol (pipe)? "CTRL": "BULK"),
- purb->actual_length,
- transfer_len, dev->status);
-#ifdef OHCI_VERBOSE_DEBUG
- if (!small) {
- int i, len;
-
- if (usb_pipecontrol (pipe)) {
- printf (__FILE__ ": cmd(8):");
- for (i = 0; i < 8 ; i++)
- printf (" %02x", ((__u8 *) setup) [i]);
- printf ("\n");
- }
- if (transfer_len > 0 && buffer) {
- printf (__FILE__ ": data(%d/%d):",
- purb->actual_length,
- transfer_len);
- len = usb_pipeout (pipe)?
- transfer_len: purb->actual_length;
- for (i = 0; i < 16 && i < len; i++)
- printf (" %02x", ((__u8 *) buffer) [i]);
- printf ("%s\n", i < len? "...": "");
- }
- }
-#endif
-}
-
-/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
-void ep_print_int_eds (ohci_t *ohci, char * str) {
- int i, j;
- __u32 * ed_p;
- for (i= 0; i < 32; i++) {
- j = 5;
- ed_p = &(ohci->hcca->int_table [i]);
- if (*ed_p == 0)
- continue;
- printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
- while (*ed_p != 0 && j--) {
- ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p);
- printf (" ed: %4x;", ed->hwINFO);
- ed_p = &ed->hwNextED;
- }
- printf ("\n");
- }
-}
-
-static void ohci_dump_intr_mask (char *label, __u32 mask)
-{
- dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
- label,
- mask,
- (mask & OHCI_INTR_MIE) ? " MIE" : "",
- (mask & OHCI_INTR_OC) ? " OC" : "",
- (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
- (mask & OHCI_INTR_FNO) ? " FNO" : "",
- (mask & OHCI_INTR_UE) ? " UE" : "",
- (mask & OHCI_INTR_RD) ? " RD" : "",
- (mask & OHCI_INTR_SF) ? " SF" : "",
- (mask & OHCI_INTR_WDH) ? " WDH" : "",
- (mask & OHCI_INTR_SO) ? " SO" : ""
- );
-}
-
-static void maybe_print_eds (char *label, __u32 value)
-{
- ed_t *edp = (ed_t *)value;
-
- if (value) {
- dbg ("%s %08x", label, value);
- dbg ("%08x", edp->hwINFO);
- dbg ("%08x", edp->hwTailP);
- dbg ("%08x", edp->hwHeadP);
- dbg ("%08x", edp->hwNextED);
- }
-}
-
-static char * hcfs2string (int state)
-{
- switch (state) {
- case OHCI_USB_RESET: return "reset";
- case OHCI_USB_RESUME: return "resume";
- case OHCI_USB_OPER: return "operational";
- case OHCI_USB_SUSPEND: return "suspend";
- }
- return "?";
-}
-
-/* dump control and status registers */
-static void ohci_dump_status (ohci_t *controller)
-{
- struct ohci_regs *regs = controller->regs;
- __u32 temp;
-
- temp = readl (®s->revision) & 0xff;
- if (temp != 0x10)
- dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
- temp = readl (®s->control);
- dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
- (temp & OHCI_CTRL_RWE) ? " RWE" : "",
- (temp & OHCI_CTRL_RWC) ? " RWC" : "",
- (temp & OHCI_CTRL_IR) ? " IR" : "",
- hcfs2string (temp & OHCI_CTRL_HCFS),
- (temp & OHCI_CTRL_BLE) ? " BLE" : "",
- (temp & OHCI_CTRL_CLE) ? " CLE" : "",
- (temp & OHCI_CTRL_IE) ? " IE" : "",
- (temp & OHCI_CTRL_PLE) ? " PLE" : "",
- temp & OHCI_CTRL_CBSR
- );
-
- temp = readl (®s->cmdstatus);
- dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
- (temp & OHCI_SOC) >> 16,
- (temp & OHCI_OCR) ? " OCR" : "",
- (temp & OHCI_BLF) ? " BLF" : "",
- (temp & OHCI_CLF) ? " CLF" : "",
- (temp & OHCI_HCR) ? " HCR" : ""
- );
-
- ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
- ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
-
- maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
-
- maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
- maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
-
- maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
- maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
-
- maybe_print_eds ("donehead", readl (®s->donehead));
-}
-
-static void ohci_dump_roothub (ohci_t *controller, int verbose)
-{
- __u32 temp, ndp, i;
-
- temp = roothub_a (controller);
- ndp = (temp & RH_A_NDP);
-
- if (verbose) {
- dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
- ((temp & RH_A_POTPGT) >> 24) & 0xff,
- (temp & RH_A_NOCP) ? " NOCP" : "",
- (temp & RH_A_OCPM) ? " OCPM" : "",
- (temp & RH_A_DT) ? " DT" : "",
- (temp & RH_A_NPS) ? " NPS" : "",
- (temp & RH_A_PSM) ? " PSM" : "",
- ndp
- );
- temp = roothub_b (controller);
- dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
- temp,
- (temp & RH_B_PPCM) >> 16,
- (temp & RH_B_DR)
- );
- temp = roothub_status (controller);
- dbg ("roothub.status: %08x%s%s%s%s%s%s",
- temp,
- (temp & RH_HS_CRWE) ? " CRWE" : "",
- (temp & RH_HS_OCIC) ? " OCIC" : "",
- (temp & RH_HS_LPSC) ? " LPSC" : "",
- (temp & RH_HS_DRWE) ? " DRWE" : "",
- (temp & RH_HS_OCI) ? " OCI" : "",
- (temp & RH_HS_LPS) ? " LPS" : ""
- );
- }
-
- for (i = 0; i < ndp; i++) {
- temp = roothub_portstatus (controller, i);
- dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
- i,
- temp,
- (temp & RH_PS_PRSC) ? " PRSC" : "",
- (temp & RH_PS_OCIC) ? " OCIC" : "",
- (temp & RH_PS_PSSC) ? " PSSC" : "",
- (temp & RH_PS_PESC) ? " PESC" : "",
- (temp & RH_PS_CSC) ? " CSC" : "",
-
- (temp & RH_PS_LSDA) ? " LSDA" : "",
- (temp & RH_PS_PPS) ? " PPS" : "",
- (temp & RH_PS_PRS) ? " PRS" : "",
- (temp & RH_PS_POCI) ? " POCI" : "",
- (temp & RH_PS_PSS) ? " PSS" : "",
-
- (temp & RH_PS_PES) ? " PES" : "",
- (temp & RH_PS_CCS) ? " CCS" : ""
- );
- }
-}
-
-static void ohci_dump (ohci_t *controller, int verbose)
-{
- dbg ("OHCI controller usb-%s state", controller->slot_name);
-
- /* dumps some of the state we know about */
- ohci_dump_status (controller);
- if (verbose)
- ep_print_int_eds (controller, "hcca");
- dbg ("hcca frame #%04x", controller->hcca->frame_no);
- ohci_dump_roothub (controller, 1);
-}
-
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*
- * Interface functions (URB)
- *-------------------------------------------------------------------------*/
-
-/* get a transfer request */
-
-int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, int interval)
-{
- ohci_t *ohci;
- ed_t * ed;
- urb_priv_t *purb_priv;
- int i, size = 0;
-
- ohci = &gohci;
-
- /* when controller's hung, permit only roothub cleanup attempts
- * such as powering down ports */
- if (ohci->disabled) {
- err("sohci_submit_job: EPIPE");
- return -1;
- }
-
- /* if we have an unfinished URB from previous transaction let's
- * fail and scream as quickly as possible so as not to corrupt
- * further communication */
- if (!urb_finished) {
- err("sohci_submit_job: URB NOT FINISHED");
- return -1;
- }
- /* we're about to begin a new transaction here so mark the URB unfinished */
- urb_finished = 0;
-
- /* every endpoint has a ed, locate and fill it */
- if (!(ed = ep_add_ed (dev, pipe))) {
- err("sohci_submit_job: ENOMEM");
- return -1;
- }
-
- /* for the private part of the URB we need the number of TDs (size) */
- switch (usb_pipetype (pipe)) {
- case PIPE_BULK: /* one TD for every 4096 Byte */
- size = (transfer_len - 1) / 4096 + 1;
- break;
- case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
- size = (transfer_len == 0)? 2:
- (transfer_len - 1) / 4096 + 3;
- break;
- }
-
- if (size >= (N_URB_TD - 1)) {
- err("need %d TDs, only have %d", size, N_URB_TD);
- return -1;
- }
- purb_priv = &urb_priv;
- purb_priv->pipe = pipe;
-
- /* fill the private part of the URB */
- purb_priv->length = size;
- purb_priv->ed = ed;
- purb_priv->actual_length = 0;
-
- /* allocate the TDs */
- /* note that td[0] was allocated in ep_add_ed */
- for (i = 0; i < size; i++) {
- purb_priv->td[i] = td_alloc (dev);
- if (!purb_priv->td[i]) {
- purb_priv->length = i;
- urb_free_priv (purb_priv);
- err("sohci_submit_job: ENOMEM");
- return -1;
- }
- }
-
- if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
- urb_free_priv (purb_priv);
- err("sohci_submit_job: EINVAL");
- return -1;
- }
-
- /* link the ed into a chain if is not already */
- if (ed->state != ED_OPER)
- ep_link (ohci, ed);
-
- /* fill the TDs and link it to the ed */
- td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-/* tell us the current USB frame number */
-
-static int sohci_get_current_frame_number (struct usb_device *usb_dev)
-{
- ohci_t *ohci = &gohci;
-
- return ohci_cpu_to_le16 (ohci->hcca->frame_no);
-}
-#endif
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-/* link an ed into one of the HC chains */
-
-static int ep_link (ohci_t *ohci, ed_t *edi)
-{
- volatile ed_t *ed = edi;
-
- ed->state = ED_OPER;
-
- switch (ed->type) {
- case PIPE_CONTROL:
- ed->hwNextED = 0;
- if (ohci->ed_controltail == NULL) {
- writel (ed, &ohci->regs->ed_controlhead);
- } else {
- ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
- }
- ed->ed_prev = ohci->ed_controltail;
- if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
- !ohci->ed_rm_list[1] && !ohci->sleeping) {
- ohci->hc_control |= OHCI_CTRL_CLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- ohci->ed_controltail = edi;
- break;
-
- case PIPE_BULK:
- ed->hwNextED = 0;
- if (ohci->ed_bulktail == NULL) {
- writel (ed, &ohci->regs->ed_bulkhead);
- } else {
- ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
- }
- ed->ed_prev = ohci->ed_bulktail;
- if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
- !ohci->ed_rm_list[1] && !ohci->sleeping) {
- ohci->hc_control |= OHCI_CTRL_BLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- ohci->ed_bulktail = edi;
- break;
- }
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* unlink an ed from one of the HC chains.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed */
-
-static int ep_unlink (ohci_t *ohci, ed_t *edi)
-{
- volatile ed_t *ed = edi;
-
- ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP);
-
- switch (ed->type) {
- case PIPE_CONTROL:
- if (ed->ed_prev == NULL) {
- if (!ed->hwNextED) {
- ohci->hc_control &= ~OHCI_CTRL_CLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
- } else {
- ed->ed_prev->hwNextED = ed->hwNextED;
- }
- if (ohci->ed_controltail == ed) {
- ohci->ed_controltail = ed->ed_prev;
- } else {
- ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
- }
- break;
-
- case PIPE_BULK:
- if (ed->ed_prev == NULL) {
- if (!ed->hwNextED) {
- ohci->hc_control &= ~OHCI_CTRL_BLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
- } else {
- ed->ed_prev->hwNextED = ed->hwNextED;
- }
- if (ohci->ed_bulktail == ed) {
- ohci->ed_bulktail = ed->ed_prev;
- } else {
- ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
- }
- break;
- }
- ed->state = ED_UNLINK;
- return 0;
-}
-
-
-/*-------------------------------------------------------------------------*/
-
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
- * but the USB stack is a little bit stateless so we do it at every transaction
- * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
- * in all other cases the state is left unchanged
- * the ed info fields are setted anyway even though most of them should not change */
-
-static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
-{
- td_t *td;
- ed_t *ed_ret;
- volatile ed_t *ed;
-
- ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
- (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
-
- if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
- err("ep_add_ed: pending delete");
- /* pending delete request */
- return NULL;
- }
-
- if (ed->state == ED_NEW) {
- ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
- /* dummy td; end of td list for ed */
- td = td_alloc (usb_dev);
- ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
- ed->hwHeadP = ed->hwTailP;
- ed->state = ED_UNLINK;
- ed->type = usb_pipetype (pipe);
- ohci_dev.ed_cnt++;
- }
-
- ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)
- | usb_pipeendpoint (pipe) << 7
- | (usb_pipeisoc (pipe)? 0x8000: 0)
- | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
- | (usb_dev->speed == USB_SPEED_LOW) << 13
- | usb_maxpacket (usb_dev, pipe) << 16);
-
- return ed_ret;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void td_fill (ohci_t *ohci, unsigned int info,
- void *data, int len,
- struct usb_device *dev, int index, urb_priv_t *urb_priv)
-{
- volatile td_t *td, *td_pt;
-#ifdef OHCI_FILL_TRACE
- int i;
-#endif
-
- if (index > urb_priv->length) {
- err("index > length");
- return;
- }
- /* use this td as the next dummy */
- td_pt = urb_priv->td [index];
- td_pt->hwNextTD = 0;
-
- /* fill the old dummy TD */
- td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);
-
- td->ed = urb_priv->ed;
- td->next_dl_td = NULL;
- td->index = index;
- td->data = (__u32)data;
-#ifdef OHCI_FILL_TRACE
- if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
- for (i = 0; i < len; i++)
- printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
- printf("\n");
- }
-#endif
- if (!len)
- data = 0;
-
- td->hwINFO = ohci_cpu_to_le32 (info);
- td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
- if (data)
- td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
- else
- td->hwBE = 0;
- td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
-
- /* append to queue */
- td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* prepare all TDs of a transfer */
-static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
-{
- ohci_t *ohci = &gohci;
- int data_len = transfer_len;
- void *data;
- int cnt = 0;
- __u32 info = 0;
- unsigned int toggle = 0;
-
- /* OHCI handles the DATA-toggles itself, we just use the
- USB-toggle bits for resetting */
- if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
- toggle = TD_T_TOGGLE;
- } else {
- toggle = TD_T_DATA0;
- usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
- }
- urb->td_cnt = 0;
- if (data_len)
- data = buffer;
- else
- data = 0;
-
- switch (usb_pipetype (pipe)) {
- case PIPE_BULK:
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
- while(data_len > 4096) {
- td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
- data += 4096; data_len -= 4096; cnt++;
- }
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
- td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
- cnt++;
-
- if (!ohci->sleeping)
- writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
- break;
-
- case PIPE_CONTROL:
- info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
- td_fill (ohci, info, setup, 8, dev, cnt++, urb);
- if (data_len > 0) {
- info = usb_pipeout (pipe)?
- TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
- /* NOTE: mishandles transfers >8K, some >4K */
- td_fill (ohci, info, data, data_len, dev, cnt++, urb);
- }
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
- td_fill (ohci, info, data, 0, dev, cnt++, urb);
- if (!ohci->sleeping)
- writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
- break;
- }
- if (urb->length != cnt)
- dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-
-/* calculate the transfer length and update the urb */
-
-static void dl_transfer_length(td_t * td)
-{
- __u32 tdBE, tdCBP;
- urb_priv_t *lurb_priv = &urb_priv;
-
- tdBE = ohci_cpu_to_le32 (td->hwBE);
- tdCBP = ohci_cpu_to_le32 (td->hwCBP);
-
-
- if (!(usb_pipecontrol(lurb_priv->pipe) &&
- ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
- if (tdBE != 0) {
- if (td->hwCBP == 0)
- lurb_priv->actual_length += tdBE - td->data + 1;
- else
- lurb_priv->actual_length += tdCBP - td->data;
- }
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* replies to the request have to be on a FIFO basis so
- * we reverse the reversed done-list */
-
-static td_t * dl_reverse_done_list (ohci_t *ohci)
-{
- __u32 td_list_hc;
- td_t *td_rev = NULL;
- td_t *td_list = NULL;
- urb_priv_t *lurb_priv = NULL;
-
- td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;
- ohci->hcca->done_head = 0;
-
- while (td_list_hc) {
- td_list = (td_t *)td_list_hc;
-
- if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {
- lurb_priv = &urb_priv;
- dbg(" USB-error/status: %x : %p",
- TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);
- if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {
- if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
- td_list->ed->hwHeadP =
- (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) |
- (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));
- lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
- } else
- td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
- }
- }
-
- td_list->next_dl_td = td_rev;
- td_rev = td_list;
- td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;
- }
- return td_list;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* td done list */
-static int dl_done_list (ohci_t *ohci, td_t *td_list)
-{
- td_t *td_list_next = NULL;
- ed_t *ed;
- int cc = 0;
- int stat = 0;
- /* urb_t *urb; */
- urb_priv_t *lurb_priv;
- __u32 tdINFO, edHeadP, edTailP;
-
- while (td_list) {
- td_list_next = td_list->next_dl_td;
-
- lurb_priv = &urb_priv;
- tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);
-
- ed = td_list->ed;
-
- dl_transfer_length(td_list);
-
- /* error code of transfer */
- cc = TD_CC_GET (tdINFO);
- if (++(lurb_priv->td_cnt) == lurb_priv->length) {
- if ((ed->state & (ED_OPER | ED_UNLINK))
- && (lurb_priv->state != URB_DEL)) {
- dbg("ConditionCode %#x", cc);
- stat = cc_to_error[cc];
- urb_finished = 1;
- }
- }
-
- if (ed->state != ED_NEW) {
- edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;
- edTailP = ohci_cpu_to_le32 (ed->hwTailP);
-
- /* unlink eds if they are not busy */
- if ((edHeadP == edTailP) && (ed->state == ED_OPER))
- ep_unlink (ohci, ed);
- }
-
- td_list = td_list_next;
- }
- return stat;
-}
-
-/*-------------------------------------------------------------------------*
- * Virtual Root Hub
- *-------------------------------------------------------------------------*/
-
-#include <usbroothubdes.h>
-
-/* Hub class-specific descriptor is constructed dynamically */
-
-
-/*-------------------------------------------------------------------------*/
-
-#define OK(x) len = (x); break
-#ifdef DEBUG
-#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
-#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
-#else
-#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
-#endif
-#define RD_RH_STAT roothub_status(&gohci)
-#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
-
-/* request to virtual root hub */
-
-int rh_check_port_status(ohci_t *controller)
-{
- __u32 temp, ndp, i;
- int res;
-
- res = -1;
- temp = roothub_a (controller);
- ndp = (temp & RH_A_NDP);
- for (i = 0; i < ndp; i++) {
- temp = roothub_portstatus (controller, i);
- /* check for a device disconnect */
- if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
- (RH_PS_PESC | RH_PS_CSC)) &&
- ((temp & RH_PS_CCS) == 0)) {
- res = i;
- break;
- }
- }
- return res;
-}
-
-static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len, struct devrequest *cmd)
-{
- void * data = buffer;
- int leni = transfer_len;
- int len = 0;
- int stat = 0;
- __u32 datab[4];
- __u8 *data_buf = (__u8 *)datab;
- __u16 bmRType_bReq;
- __u16 wValue;
- __u16 wIndex;
- __u16 wLength;
-
-#ifdef DEBUG
-urb_priv.actual_length = 0;
-pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
-#endif
- if (usb_pipeint(pipe)) {
- info("Root-Hub submit IRQ: NOT implemented");
- return 0;
- }
-
- bmRType_bReq = cmd->requesttype | (cmd->request << 8);
- wValue = m16_swap (cmd->value);
- wIndex = m16_swap (cmd->index);
- wLength = m16_swap (cmd->length);
-
- info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
- dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
-
- switch (bmRType_bReq) {
- /* Request Destination:
- without flags: Device,
- RH_INTERFACE: interface,
- RH_ENDPOINT: endpoint,
- RH_CLASS means HUB here,
- RH_OTHER | RH_CLASS almost ever means HUB_PORT here
- */
-
- case RH_GET_STATUS:
- *(__u16 *) data_buf = m16_swap (1); OK (2);
- case RH_GET_STATUS | RH_INTERFACE:
- *(__u16 *) data_buf = m16_swap (0); OK (2);
- case RH_GET_STATUS | RH_ENDPOINT:
- *(__u16 *) data_buf = m16_swap (0); OK (2);
- case RH_GET_STATUS | RH_CLASS:
- *(__u32 *) data_buf = m32_swap (
- RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
- OK (4);
- case RH_GET_STATUS | RH_OTHER | RH_CLASS:
- *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
-
- case RH_CLEAR_FEATURE | RH_ENDPOINT:
- switch (wValue) {
- case (RH_ENDPOINT_STALL): OK (0);
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_CLASS:
- switch (wValue) {
- case RH_C_HUB_LOCAL_POWER:
- OK(0);
- case (RH_C_HUB_OVER_CURRENT):
- WR_RH_STAT(RH_HS_OCIC); OK (0);
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
- switch (wValue) {
- case (RH_PORT_ENABLE):
- WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
- case (RH_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
- case (RH_PORT_POWER):
- WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
- case (RH_C_PORT_CONNECTION):
- WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
- case (RH_C_PORT_ENABLE):
- WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
- case (RH_C_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
- case (RH_C_PORT_OVER_CURRENT):
- WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
- case (RH_C_PORT_RESET):
- WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
- }
- break;
-
- case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
- switch (wValue) {
- case (RH_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
- case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
- if (RD_RH_PORTSTAT & RH_PS_CCS)
- WR_RH_PORTSTAT (RH_PS_PRS);
- OK (0);
- case (RH_PORT_POWER):
- WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
- case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
- if (RD_RH_PORTSTAT & RH_PS_CCS)
- WR_RH_PORTSTAT (RH_PS_PES );
- OK (0);
- }
- break;
-
- case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
-
- case RH_GET_DESCRIPTOR:
- switch ((wValue & 0xff00) >> 8) {
- case (0x01): /* device descriptor */
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_dev_des),
- wLength));
- data_buf = root_hub_dev_des; OK(len);
- case (0x02): /* configuration descriptor */
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_config_des),
- wLength));
- data_buf = root_hub_config_des; OK(len);
- case (0x03): /* string descriptors */
- if(wValue==0x0300) {
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_str_index0),
- wLength));
- data_buf = root_hub_str_index0;
- OK(len);
- }
- if(wValue==0x0301) {
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_str_index1),
- wLength));
- data_buf = root_hub_str_index1;
- OK(len);
- }
- default:
- stat = USB_ST_STALLED;
- }
- break;
-
- case RH_GET_DESCRIPTOR | RH_CLASS:
- {
- __u32 temp = roothub_a (&gohci);
-
- data_buf [0] = 9; /* min length; */
- data_buf [1] = 0x29;
- data_buf [2] = temp & RH_A_NDP;
- data_buf [3] = 0;
- if (temp & RH_A_PSM) /* per-port power switching? */
- data_buf [3] |= 0x1;
- if (temp & RH_A_NOCP) /* no overcurrent reporting? */
- data_buf [3] |= 0x10;
- else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
- data_buf [3] |= 0x8;
-
- /* corresponds to data_buf[4-7] */
- datab [1] = 0;
- data_buf [5] = (temp & RH_A_POTPGT) >> 24;
- temp = roothub_b (&gohci);
- data_buf [7] = temp & RH_B_DR;
- if (data_buf [2] < 7) {
- data_buf [8] = 0xff;
- } else {
- data_buf [0] += 2;
- data_buf [8] = (temp & RH_B_DR) >> 8;
- data_buf [10] = data_buf [9] = 0xff;
- }
-
- len = min_t(unsigned int, leni,
- min_t(unsigned int, data_buf [0], wLength));
- OK (len);
- }
-
- case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
-
- case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
-
- default:
- dbg ("unsupported root hub command");
- stat = USB_ST_STALLED;
- }
-
-#ifdef DEBUG
- ohci_dump_roothub (&gohci, 1);
-#endif
-
- len = min_t(int, len, leni);
- if (data != data_buf)
- memcpy (data, data_buf, len);
- dev->act_len = len;
- dev->status = stat;
-
-#ifdef DEBUG
- if (transfer_len)
- urb_priv.actual_length = transfer_len;
- pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
-#endif
-
- return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* common code for handling submit messages - used for all but root hub */
-/* accesses. */
-int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, int interval)
-{
- int stat = 0;
- int maxsize = usb_maxpacket(dev, pipe);
- int timeout;
-
- /* device pulled? Shortcut the action. */
- if (devgone == dev) {
- dev->status = USB_ST_CRC_ERR;
- return 0;
- }
-
-#ifdef DEBUG
- urb_priv.actual_length = 0;
- pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#endif
- if (!maxsize) {
- err("submit_common_message: pipesize for pipe %lx is zero",
- pipe);
- return -1;
- }
-
- if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
- err("sohci_submit_job failed");
- return -1;
- }
-
- /* allow more time for a BULK device to react - some are slow */
-#define BULK_TO 5000 /* timeout in milliseconds */
- if (usb_pipebulk(pipe))
- timeout = BULK_TO;
- else
- timeout = 100;
-
- /* wait for it to complete */
- for (;;) {
- /* check whether the controller is done */
- stat = hc_interrupt();
- if (stat < 0) {
- stat = USB_ST_CRC_ERR;
- break;
- }
-
- /* NOTE: since we are not interrupt driven in U-Boot and always
- * handle only one URB at a time, we cannot assume the
- * transaction finished on the first successful return from
- * hc_interrupt().. unless the flag for current URB is set,
- * meaning that all TD's to/from device got actually
- * transferred and processed. If the current URB is not
- * finished we need to re-iterate this loop so as
- * hc_interrupt() gets called again as there needs to be some
- * more TD's to process still */
- if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
- /* 0xff is returned for an SF-interrupt */
- break;
- }
-
- if (--timeout) {
- mdelay(1);
- if (!urb_finished)
- dbg("\%");
-
- } else {
- err("CTL:TIMEOUT ");
- dbg("submit_common_msg: TO status %x\n", stat);
- stat = USB_ST_CRC_ERR;
- urb_finished = 1;
- break;
- }
- }
-#if 0
- /* we got an Root Hub Status Change interrupt */
- if (got_rhsc) {
-#ifdef DEBUG
- ohci_dump_roothub (&gohci, 1);
-#endif
- got_rhsc = 0;
- /* abuse timeout */
- timeout = rh_check_port_status(&gohci);
- if (timeout >= 0) {
-#if 0 /* this does nothing useful, but leave it here in case that changes */
- /* the called routine adds 1 to the passed value */
- usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
-#endif
- /*
- * XXX
- * This is potentially dangerous because it assumes
- * that only one device is ever plugged in!
- */
- devgone = dev;
- }
- }
-#endif
-
- dev->status = stat;
- dev->act_len = transfer_len;
-
-#ifdef DEBUG
- pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
-#endif
-
- /* free TDs in urb_priv */
- urb_free_priv (&urb_priv);
- return 0;
-}
-
-/* submit routines called from usb.c */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len)
-{
- info("submit_bulk_msg");
- return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup)
-{
- int maxsize = usb_maxpacket(dev, pipe);
-
- info("submit_control_msg");
-#ifdef DEBUG
- urb_priv.actual_length = 0;
- pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#endif
- if (!maxsize) {
- err("submit_control_message: pipesize for pipe %lx is zero",
- pipe);
- return -1;
- }
- if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
- gohci.rh.dev = dev;
- /* root hub - redirect */
- return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
- setup);
- }
-
- return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
-}
-
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, int interval)
-{
- info("submit_int_msg");
- return -1;
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-/* reset the HC and BUS */
-
-static int hc_reset (ohci_t *ohci)
-{
- int timeout = 30;
- int smm_timeout = 50; /* 0,5 sec */
-
- if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
- writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
- info("USB HC TakeOver from SMM");
- while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
- mdelay (10);
- if (--smm_timeout == 0) {
- err("USB HC TakeOver failed!");
- return -1;
- }
- }
- }
-
- /* Disable HC interrupts */
- writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
-
- dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
- ohci->slot_name,
- readl (&ohci->regs->control));
-
- /* Reset USB (needed by some controllers) */
- ohci->hc_control = 0;
- writel (ohci->hc_control, &ohci->regs->control);
-
- /* HC Reset requires max 10 us delay */
- writel (OHCI_HCR, &ohci->regs->cmdstatus);
- while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
- if (--timeout == 0) {
- err("USB HC reset timed out!");
- return -1;
- }
- udelay (1);
- }
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * enable interrupts
- * connect the virtual root hub */
-
-static int hc_start (ohci_t * ohci)
-{
- __u32 mask;
- unsigned int fminterval;
-
- ohci->disabled = 1;
-
- /* Tell the controller where the control and bulk lists are
- * The lists are empty now. */
-
- writel (0, &ohci->regs->ed_controlhead);
- writel (0, &ohci->regs->ed_bulkhead);
-
- writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
-
- fminterval = 0x2edf;
- writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
- fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
- writel (fminterval, &ohci->regs->fminterval);
- writel (0x628, &ohci->regs->lsthresh);
-
- /* start controller operations */
- ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
- ohci->disabled = 0;
- writel (ohci->hc_control, &ohci->regs->control);
-
- /* disable all interrupts */
- mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
- OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
- OHCI_INTR_OC | OHCI_INTR_MIE);
- writel (mask, &ohci->regs->intrdisable);
- /* clear all interrupts */
- mask &= ~OHCI_INTR_MIE;
- writel (mask, &ohci->regs->intrstatus);
- /* Choose the interrupts we care about now - but w/o MIE */
- mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
- writel (mask, &ohci->regs->intrenable);
-
-#ifdef OHCI_USE_NPS
- /* required for AMD-756 and some Mac platforms */
- writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
- &ohci->regs->roothub.a);
- writel (RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif /* OHCI_USE_NPS */
-
- /* POTPGT delay is bits 24-31, in 2 ms units. */
- mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
-
- /* connect the virtual root hub */
- ohci->rh.devnum = 0;
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static int
-hc_interrupt (void)
-{
- ohci_t *ohci = &gohci;
- struct ohci_regs *regs = ohci->regs;
- int ints;
- int stat = -1;
-
- if ((ohci->hcca->done_head != 0) &&
- !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
-
- ints = OHCI_INTR_WDH;
-
- } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) {
- ohci->disabled++;
- err ("%s device removed!", ohci->slot_name);
- return -1;
-
- } else if ((ints &= readl (®s->intrenable)) == 0) {
- dbg("hc_interrupt: returning..\n");
- return 0xff;
- }
-
- /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
-
- if (ints & OHCI_INTR_RHSC) {
- got_rhsc = 1;
- stat = 0xff;
- }
-
- if (ints & OHCI_INTR_UE) {
- ohci->disabled++;
- err ("OHCI Unrecoverable Error, controller usb-%s disabled",
- ohci->slot_name);
- /* e.g. due to PCI Master/Target Abort */
-
-#ifdef DEBUG
- ohci_dump (ohci, 1);
-#endif
- /* FIXME: be optimistic, hope that bug won't repeat often. */
- /* Make some non-interrupt context restart the controller. */
- /* Count and limit the retries though; either hardware or */
- /* software errors can go forever... */
- hc_reset (ohci);
- return -1;
- }
-
- if (ints & OHCI_INTR_WDH) {
- writel (OHCI_INTR_WDH, ®s->intrdisable);
- stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
- writel (OHCI_INTR_WDH, ®s->intrenable);
- }
-
- if (ints & OHCI_INTR_SO) {
- dbg("USB Schedule overrun\n");
- writel (OHCI_INTR_SO, ®s->intrenable);
- stat = -1;
- }
-
- /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
- if (ints & OHCI_INTR_SF) {
- unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
- mdelay(1);
- writel (OHCI_INTR_SF, ®s->intrdisable);
- if (ohci->ed_rm_list[frame] != NULL)
- writel (OHCI_INTR_SF, ®s->intrenable);
- stat = 0xff;
- }
-
- writel (ints, ®s->intrstatus);
- return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------------*/
-
-/* De-allocate all resources.. */
-
-static void hc_release_ohci (ohci_t *ohci)
-{
- dbg ("USB HC release ohci usb-%s", ohci->slot_name);
-
- if (!ohci->disabled)
- hc_reset (ohci);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * low level initalisation routine, called from usb.c
- */
-static char ohci_inited = 0;
-
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
- memset (&gohci, 0, sizeof (ohci_t));
- memset (&urb_priv, 0, sizeof (urb_priv_t));
-
- /* align the storage */
- if ((__u32)&ghcca[0] & 0xff) {
- err("HCCA not aligned!!");
- return -1;
- }
- phcca = &ghcca[0];
- info("aligned ghcca %p", phcca);
- memset(&ohci_dev, 0, sizeof(struct ohci_device));
- if ((__u32)&ohci_dev.ed[0] & 0x7) {
- err("EDs not aligned!!");
- return -1;
- }
- memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
- if ((__u32)gtd & 0x7) {
- err("TDs not aligned!!");
- return -1;
- }
- ptd = gtd;
- gohci.hcca = phcca;
- memset (phcca, 0, sizeof (struct ohci_hcca));
-
- gohci.disabled = 1;
- gohci.sleeping = 0;
- gohci.irq = -1;
-#if defined(CONFIG_440EP)
- gohci.regs = (struct ohci_regs *)(CONFIG_SYS_PERIPHERAL_BASE | 0x1000);
-#elif defined(CONFIG_440EPX) || defined(CONFIG_SYS_USB_HOST)
- gohci.regs = (struct ohci_regs *)(CONFIG_SYS_USB_HOST);
-#endif
-
- gohci.flags = 0;
- gohci.slot_name = "ppc440";
-
- if (hc_reset (&gohci) < 0) {
- hc_release_ohci (&gohci);
- return -1;
- }
-
- if (hc_start (&gohci) < 0) {
- err ("can't start usb-%s", gohci.slot_name);
- hc_release_ohci (&gohci);
- return -1;
- }
-
-#ifdef DEBUG
- ohci_dump (&gohci, 1);
-#endif
- ohci_inited = 1;
- urb_finished = 1;
-
- return 0;
-}
-
-int usb_lowlevel_stop(int index)
-{
- /* this gets called really early - before the controller has */
- /* even been initialized! */
- if (!ohci_inited)
- return 0;
- /* TODO release any interrupts, etc. */
- /* call hc_release_ohci() here ? */
- hc_reset (&gohci);
- return 0;
-}
-
-#endif /* CONFIG_USB_OHCI */
+++ /dev/null
-/*
- * URB OHCI HCD (Host Controller Driver) for USB.
- *
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
- *
- * usb-ohci.h
- */
-
-static int cc_to_error[16] = {
-
-/* mapping of the OHCI CC status to error codes */
- /* No Error */ 0,
- /* CRC Error */ USB_ST_CRC_ERR,
- /* Bit Stuff */ USB_ST_BIT_ERR,
- /* Data Togg */ USB_ST_CRC_ERR,
- /* Stall */ USB_ST_STALLED,
- /* DevNotResp */ -1,
- /* PIDCheck */ USB_ST_BIT_ERR,
- /* UnExpPID */ USB_ST_BIT_ERR,
- /* DataOver */ USB_ST_BUF_ERR,
- /* DataUnder */ USB_ST_BUF_ERR,
- /* reservd */ -1,
- /* reservd */ -1,
- /* BufferOver */ USB_ST_BUF_ERR,
- /* BuffUnder */ USB_ST_BUF_ERR,
- /* Not Access */ -1,
- /* Not Access */ -1
-};
-
-/* ED States */
-
-#define ED_NEW 0x00
-#define ED_UNLINK 0x01
-#define ED_OPER 0x02
-#define ED_DEL 0x04
-#define ED_URB_DEL 0x08
-
-/* usb_ohci_ed */
-struct ed {
- __u32 hwINFO;
- __u32 hwTailP;
- __u32 hwHeadP;
- __u32 hwNextED;
-
- struct ed *ed_prev;
- __u8 int_period;
- __u8 int_branch;
- __u8 int_load;
- __u8 int_interval;
- __u8 state;
- __u8 type;
- __u16 last_iso;
- struct ed *ed_rm_list;
-
- struct usb_device *usb_dev;
- __u32 unused[3];
-} __attribute__((aligned(16)));
-typedef struct ed ed_t;
-
-/* TD info field */
-#define TD_CC 0xf0000000
-#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
-#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
-#define TD_EC 0x0C000000
-#define TD_T 0x03000000
-#define TD_T_DATA0 0x02000000
-#define TD_T_DATA1 0x03000000
-#define TD_T_TOGGLE 0x00000000
-#define TD_R 0x00040000
-#define TD_DI 0x00E00000
-#define TD_DI_SET(X) (((X) & 0x07)<< 21)
-#define TD_DP 0x00180000
-#define TD_DP_SETUP 0x00000000
-#define TD_DP_IN 0x00100000
-#define TD_DP_OUT 0x00080000
-
-#define TD_ISO 0x00010000
-#define TD_DEL 0x00020000
-
-/* CC Codes */
-#define TD_CC_NOERROR 0x00
-#define TD_CC_CRC 0x01
-#define TD_CC_BITSTUFFING 0x02
-#define TD_CC_DATATOGGLEM 0x03
-#define TD_CC_STALL 0x04
-#define TD_DEVNOTRESP 0x05
-#define TD_PIDCHECKFAIL 0x06
-#define TD_UNEXPECTEDPID 0x07
-#define TD_DATAOVERRUN 0x08
-#define TD_DATAUNDERRUN 0x09
-#define TD_BUFFEROVERRUN 0x0C
-#define TD_BUFFERUNDERRUN 0x0D
-#define TD_NOTACCESSED 0x0F
-
-#define MAXPSW 1
-
-struct td {
- __u32 hwINFO;
- __u32 hwCBP; /* Current Buffer Pointer */
- __u32 hwNextTD; /* Next TD Pointer */
- __u32 hwBE; /* Memory Buffer End Pointer */
-
- __u16 hwPSW[MAXPSW];
- __u8 unused;
- __u8 index;
- struct ed *ed;
- struct td *next_dl_td;
- struct usb_device *usb_dev;
- int transfer_len;
- __u32 data;
-
- __u32 unused2[2];
-} __attribute__((aligned(32)));
-typedef struct td td_t;
-
-#define OHCI_ED_SKIP (1 << 14)
-
-/*
- * The HCCA (Host Controller Communications Area) is a 256 byte
- * structure defined in the OHCI spec. that the host controller is
- * told the base address of. It must be 256-byte aligned.
- */
-
-#define NUM_INTS 32 /* part of the OHCI standard */
-struct ohci_hcca {
- __u32 int_table[NUM_INTS]; /* Interrupt ED table */
- __u16 frame_no; /* current frame number */
- __u16 pad1; /* set to 0 on each frame_no change */
- __u32 done_head; /* info returned for an interrupt */
- u8 reserved_for_hc[116];
-} __attribute__((aligned(256)));
-
-/*
- * Maximum number of root hub ports.
- */
-#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O
- * region. This is Memory Mapped I/O. You must use the readl() and
- * writel() macros defined in asm/io.h to access these!!
- */
-struct ohci_regs {
- /* control and status registers */
- __u32 revision;
- __u32 control;
- __u32 cmdstatus;
- __u32 intrstatus;
- __u32 intrenable;
- __u32 intrdisable;
- /* memory pointers */
- __u32 hcca;
- __u32 ed_periodcurrent;
- __u32 ed_controlhead;
- __u32 ed_controlcurrent;
- __u32 ed_bulkhead;
- __u32 ed_bulkcurrent;
- __u32 donehead;
- /* frame counters */
- __u32 fminterval;
- __u32 fmremaining;
- __u32 fmnumber;
- __u32 periodicstart;
- __u32 lsthresh;
- /* Root hub ports */
- struct ohci_roothub_regs {
- __u32 a;
- __u32 b;
- __u32 status;
- __u32 portstatus[MAX_ROOT_PORTS];
- } roothub;
-} __attribute__((aligned(32)));
-
-/* OHCI CONTROL AND STATUS REGISTER MASKS */
-
-/*
- * HcControl (control) register masks
- */
-#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
-#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
-#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
-#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
-#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
-#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
-#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
-#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
-#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
-
-/* pre-shifted values for HCFS */
-# define OHCI_USB_RESET (0 << 6)
-# define OHCI_USB_RESUME (1 << 6)
-# define OHCI_USB_OPER (2 << 6)
-# define OHCI_USB_SUSPEND (3 << 6)
-
-/*
- * HcCommandStatus (cmdstatus) register masks
- */
-#define OHCI_HCR (1 << 0) /* host controller reset */
-#define OHCI_CLF (1 << 1) /* control list filled */
-#define OHCI_BLF (1 << 2) /* bulk list filled */
-#define OHCI_OCR (1 << 3) /* ownership change request */
-#define OHCI_SOC (3 << 16) /* scheduling overrun count */
-
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
-#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
-#define OHCI_INTR_SF (1 << 2) /* start frame */
-#define OHCI_INTR_RD (1 << 3) /* resume detect */
-#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
-#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
-#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
-#define OHCI_INTR_OC (1 << 30) /* ownership change */
-#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
-
-/* Virtual Root HUB */
-struct virt_root_hub {
- int devnum; /* Address of Root Hub endpoint */
- void *dev; /* was urb */
- void *int_addr;
- int send;
- int interval;
-};
-
-/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
-
-/* destination of request */
-#define RH_INTERFACE 0x01
-#define RH_ENDPOINT 0x02
-#define RH_OTHER 0x03
-
-#define RH_CLASS 0x20
-#define RH_VENDOR 0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS 0x0080
-#define RH_CLEAR_FEATURE 0x0100
-#define RH_SET_FEATURE 0x0300
-#define RH_SET_ADDRESS 0x0500
-#define RH_GET_DESCRIPTOR 0x0680
-#define RH_SET_DESCRIPTOR 0x0700
-#define RH_GET_CONFIGURATION 0x0880
-#define RH_SET_CONFIGURATION 0x0900
-#define RH_GET_STATE 0x0280
-#define RH_GET_INTERFACE 0x0A80
-#define RH_SET_INTERFACE 0x0B00
-#define RH_SYNC_FRAME 0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP 0x2000
-
-/* Hub port features */
-#define RH_PORT_CONNECTION 0x00
-#define RH_PORT_ENABLE 0x01
-#define RH_PORT_SUSPEND 0x02
-#define RH_PORT_OVER_CURRENT 0x03
-#define RH_PORT_RESET 0x04
-#define RH_PORT_POWER 0x08
-#define RH_PORT_LOW_SPEED 0x09
-
-#define RH_C_PORT_CONNECTION 0x10
-#define RH_C_PORT_ENABLE 0x11
-#define RH_C_PORT_SUSPEND 0x12
-#define RH_C_PORT_OVER_CURRENT 0x13
-#define RH_C_PORT_RESET 0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER 0x00
-#define RH_C_HUB_OVER_CURRENT 0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL 0x01
-
-#define RH_ACK 0x01
-#define RH_REQ_ERR -1
-#define RH_NACK 0x00
-
-/* OHCI ROOT HUB REGISTER MASKS */
-
-/* roothub.portstatus [i] bits */
-#define RH_PS_CCS 0x00000001 /* current connect status */
-#define RH_PS_PES 0x00000002 /* port enable status */
-#define RH_PS_PSS 0x00000004 /* port suspend status */
-#define RH_PS_POCI 0x00000008 /* port over current indicator */
-#define RH_PS_PRS 0x00000010 /* port reset status */
-#define RH_PS_PPS 0x00000100 /* port power status */
-#define RH_PS_LSDA 0x00000200 /* low speed device attached */
-#define RH_PS_CSC 0x00010000 /* connect status change */
-#define RH_PS_PESC 0x00020000 /* port enable status change */
-#define RH_PS_PSSC 0x00040000 /* port suspend status change */
-#define RH_PS_OCIC 0x00080000 /* over current indicator change */
-#define RH_PS_PRSC 0x00100000 /* port reset status change */
-
-/* roothub.status bits */
-#define RH_HS_LPS 0x00000001 /* local power status */
-#define RH_HS_OCI 0x00000002 /* over current indicator */
-#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
-#define RH_HS_LPSC 0x00010000 /* local power status change */
-#define RH_HS_OCIC 0x00020000 /* over current indicator change */
-#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
-
-/* roothub.b masks */
-#define RH_B_DR 0x0000ffff /* device removable flags */
-#define RH_B_PPCM 0xffff0000 /* port power control mask */
-
-/* roothub.a masks */
-#define RH_A_NDP (0xff << 0) /* number of downstream ports */
-#define RH_A_PSM (1 << 8) /* power switching mode */
-#define RH_A_NPS (1 << 9) /* no power switching */
-#define RH_A_DT (1 << 10) /* device type (mbz) */
-#define RH_A_OCPM (1 << 11) /* over current protection mode */
-#define RH_A_NOCP (1 << 12) /* no over current protection */
-#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
-
-/* urb */
-#define N_URB_TD 48
-typedef struct {
- ed_t *ed;
- __u16 length; /* number of tds associated with this request */
- __u16 td_cnt; /* number of tds already serviced */
- int state;
- unsigned long pipe;
- int actual_length;
- td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
-} urb_priv_t;
-#define URB_DEL 1
-
-/*
- * This is the full ohci controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-typedef struct ohci {
- struct ohci_hcca *hcca; /* hcca */
- /*dma_addr_t hcca_dma; */
-
- int irq;
- int disabled; /* e.g. got a UE, we're hung */
- int sleeping;
- unsigned long flags; /* for HC bugs */
-
- struct ohci_regs *regs; /* OHCI controller's memory */
-
- ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
- ed_t *ed_bulktail; /* last endpoint of bulk list */
- ed_t *ed_controltail; /* last endpoint of control list */
- int intrstatus;
- __u32 hc_control; /* copy of the hc control reg */
- struct usb_device *dev[32];
- struct virt_root_hub rh;
-
- const char *slot_name;
-} ohci_t;
-
-#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
-
-struct ohci_device {
- ed_t ed[NUM_EDS];
- int ed_cnt;
-};
-
-/* hcd */
-/* endpoint */
-static int ep_link(ohci_t * ohci, ed_t * ed);
-static int ep_unlink(ohci_t * ohci, ed_t * ed);
-static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
-
-/*-------------------------------------------------------------------------*/
-
-/* we need more TDs than EDs */
-#define NUM_TD 64
-
-/* +1 so we can align the storage */
-td_t gtd[NUM_TD + 1];
-/* pointers to aligned storage */
-td_t *ptd;
-
-/* TDs ... */
-static inline struct td *td_alloc(struct usb_device *usb_dev)
-{
- int i;
- struct td *td;
-
- td = NULL;
- for (i = 0; i < NUM_TD; i++) {
- if (ptd[i].usb_dev == NULL) {
- td = &ptd[i];
- td->usb_dev = usb_dev;
- break;
- }
- }
-
- return td;
-}
-
-static inline void ed_free(struct ed *ed)
-{
- ed->usb_dev = NULL;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
- * SPDX-License-Identifier: GPL-2.0+
-*/
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/interrupt.h>
-#include <asm/ppc4xx.h>
-#include <ppc_asm.tmpl>
-#include <asm/io.h>
-#include <asm/xilinx_irq.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void pic_enable(void)
-{
- debug("Xilinx PIC at 0x%8x\n", intc);
-
- /*
- * Disable all external interrupts until they are
- * explicitly requested.
- */
- out_be32((u32 *) IER, 0);
-
- /* Acknowledge any pending interrupts just in case. */
- out_be32((u32 *) IAR, 0xffffffff);
-
- /* Turn on the Master Enable. */
- out_be32((u32 *) MER, 0x3UL);
-
- return;
-}
-
-int xilinx_pic_irq_get(void)
-{
- u32 irq;
- irq = in_be32((u32 *) IVR);
-
- /* If no interrupt is pending then all bits of the IVR are set to 1. As
- * the IVR is as many bits wide as numbers of inputs are available.
- * Therefore, if all bits of the IVR are set to one, its content will
- * be bigger than XPAR_INTC_MAX_NUM_INTR_INPUTS.
- */
- if (irq >= XPAR_INTC_MAX_NUM_INTR_INPUTS)
- irq = -1; /* report no pending interrupt. */
-
- debug("get_irq: %d\n", irq);
- return (irq);
-}
-
-void pic_irq_enable(unsigned int irq)
-{
- u32 mask = IRQ_MASK(irq);
- debug("enable: %d\n", irq);
- out_be32((u32 *) SIE, mask);
-}
-
-void pic_irq_disable(unsigned int irq)
-{
- u32 mask = IRQ_MASK(irq);
- debug("disable: %d\n", irq);
- out_be32((u32 *) CIE, mask);
-}
-
-void pic_irq_ack(unsigned int irq)
-{
- u32 mask = IRQ_MASK(irq);
- debug("ack: %d\n", irq);
- out_be32((u32 *) IAR, mask);
-}
-
-void external_interrupt(struct pt_regs *regs)
-{
- int irq;
-
- irq = xilinx_pic_irq_get();
- if (irq < 0)
- return;
-
- interrupt_run_handler(irq);
-
- return;
-}
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb
-dtb-$(CONFIG_TARGET_XILINX_PPC440_GENERIC) += xilinx-ppc440-generic.dtb
-dtb-$(CONFIG_TARGET_XILINX_PPC405_GENERIC) += xilinx-ppc405-generic.dtb
-
-targets += $(dtb-y)
-
-DTC_FLAGS += -R 4 -p 0x1000
-
-PHONY += dtbs
-dtbs: $(addprefix $(obj)/, $(dtb-y))
- @:
-
-clean-files := *.dtb
+++ /dev/null
-/*
- * Device Tree Source for AMCC Arches (dual 460GT board)
- *
- * (C) Copyright 2008 Applied Micro Circuits Corporation
- * Victor Gallardo <vgallardo@amcc.com>
- * Adam Graham <agraham@amcc.com>
- *
- * Based on the glacier.dts file
- * Stefan Roese <sr@denx.de>
- * Copyright 2008 DENX Software Engineering
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <2>;
- #size-cells = <1>;
- model = "amcc,arches";
- compatible = "amcc,arches";
- dcr-parent = <&{/cpus/cpu@0}>;
-
- aliases {
- ethernet0 = &EMAC0;
- ethernet1 = &EMAC1;
- ethernet2 = &EMAC2;
- serial0 = &UART0;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,460GT";
- reg = <0x00000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- timebase-frequency = <0>; /* Filled in by U-Boot */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <32768>;
- d-cache-size = <32768>;
- dcr-controller;
- dcr-access-method = "native";
- next-level-cache = <&L2C0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
- };
-
- UIC0: interrupt-controller0 {
- compatible = "ibm,uic-460gt","ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- UIC1: interrupt-controller1 {
- compatible = "ibm,uic-460gt","ibm,uic";
- interrupt-controller;
- cell-index = <1>;
- dcr-reg = <0x0d0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC2: interrupt-controller2 {
- compatible = "ibm,uic-460gt","ibm,uic";
- interrupt-controller;
- cell-index = <2>;
- dcr-reg = <0x0e0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC3: interrupt-controller3 {
- compatible = "ibm,uic-460gt","ibm,uic";
- interrupt-controller;
- cell-index = <3>;
- dcr-reg = <0x0f0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- SDR0: sdr {
- compatible = "ibm,sdr-460gt";
- dcr-reg = <0x00e 0x002>;
- };
-
- CPR0: cpr {
- compatible = "ibm,cpr-460gt";
- dcr-reg = <0x00c 0x002>;
- };
-
- L2C0: l2c {
- compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
- dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
- 0x030 0x008>; /* L2 cache DCR's */
- cache-line-size = <32>; /* 32 bytes */
- cache-size = <262144>; /* L2, 256K */
- interrupt-parent = <&UIC1>;
- interrupts = <11 1>;
- };
-
- plb {
- compatible = "ibm,plb-460gt", "ibm,plb4";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- SDRAM0: sdram {
- compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
- dcr-reg = <0x010 0x002>;
- };
-
- CRYPTO: crypto@180000 {
- compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
- reg = <4 0x00180000 0x80400>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1d 0x4>;
- };
-
- MAL0: mcmal {
- compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <3>;
- num-rx-chans = <24>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-parent = <&UIC2>;
- interrupts = < /*TXEOB*/ 0x6 0x4
- /*RXEOB*/ 0x7 0x4
- /*SERR*/ 0x3 0x4
- /*TXDE*/ 0x4 0x4
- /*RXDE*/ 0x5 0x4>;
- desc-base-addr-high = <0x8>;
- };
-
- POB0: opb {
- compatible = "ibm,opb-460gt", "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- EBC0: ebc {
- compatible = "ibm,ebc-460gt", "ibm,ebc";
- dcr-reg = <0x012 0x002>;
- #address-cells = <2>;
- #size-cells = <1>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- /* ranges property is supplied by U-Boot */
- interrupts = <0x6 0x4>;
- interrupt-parent = <&UIC1>;
-
- nor_flash@0,0 {
- compatible = "amd,s29gl256n", "cfi-flash";
- bank-width = <2>;
- reg = <0x00000000 0x00000000 0x02000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "kernel";
- reg = <0x00000000 0x001e0000>;
- };
- partition@1e0000 {
- label = "dtb";
- reg = <0x001e0000 0x00020000>;
- };
- partition@200000 {
- label = "root";
- reg = <0x00200000 0x00200000>;
- };
- partition@400000 {
- label = "user";
- reg = <0x00400000 0x01b60000>;
- };
- partition@1f60000 {
- label = "env";
- reg = <0x01f60000 0x00040000>;
- };
- partition@1fa0000 {
- label = "u-boot";
- reg = <0x01fa0000 0x00060000>;
- };
- };
- };
-
- UART0: serial@ef600300 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600300 0x00000008>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC1>;
- interrupts = <0x1 0x4>;
- };
-
- IIC0: i2c@ef600700 {
- compatible = "ibm,iic-460gt", "ibm,iic";
- reg = <0xef600700 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x2 0x4>;
- #address-cells = <1>;
- #size-cells = <0>;
- sttm@4a {
- compatible = "ad,ad7414";
- reg = <0x4a>;
- interrupt-parent = <&UIC1>;
- interrupts = <0x0 0x8>;
- };
- };
-
- IIC1: i2c@ef600800 {
- compatible = "ibm,iic-460gt", "ibm,iic";
- reg = <0xef600800 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x3 0x4>;
- };
-
- TAH0: emac-tah@ef601350 {
- compatible = "ibm,tah-460gt", "ibm,tah";
- reg = <0xef601350 0x00000030>;
- };
-
- TAH1: emac-tah@ef601450 {
- compatible = "ibm,tah-460gt", "ibm,tah";
- reg = <0xef601450 0x00000030>;
- };
-
- EMAC0: ethernet@ef600e00 {
- device_type = "network";
- compatible = "ibm,emac-460gt", "ibm,emac4sync";
- interrupt-parent = <&EMAC0>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
- /*Wake*/ 0x1 &UIC2 0x14 0x4>;
- reg = <0xef600e00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- phy-mode = "sgmii";
- phy-map = <0xffffffff>;
- gpcs-address = <0x0000000a>;
- tah-device = <&TAH0>;
- tah-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
-
- EMAC1: ethernet@ef600f00 {
- device_type = "network";
- compatible = "ibm,emac-460gt", "ibm,emac4sync";
- interrupt-parent = <&EMAC1>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
- /*Wake*/ 0x1 &UIC2 0x15 0x4>;
- reg = <0xef600f00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <1>;
- mal-rx-channel = <8>;
- cell-index = <1>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- phy-mode = "sgmii";
- phy-map = <0x00000000>;
- gpcs-address = <0x0000000b>;
- tah-device = <&TAH1>;
- tah-channel = <1>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- mdio-device = <&EMAC0>;
- };
-
- EMAC2: ethernet@ef601100 {
- device_type = "network";
- compatible = "ibm,emac-460gt", "ibm,emac4sync";
- interrupt-parent = <&EMAC2>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
- /*Wake*/ 0x1 &UIC2 0x16 0x4>;
- reg = <0xef601100 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <2>;
- mal-rx-channel = <16>;
- cell-index = <2>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- tx-fifo-size-gige = <16384>; /* emac2&3 only */
- phy-mode = "sgmii";
- phy-map = <0x00000001>;
- gpcs-address = <0x0000000C>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- mdio-device = <&EMAC0>;
- };
- };
- };
-};
+++ /dev/null
-/*
- * Device Tree Source for AMCC Canyonlands (460EX)
- *
- * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <2>;
- #size-cells = <1>;
- model = "amcc,canyonlands";
- compatible = "amcc,canyonlands";
- dcr-parent = <&{/cpus/cpu@0}>;
-
- aliases {
- ethernet0 = &EMAC0;
- ethernet1 = &EMAC1;
- serial0 = &UART0;
- serial1 = &UART1;
- };
-
- chosen {
- stdout-path = &UART0;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,460EX";
- reg = <0x00000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- timebase-frequency = <0>; /* Filled in by U-Boot */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <32768>;
- d-cache-size = <32768>;
- dcr-controller;
- dcr-access-method = "native";
- next-level-cache = <&L2C0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
- };
-
- UIC0: interrupt-controller0 {
- compatible = "ibm,uic-460ex","ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- UIC1: interrupt-controller1 {
- compatible = "ibm,uic-460ex","ibm,uic";
- interrupt-controller;
- cell-index = <1>;
- dcr-reg = <0x0d0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC2: interrupt-controller2 {
- compatible = "ibm,uic-460ex","ibm,uic";
- interrupt-controller;
- cell-index = <2>;
- dcr-reg = <0x0e0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC3: interrupt-controller3 {
- compatible = "ibm,uic-460ex","ibm,uic";
- interrupt-controller;
- cell-index = <3>;
- dcr-reg = <0x0f0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- SDR0: sdr {
- compatible = "ibm,sdr-460ex";
- dcr-reg = <0x00e 0x002>;
- };
-
- CPR0: cpr {
- compatible = "ibm,cpr-460ex";
- dcr-reg = <0x00c 0x002>;
- };
-
- CPM0: cpm {
- compatible = "ibm,cpm";
- dcr-access-method = "native";
- dcr-reg = <0x160 0x003>;
- unused-units = <0x00000100>;
- idle-doze = <0x02000000>;
- standby = <0xfeff791d>;
- };
-
- L2C0: l2c {
- compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
- dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
- 0x030 0x008>; /* L2 cache DCR's */
- cache-line-size = <32>; /* 32 bytes */
- cache-size = <262144>; /* L2, 256K */
- interrupt-parent = <&UIC1>;
- interrupts = <11 1>;
- };
-
- plb {
- compatible = "ibm,plb-460ex", "ibm,plb4";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- SDRAM0: sdram {
- compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
- dcr-reg = <0x010 0x002>;
- };
-
- CRYPTO: crypto@180000 {
- compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
- reg = <4 0x00180000 0x80400>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1d 0x4>;
- };
-
- HWRNG: hwrng@110000 {
- compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
- reg = <4 0x00110000 0x50>;
- };
-
- MAL0: mcmal {
- compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <2>;
- num-rx-chans = <16>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-parent = <&UIC2>;
- interrupts = < /*TXEOB*/ 0x6 0x4
- /*RXEOB*/ 0x7 0x4
- /*SERR*/ 0x3 0x4
- /*TXDE*/ 0x4 0x4
- /*RXDE*/ 0x5 0x4>;
- };
-
- USB0: ehci@bffd0400 {
- compatible = "ibm,usb-ehci-460ex", "usb-ehci";
- interrupt-parent = <&UIC2>;
- interrupts = <0x1d 4>;
- reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
- };
-
- USB1: usb@bffd0000 {
- compatible = "ohci-le";
- reg = <4 0xbffd0000 0x60>;
- interrupt-parent = <&UIC2>;
- interrupts = <0x1e 4>;
- };
-
- USBOTG0: usbotg@bff80000 {
- compatible = "amcc,dwc-otg";
- reg = <0x4 0xbff80000 0x10000>;
- interrupt-parent = <&USBOTG0>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupts = <0x0 0x1 0x2>;
- interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
- /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
- /* DMA */ 0x2 &UIC0 0xc 0x4>;
- };
-
- SATA0: sata@bffd1000 {
- compatible = "amcc,sata-460ex";
- reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
- interrupt-parent = <&UIC3>;
- interrupts = <0x0 0x4 /* SATA */
- 0x5 0x4>; /* AHBDMA */
- };
-
- POB0: opb {
- compatible = "ibm,opb-460ex", "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- EBC0: ebc {
- compatible = "ibm,ebc-460ex", "ibm,ebc";
- dcr-reg = <0x012 0x002>;
- #address-cells = <2>;
- #size-cells = <1>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- /* ranges property is supplied by U-Boot */
- interrupts = <0x6 0x4>;
- interrupt-parent = <&UIC1>;
-
- nor_flash@0,0 {
- compatible = "amd,s29gl512n", "cfi-flash";
- bank-width = <2>;
- reg = <0x00000000 0x00000000 0x04000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "kernel";
- reg = <0x00000000 0x001e0000>;
- };
- partition@1e0000 {
- label = "dtb";
- reg = <0x001e0000 0x00020000>;
- };
- partition@200000 {
- label = "ramdisk";
- reg = <0x00200000 0x01400000>;
- };
- partition@1600000 {
- label = "jffs2";
- reg = <0x01600000 0x00400000>;
- };
- partition@1a00000 {
- label = "user";
- reg = <0x01a00000 0x02560000>;
- };
- partition@3f60000 {
- label = "env";
- reg = <0x03f60000 0x00040000>;
- };
- partition@3fa0000 {
- label = "u-boot";
- reg = <0x03fa0000 0x00060000>;
- };
- };
-
- cpld@2,0 {
- compatible = "amcc,ppc460ex-bcsr";
- reg = <2 0x0 0x9>;
- };
-
- ndfc@3,0 {
- compatible = "ibm,ndfc";
- reg = <0x00000003 0x00000000 0x00002000>;
- ccr = <0x00001000>;
- bank-settings = <0x80002222>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- nand {
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x00000000 0x00100000>;
- };
- partition@100000 {
- label = "user";
- reg = <0x00000000 0x03f00000>;
- };
- };
- };
- };
-
- UART0: serial@ef600300 {
- device_type = "serial";
- reg-shift = <0>;
- compatible = "ns16550";
- reg = <0xef600300 0x00000008>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC1>;
- interrupts = <0x1 0x4>;
- };
-
- UART1: serial@ef600400 {
- device_type = "serial";
- reg-shift = <0>;
- compatible = "ns16550";
- reg = <0xef600400 0x00000008>;
- virtual-reg = <0xef600400>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC0>;
- interrupts = <0x1 0x4>;
- };
-
- IIC0: i2c@ef600700 {
- compatible = "ibm,iic-460ex", "ibm,iic";
- reg = <0xef600700 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x2 0x4>;
- #address-cells = <1>;
- #size-cells = <0>;
- rtc@68 {
- compatible = "stm,m41t80";
- reg = <0x68>;
- interrupt-parent = <&UIC2>;
- interrupts = <0x19 0x8>;
- };
- sttm@48 {
- compatible = "ad,ad7414";
- reg = <0x48>;
- interrupt-parent = <&UIC1>;
- interrupts = <0x14 0x8>;
- };
- };
-
- IIC1: i2c@ef600800 {
- compatible = "ibm,iic-460ex", "ibm,iic";
- reg = <0xef600800 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x3 0x4>;
- };
-
- GPIO0: gpio@ef600b00 {
- compatible = "ibm,ppc4xx-gpio";
- reg = <0xef600b00 0x00000048>;
- gpio-controller;
- };
-
- ZMII0: emac-zmii@ef600d00 {
- compatible = "ibm,zmii-460ex", "ibm,zmii";
- reg = <0xef600d00 0x0000000c>;
- };
-
- RGMII0: emac-rgmii@ef601500 {
- compatible = "ibm,rgmii-460ex", "ibm,rgmii";
- reg = <0xef601500 0x00000008>;
- has-mdio;
- };
-
- TAH0: emac-tah@ef601350 {
- compatible = "ibm,tah-460ex", "ibm,tah";
- reg = <0xef601350 0x00000030>;
- };
-
- TAH1: emac-tah@ef601450 {
- compatible = "ibm,tah-460ex", "ibm,tah";
- reg = <0xef601450 0x00000030>;
- };
-
- EMAC0: ethernet@ef600e00 {
- device_type = "network";
- compatible = "ibm,emac-460ex", "ibm,emac4sync";
- interrupt-parent = <&EMAC0>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
- /*Wake*/ 0x1 &UIC2 0x14 0x4>;
- reg = <0xef600e00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <0>;
- tah-device = <&TAH0>;
- tah-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
-
- EMAC1: ethernet@ef600f00 {
- device_type = "network";
- compatible = "ibm,emac-460ex", "ibm,emac4sync";
- interrupt-parent = <&EMAC1>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
- /*Wake*/ 0x1 &UIC2 0x15 0x4>;
- reg = <0xef600f00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <1>;
- mal-rx-channel = <8>;
- cell-index = <1>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <1>;
- tah-device = <&TAH1>;
- tah-channel = <1>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- mdio-device = <&EMAC0>;
- };
- };
-
- PCIX0: pci@c0ec00000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
- primary;
- large-inbound-windows;
- enable-msi-hole;
- reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
- 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
- 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
- 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
- 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
- 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
- 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 0 to 0x3f */
- bus-range = <0x0 0x3f>;
-
- /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
- interrupt-map-mask = <0x0 0x0 0x0 0x0>;
- interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
- };
-
- PCIE0: pciex@d00000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
- primary;
- port = <0x0>; /* port number */
- reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
- 0x0000000c 0x08010000 0x00001000>; /* Registers */
- dcr-reg = <0x100 0x020>;
- sdr-base = <0x300>;
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 40 to 0x7f */
- bus-range = <0x40 0x7f>;
-
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
- };
-
- PCIE1: pciex@d20000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
- primary;
- port = <0x1>; /* port number */
- reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
- 0x0000000c 0x08011000 0x00001000>; /* Registers */
- dcr-reg = <0x120 0x020>;
- sdr-base = <0x340>;
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 80 to 0xbf */
- bus-range = <0x80 0xbf>;
-
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
- };
-
- MSI: ppc4xx-msi@C10000000 {
- compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
- reg = < 0xC 0x10000000 0x100>;
- sdr-base = <0x36C>;
- msi-data = <0x00000000>;
- msi-mask = <0x44440000>;
- interrupt-count = <3>;
- interrupts = <0 1 2 3>;
- interrupt-parent = <&UIC3>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0 &UIC3 0x18 1
- 1 &UIC3 0x19 1
- 2 &UIC3 0x1A 1
- 3 &UIC3 0x1B 1>;
- };
- };
-};
+++ /dev/null
-/*
- * Device Tree Source for AMCC Glacier (460GT)
- *
- * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <2>;
- #size-cells = <1>;
- model = "amcc,glacier";
- compatible = "amcc,glacier";
- dcr-parent = <&{/cpus/cpu@0}>;
-
- aliases {
- ethernet0 = &EMAC0;
- ethernet1 = &EMAC1;
- ethernet2 = &EMAC2;
- ethernet3 = &EMAC3;
- serial0 = &UART0;
- serial1 = &UART1;
- };
-
- chosen {
- stdout-path = &UART0;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,460GT";
- reg = <0x00000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- timebase-frequency = <0>; /* Filled in by U-Boot */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <32768>;
- d-cache-size = <32768>;
- dcr-controller;
- dcr-access-method = "native";
- next-level-cache = <&L2C0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
- };
-
- UIC0: interrupt-controller0 {
- compatible = "ibm,uic-460gt","ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- UIC1: interrupt-controller1 {
- compatible = "ibm,uic-460gt","ibm,uic";
- interrupt-controller;
- cell-index = <1>;
- dcr-reg = <0x0d0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC2: interrupt-controller2 {
- compatible = "ibm,uic-460gt","ibm,uic";
- interrupt-controller;
- cell-index = <2>;
- dcr-reg = <0x0e0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC3: interrupt-controller3 {
- compatible = "ibm,uic-460gt","ibm,uic";
- interrupt-controller;
- cell-index = <3>;
- dcr-reg = <0x0f0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- SDR0: sdr {
- compatible = "ibm,sdr-460gt";
- dcr-reg = <0x00e 0x002>;
- };
-
- CPR0: cpr {
- compatible = "ibm,cpr-460gt";
- dcr-reg = <0x00c 0x002>;
- };
-
- L2C0: l2c {
- compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
- dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
- 0x030 0x008>; /* L2 cache DCR's */
- cache-line-size = <32>; /* 32 bytes */
- cache-size = <262144>; /* L2, 256K */
- interrupt-parent = <&UIC1>;
- interrupts = <11 1>;
- };
-
- plb {
- compatible = "ibm,plb-460gt", "ibm,plb4";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- SDRAM0: sdram {
- compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
- dcr-reg = <0x010 0x002>;
- };
-
- CRYPTO: crypto@180000 {
- compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto",
- "amcc,ppc4xx-crypto";
- reg = <4 0x00180000 0x80400>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1d 0x4>;
- };
-
- HWRNG: hwrng@110000 {
- compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
- reg = <4 0x00110000 0x50>;
- };
-
- MAL0: mcmal {
- compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <4>;
- num-rx-chans = <32>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-parent = <&UIC2>;
- interrupts = < /*TXEOB*/ 0x6 0x4
- /*RXEOB*/ 0x7 0x4
- /*SERR*/ 0x3 0x4
- /*TXDE*/ 0x4 0x4
- /*RXDE*/ 0x5 0x4>;
- desc-base-addr-high = <0x8>;
- };
-
- POB0: opb {
- compatible = "ibm,opb-460gt", "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- EBC0: ebc {
- compatible = "ibm,ebc-460gt", "ibm,ebc";
- dcr-reg = <0x012 0x002>;
- #address-cells = <2>;
- #size-cells = <1>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- /* ranges property is supplied by U-Boot */
- interrupts = <0x6 0x4>;
- interrupt-parent = <&UIC1>;
-
- nor_flash@0,0 {
- compatible = "amd,s29gl512n", "cfi-flash";
- bank-width = <2>;
- reg = <0x00000000 0x00000000 0x04000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "kernel";
- reg = <0x00000000 0x001e0000>;
- };
- partition@1e0000 {
- label = "dtb";
- reg = <0x001e0000 0x00020000>;
- };
- partition@200000 {
- label = "ramdisk";
- reg = <0x00200000 0x01400000>;
- };
- partition@1600000 {
- label = "jffs2";
- reg = <0x01600000 0x00400000>;
- };
- partition@1a00000 {
- label = "user";
- reg = <0x01a00000 0x02560000>;
- };
- partition@3f60000 {
- label = "env";
- reg = <0x03f60000 0x00040000>;
- };
- partition@3fa0000 {
- label = "u-boot";
- reg = <0x03fa0000 0x00060000>;
- };
- };
-
- ndfc@3,0 {
- compatible = "ibm,ndfc";
- reg = <0x00000003 0x00000000 0x00002000>;
- ccr = <0x00001000>;
- bank-settings = <0x80002222>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- nand {
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x00000000 0x00100000>;
- };
- partition@100000 {
- label = "user";
- reg = <0x00000000 0x03f00000>;
- };
- };
- };
- };
-
- UART0: serial@ef600300 {
- device_type = "serial";
- reg-shift = <0>;
- compatible = "ns16550";
- reg = <0xef600300 0x00000008>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC1>;
- interrupts = <0x1 0x4>;
- };
-
- UART1: serial@ef600400 {
- device_type = "serial";
- reg-shift = <0>;
- compatible = "ns16550";
- reg = <0xef600400 0x00000008>;
- virtual-reg = <0xef600400>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC0>;
- interrupts = <0x1 0x4>;
- };
-
- UART2: serial@ef600500 {
- device_type = "serial";
- reg-shift = <0>;
- compatible = "ns16550";
- reg = <0xef600500 0x00000008>;
- virtual-reg = <0xef600500>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC1>;
- interrupts = <28 0x4>;
- };
-
- UART3: serial@ef600600 {
- device_type = "serial";
- reg-shift = <0>;
- compatible = "ns16550";
- reg = <0xef600600 0x00000008>;
- virtual-reg = <0xef600600>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC1>;
- interrupts = <29 0x4>;
- };
-
- IIC0: i2c@ef600700 {
- compatible = "ibm,iic-460gt", "ibm,iic";
- reg = <0xef600700 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x2 0x4>;
- #address-cells = <1>;
- #size-cells = <0>;
- rtc@68 {
- compatible = "stm,m41t80";
- reg = <0x68>;
- interrupt-parent = <&UIC2>;
- interrupts = <0x19 0x8>;
- };
- sttm@48 {
- compatible = "ad,ad7414";
- reg = <0x48>;
- interrupt-parent = <&UIC1>;
- interrupts = <0x14 0x8>;
- };
- };
-
- IIC1: i2c@ef600800 {
- compatible = "ibm,iic-460gt", "ibm,iic";
- reg = <0xef600800 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x3 0x4>;
- };
-
- ZMII0: emac-zmii@ef600d00 {
- compatible = "ibm,zmii-460gt", "ibm,zmii";
- reg = <0xef600d00 0x0000000c>;
- };
-
- RGMII0: emac-rgmii@ef601500 {
- compatible = "ibm,rgmii-460gt", "ibm,rgmii";
- reg = <0xef601500 0x00000008>;
- has-mdio;
- };
-
- RGMII1: emac-rgmii@ef601600 {
- compatible = "ibm,rgmii-460gt", "ibm,rgmii";
- reg = <0xef601600 0x00000008>;
- has-mdio;
- };
-
- TAH0: emac-tah@ef601350 {
- compatible = "ibm,tah-460gt", "ibm,tah";
- reg = <0xef601350 0x00000030>;
- };
-
- TAH1: emac-tah@ef601450 {
- compatible = "ibm,tah-460gt", "ibm,tah";
- reg = <0xef601450 0x00000030>;
- };
-
- EMAC0: ethernet@ef600e00 {
- device_type = "network";
- compatible = "ibm,emac-460gt", "ibm,emac4sync";
- interrupt-parent = <&EMAC0>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
- /*Wake*/ 0x1 &UIC2 0x14 0x4>;
- reg = <0xef600e00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <0>;
- tah-device = <&TAH0>;
- tah-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
-
- EMAC1: ethernet@ef600f00 {
- device_type = "network";
- compatible = "ibm,emac-460gt", "ibm,emac4sync";
- interrupt-parent = <&EMAC1>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
- /*Wake*/ 0x1 &UIC2 0x15 0x4>;
- reg = <0xef600f00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <1>;
- mal-rx-channel = <8>;
- cell-index = <1>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <1>;
- tah-device = <&TAH1>;
- tah-channel = <1>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- mdio-device = <&EMAC0>;
- };
-
- EMAC2: ethernet@ef601100 {
- device_type = "network";
- compatible = "ibm,emac-460gt", "ibm,emac4sync";
- interrupt-parent = <&EMAC2>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
- /*Wake*/ 0x1 &UIC2 0x16 0x4>;
- reg = <0xef601100 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <2>;
- mal-rx-channel = <16>;
- cell-index = <2>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- tx-fifo-size-gige = <16384>; /* emac2&3 only */
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII1>;
- rgmii-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- mdio-device = <&EMAC0>;
- };
-
- EMAC3: ethernet@ef601200 {
- device_type = "network";
- compatible = "ibm,emac-460gt", "ibm,emac4sync";
- interrupt-parent = <&EMAC3>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
- /*Wake*/ 0x1 &UIC2 0x17 0x4>;
- reg = <0xef601200 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <3>;
- mal-rx-channel = <24>;
- cell-index = <3>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- tx-fifo-size-gige = <16384>; /* emac2&3 only */
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII1>;
- rgmii-channel = <1>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- mdio-device = <&EMAC0>;
- };
- };
-
- PCIX0: pci@c0ec00000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
- primary;
- large-inbound-windows;
- enable-msi-hole;
- reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
- 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
- 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
- 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
- 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
- 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
- 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 0 to 0x3f */
- bus-range = <0x0 0x3f>;
-
- /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
- interrupt-map-mask = <0x0 0x0 0x0 0x0>;
- interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
- };
-
- PCIE0: pciex@d00000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
- primary;
- port = <0x0>; /* port number */
- reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
- 0x0000000c 0x08010000 0x00001000>; /* Registers */
- dcr-reg = <0x100 0x020>;
- sdr-base = <0x300>;
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 40 to 0x7f */
- bus-range = <0x40 0x7f>;
-
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
- };
-
- PCIE1: pciex@d20000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
- primary;
- port = <0x1>; /* port number */
- reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
- 0x0000000c 0x08011000 0x00001000>; /* Registers */
- dcr-reg = <0x120 0x020>;
- sdr-base = <0x340>;
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 80 to 0xbf */
- bus-range = <0x80 0xbf>;
-
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
- };
- };
-};
+++ /dev/null
-/dts-v1/;
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- console = &uart0;
- };
-
- uart0: serial@84000000 {
- compatible = "xlnx,xps-uartlite-1.00.a";
- interrupts = <0 0>;
- reg = <0x84000000 0x10000>;
- };
-} ;
+++ /dev/null
-/dts-v1/;
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- console = &uart0;
- };
-
- uart0: serial@8b000000 {
- compatible = "xlnx,xps-uartlite-1.00.a";
- interrupts = <0 0>;
- reg = <0x8b000000 0x10000>;
- };
-} ;
+++ /dev/null
-#ifndef _405GP_PCI_H
-#define _405GP_PCI_H
-
-#include <pci.h>
-
-/*----------------------------------------------------------------------------+
-| 405GP PCI core memory map defines.
-+----------------------------------------------------------------------------*/
-#define MIN_PCI_MEMADDR1 0x80000000
-#define MIN_PCI_MEMADDR2 0x00000000
-#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */
-#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */
-#define MAX_PCI_DEVICES 32
-
-/*----------------------------------------------------------------------------+
-| Defines for the 405GP PCI Config address and data registers followed by
-| defines for the standard PCI device configuration header.
-+----------------------------------------------------------------------------*/
-#define PCICFGADR 0xEEC00000
-#define PCICFGDATA 0xEEC00004
-
-#define PCIBUSNUM 0x40 /* 405GP specific parameters */
-#define PCISUBBUSNUM 0x41
-#define PCIDISCOUNT 0x42
-#define PCIBRDGOPT1 0x4A
-#define PCIBRDGOPT2 0x60
-
-/*----------------------------------------------------------------------------+
-| Defines for 405GP PCI Master local configuration regs.
-+----------------------------------------------------------------------------*/
-#define PMM0LA 0xEF400000
-#define PMM0MA 0xEF400004
-#define PMM0PCILA 0xEF400008
-#define PMM0PCIHA 0xEF40000C
-#define PMM1LA 0xEF400010
-#define PMM1MA 0xEF400014
-#define PMM1PCILA 0xEF400018
-#define PMM1PCIHA 0xEF40001C
-#define PMM2LA 0xEF400020
-#define PMM2MA 0xEF400024
-#define PMM2PCILA 0xEF400028
-#define PMM2PCIHA 0xEF40002C
-
-/*----------------------------------------------------------------------------+
-| Defines for 405GP PCI Target local configuration regs.
-+----------------------------------------------------------------------------*/
-#define PTM1MS 0xEF400030
-#define PTM1LA 0xEF400034
-#define PTM2MS 0xEF400038
-#define PTM2LA 0xEF40003C
-
-#define PCIDEVID_405GP 0x0
-
-void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
-int pci_arbiter_enabled(void);
-int __pci_pre_init(struct pci_controller *hose);
-void __pci_target_init(struct pci_controller *hose);
-void __pci_master_init(struct pci_controller *hose);
-void pci_target_init(struct pci_controller *);
-void pcie_setup_hoses(int busno);
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2005 Cisco Systems. All rights reserved.
- * Roland Dreier <rolandd@cisco.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __4XX_PCIE_H
-#define __4XX_PCIE_H
-
-#include <asm/ppc4xx.h>
-#include <pci.h>
-
-#define DCRN_SDR0_CFGADDR 0x00e
-#define DCRN_SDR0_CFGDATA 0x00f
-
-#if defined(CONFIG_440SPE)
-#define CONFIG_SYS_PCIE_NR_PORTS 3
-
-#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
-
-#define DCRN_PCIE0_BASE 0x100
-#define DCRN_PCIE1_BASE 0x120
-#define DCRN_PCIE2_BASE 0x140
-
-#define PCIE0_SDR 0x300
-#define PCIE1_SDR 0x340
-#define PCIE2_SDR 0x370
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define CONFIG_SYS_PCIE_NR_PORTS 2
-
-#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
-
-#define DCRN_PCIE0_BASE 0x100
-#define DCRN_PCIE1_BASE 0x120
-
-#define PCIE0_SDR 0x300
-#define PCIE1_SDR 0x340
-#endif
-
-#if defined(CONFIG_405EX)
-#define CONFIG_SYS_PCIE_NR_PORTS 2
-
-#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000
-
-#define DCRN_PCIE0_BASE 0x040
-#define DCRN_PCIE1_BASE 0x060
-
-#define PCIE0_SDR 0x400
-#define PCIE1_SDR 0x440
-#endif
-
-#define PCIE0 DCRN_PCIE0_BASE
-#define PCIE1 DCRN_PCIE1_BASE
-#define PCIE2 DCRN_PCIE2_BASE
-
-#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
-#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
-#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
-#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
-#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
-#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
-#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
-#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
-#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
-#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
-#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
-#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
-#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
-#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
-#define DCRN_PEGPL_CFG(base) (base + 0x16)
-
-/*
- * System DCRs (SDRs)
- */
-#define PESDR0_PLLLCT1 0x03a0
-#define PESDR0_PLLLCT2 0x03a1
-#define PESDR0_PLLLCT3 0x03a2
-
-/* common regs, at for all 4xx with PCIe core */
-#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00)
-#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01)
-#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02)
-#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03)
-#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04)
-#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05)
-
-#if defined(CONFIG_440SPE)
-#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06)
-#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07)
-#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08)
-#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09)
-#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a)
-#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b)
-#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c)
-#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d)
-#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e)
-#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f)
-#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10)
-#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11)
-
-#define PESDR0_UTLSET1 0x0300
-#define PESDR0_UTLSET2 0x0301
-#define PESDR0_DLPSET 0x0302
-#define PESDR0_LOOP 0x0303
-#define PESDR0_RCSSET 0x0304
-#define PESDR0_RCSSTS 0x0305
-#define PESDR0_HSSL0SET1 0x0306
-#define PESDR0_HSSL0SET2 0x0307
-#define PESDR0_HSSL0STS 0x0308
-#define PESDR0_HSSL1SET1 0x0309
-#define PESDR0_HSSL1SET2 0x030a
-#define PESDR0_HSSL1STS 0x030b
-#define PESDR0_HSSL2SET1 0x030c
-#define PESDR0_HSSL2SET2 0x030d
-#define PESDR0_HSSL2STS 0x030e
-#define PESDR0_HSSL3SET1 0x030f
-#define PESDR0_HSSL3SET2 0x0310
-#define PESDR0_HSSL3STS 0x0311
-#define PESDR0_HSSL4SET1 0x0312
-#define PESDR0_HSSL4SET2 0x0313
-#define PESDR0_HSSL4STS 0x0314
-#define PESDR0_HSSL5SET1 0x0315
-#define PESDR0_HSSL5SET2 0x0316
-#define PESDR0_HSSL5STS 0x0317
-#define PESDR0_HSSL6SET1 0x0318
-#define PESDR0_HSSL6SET2 0x0319
-#define PESDR0_HSSL6STS 0x031a
-#define PESDR0_HSSL7SET1 0x031b
-#define PESDR0_HSSL7SET2 0x031c
-#define PESDR0_HSSL7STS 0x031d
-#define PESDR0_HSSCTLSET 0x031e
-#define PESDR0_LANE_ABCD 0x031f
-#define PESDR0_LANE_EFGH 0x0320
-
-#define PESDR1_UTLSET1 0x0340
-#define PESDR1_UTLSET2 0x0341
-#define PESDR1_DLPSET 0x0342
-#define PESDR1_LOOP 0x0343
-#define PESDR1_RCSSET 0x0344
-#define PESDR1_RCSSTS 0x0345
-#define PESDR1_HSSL0SET1 0x0346
-#define PESDR1_HSSL0SET2 0x0347
-#define PESDR1_HSSL0STS 0x0348
-#define PESDR1_HSSL1SET1 0x0349
-#define PESDR1_HSSL1SET2 0x034a
-#define PESDR1_HSSL1STS 0x034b
-#define PESDR1_HSSL2SET1 0x034c
-#define PESDR1_HSSL2SET2 0x034d
-#define PESDR1_HSSL2STS 0x034e
-#define PESDR1_HSSL3SET1 0x034f
-#define PESDR1_HSSL3SET2 0x0350
-#define PESDR1_HSSL3STS 0x0351
-#define PESDR1_HSSCTLSET 0x0352
-#define PESDR1_LANE_ABCD 0x0353
-
-#define PESDR2_UTLSET1 0x0370
-#define PESDR2_UTLSET2 0x0371
-#define PESDR2_DLPSET 0x0372
-#define PESDR2_LOOP 0x0373
-#define PESDR2_RCSSET 0x0374
-#define PESDR2_RCSSTS 0x0375
-#define PESDR2_HSSL0SET1 0x0376
-#define PESDR2_HSSL0SET2 0x0377
-#define PESDR2_HSSL0STS 0x0378
-#define PESDR2_HSSL1SET1 0x0379
-#define PESDR2_HSSL1SET2 0x037a
-#define PESDR2_HSSL1STS 0x037b
-#define PESDR2_HSSL2SET1 0x037c
-#define PESDR2_HSSL2SET2 0x037d
-#define PESDR2_HSSL2STS 0x037e
-#define PESDR2_HSSL3SET1 0x037f
-#define PESDR2_HSSL3SET2 0x0380
-#define PESDR2_HSSL3STS 0x0381
-#define PESDR2_HSSCTLSET 0x0382
-#define PESDR2_LANE_ABCD 0x0383
-
-#elif defined(CONFIG_405EX)
-
-#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06)
-#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07)
-#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08)
-#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b)
-#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c)
-
-#define PESDR0_UTLSET1 0x0400
-#define PESDR0_UTLSET2 0x0401
-#define PESDR0_DLPSET 0x0402
-#define PESDR0_LOOP 0x0403
-#define PESDR0_RCSSET 0x0404
-#define PESDR0_RCSSTS 0x0405
-#define PESDR0_PHYSET1 0x0406
-#define PESDR0_PHYSET2 0x0407
-#define PESDR0_BIST 0x0408
-#define PESDR0_LPB 0x040B
-#define PESDR0_PHYSTA 0x040C
-
-#define PESDR1_UTLSET1 0x0440
-#define PESDR1_UTLSET2 0x0441
-#define PESDR1_DLPSET 0x0442
-#define PESDR1_LOOP 0x0443
-#define PESDR1_RCSSET 0x0444
-#define PESDR1_RCSSTS 0x0445
-#define PESDR1_PHYSET1 0x0446
-#define PESDR1_PHYSET2 0x0447
-#define PESDR1_BIST 0x0448
-#define PESDR1_LPB 0x044B
-#define PESDR1_PHYSTA 0x044C
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-#define PESDR0_L0BIST 0x0308 /* PE0 L0 built in self test */
-#define PESDR0_L0BISTSTS 0x0309 /* PE0 L0 built in self test status */
-#define PESDR0_L0CDRCTL 0x030A /* PE0 L0 CDR control */
-#define PESDR0_L0DRV 0x030B /* PE0 L0 drive */
-#define PESDR0_L0REC 0x030C /* PE0 L0 receiver */
-#define PESDR0_L0LPB 0x030D /* PE0 L0 loopback */
-#define PESDR0_L0CLK 0x030E /* PE0 L0 clocking */
-#define PESDR0_PHY_CTL_RST 0x030F /* PE0 PHY control reset */
-#define PESDR0_RSTSTA 0x0310 /* PE0 reset status */
-#define PESDR0_OBS 0x0311 /* PE0 observation register */
-#define PESDR0_L0ERRC 0x0320 /* PE0 L0 error counter */
-
-#define PESDR1_L0BIST 0x0348 /* PE1 L0 built in self test */
-#define PESDR1_L1BIST 0x0349 /* PE1 L1 built in self test */
-#define PESDR1_L2BIST 0x034A /* PE1 L2 built in self test */
-#define PESDR1_L3BIST 0x034B /* PE1 L3 built in self test */
-#define PESDR1_L0BISTSTS 0x034C /* PE1 L0 built in self test status */
-#define PESDR1_L1BISTSTS 0x034D /* PE1 L1 built in self test status */
-#define PESDR1_L2BISTSTS 0x034E /* PE1 L2 built in self test status */
-#define PESDR1_L3BISTSTS 0x034F /* PE1 L3 built in self test status */
-#define PESDR1_L0CDRCTL 0x0350 /* PE1 L0 CDR control */
-#define PESDR1_L1CDRCTL 0x0351 /* PE1 L1 CDR control */
-#define PESDR1_L2CDRCTL 0x0352 /* PE1 L2 CDR control */
-#define PESDR1_L3CDRCTL 0x0353 /* PE1 L3 CDR control */
-#define PESDR1_L0DRV 0x0354 /* PE1 L0 drive */
-#define PESDR1_L1DRV 0x0355 /* PE1 L1 drive */
-#define PESDR1_L2DRV 0x0356 /* PE1 L2 drive */
-#define PESDR1_L3DRV 0x0357 /* PE1 L3 drive */
-#define PESDR1_L0REC 0x0358 /* PE1 L0 receiver */
-#define PESDR1_L1REC 0x0359 /* PE1 L1 receiver */
-#define PESDR1_L2REC 0x035A /* PE1 L2 receiver */
-#define PESDR1_L3REC 0x035B /* PE1 L3 receiver */
-#define PESDR1_L0LPB 0x035C /* PE1 L0 loopback */
-#define PESDR1_L1LPB 0x035D /* PE1 L1 loopback */
-#define PESDR1_L2LPB 0x035E /* PE1 L2 loopback */
-#define PESDR1_L3LPB 0x035F /* PE1 L3 loopback */
-#define PESDR1_L0CLK 0x0360 /* PE1 L0 clocking */
-#define PESDR1_L1CLK 0x0361 /* PE1 L1 clocking */
-#define PESDR1_L2CLK 0x0362 /* PE1 L2 clocking */
-#define PESDR1_L3CLK 0x0363 /* PE1 L3 clocking */
-#define PESDR1_PHY_CTL_RST 0x0364 /* PE1 PHY control reset */
-#define PESDR1_RSTSTA 0x0365 /* PE1 reset status */
-#define PESDR1_OBS 0x0366 /* PE1 observation register */
-#define PESDR1_L0ERRC 0x0368 /* PE1 L0 error counter */
-#define PESDR1_L1ERRC 0x0369 /* PE1 L1 error counter */
-#define PESDR1_L2ERRC 0x036A /* PE1 L2 error counter */
-#define PESDR1_L3ERRC 0x036B /* PE1 L3 error counter */
-#define PESDR0_IHS1 0x036C /* PE interrupt handler interfact setting 1 */
-#define PESDR0_IHS2 0x036D /* PE interrupt handler interfact setting 2 */
-
-#endif
-
-/* SDR Bit Mappings */
-#define PESDRx_RCSSET_HLDPLB 0x10000000
-#define PESDRx_RCSSET_RSTGU 0x01000000
-#define PESDRx_RCSSET_RDY 0x00100000
-#define PESDRx_RCSSET_RSTDL 0x00010000
-#define PESDRx_RCSSET_RSTPYN 0x00001000
-
-#define PESDRx_RCSSTS_PLBIDL 0x10000000
-#define PESDRx_RCSSTS_HRSTRQ 0x01000000
-#define PESDRx_RCSSTS_PGRST 0x00100000
-#define PESDRx_RCSSTS_VC0ACT 0x00010000
-#define PESDRx_RCSSTS_BMEN 0x00000100
-
-/*
- * UTL register offsets
- */
-#define PEUTL_PBCTL 0x00
-#define PEUTL_PBBSZ 0x20
-#define PEUTL_OPDBSZ 0x68
-#define PEUTL_IPHBSZ 0x70
-#define PEUTL_IPDBSZ 0x78
-#define PEUTL_OUTTR 0x90
-#define PEUTL_INTR 0x98
-#define PEUTL_PCTL 0xa0
-#define PEUTL_RCSTA 0xb0
-#define PEUTL_RCIRQEN 0xb8
-
-/*
- * Config space register offsets
- */
-#define PECFG_BAR0LMPA 0x210
-#define PECFG_BAR0HMPA 0x214
-#define PECFG_BAR1MPA 0x218
-#define PECFG_BAR2LMPA 0x220
-#define PECFG_BAR2HMPA 0x224
-
-#define PECFG_PIMEN 0x33c
-#define PECFG_PIM0LAL 0x340
-#define PECFG_PIM0LAH 0x344
-#define PECFG_PIM1LAL 0x348
-#define PECFG_PIM1LAH 0x34c
-#define PECFG_PIM01SAL 0x350
-#define PECFG_PIM01SAH 0x354
-
-#define PECFG_POM0LAL 0x380
-#define PECFG_POM0LAH 0x384
-
-#define SDR_READ(offset) ({\
- mtdcr(DCRN_SDR0_CFGADDR, offset); \
- mfdcr(DCRN_SDR0_CFGDATA);})
-
-#define SDR_WRITE(offset, data) ({\
- mtdcr(DCRN_SDR0_CFGADDR, offset); \
- mtdcr(DCRN_SDR0_CFGDATA,data);})
-
-#define GPL_DMER_MASK_DISA 0x02000000
-
-#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
-#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
-
-/*
- * Prototypes
- */
-int ppc4xx_init_pcie(void);
-int ppc4xx_init_pcie_rootport(int port);
-int ppc4xx_init_pcie_endport(int port);
-void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
-int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
-int pcie_hose_scan(struct pci_controller *hose, int bus);
-
-/*
- * Function to determine root port or endport from env variable.
- */
-static inline int is_end_point(int port)
-{
- char s[10], *tk;
- char *pcie_mode = getenv("pcie_mode");
-
- if (pcie_mode == NULL)
- return 0;
-
- strcpy(s, pcie_mode);
- tk = strtok(s, ":");
-
- switch (port) {
- case 0:
- if (tk != NULL) {
- if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
- return 1;
- else
- return 0;
- }
- else
- return 0;
-
- case 1:
- tk = strtok(NULL, ":");
- if (tk != NULL) {
- if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
- return 1;
- else
- return 0;
- }
- else
- return 0;
-
- case 2:
- tk = strtok(NULL, ":");
- if (tk != NULL)
- tk = strtok(NULL, ":");
- if (tk != NULL) {
- if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
- return 1;
- else
- return 0;
- }
- else
- return 0;
- }
-
- return 0;
-}
-
-#if defined(PCIE0_SDR)
-static inline u32 sdr_base(int port)
-{
- switch (port) {
- default: /* to satisfy compiler */
- case 0:
- return PCIE0_SDR;
- case 1:
- return PCIE1_SDR;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- case 2:
- return PCIE2_SDR;
-#endif
- }
-}
-#endif /* defined(PCIE0_SDR) */
-
-#endif /* __4XX_PCIE_H */
#define CONFIG_SYS_BOOT_GET_KBD
#ifndef CONFIG_MAX_MEM_MAPPED
-#if defined(CONFIG_4xx) || \
- defined(CONFIG_E500) || \
+#if defined(CONFIG_E500) || \
defined(CONFIG_MPC86xx) || \
defined(CONFIG_E300)
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
#endif
-#if defined(CONFIG_4xx)
- u32 uart_clk;
-#endif /* CONFIG_4xx */
#ifdef CONFIG_SYS_FPGA_COUNT
unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
#endif
#ifndef INTERRUPT_H
#define INTERRUPT_H
-#if defined(CONFIG_XILINX_440)
-#include <asm/xilinx_irq.h>
-#else
-#include <asm/ppc4xx-uic.h>
-#endif
-
-void pic_enable(void);
-void pic_irq_enable(unsigned int irq);
-void pic_irq_disable(unsigned int irq);
-void pic_irq_ack(unsigned int irq);
void external_interrupt(struct pt_regs *regs);
-void interrupt_run_handler(int vec);
#endif
#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
#endif
-#ifdef CONFIG_440
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-/* Some additional macros for combinations often used */
-#define SA_IG (SA_I | SA_G)
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-/* Some additional macros for combinations often used */
-#define AC_RW (AC_R | AC_W)
-#define AC_RWX (AC_R | AC_W | AC_X)
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
-#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
-#define TLB2(a) ((a) & 0x00000fbf)
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ;\
-0: mflr r0 ;\
- mtlr r1 ;\
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-/*----------------------------------------------------------------------------+
-| TLB specific defines.
-+----------------------------------------------------------------------------*/
-#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
-#define TLB_16MB_ALIGN_MASK 0xFFF000000ULL
-#define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL
-#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
-#define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL
-#define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL
-#define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL
-#define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL
-#define TLB_256MB_SIZE 0x10000000
-#define TLB_16MB_SIZE 0x01000000
-#define TLB_1MB_SIZE 0x00100000
-#define TLB_256KB_SIZE 0x00040000
-#define TLB_64KB_SIZE 0x00010000
-#define TLB_16KB_SIZE 0x00004000
-#define TLB_4KB_SIZE 0x00001000
-#define TLB_1KB_SIZE 0x00000400
-
-#define TLB_WORD0_EPN_MASK 0xFFFFFC00
-#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD0_V_MASK 0x00000200
-#define TLB_WORD0_V_ENABLE 0x00000200
-#define TLB_WORD0_V_DISABLE 0x00000000
-#define TLB_WORD0_TS_MASK 0x00000100
-#define TLB_WORD0_TS_1 0x00000100
-#define TLB_WORD0_TS_0 0x00000000
-#define TLB_WORD0_SIZE_MASK 0x000000F0
-#define TLB_WORD0_SIZE_1KB 0x00000000
-#define TLB_WORD0_SIZE_4KB 0x00000010
-#define TLB_WORD0_SIZE_16KB 0x00000020
-#define TLB_WORD0_SIZE_64KB 0x00000030
-#define TLB_WORD0_SIZE_256KB 0x00000040
-#define TLB_WORD0_SIZE_1MB 0x00000050
-#define TLB_WORD0_SIZE_16MB 0x00000070
-#define TLB_WORD0_SIZE_256MB 0x00000090
-#define TLB_WORD0_TPAR_MASK 0x0000000F
-#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
-#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
-
-#define TLB_WORD1_RPN_MASK 0xFFFFFC00
-#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD1_PAR1_MASK 0x00000300
-#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
-#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
-#define TLB_WORD1_PAR1_0 0x00000000
-#define TLB_WORD1_PAR1_1 0x00000100
-#define TLB_WORD1_PAR1_2 0x00000200
-#define TLB_WORD1_PAR1_3 0x00000300
-#define TLB_WORD1_ERPN_MASK 0x0000000F
-#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
-#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
-
-#define TLB_WORD2_PAR2_MASK 0xC0000000
-#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
-#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
-#define TLB_WORD2_PAR2_0 0x00000000
-#define TLB_WORD2_PAR2_1 0x40000000
-#define TLB_WORD2_PAR2_2 0x80000000
-#define TLB_WORD2_PAR2_3 0xC0000000
-#define TLB_WORD2_U0_MASK 0x00008000
-#define TLB_WORD2_U0_ENABLE 0x00008000
-#define TLB_WORD2_U0_DISABLE 0x00000000
-#define TLB_WORD2_U1_MASK 0x00004000
-#define TLB_WORD2_U1_ENABLE 0x00004000
-#define TLB_WORD2_U1_DISABLE 0x00000000
-#define TLB_WORD2_U2_MASK 0x00002000
-#define TLB_WORD2_U2_ENABLE 0x00002000
-#define TLB_WORD2_U2_DISABLE 0x00000000
-#define TLB_WORD2_U3_MASK 0x00001000
-#define TLB_WORD2_U3_ENABLE 0x00001000
-#define TLB_WORD2_U3_DISABLE 0x00000000
-#define TLB_WORD2_W_MASK 0x00000800
-#define TLB_WORD2_W_ENABLE 0x00000800
-#define TLB_WORD2_W_DISABLE 0x00000000
-#define TLB_WORD2_I_MASK 0x00000400
-#define TLB_WORD2_I_ENABLE 0x00000400
-#define TLB_WORD2_I_DISABLE 0x00000000
-#define TLB_WORD2_M_MASK 0x00000200
-#define TLB_WORD2_M_ENABLE 0x00000200
-#define TLB_WORD2_M_DISABLE 0x00000000
-#define TLB_WORD2_G_MASK 0x00000100
-#define TLB_WORD2_G_ENABLE 0x00000100
-#define TLB_WORD2_G_DISABLE 0x00000000
-#define TLB_WORD2_E_MASK 0x00000080
-#define TLB_WORD2_E_ENABLE 0x00000080
-#define TLB_WORD2_E_DISABLE 0x00000000
-#define TLB_WORD2_UX_MASK 0x00000020
-#define TLB_WORD2_UX_ENABLE 0x00000020
-#define TLB_WORD2_UX_DISABLE 0x00000000
-#define TLB_WORD2_UW_MASK 0x00000010
-#define TLB_WORD2_UW_ENABLE 0x00000010
-#define TLB_WORD2_UW_DISABLE 0x00000000
-#define TLB_WORD2_UR_MASK 0x00000008
-#define TLB_WORD2_UR_ENABLE 0x00000008
-#define TLB_WORD2_UR_DISABLE 0x00000000
-#define TLB_WORD2_SX_MASK 0x00000004
-#define TLB_WORD2_SX_ENABLE 0x00000004
-#define TLB_WORD2_SX_DISABLE 0x00000000
-#define TLB_WORD2_SW_MASK 0x00000002
-#define TLB_WORD2_SW_ENABLE 0x00000002
-#define TLB_WORD2_SW_DISABLE 0x00000000
-#define TLB_WORD2_SR_MASK 0x00000001
-#define TLB_WORD2_SR_ENABLE 0x00000001
-#define TLB_WORD2_SR_DISABLE 0x00000000
-
-/*----------------------------------------------------------------------------+
-| Following instructions are not available in Book E mode of the GNU assembler.
-+----------------------------------------------------------------------------*/
-#define DCCCI(ra,rb) .long 0x7c000000|\
- (ra<<16)|(rb<<11)|(454<<1)
-
-#define ICCCI(ra,rb) .long 0x7c000000|\
- (ra<<16)|(rb<<11)|(966<<1)
-
-#define DCREAD(rt,ra,rb) .long 0x7c000000|\
- (rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
-
-#define ICREAD(ra,rb) .long 0x7c000000|\
- (ra<<16)|(rb<<11)|(998<<1)
-
-#define TLBSX(rt,ra,rb) .long 0x7c000000|\
- (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
-
-#define TLBWE(rs,ra,ws) .long 0x7c000000|\
- (rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
-
-#define TLBRE(rt,ra,ws) .long 0x7c000000|\
- (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
-
-#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\
- (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
-
-#define MSYNC .long 0x7c000000|\
- (598<<1)
-
-#define MBAR_INST .long 0x7c000000|\
- (854<<1)
-
-#ifndef __ASSEMBLY__
-/* Prototypes */
-void mttlb1(unsigned long index, unsigned long value);
-void mttlb2(unsigned long index, unsigned long value);
-void mttlb3(unsigned long index, unsigned long value);
-unsigned long mftlb1(unsigned long index);
-unsigned long mftlb2(unsigned long index);
-unsigned long mftlb3(unsigned long index);
-
-void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
-void remove_tlb(u32 vaddr, u32 size);
-void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
-#endif /* __ASSEMBLY__ */
-
-#endif /* CONFIG_440 */
#endif /* _PPC_MMU_H_ */
#include <mpc83xx.h>
#include <asm/immap_83xx.h>
#endif
-#ifdef CONFIG_4xx
-#include <asm/ppc4xx.h>
-#endif
#ifdef CONFIG_SOC_DA8XX
#include <asm/arch/hardware.h>
#endif
void wr_dc_cst(uint);
void wr_dc_adr(uint);
-#if defined(CONFIG_4xx) || \
- defined(CONFIG_MPC85xx) || \
+#if defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
unsigned char in8(unsigned int);
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-
-#ifndef __PPC405_H__
-#define __PPC405_H__
-
-/* Define bits and masks for real-mode storage attribute control registers */
-#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
-#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
-
-#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
-
-/* DCR registers */
-#define PLB0_ACR 0x0087
-
-/* SDR registers */
-#define SDR0_PINSTP 0x0040
-
-/* CPR registers */
-#define CPR0_CLKUPD 0x0020
-#define CPR0_PLLC 0x0040
-#define CPR0_PLLD 0x0060
-#define CPR0_CPUD 0x0080
-#define CPR0_PLBD 0x00a0
-#define CPR0_OPBD0 0x00c0
-#define CPR0_PERD 0x00e0
-
-/*
- * DMA
- */
-#define DMA_DCR_BASE 0x0100
-#define DMACR0 (DMA_DCR_BASE + 0x00) /* DMA channel control reg 0 */
-#define DMACT0 (DMA_DCR_BASE + 0x01) /* DMA count reg 0 */
-#define DMADA0 (DMA_DCR_BASE + 0x02) /* DMA destination address reg 0 */
-#define DMASA0 (DMA_DCR_BASE + 0x03) /* DMA source address reg 0 */
-#define DMASB0 (DMA_DCR_BASE + 0x04) /* DMA sg descriptor addr 0 */
-#define DMACR1 (DMA_DCR_BASE + 0x08) /* DMA channel control reg 1 */
-#define DMACT1 (DMA_DCR_BASE + 0x09) /* DMA count reg 1 */
-#define DMADA1 (DMA_DCR_BASE + 0x0a) /* DMA destination address reg 1 */
-#define DMASA1 (DMA_DCR_BASE + 0x0b) /* DMA source address reg 1 */
-#define DMASB1 (DMA_DCR_BASE + 0x0c) /* DMA sg descriptor addr 1 */
-#define DMACR2 (DMA_DCR_BASE + 0x10) /* DMA channel control reg 2 */
-#define DMACT2 (DMA_DCR_BASE + 0x11) /* DMA count reg 2 */
-#define DMADA2 (DMA_DCR_BASE + 0x12) /* DMA destination address reg 2 */
-#define DMASA2 (DMA_DCR_BASE + 0x13) /* DMA source address reg 2 */
-#define DMASB2 (DMA_DCR_BASE + 0x14) /* DMA sg descriptor addr 2 */
-#define DMACR3 (DMA_DCR_BASE + 0x18) /* DMA channel control reg 3 */
-#define DMACT3 (DMA_DCR_BASE + 0x19) /* DMA count reg 3 */
-#define DMADA3 (DMA_DCR_BASE + 0x1a) /* DMA destination address reg 3 */
-#define DMASA3 (DMA_DCR_BASE + 0x1b) /* DMA source address reg 3 */
-#define DMASB3 (DMA_DCR_BASE + 0x1c) /* DMA sg descriptor addr 3 */
-#define DMASR (DMA_DCR_BASE + 0x20) /* DMA status reg */
-#define DMASGC (DMA_DCR_BASE + 0x23) /* DMA scatter/gather command reg*/
-#define DMAADR (DMA_DCR_BASE + 0x24) /* DMA address decode reg */
-
-#endif /* __PPC405_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC405EP_H_
-#define _PPC405EP_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-/* DCR */
-#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */
-#define OCM0_DSARC 0x001a /* OCM D-side address compare */
-#define OCM0_DSCNTL 0x001b /* OCM D-side control */
-#define CPC0_PLLMR0 0x00f0 /* PLL mode register 0 */
-#define CPC0_BOOT 0x00f1 /* Clock status register */
-#define CPC0_CR1 0x00f2 /* Chip Control 1 register */
-#define CPC0_EPCTL 0x00f3 /* EMAC to PHY control register */
-#define CPC0_PLLMR1 0x00f4 /* PLL mode register 1 */
-#define CPC0_UCR 0x00f5 /* UART control register */
-#define CPC0_SRR 0x00f6 /* Soft Reset register */
-#define CPC0_PCI 0x00f9 /* PCI control register */
-
-/* Defines for CPC0_EPCTL register */
-#define CPC0_EPCTL_E0NFE 0x80000000
-#define CPC0_EPCTL_E1NFE 0x40000000
-
-/* Defines for CPC0_PCI Register */
-#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
-#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
-#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */
-
-/* Defines for CPC0_BOOR Register */
-#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
-
-/* Bit definitions */
-#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
-#define PLLMR0_CPU_DIV_BYPASS 0x00000000
-#define PLLMR0_CPU_DIV_2 0x00100000
-#define PLLMR0_CPU_DIV_3 0x00200000
-#define PLLMR0_CPU_DIV_4 0x00300000
-
-#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
-#define PLLMR0_CPU_PLB_DIV_1 0x00000000
-#define PLLMR0_CPU_PLB_DIV_2 0x00010000
-#define PLLMR0_CPU_PLB_DIV_3 0x00020000
-#define PLLMR0_CPU_PLB_DIV_4 0x00030000
-
-#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
-#define PLLMR0_OPB_PLB_DIV_1 0x00000000
-#define PLLMR0_OPB_PLB_DIV_2 0x00001000
-#define PLLMR0_OPB_PLB_DIV_3 0x00002000
-#define PLLMR0_OPB_PLB_DIV_4 0x00003000
-
-#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
-#define PLLMR0_EXB_PLB_DIV_2 0x00000000
-#define PLLMR0_EXB_PLB_DIV_3 0x00000100
-#define PLLMR0_EXB_PLB_DIV_4 0x00000200
-#define PLLMR0_EXB_PLB_DIV_5 0x00000300
-
-#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
-#define PLLMR0_MAL_PLB_DIV_1 0x00000000
-#define PLLMR0_MAL_PLB_DIV_2 0x00000010
-#define PLLMR0_MAL_PLB_DIV_3 0x00000020
-#define PLLMR0_MAL_PLB_DIV_4 0x00000030
-
-#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
-#define PLLMR0_PCI_PLB_DIV_1 0x00000000
-#define PLLMR0_PCI_PLB_DIV_2 0x00000001
-#define PLLMR0_PCI_PLB_DIV_3 0x00000002
-#define PLLMR0_PCI_PLB_DIV_4 0x00000003
-
-#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
-#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
-#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
-
-#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
-#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
-#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE 0x80000000
-#define CPC0_PLLMR1_SSCS 0x80000000
-#define PLL_RESET 0x40000000
-#define CPC0_PLLMR1_PLLR 0x40000000
-/* Feedback multiplier */
-#define PLL_FBKDIV 0x00F00000
-#define CPC0_PLLMR1_FBDV 0x00F00000
-#define PLL_FBKDIV_16 0x00000000
-#define PLL_FBKDIV_1 0x00100000
-#define PLL_FBKDIV_2 0x00200000
-#define PLL_FBKDIV_3 0x00300000
-#define PLL_FBKDIV_4 0x00400000
-#define PLL_FBKDIV_5 0x00500000
-#define PLL_FBKDIV_6 0x00600000
-#define PLL_FBKDIV_7 0x00700000
-#define PLL_FBKDIV_8 0x00800000
-#define PLL_FBKDIV_9 0x00900000
-#define PLL_FBKDIV_10 0x00A00000
-#define PLL_FBKDIV_11 0x00B00000
-#define PLL_FBKDIV_12 0x00C00000
-#define PLL_FBKDIV_13 0x00D00000
-#define PLL_FBKDIV_14 0x00E00000
-#define PLL_FBKDIV_15 0x00F00000
-/* Forward A divisor */
-#define PLL_FWDDIVA 0x00070000
-#define CPC0_PLLMR1_FWDVA 0x00070000
-#define PLL_FWDDIVA_8 0x00000000
-#define PLL_FWDDIVA_7 0x00010000
-#define PLL_FWDDIVA_6 0x00020000
-#define PLL_FWDDIVA_5 0x00030000
-#define PLL_FWDDIVA_4 0x00040000
-#define PLL_FWDDIVA_3 0x00050000
-#define PLL_FWDDIVA_2 0x00060000
-#define PLL_FWDDIVA_1 0x00070000
-/* Forward B divisor */
-#define PLL_FWDDIVB 0x00007000
-#define CPC0_PLLMR1_FWDVB 0x00007000
-#define PLL_FWDDIVB_8 0x00000000
-#define PLL_FWDDIVB_7 0x00001000
-#define PLL_FWDDIVB_6 0x00002000
-#define PLL_FWDDIVB_5 0x00003000
-#define PLL_FWDDIVB_4 0x00004000
-#define PLL_FWDDIVB_3 0x00005000
-#define PLL_FWDDIVB_2 0x00006000
-#define PLL_FWDDIVB_1 0x00007000
-/* PLL tune bits */
-#define PLL_TUNE_MASK 0x000003FF
-#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
-#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
-#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
-#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
-#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
-#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
-#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
-
-/* Defines for CPC0_PLLMR0 Register fields */
-/* CPU divisor */
-#define PLL_CPUDIV 0x00300000
-#define CPC0_PLLMR0_CCDV 0x00300000
-#define PLL_CPUDIV_1 0x00000000
-#define PLL_CPUDIV_2 0x00100000
-#define PLL_CPUDIV_3 0x00200000
-#define PLL_CPUDIV_4 0x00300000
-/* PLB divisor */
-#define PLL_PLBDIV 0x00030000
-#define CPC0_PLLMR0_CBDV 0x00030000
-#define PLL_PLBDIV_1 0x00000000
-#define PLL_PLBDIV_2 0x00010000
-#define PLL_PLBDIV_3 0x00020000
-#define PLL_PLBDIV_4 0x00030000
-/* OPB divisor */
-#define PLL_OPBDIV 0x00003000
-#define CPC0_PLLMR0_OPDV 0x00003000
-#define PLL_OPBDIV_1 0x00000000
-#define PLL_OPBDIV_2 0x00001000
-#define PLL_OPBDIV_3 0x00002000
-#define PLL_OPBDIV_4 0x00003000
-/* EBC divisor */
-#define PLL_EXTBUSDIV 0x00000300
-#define CPC0_PLLMR0_EPDV 0x00000300
-#define PLL_EXTBUSDIV_2 0x00000000
-#define PLL_EXTBUSDIV_3 0x00000100
-#define PLL_EXTBUSDIV_4 0x00000200
-#define PLL_EXTBUSDIV_5 0x00000300
-/* MAL divisor */
-#define PLL_MALDIV 0x00000030
-#define CPC0_PLLMR0_MPDV 0x00000030
-#define PLL_MALDIV_1 0x00000000
-#define PLL_MALDIV_2 0x00000010
-#define PLL_MALDIV_3 0x00000020
-#define PLL_MALDIV_4 0x00000030
-/* PCI divisor */
-#define PLL_PCIDIV 0x00000003
-#define CPC0_PLLMR0_PPFD 0x00000003
-#define PLL_PCIDIV_1 0x00000000
-#define PLL_PCIDIV_2 0x00000001
-#define PLL_PCIDIV_3 0x00000002
-#define PLL_PCIDIV_4 0x00000003
-
-/*
- * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
- * assuming a 33.3MHz input clock to the 405EP.
- */
-#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_1)
-#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#endif /* _PPC405EP_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC405EX_H_
-#define _PPC405EX_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
-
-#define CONFIG_NAND_NDFC
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
-
-/* SDR */
-#define SDR0_SDCS0 0x0060
-#define SDR0_UART0 0x0120 /* UART0 Config */
-#define SDR0_UART1 0x0121 /* UART1 Config */
-#define SDR0_SRST 0x0200
-#define SDR0_CUST0 0x4000
-#define SDR0_PFC0 0x4100
-#define SDR0_PFC1 0x4101
-#define SDR0_MFR 0x4300 /* SDR0_MFR reg */
-
-#define SDR0_ECID0 0x0080
-#define SDR0_ECID1 0x0081
-#define SDR0_ECID2 0x0082
-#define SDR0_ECID3 0x0083
-
-#define SDR0_SDCS_SDD (0x80000000 >> 31)
-
-#define SDR0_SRST_DMC (0x80000000 >> 10)
-
-#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
-
-#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
-
-#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */
-
-#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF)
-
-#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3)
-
-#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
-
-#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
-
-#define SDR0_PFC1_U1ME 0x02000000
-#define SDR0_PFC1_U0ME 0x00080000
-#define SDR0_PFC1_U0IM 0x00040000
-#define SDR0_PFC1_SIS 0x00020000
-#define SDR0_PFC1_DMAAEN 0x00010000
-#define SDR0_PFC1_DMADEN 0x00008000
-#define SDR0_PFC1_USBEN 0x00004000
-#define SDR0_PFC1_AHBSWAP 0x00000020
-#define SDR0_PFC1_USBBIGEN 0x00000010
-#define SDR0_PFC1_GPT_FREQ 0x0000000f
-
-#endif /* _PPC405EX_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC405EZ_H_
-#define _PPC405EZ_H_
-
-#define CONFIG_NAND_NDFC
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
-
-/* DCR register */
-#define OCM0_PLBCR1 0x0020 /* OCM PLB3 Bank 1 Config */
-#define OCM0_PLBCR2 0x0021 /* OCM PLB3 Bank 2 Config */
-#define OCM0_PLBBEAR 0x0022 /* OCM PLB3 Bus Error Add */
-#define OCM0_DSRC1 0x0028 /* OCM D-side Bank 1 Config */
-#define OCM0_DSRC2 0x0029 /* OCM D-side Bank 2 Config */
-#define OCM0_ISRC1 0x002A /* OCM I-side Bank 1Config */
-#define OCM0_ISRC2 0x002B /* OCM I-side Bank 2 Config */
-#define OCM0_DISDPC 0x002C /* OCM D-/I-side Data Par Chk */
-
-/* SDR register */
-#define SDR0_NAND0 0x4000
-#define SDR0_ULTRA0 0x4040
-#define SDR0_ULTRA1 0x4050
-#define SDR0_ICINTSTAT 0x4510
-
-/* CPR register */
-#define CPR0_PRIMAD 0x0080
-#define CPR0_PERD0 0x00e0
-#define CPR0_PERD1 0x00e1
-#define CPR0_PERC0 0x0180
-
-#define MAL_DCR_BASE 0x380
-
-#define SDR_NAND0_NDEN 0x80000000
-#define SDR_NAND0_NDBTEN 0x40000000
-#define SDR_NAND0_NDBADR_MASK 0x30000000
-#define SDR_NAND0_NDBPG_MASK 0x0f000000
-#define SDR_NAND0_NDAREN 0x00800000
-#define SDR_NAND0_NDRBEN 0x00400000
-
-#define SDR_ULTRA0_NDGPIOBP 0x80000000
-#define SDR_ULTRA0_CSN_MASK 0x78000000
-#define SDR_ULTRA0_CSNSEL0 0x40000000
-#define SDR_ULTRA0_CSNSEL1 0x20000000
-#define SDR_ULTRA0_CSNSEL2 0x10000000
-#define SDR_ULTRA0_CSNSEL3 0x08000000
-#define SDR_ULTRA0_EBCRDYEN 0x04000000
-#define SDR_ULTRA0_SPISSINEN 0x02000000
-#define SDR_ULTRA0_NFSRSTEN 0x01000000
-
-#define SDR_ULTRA1_LEDNENABLE 0x40000000
-
-#define SDR_ICRX_STAT 0x80000000
-#define SDR_ICTX0_STAT 0x40000000
-#define SDR_ICTX1_STAT 0x20000000
-
-#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
-#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
-#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
-
-#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
-
-#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
-#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
-#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
-
-#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
-#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
-#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
-#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
-
-#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
-#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
-#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
-#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
-
-#endif /* _PPC405EZ_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC405GP_H_
-#define _PPC405GP_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-/* DCR's */
-#define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */
-#define DCP0_CFGDATA 0x0015 /* Decompression controller data reg */
-#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */
-#define OCM0_DSARC 0x001a /* OCM D-side address compare */
-#define OCM0_DSCNTL 0x001b /* OCM D-side control */
-#define CPC0_PLLMR 0x00b0 /* PLL mode register */
-#define CPC0_CR0 0x00b1 /* chip control register 0 */
-#define CPC0_CR1 0x00b2 /* chip control register 1 */
-#define CPC0_PSR 0x00b4 /* chip pin strapping reg */
-#define CPC0_EIRR 0x00b6 /* ext interrupt routing reg */
-#define CPC0_SR 0x00b8 /* Power management status */
-#define CPC0_ER 0x00b9 /* Power management enable */
-#define CPC0_FR 0x00ba /* Power management force */
-#define CPC0_ECR 0x00aa /* edge conditioner register */
-
-/* values for kiar register - indirect addressing of these regs */
-#define KCONF 0x40 /* decompression core config register */
-
-#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
-#define PLLMR_FWD_DIV_BYPASS 0xE0000000
-#define PLLMR_FWD_DIV_3 0xA0000000
-#define PLLMR_FWD_DIV_4 0x80000000
-#define PLLMR_FWD_DIV_6 0x40000000
-
-#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
-#define PLLMR_FB_DIV_1 0x02000000
-#define PLLMR_FB_DIV_2 0x04000000
-#define PLLMR_FB_DIV_3 0x06000000
-#define PLLMR_FB_DIV_4 0x08000000
-
-#define PLLMR_TUNING_MASK 0x01F80000
-
-#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
-#define PLLMR_CPU_PLB_DIV_1 0x00000000
-#define PLLMR_CPU_PLB_DIV_2 0x00020000
-#define PLLMR_CPU_PLB_DIV_3 0x00040000
-#define PLLMR_CPU_PLB_DIV_4 0x00060000
-
-#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
-#define PLLMR_OPB_PLB_DIV_1 0x00000000
-#define PLLMR_OPB_PLB_DIV_2 0x00008000
-#define PLLMR_OPB_PLB_DIV_3 0x00010000
-#define PLLMR_OPB_PLB_DIV_4 0x00018000
-
-#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
-#define PLLMR_PCI_PLB_DIV_1 0x00000000
-#define PLLMR_PCI_PLB_DIV_2 0x00002000
-#define PLLMR_PCI_PLB_DIV_3 0x00004000
-#define PLLMR_PCI_PLB_DIV_4 0x00006000
-
-#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
-#define PLLMR_EXB_PLB_DIV_2 0x00000000
-#define PLLMR_EXB_PLB_DIV_3 0x00000800
-#define PLLMR_EXB_PLB_DIV_4 0x00001000
-#define PLLMR_EXB_PLB_DIV_5 0x00001800
-
-/* definitions for PPC405GPr (new mode strapping) */
-#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
-
-#define PSR_PLL_FWD_MASK 0xC0000000
-#define PSR_PLL_FDBACK_MASK 0x30000000
-#define PSR_PLL_TUNING_MASK 0x0E000000
-#define PSR_PLB_CPU_MASK 0x01800000
-#define PSR_OPB_PLB_MASK 0x00600000
-#define PSR_PCI_PLB_MASK 0x00180000
-#define PSR_EB_PLB_MASK 0x00060000
-#define PSR_ROM_WIDTH_MASK 0x00018000
-#define PSR_ROM_LOC 0x00004000
-#define PSR_PCI_ASYNC_EN 0x00001000
-#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
-#define PSR_PCI_ARBIT_EN 0x00000400
-#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
-
-#endif /* _PPC405GP_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-
-#ifndef __PPC440_H__
-#define __PPC440_H__
-
-#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
-
-/*
- * DCRs & Related
- */
-
-/* Memory mapped registers */
-#define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
-#define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004)
-#define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000)
-#define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000)
-
-/* DCR registers */
-
-/* CPR register declarations */
-#define CPR0_PLLC 0x0040
-#define CPR0_PLLD 0x0060
-#define CPR0_PRIMAD0 0x0080
-#define CPR0_PRIMBD0 0x00a0
-#define CPR0_OPBD0 0x00c0
-#define CPR0_PERD 0x00e0
-#define CPR0_MALD 0x0100
-#define CPR0_SPCID 0x0120
-#define CPR0_ICFG 0x0140
-
-/* SDR register definations */
-#define SDR0_SDSTP0 0x0020
-#define SDR0_SDSTP1 0x0021
-#define SDR0_PINSTP 0x0040
-#define SDR0_SDCS0 0x0060
-#define SDR0_ECID0 0x0080
-#define SDR0_ECID1 0x0081
-#define SDR0_ECID2 0x0082
-#define SDR0_ECID3 0x0083
-#define SDR0_DDR0 0x00e1
-#define SDR0_EBC 0x0100
-#define SDR0_UART0 0x0120
-#define SDR0_UART1 0x0121
-#define SDR0_UART2 0x0122
-#define SDR0_UART3 0x0123
-#define SDR0_CP440 0x0180
-#define SDR0_XCR 0x01c0
-#define SDR0_XCR0 0x01c0
-#define SDR0_XPLLC 0x01c1
-#define SDR0_XPLLD 0x01c2
-#define SDR0_SRST 0x0200
-#define SDR0_SRST0 SDR0_SRST
-#define SDR0_SRST1 0x0201
-#define SDR0_AMP0 0x0240
-#define SDR0_AMP1 0x0241
-#define SDR0_USB0 0x0320
-#define SDR0_CUST0 0x4000
-#define SDR0_CUST1 0x4002
-#define SDR0_CUST2 0x4004
-#define SDR0_CUST3 0x4006
-#define SDR0_PFC0 0x4100
-#define SDR0_PFC1 0x4101
-#define SDR0_PFC2 0x4102
-#define SDR0_PFC4 0x4104
-#define SDR0_MFR 0x4300
-
-#define SDR0_DDR0_DDRM_DECODE(n) ((((u32)(n)) >> 29) & 0x03)
-
-#define SDR0_PCI0_PAE_MASK (0x80000000 >> 0)
-#define SDR0_XCR0_PAE_MASK (0x80000000 >> 0)
-
-#define SDR0_PFC0_GEIE_MASK 0x00003e00
-#define SDR0_PFC0_GEIE_TRE 0x00003e00
-#define SDR0_PFC0_GEIE_NOTRE 0x00000000
-#define SDR0_PFC0_TRE_MASK (0x80000000 >> 23)
-#define SDR0_PFC0_TRE_DISABLE 0x00000000
-#define SDR0_PFC0_TRE_ENABLE (0x80000000 >> 23)
-
-/*
- * Core Configuration/MMU configuration for 440
- */
-#define CCR0_DAPUIB 0x00100000
-#define CCR0_DTB 0x00008000
-
-#define SDR0_SDCS_SDD (0x80000000 >> 31)
-
-/* todo: move this code from macro offsets to struct */
-#define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID )
-#define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID )
-#define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND )
-#define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS )
-#define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID )
-#define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE)
-#define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE )
-#define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER )
-#define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE )
-#define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
-#define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 )
-#define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 )
-#define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 )
-#define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 )
-#define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 )
-#define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 )
-#define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS )
-#define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
-#define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID )
-#define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS )
-#define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST )
-#define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
-#define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
-#define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
-#define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
-#define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
-
-#define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT )
-#define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT )
-
-#define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068)
-#define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c)
-#define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
-#define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074)
-#define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078)
-#define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c)
-#define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080)
-#define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
-#define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088)
-#define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c)
-#define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
-
-#define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
-#define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c)
-#define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0)
-#define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
-#define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8)
-#define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac)
-#define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
-#define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4)
-#define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8)
-
-#define PCIL0_STS (PCIL0_CFGBASE + 0x00e0)
-
-#endif /* __PPC440_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC440EP_GR_H_
-#define _PPC440EP_GR_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
-
-#define CONFIG_NAND_NDFC
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
-#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
-
-/* SDR's */
-#define SDR0_PCI0 0x0300
-#define SDR0_SDSTP2 0x4001
-#define SDR0_SDSTP3 0x4003
-
-#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
-#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
-
-/* Pin Function Control Register 1 */
-#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
-#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
-#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
-#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
-#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
-#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
-#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
-#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
-#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
-#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
-#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
-#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
-#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold
- Req Selection */
-#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
-#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
-#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
- Selection */
-#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
-#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
-#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
- Selection */
-#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En.
- Selected */
-#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
-#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject
- Selection */
-#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject
- Disable */
-#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject
- Enable */
-#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable
- Selection */
-#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor
- Enable */
-#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor
- Enable */
-#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation
- Gated In */
-
-/* USB Control Register */
-#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
-#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
-#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
-#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
-#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
-#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
-
-/* Miscealleneaous Function Reg. */
-#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
-#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
-#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
-#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
-#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
-#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
-#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
-#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
-#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
-#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
-#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
-#define SDR0_MFR_ZM_ENCODE(n) ((((u32)(n)) & 0x3) << 24)
-#define SDR0_MFR_ZM_DECODE(n) ((((u32)(n)) << 24) & 0x3)
-
-#define SDR0_MFR_ERRATA3_EN0 0x00800000
-#define SDR0_MFR_ERRATA3_EN1 0x00400000
-#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
-#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
-#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
-#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
-#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
-
-/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
-
-#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
-
-#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
-
-#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF)
-
-#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3)
-
-#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
-
-#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
-
-#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
-#define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4)
-#define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF)
-
-#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
-#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
-#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/
-#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
-
-#define SDR0_SRST_DMC 0x00200000
-
-#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
-#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
-#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
-#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
-#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
-#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
-
-#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
-#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
-#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
-#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
-#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
-#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
-
-#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
-#define PRADV_MASK 0x07000000 /* Primary Divisor A */
-#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
-#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
-
-/* Strap 1 Register */
-#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
-#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
-#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
-#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
-#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
-#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
-#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
-#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
-#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
-#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
-#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
-#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
-#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
-#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
-#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
-#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
-#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
-
-#define CPR0_ICFG_RLI_MASK 0x80000000
-#define CPR0_ICFG_ICS_MASK 0x00000007
-#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
-#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000
-#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000
-#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000
-#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000
-#define CPR0_PERD_PERDV0_MASK 0x07000000
-
-#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real =>
- 0x0EF400000 */
-
-/* PCI Master Local Configuration Registers */
-#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
-#define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
-#define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
-#define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
-#define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
-#define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
-#define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
-#define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
-#define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
-#define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
-#define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
-#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
-
-/* PCI Target Local Configuration Registers */
-#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/
- Attribute */
-#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
-#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/
- Attribute */
-#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
-
-#endif /* _PPC440EP_GR_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC440EPX_GRX_H_
-#define _PPC440EPX_GRX_H_
-
-#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
-
-#define CONFIG_NAND_NDFC
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
-
-#define SPI0_MODE (CONFIG_SYS_PERIPHERAL_BASE + 0x0090)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
-#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
-
-/* DCR */
-#define CPM0_ER 0x00b0
-#define CPM1_ER 0x00f0
-#define PLB3A0_ACR 0x0077
-#define PLB4A0_ACR 0x0081
-#define PLB4A1_ACR 0x0089
-#define OPB2PLB40_BCTRL 0x0350
-#define P4P3BO0_CFG 0x0026
-
-/* SDR */
-#define SDR0_DDRCFG 0x00e0
-#define SDR0_PCI0 0x0300
-#define SDR0_SDSTP2 0x4001
-#define SDR0_SDSTP3 0x4003
-#define SDR0_EMAC0RXST 0x4301
-#define SDR0_EMAC0TXST 0x4302
-#define SDR0_CRYP0 0x4500
-
-#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
-#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
-
-/* Pin Function Control Register 1 */
-#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
-#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
-#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
-#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select
- EMAC 0 */
-#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII
- bridge */
-#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII
- bridge */
-#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII
- bridge */
-#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII
- bridge */
-#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII
- bridge */
-#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII
- bridge */
-#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII
- bridge */
-#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
-#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
-#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
-#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
-#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
-#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
-#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
-#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
-#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
-#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold
- Req Selection */
-#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
-#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
-#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
- Selection */
-#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
-#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
-#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
- Selection */
-#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En.
- Selected */
-#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
-#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject
- Selection */
-#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject
- Disable */
-#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject
- Enable */
-#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable
- Selection */
-#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor
- Enable */
-#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor
- Enable */
-#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation
- Gated In */
-
-#define SDR0_PFC2_SELECT_MASK 0xe0000000 /* Ethernet Pin select EMAC1 */
-#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_4 0xa0000000 /* 2xRGMII using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_5 0xc0000000 /* 2xRTBI using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
-
-#define SDR0_USB2D0CR 0x0320
-#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC
- Master Selection */
-#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection*/
-#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
-
-#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface
- Selection */
-#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
-#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
-
-#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
-#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
-#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
-
-/* USB2 Host Control Register */
-#define SDR0_USB2H0CR 0x0340
-#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface*/
-#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
-#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
-#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length
- Adjustment */
-/* USB2PHY0 Control Register */
-#define SDR0_USB2PHY0CR 0x4103
-#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000
-
- /* PHY UTMI interface connection */
-#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
-#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
-
-#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
-#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
-#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
-
-/* VBus detect (Device mode only) */
-#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000
-/* Pull-up resistance on D+ is disabled */
-#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000
-/* Pull-up resistance on D+ is enabled */
-#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000
-
-/* PHY UTMI data width and clock select */
-#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000
-#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
-#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
-
-#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
-#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
-/* Loop back enabled (only test purposes) */
-#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000
-
-/* Force XO block on during a suspend */
-#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000
-#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
-/* PHY XO block is powered-off when all ports are suspended */
-#define SDR0_USB2PHY0CR_XO_OFF 0x04000000
-
-#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
-#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
-#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only
- for full-speed operation */
-
-#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock
- source */
-#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal
- 48M clock as a reference */
-#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO
- block output as a reference */
-
-#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO
- block*/
-#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external
- clock */
-#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock
- from a crystal */
-
-#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
-#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq
- = 12 MHz */
-#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq
- = 48 MHz */
-#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq
- = 24 MHz */
-
-/* USB2.0 Device */
-/*
- * todo: check if this can be completely removed, only used in
- * cpu/ppc4xx/usbdev.c. And offsets are completely wrong. This could
- * never have actually worked. Best probably is to remove this
- * usbdev.c file completely (and these defines).
- */
-#define USB2D0_BASE CONFIG_SYS_USB2D0_BASE
-
-#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
-
-#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for
- Endpoint 0 plus IN Endpoints 1 to 3 */
-#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management
- register */
-#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address
- register */
-#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable
- register for USB2D0_INTRIN */
-#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for
- OUT Endpoints 1 to 3 */
-#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable
- register for USB2D0_INTRUSB */
-#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for
- common USB interrupts */
-#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable
- register for IntrOut */
-#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0
- test modes */
-#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for
- selecting the Endpoint status/control registers */
-#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
-#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status
- register for Endpoint 0. (Index register set to select Endpoint 0) */
-#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status
- register for IN Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet
- size for IN Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status
- register for OUT Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet
- size for OUT Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received
- bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
-#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in
- OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
-
-/* Miscealleneaous Function Reg. */
-#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
-#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
-#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
-#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
-#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
-#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
-#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
-#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
-#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
-#define SDR0_MFR_ZM_ENCODE(n) ((((u32)(n)) & 0x3) << 24)
-#define SDR0_MFR_ZM_DECODE(n) ((((u32)(n)) << 24) & 0x3)
-#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
-#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
-#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
-#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
-#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
-
-/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
-
-#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
-
-#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
-
-#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF)
-
-#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3)
-
-#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
-
-#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
-
-#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
-#define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4)
-#define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF)
-
-#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
-#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
-#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/
-#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
-
-#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
-#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
-#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
-#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
-#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/
- transmitter 0 */
-#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/
- transmitter 1 */
-#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
-#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
-#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
-#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
-#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
-#define SDR0_SRST0_PCI 0x00100000 /* PCI */
-#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
-#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
-#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
-#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
-#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
-#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
-#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
-#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
-#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
-#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
-#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
-#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
-#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
-#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
-#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
-#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
-#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
-#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/
- transmitter 2 */
-#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/
- transmitter 3 */
-
-#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
-#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
-#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
-#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
-#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
-#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
-#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4
- USB 2.0 Host */
-#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to
- USB 2.0 Host */
-#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to
- USB 2.0 Host */
-#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
-#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2*/
-#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
-#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
-#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
-#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
-#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
-#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
-#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
-#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
-#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
-
-#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
-#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
-#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
-#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
-#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
-#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
-
-#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
-#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
-#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
-#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
-#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
-#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
-
-#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
-#define PRADV_MASK 0x07000000 /* Primary Divisor A */
-#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
-#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
-
-/* Strap 1 Register */
-#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
-#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
-#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
-#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
-#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
-#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
-#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
-#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
-#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
-#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
-#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
-#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
-#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
-#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
-#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
-#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
-#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
-
-#define CPR0_ICFG_RLI_MASK 0x80000000
-#define CPR0_ICFG_ICS_MASK 0x00000007
-#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
-#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000
-#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000
-#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000
-#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000
-#define CPR0_PERD_PERDV0_MASK 0x07000000
-
-#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real =>
- 0x0EF400000 */
-
-/* PCI Master Local Configuration Registers */
-#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
-#define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
-#define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
-#define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
-#define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
-#define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
-#define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
-#define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
-#define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
-#define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
-#define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
-#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
-
-/* PCI Target Local Configuration Registers */
-#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/
- Attribute */
-#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
-#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/
- Attribute */
-#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
-
-/* 440EPx boot strap options */
-#define BOOT_STRAP_OPTION_A 0x00000000
-#define BOOT_STRAP_OPTION_B 0x00000001
-#define BOOT_STRAP_OPTION_D 0x00000003
-#define BOOT_STRAP_OPTION_E 0x00000004
-
-#endif /* _PPC440EPX_GRX_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC440GP_H_
-#define _PPC440GP_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-#define SDR0_PCI0 0x0300
-
-#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
-#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
-
-#define CNTRL_DCR_BASE 0x0b0
-
-#define CPC0_SYS0 (CNTRL_DCR_BASE + 0x30) /* System configuration reg 0 */
-#define CPC0_SYS1 (CNTRL_DCR_BASE + 0x31) /* System configuration reg 1 */
-
-#define CPC0_STRP0 (CNTRL_DCR_BASE + 0x34) /* Power-on config reg 0 (RO) */
-#define CPC0_STRP1 (CNTRL_DCR_BASE + 0x35) /* Power-on config reg 1 (RO) */
-
-#define CPC0_GPIO (CNTRL_DCR_BASE + 0x38) /* GPIO config reg (440GP) */
-
-#define CPC0_CR0 (CNTRL_DCR_BASE + 0x3b) /* Control 0 register */
-#define CPC0_CR1 (CNTRL_DCR_BASE + 0x3a) /* Control 1 register */
-
-#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
-#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
-#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
-#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
-#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
-#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
-#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
-#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
-#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
-#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
-#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
-
-#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
-#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
-
-#endif /* _PPC440GP_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC440GX_H_
-#define _PPC440GX_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-/* SDR's */
-#define SDR0_PCI0 0x0300
-
-#define SDR0_SDSTP2 0x4001
-#define SDR0_SDSTP3 0x4003
-
-#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
-#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
-
-#define SDR0_PFC1_EPS_DECODE(n) ((((u32)(n)) >> 22) & 0x07)
-#define SDR0_PFC1_CTEMS_MASK (0x80000000 >> 11)
-#define SDR0_PFC1_CTEMS_EMS 0x00000000
-#define SDR0_PFC1_CTEMS_CPUTRACE (0x80000000 >> 11)
-
-#define SDR0_MFR_ECS_MASK 0x10000000
-
-#define SDR0_SRST_DMC 0x00200000
-
-#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
-#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
-#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
-#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
-#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
-#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
-
-#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
-#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
-#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
-#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
-#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
-#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
-
-#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
-#define PRADV_MASK 0x07000000 /* Primary Divisor A */
-#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
-#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
-
-/* Strap 1 Register */
-#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
-#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
-#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
-#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
-#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
-#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
-#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
-#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
-#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
-#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
-#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
-#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
-#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
-#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
-#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
-#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
-#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
-
-#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
-#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
-
-#endif /* _PPC440GX_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC440SP_H_
-#define _PPC440SP_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xf0000000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-/* SDR's */
-#define SDR0_PCI0 0x0300
-#define SDR0_SDSTP2 0x0022
-#define SDR0_SDSTP3 0x0023
-
-#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
-#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
-
-#define SDR0_PFC1_EM_1000 (0x80000000 >> 10)
-
-#define SDR0_MFR_FIXD (0x80000000 >> 3) /* Workaround for PCI/DMA */
-
-#define SDR0_SRST0_DMC 0x00200000
-
-#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
-#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
-#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
-#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
-#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
-#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
-
-#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
-#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
-#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
-#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
-#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
-#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
-
-#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
-#define PRADV_MASK 0x07000000 /* Primary Divisor A */
-#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
-#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
-
-/* Strap 1 Register */
-#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
-#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
-#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
-#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
-#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
-#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
-#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
-#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
-#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
-#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
-#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
-#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
-#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
-#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
-#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
-#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
-#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
-
-#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
-#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
-
-#endif /* _PPC440SP_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC440SPE_H_
-#define _PPC440SPE_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
-
-/*
- * Some SoC specific registers (not common for all 440 SoC's)
- */
-
-/* Memory mapped register */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-/* SDR's */
-#define SDR0_PCI0 0x0300
-#define SDR0_SDSTP2 0x0022
-#define SDR0_SDSTP3 0x0023
-
-#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
-#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
-#define SDR0_SDSTP1_ERPN_MASK (0x80000000 >> 12)
-#define SDR0_SDSTP1_ERPN_EBC 0
-#define SDR0_SDSTP1_ERPN_PCI (0x80000000 >> 12)
-#define SDR0_SDSTP1_EBCW_MASK (0x80000000 >> 24)
-#define SDR0_SDSTP1_EBCW_8_BITS 0
-#define SDR0_SDSTP1_EBCW_16_BITS (0x80000000 >> 24)
-
-#define SDR0_PFC1_EM_1000 (0x80000000 >> 10)
-
-#define SDR0_MFR_FIXD (0x80000000 >> 3) /* Workaround for PCI/DMA */
-
-#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
-#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0
- (EBC boot) */
-#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1
- (PCI boot) */
-#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled -
- Addr = 0x54 */
-#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled -
- Addr = 0x50 */
-
-#define SDR0_SRST0_DMC 0x00200000
-
-#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
-#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
-#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
-#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
-#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
-#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
-#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
-
-#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
-#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
-#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
-#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
-#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
-#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
-
-#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
-#define PRADV_MASK 0x07000000 /* Primary Divisor A */
-#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
-#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
-
-/* Strap 1 Register */
-#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
-#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
-#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
-#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
-#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
-#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
-#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
-#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
-#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
-#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
-#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
-#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
-#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
-#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
-#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
-#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
-#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
-
-#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
-#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
-
-#endif /* _PPC440SPE_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC460EX_GT_H_
-#define _PPC460EX_GT_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
-
-#define CONFIG_NAND_NDFC
-
-/*
- * Some SoC specific registers
- */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
-
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
-#endif
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
-#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
-
-/* DCR */
-#define AHB_TOP 0x00a4
-#define AHB_BOT 0x00a5
-
-/* SDR */
-#define SDR0_PCI0 0x01c0
-#define SDR0_AHB_CFG 0x0370
-#define SDR0_USB2HOST_CFG 0x0371
-#define SDR0_ETH_PLL 0x4102
-#define SDR0_ETH_CFG 0x4103
-#define SDR0_ETH_STS 0x4104
-
-/*
- * Register bits and masks
- */
-#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
-#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
-
-/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
-
-#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
-
-#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
-
-#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF)
-
-#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3)
-
-#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
-
-#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
-
-#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
-#define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4)
-#define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF)
-
-#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
-#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
-#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/
-#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
-
-/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
-#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /* Ethernet PLL lock indication */
-
-/* Ethernet Configuration Register (SDR0_ETH_CFG) */
-#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /*SGMII3 port loopback
- enable */
-#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /*SGMII2 port loopback
- enable */
-#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /*SGMII1 port loopback
- enable */
-#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /*SGMII0 port loopback
- enable */
-#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /*SGMII Mask */
-#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /*SGMII2 port enable */
-#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /*SGMII1 port enable */
-#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /*SGMII0 port enable */
-#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /*TAHOE1 Bypass selector */
-#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /*TAHOE0 Bypass selector */
-#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /*EMAC 3 PHY clock selector*/
-#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /*EMAC 2 PHY clock selector*/
-#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /*EMAC 1 PHY clock selector*/
-#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /*EMAC 0 PHY clock selector*/
-#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /*Swap EMAC2 with EMAC1 */
-#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /*Swap EMAC0 with EMAC3 */
-#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /*MDIO source selector mask*/
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /*MDIO source - EMAC0 */
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /*MDIO source - EMAC1 */
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /*MDIO source - EMAC2 */
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /*MDIO source - EMAC3 */
-#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /*GMC Port 1 bridge
- selector */
-#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /*GMC Port 0 bridge
- selector */
-
-#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
-#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
-#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
-#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
-#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/
- transmitter 0 */
-#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/
- transmitter 1 */
-#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
-#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */
-#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */
-#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
-#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
-#define SDR0_SRST0_PCI 0x00100000 /* PCI */
-#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
-#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */
-#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/
-#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/
-#define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/
-#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/
-#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/
-#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/
-#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/
- transmitter 2 */
-#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
-#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
-#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */
-#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/
- transmitter 3 */
-#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */
-
-#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */
-#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */
-#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */
-#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */
-#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */
-#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access
- controller 0 */
-#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access
- controller 1 */
-#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access
- controller 2 */
-#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access
- controller 3 */
-#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */
-#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */
-#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */
-#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */
-#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */
-#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */
-#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and
- serdes */
-#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */
-#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */
-#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */
-#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */
-#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */
-#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */
-#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */
-#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */
-#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */
-#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
-#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */
-#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */
-#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */
-#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */
-#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */
-#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */
-
-#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
-#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
-#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
-#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
-#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
-#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
-
-#define CPR0_ICFG_RLI_MASK 0x80000000
-
-#define CPR0_PLLC_RST 0x80000000
-#define CPR0_PLLC_ENG 0x40000000
-
-#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
-#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
-
-#endif /* _PPC460EX_GT_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC460SX_H_
-#define _PPC460SX_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-#define SDR0_SRST0_DMC 0x00200000
-
-#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
-#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
-#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
-#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
-#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
-#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
-
-#endif /* _PPC460SX_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC4xx_EBC_H_
-#define _PPC4xx_EBC_H_
-
-/*
- * Currently there are two register layout versions for the IBM EBC core
- * used on 4xx PPC's. The following grouping lists the first layout.
- * Within this group there is a slight variation concerning the bit field
- * position of the EMPL and EMPH fields:
- */
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405EP) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define CONFIG_EBC_PPC4xx_IBM_VER1
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405EP)
-#define EBC_CFG_EMPH_POS 8
-#define EBC_CFG_EMPL_POS 6
-#else
-#define EBC_CFG_EMPH_POS 6
-#define EBC_CFG_EMPL_POS 8
-#endif
-#endif
-
-/*
- * Define the max number of EBC banks (chip selects)
- */
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405EZ) || \
- defined(CONFIG_440GP) || defined(CONFIG_440GX)
-#define EBC_NUM_BANKS 8
-#endif
-
-#if defined(CONFIG_405EP)
-#define EBC_NUM_BANKS 5
-#endif
-
-#if defined(CONFIG_405EX) || \
- defined(CONFIG_460SX)
-#define EBC_NUM_BANKS 4
-#endif
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define EBC_NUM_BANKS 6
-#endif
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define EBC_NUM_BANKS 3
-#endif
-
-/* Bank Configuration Register */
-#define EBC_BXCR(n) (n)
-#define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17))
-
-#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF)
-#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK))
-#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7)
-#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0)
-#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1)
-#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2)
-#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3)
-#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4)
-#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5)
-#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6)
-#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7)
-#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3)
-#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0)
-#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1)
-#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2)
-#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3)
-#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3)
-#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0)
-#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1)
-#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
-#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x2)
-#else
-#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3)
-#endif
-
-/* Bank Access Parameter Register */
-#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1)
-#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0)
-#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF)
-#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F)
-#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7)
-#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0)
-#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1)
-#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3)
-#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0)
-#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1)
-#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2)
-#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3)
-#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3)
-#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3)
-#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3)
-#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3)
-#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7)
-#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1)
-#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0)
-#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0)
-#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1)
-#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0)
-#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1)
-#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0)
-#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1)
-
-/* Common fields in EBC0_CFG register */
-#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1)
-#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0)
-#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1)
-#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7)
-#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0)
-#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1)
-#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2)
-#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3)
-#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4)
-#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5)
-#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6)
-#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7)
-#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1)
-#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0)
-#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1)
-#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F)
-#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F)
-
-/* Now the two versions of the other bits */
-#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
-#define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0)
-#define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_EMPH_MASK PPC_REG_VAL(EBC_CFG_EMPH_POS, 0x3)
-#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \
- (static_cast(u32, n)) & 0x3)
-#define EBC_CFG_EMPL_MASK PPC_REG_VAL(EBC_CFG_EMPL_POS, 0x3)
-#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \
- (static_cast(u32, n)) & 0x3)
-#define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0)
-#define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_BPR_MASK PPC_REG_VAL(11, 0x3)
-#define EBC_CFG_BPR_1DW PPC_REG_VAL(11, 0x0)
-#define EBC_CFG_BPR_2DW PPC_REG_VAL(11, 0x1)
-#define EBC_CFG_BPR_4DW PPC_REG_VAL(11, 0x2)
-#define EBC_CFG_EMS_MASK PPC_REG_VAL(13, 0x3)
-#define EBC_CFG_EMS_8BIT PPC_REG_VAL(13, 0x0)
-#define EBC_CFG_EMS_16BIT PPC_REG_VAL(13, 0x1)
-#define EBC_CFG_EMS_32BIT PPC_REG_VAL(13, 0x2)
-#else
-#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0)
-#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1)
-#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0)
-#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1)
-#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1)
-#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0)
-#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1)
-#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1)
-#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0)
-#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1)
-#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1)
-#define EBC_CFG_OEO_HI PPC_REG_VAL(8, 0x0)
-#define EBC_CFG_OEO_PREVIOUS PPC_REG_VAL(8, 0x1)
-#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0)
-#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3)
-#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0)
-#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1)
-#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2)
-#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3)
-#endif
-
-#endif /* _PPC4xx_EBC_H_ */
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*----------------------------------------------------------------------------+
-|
-| File Name: enetemac.h
-|
-| Function: Header file for the EMAC3 macro on the 405GP.
-|
-| Author: Mark Wisner
-|
-| Change Activity-
-|
-| Date Description of Change BY
-| --------- --------------------- ---
-| 29-Apr-99 Created MKW
-|
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-| 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
-| ported to handle 440GP and 440GX multiple EMACs
-+----------------------------------------------------------------------------*/
-
-#ifndef _PPC4XX_ENET_H_
-#define _PPC4XX_ENET_H_
-
-#include <net.h>
-#include "asm/ppc4xx-mal.h"
-
-
-/*-----------------------------------------------------------------------------+
-| General enternet defines. 802 frames are not supported.
-+-----------------------------------------------------------------------------*/
-#define ENET_ADDR_LENGTH 6
-#define ENET_ARPTYPE 0x806
-#define ARP_REQUEST 1
-#define ARP_REPLY 2
-#define ENET_IPTYPE 0x800
-#define ARP_CACHE_SIZE 5
-
-#define NUM_TX_BUFF 1
-#define NUM_RX_BUFF PKTBUFSRX
-
-struct enet_frame {
- unsigned char dest_addr[ENET_ADDR_LENGTH];
- unsigned char source_addr[ENET_ADDR_LENGTH];
- unsigned short type;
- unsigned char enet_data[1];
-};
-
-struct arp_entry {
- unsigned long inet_address;
- unsigned char mac_address[ENET_ADDR_LENGTH];
- unsigned long valid;
- unsigned long sec;
- unsigned long nsec;
-};
-
-
-/* Statistic Areas */
-#define MAX_ERR_LOG 10
-
-typedef struct emac_stats_st{ /* Statistic Block */
- int data_len_err;
- int rx_frames;
- int rx;
- int rx_prot_err;
- int int_err;
- int pkts_tx;
- int pkts_rx;
- int pkts_handled;
- short tx_err_log[MAX_ERR_LOG];
- short rx_err_log[MAX_ERR_LOG];
-} EMAC_STATS_ST, *EMAC_STATS_PST;
-
-/* Structure containing variables used by the shared code (4xx_enet.c) */
-typedef struct emac_4xx_hw_st {
- uint32_t hw_addr; /* EMAC offset */
- uint32_t tah_addr; /* TAH offset */
- uint32_t phy_id;
- uint32_t phy_addr;
- uint32_t original_fc;
- uint32_t txcw;
- uint32_t autoneg_failed;
- uint32_t emac_ier;
- volatile mal_desc_t *tx;
- volatile mal_desc_t *rx;
- u32 tx_phys;
- u32 rx_phys;
- bd_t *bis; /* for eth_init upon mal error */
- mal_desc_t *alloc_tx_buf;
- mal_desc_t *alloc_rx_buf;
- char *txbuf_ptr;
- uint16_t devnum;
- int get_link_status;
- int tbi_compatibility_en;
- int tbi_compatibility_on;
- int fc_send_xon;
- int report_tx_early;
- int first_init;
- int tx_err_index;
- int rx_err_index;
- int rx_slot; /* MAL Receive Slot */
- int rx_i_index; /* Receive Interrupt Queue Index */
- int rx_u_index; /* Receive User Queue Index */
- int tx_slot; /* MAL Transmit Slot */
- int tx_i_index; /* Transmit Interrupt Queue Index */
- int tx_u_index; /* Transmit User Queue Index */
- int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
- int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
- int is_receiving; /* sync with eth interrupt */
- int print_speed; /* print speed message upon start */
- EMAC_STATS_ST stats;
-} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
-
-
-#if defined(CONFIG_440GX) || defined(CONFIG_460GT)
-#define EMAC_NUM_DEV 4
-#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
- !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
-#define EMAC_NUM_DEV 2
-#else
-#define EMAC_NUM_DEV 1
-#endif
-
-#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
-#define EMAC_STACR_OC_MASK (0x00008000)
-#else
-#define EMAC_STACR_OC_MASK (0x00000000)
-#endif
-
-/*
- * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
- * not have a pin function control (PFC) register to otherwise determine
- * the bridge configuration.
- */
-#define EMAC_PHY_MODE_NONE 0
-#define EMAC_PHY_MODE_NONE_RGMII 1
-#define EMAC_PHY_MODE_RGMII_NONE 2
-#define EMAC_PHY_MODE_RGMII_RGMII 3
-#define EMAC_PHY_MODE_NONE_GMII 4
-#define EMAC_PHY_MODE_GMII_NONE 5
-#define EMAC_PHY_MODE_NONE_MII 6
-#define EMAC_PHY_MODE_MII_NONE 7
-
-/* ZMII Bridge Register addresses */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
-#else
-#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
-#endif
-#define ZMII0_FER (ZMII0_BASE)
-#define ZMII0_SSR (ZMII0_BASE + 4)
-#define ZMII0_SMIISR (ZMII0_BASE + 8)
-
-/* ZMII FER Register Bit Definitions */
-#define ZMII_FER_DIS (0x0)
-#define ZMII_FER_MDI (0x8)
-#define ZMII_FER_SMII (0x4)
-#define ZMII_FER_RMII (0x2)
-#define ZMII_FER_MII (0x1)
-
-#define ZMII_FER_RSVD11 (0x00200000)
-#define ZMII_FER_RSVD10 (0x00100000)
-#define ZMII_FER_RSVD14_31 (0x0003FFFF)
-
-#define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
-
-
-/* ZMII Speed Selection Register Bit Definitions */
-#define ZMII0_SSR_SCI (0x4)
-#define ZMII0_SSR_FSS (0x2)
-#define ZMII0_SSR_SP (0x1)
-#define ZMII0_SSR_RSVD16_31 (0x0000FFFF)
-
-#define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16)
-
-
-/* ZMII SMII Status Register Bit Definitions */
-#define ZMII0_SMIISR_E1 (0x80)
-#define ZMII0_SMIISR_EC (0x40)
-#define ZMII0_SMIISR_EN (0x20)
-#define ZMII0_SMIISR_EJ (0x10)
-#define ZMII0_SMIISR_EL (0x08)
-#define ZMII0_SMIISR_ED (0x04)
-#define ZMII0_SMIISR_ES (0x02)
-#define ZMII0_SMIISR_EF (0x01)
-
-#define ZMII0_SMIISR_V(__x) ((3 - __x) * 8)
-
-/* RGMII Register Addresses */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
-#elif defined(CONFIG_405EX)
-#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
-#else
-#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
-#endif
-#define RGMII_FER (RGMII_BASE + 0x00)
-#define RGMII_SSR (RGMII_BASE + 0x04)
-
-#if defined(CONFIG_460GT)
-#define RGMII1_BASE_OFFSET 0x100
-#endif
-
-/* RGMII Function Enable (FER) Register Bit Definitions */
-#define RGMII_FER_DIS (0x00)
-#define RGMII_FER_RTBI (0x04)
-#define RGMII_FER_RGMII (0x05)
-#define RGMII_FER_TBI (0x06)
-#define RGMII_FER_GMII (0x07)
-#define RGMII_FER_MII (RGMII_FER_GMII)
-
-#define RGMII_FER_V(__x) ((__x - 2) * 4)
-
-#define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
-
-/* RGMII Speed Selection Register Bit Definitions */
-#define RGMII_SSR_SP_10MBPS (0x00)
-#define RGMII_SSR_SP_100MBPS (0x02)
-#define RGMII_SSR_SP_1000MBPS (0x04)
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
-#define RGMII_SSR_V(__x) ((__x) * 8)
-#else
-#define RGMII_SSR_V(__x) ((__x -2) * 8)
-#endif
-
-/*---------------------------------------------------------------------------+
-| TCP/IP Acceleration Hardware (TAH) 440GX Only
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX)
-#define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
-#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
-#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
-#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
-#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
-#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
-#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
-#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
-#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
-#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
-
-/* TAH Revision */
-#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
-#define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
-
-#define TAH_REV_RN_V (8)
-#define TAH_REV_BN_V (0)
-
-/* TAH Mode Register */
-#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
-#define TAH_MR_SR (0x40000000) /* Software reset */
-#define TAH_MR_ST (0x3F000000) /* Send Threshold */
-#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
-#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
-#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
-#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
-
-#define TAH_MR_ST_V (20)
-#define TAH_MR_TFS_V (17)
-
-#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
-#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
-#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
-#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
-#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
-
-
-/* TAH Segment Size Registers 0:5 */
-#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
-#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
-#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
-
-/* TAH Transmit Status Register */
-#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
-#define TAH_TSR_UH (0x40000000) /* Unrecognized header */
-#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
-#define TAH_TSR_IPOP (0x10000000) /* IP option present */
-#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
-#define TAH_TSR_ILTS (0x04000000) /* IP length too short */
-#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
-#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
-#define TAH_TSR_TFP (0x00800000) /* TCP flags present */
-#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
-#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
-#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
-#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
-#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
-#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
-#endif /* CONFIG_440GX */
-
-
-/* Ethernet MAC Regsiter Addresses */
-#if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
-#else
-#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
-#endif
-#else
-#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
-#define EMAC0_BASE 0xEF600900
-#else
-#define EMAC0_BASE 0xEF600800
-#endif
-#endif
-
-#if defined(CONFIG_440EPX)
-#define EMAC1_BASE 0xEF600F00
-#define EMAC1_MR1 (EMAC1_BASE + 0x04)
-#endif
-
-#define EMAC0_MR0 (EMAC0_BASE)
-#define EMAC0_MR1 (EMAC0_BASE + 0x04)
-#define EMAC0_TMR0 (EMAC0_BASE + 0x08)
-#define EMAC0_TMR1 (EMAC0_BASE + 0x0c)
-#define EMAC0_RXM (EMAC0_BASE + 0x10)
-#define EMAC0_ISR (EMAC0_BASE + 0x14)
-#define EMAC0_IER (EMAC0_BASE + 0x18)
-#define EMAC0_IAH (EMAC0_BASE + 0x1c)
-#define EMAC0_IAL (EMAC0_BASE + 0x20)
-#define EMAC0_PTR (EMAC0_BASE + 0x2c)
-#define EMAC0_PAUSE_TIME_REG EMAC0_PTR
-#define EMAC0_IPGVR (EMAC0_BASE + 0x58)
-#define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR
-#define EMAC0_STACR (EMAC0_BASE + 0x5c)
-#define EMAC0_TRTR (EMAC0_BASE + 0x60)
-#define EMAC0_RWMR (EMAC0_BASE + 0x64)
-#define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR
-
-/* bit definitions */
-/* MODE REG 0 */
-#define EMAC_MR0_RXI (0x80000000)
-#define EMAC_MR0_TXI (0x40000000)
-#define EMAC_MR0_SRST (0x20000000)
-#define EMAC_MR0_TXE (0x10000000)
-#define EMAC_MR0_RXE (0x08000000)
-#define EMAC_MR0_WKE (0x04000000)
-
-/* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
-/* MODE Reg 1 */
-#define EMAC_MR1_FDE (0x80000000)
-#define EMAC_MR1_ILE (0x40000000)
-#define EMAC_MR1_VLE (0x20000000)
-#define EMAC_MR1_EIFC (0x10000000)
-#define EMAC_MR1_APP (0x08000000)
-#define EMAC_MR1_RSVD (0x06000000)
-#define EMAC_MR1_IST (0x01000000)
-#define EMAC_MR1_MF_1000GPCS (0x00C00000)
-#define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
-#define EMAC_MR1_MF_100MBPS (0x00400000)
-#define EMAC_MR1_RFS_MASK (0x00380000)
-#define EMAC_MR1_RFS_16K (0x00280000)
-#define EMAC_MR1_RFS_8K (0x00200000)
-#define EMAC_MR1_RFS_4K (0x00180000)
-#define EMAC_MR1_RFS_2K (0x00100000)
-#define EMAC_MR1_RFS_1K (0x00080000)
-#define EMAC_MR1_TX_FIFO_MASK (0x00070000)
-#define EMAC_MR1_TX_FIFO_16K (0x00050000)
-#define EMAC_MR1_TX_FIFO_8K (0x00040000)
-#define EMAC_MR1_TX_FIFO_4K (0x00030000)
-#define EMAC_MR1_TX_FIFO_2K (0x00020000)
-#define EMAC_MR1_TX_FIFO_1K (0x00010000)
-#define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */
-#define EMAC_MR1_MWSW (0x00007000)
-#define EMAC_MR1_JUMBO_ENABLE (0x00000800)
-#define EMAC_MR1_IPPA (0x000007c0)
-#define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6)
-#define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f)
-#define EMAC_MR1_OBCI_GT100 (0x00000020)
-#define EMAC_MR1_OBCI_100 (0x00000018)
-#define EMAC_MR1_OBCI_83 (0x00000010)
-#define EMAC_MR1_OBCI_66 (0x00000008)
-#define EMAC_MR1_RSVD1 (0x00000007)
-#else /* defined(CONFIG_440GX) */
-/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
-#define EMAC_MR1_FDE 0x80000000
-#define EMAC_MR1_ILE 0x40000000
-#define EMAC_MR1_VLE 0x20000000
-#define EMAC_MR1_EIFC 0x10000000
-#define EMAC_MR1_APP 0x08000000
-#define EMAC_MR1_AEMI 0x02000000
-#define EMAC_MR1_IST 0x01000000
-#define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
-#define EMAC_MR1_MF_100MBPS 0x00400000
-#define EMAC_MR1_RFS_MASK 0x00300000
-#define EMAC_MR1_RFS_4K 0x00300000
-#define EMAC_MR1_RFS_2K 0x00200000
-#define EMAC_MR1_RFS_1K 0x00100000
-#define EMAC_MR1_RFS_512 0x00000000
-#define EMAC_MR1_TX_FIFO_MASK 0x000c0000
-#define EMAC_MR1_TX_FIFO_2K 0x00080000
-#define EMAC_MR1_TX_FIFO_1K 0x00040000
-#define EMAC_MR1_TX_FIFO_512 0x00000000
-#define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
-#define EMAC_MR1_TR0_MULTI 0x00008000
-#define EMAC_MR1_TR1_DEPEND 0x00004000
-#define EMAC_MR1_TR1_MULTI 0x00002000
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define EMAC_MR1_JUMBO_ENABLE 0x00001000
-#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
-#endif /* defined(CONFIG_440GX) */
-
-#define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
-#if defined(CONFIG_405EZ)
-/* 405EZ only supports 512 bytes fifos */
-#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
-#else
-/* Set receive fifo to 4k and tx fifo to 2k */
-#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
-#endif
-
-/* Transmit Mode Register 0 */
-#define EMAC_TMR0_GNP0 (0x80000000)
-#define EMAC_TMR0_GNP1 (0x40000000)
-#define EMAC_TMR0_GNPD (0x20000000)
-#define EMAC_TMR0_FC (0x10000000)
-
-/* Receive Mode Register */
-#define EMAC_RMR_SP (0x80000000)
-#define EMAC_RMR_SFCS (0x40000000)
-#define EMAC_RMR_ARRP (0x20000000)
-#define EMAC_RMR_ARP (0x10000000)
-#define EMAC_RMR_AROP (0x08000000)
-#define EMAC_RMR_ARPI (0x04000000)
-#define EMAC_RMR_PPP (0x02000000)
-#define EMAC_RMR_PME (0x01000000)
-#define EMAC_RMR_PMME (0x00800000)
-#define EMAC_RMR_IAE (0x00400000)
-#define EMAC_RMR_MIAE (0x00200000)
-#define EMAC_RMR_BAE (0x00100000)
-#define EMAC_RMR_MAE (0x00080000)
-
-/* Interrupt Status & enable Regs */
-#define EMAC_ISR_OVR (0x02000000)
-#define EMAC_ISR_PP (0x01000000)
-#define EMAC_ISR_BP (0x00800000)
-#define EMAC_ISR_RP (0x00400000)
-#define EMAC_ISR_SE (0x00200000)
-#define EMAC_ISR_SYE (0x00100000)
-#define EMAC_ISR_BFCS (0x00080000)
-#define EMAC_ISR_PTLE (0x00040000)
-#define EMAC_ISR_ORE (0x00020000)
-#define EMAC_ISR_IRE (0x00010000)
-#define EMAC_ISR_DBDM (0x00000200)
-#define EMAC_ISR_DB0 (0x00000100)
-#define EMAC_ISR_SE0 (0x00000080)
-#define EMAC_ISR_TE0 (0x00000040)
-#define EMAC_ISR_DB1 (0x00000020)
-#define EMAC_ISR_SE1 (0x00000010)
-#define EMAC_ISR_TE1 (0x00000008)
-#define EMAC_ISR_MOS (0x00000002)
-#define EMAC_ISR_MOF (0x00000001)
-
-/* STA CONTROL REG */
-#define EMAC_STACR_OC (0x00008000)
-#define EMAC_STACR_PHYE (0x00004000)
-
-#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
-#define EMAC_STACR_INDIRECT_MODE (0x00002000)
-#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
-#define EMAC_STACR_READ (0x00001000) /* $BUC */
-#define EMAC_STACR_OP_MASK (0x00001800)
-#define EMAC_STACR_MDIO_ADDR (0x00000000)
-#define EMAC_STACR_MDIO_WRITE (0x00000800)
-#define EMAC_STACR_MDIO_READ (0x00001800)
-#define EMAC_STACR_MDIO_READ_INC (0x00001000)
-#else
-#define EMAC_STACR_WRITE (0x00002000)
-#define EMAC_STACR_READ (0x00001000)
-#endif
-
-#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
-#define EMAC_STACR_CLK_66MHZ (0x00000400)
-#define EMAC_STACR_CLK_100MHZ (0x00000C00)
-
-/* Transmit Request Threshold Register */
-#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
-#define EMAC_TRTR_192 (0x10000000)
-#define EMAC_TRTR_128 (0x01000000)
-
-/* the follwing defines are for the MadMAL status and control registers. */
-/* For bits 0..5 look at the mal.h file */
-#define EMAC_TX_CTRL_GFCS (0x0200)
-#define EMAC_TX_CTRL_GP (0x0100)
-#define EMAC_TX_CTRL_ISA (0x0080)
-#define EMAC_TX_CTRL_RSA (0x0040)
-#define EMAC_TX_CTRL_IVT (0x0020)
-#define EMAC_TX_CTRL_RVT (0x0010)
-
-#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
-
-#define EMAC_TX_ST_BFCS (0x0200)
-#define EMAC_TX_ST_BPP (0x0100)
-#define EMAC_TX_ST_LCS (0x0080)
-#define EMAC_TX_ST_ED (0x0040)
-#define EMAC_TX_ST_EC (0x0020)
-#define EMAC_TX_ST_LC (0x0010)
-#define EMAC_TX_ST_MC (0x0008)
-#define EMAC_TX_ST_SC (0x0004)
-#define EMAC_TX_ST_UR (0x0002)
-#define EMAC_TX_ST_SQE (0x0001)
-
-#define EMAC_TX_ST_DEFAULT (0x03F3)
-
-
-/* madmal receive status / Control bits */
-
-#define EMAC_RX_ST_OE (0x0200)
-#define EMAC_RX_ST_PP (0x0100)
-#define EMAC_RX_ST_BP (0x0080)
-#define EMAC_RX_ST_RP (0x0040)
-#define EMAC_RX_ST_SE (0x0020)
-#define EMAC_RX_ST_AE (0x0010)
-#define EMAC_RX_ST_BFCS (0x0008)
-#define EMAC_RX_ST_PTL (0x0004)
-#define EMAC_RX_ST_ORE (0x0002)
-#define EMAC_RX_ST_IRE (0x0001)
-/* all the errors we care about */
-#define EMAC_RX_ERRORS (0x03FF)
-
-#endif /* _PPC4XX_ENET_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_PPC_GPIO_H
-#define __ASM_PPC_GPIO_H
-
-#include <asm/types.h>
-
-/* 4xx PPC's have 2 GPIO controllers */
-#if defined(CONFIG_405EZ) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define GPIO_GROUP_MAX 2
-#else
-#define GPIO_GROUP_MAX 1
-#endif
-
-/* GPIO controller */
-struct ppc4xx_gpio {
- u32 or; /* Output Control */
- u32 tcr; /* Tri-State Control */
- u32 osl; /* Output Select 16..31 */
- u32 osh; /* Output Select 0..15 */
- u32 tsl; /* Tri-State Select 16..31 */
- u32 tsh; /* Tri-State Select 0..15 */
- u32 odr; /* Open Drain */
- u32 ir; /* Input */
- u32 rr1; /* Receive Register 1 */
- u32 rr2; /* Receive Register 2 */
- u32 rr3; /* Receive Register 3 */
- u32 reserved;
- u32 is1l; /* Input Select 1 16..31 */
- u32 is1h; /* Input Select 1 0..15 */
- u32 is2l; /* Input Select 2 16..31 */
- u32 is2h; /* Input Select 2 0..15 */
- u32 is3l; /* Input Select 3 16..31 */
- u32 is3h; /* Input Select 3 0..15 */
-};
-
-/* Offsets */
-#define GPIOx_OR 0x00 /* GPIO Output Register */
-#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
-#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
-#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
-#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
-#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
-#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
-#define GPIOx_IR 0x1C /* GPIO Input Register */
-#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
-#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
-#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
-#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
-#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
-#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
-#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
-#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
-#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
-
-#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */
-#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */
-#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */
-#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
-#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
-#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
-#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
-
-#define GPIO0 0
-#define GPIO1 1
-
-#define GPIO_MAX 32
-#define GPIO_ALT1_SEL 0x40000000
-#define GPIO_ALT2_SEL 0x80000000
-#define GPIO_ALT3_SEL 0xc0000000
-#define GPIO_IN_SEL 0x40000000
-#define GPIO_MASK 0xc0000000
-
-#define GPIO_VAL(gpio) (0x80000000 >> (gpio))
-
-#ifndef __ASSEMBLY__
-typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
-typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
-typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
-
-typedef struct {
- unsigned long add; /* gpio core base address */
- gpio_driver_t in_out; /* Driver Setting */
- gpio_select_t alt_nb; /* Selected Alternate */
- gpio_out_t out_val;/* Default Output Value */
-} gpio_param_s;
-#endif
-
-void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
-void gpio_write_bit(int pin, int val);
-int gpio_read_out_bit(int pin);
-int gpio_read_in_bit(int pin);
-void gpio_set_chip_configuration(void);
-
-#endif /* __ASM_PPC_GPIO_H */
+++ /dev/null
-/*
- * (C) Copyright 2007-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _4xx_i2c_h_
-#define _4xx_i2c_h_
-
-#define IIC_OK 0
-#define IIC_NOK 1
-#define IIC_NOK_LA 2 /* Lost arbitration */
-#define IIC_NOK_ICT 3 /* Incomplete transfer */
-#define IIC_NOK_XFRA 4 /* Transfer aborted */
-#define IIC_NOK_DATA 5 /* No data in buffer */
-#define IIC_NOK_TOUT 6 /* Transfer timeout */
-
-#define IIC_TIMEOUT 1 /* 1 second */
-
-struct ppc4xx_i2c {
- u8 mdbuf;
- u8 res1;
- u8 sdbuf;
- u8 res2;
- u8 lmadr;
- u8 hmadr;
- u8 cntl;
- u8 mdcntl;
- u8 sts;
- u8 extsts;
- u8 lsadr;
- u8 hsadr;
- u8 clkdiv;
- u8 intrmsk;
- u8 xfrcnt;
- u8 xtcntlss;
- u8 directcntl;
- u8 intr;
-};
-
-/* MDCNTL Register Bit definition */
-#define IIC_MDCNTL_HSCL 0x01
-#define IIC_MDCNTL_EUBS 0x02
-#define IIC_MDCNTL_EINT 0x04
-#define IIC_MDCNTL_ESM 0x08
-#define IIC_MDCNTL_FSM 0x10
-#define IIC_MDCNTL_EGC 0x20
-#define IIC_MDCNTL_FMDB 0x40
-#define IIC_MDCNTL_FSDB 0x80
-
-/* CNTL Register Bit definition */
-#define IIC_CNTL_PT 0x01
-#define IIC_CNTL_READ 0x02
-#define IIC_CNTL_CHT 0x04
-#define IIC_CNTL_RPST 0x08
-/* bit 2/3 for Transfer count*/
-#define IIC_CNTL_AMD 0x40
-#define IIC_CNTL_HMT 0x80
-
-/* STS Register Bit definition */
-#define IIC_STS_PT 0x01
-#define IIC_STS_IRQA 0x02
-#define IIC_STS_ERR 0x04
-#define IIC_STS_SCMP 0x08
-#define IIC_STS_MDBF 0x10
-#define IIC_STS_MDBS 0x20
-#define IIC_STS_SLPR 0x40
-#define IIC_STS_SSS 0x80
-
-/* EXTSTS Register Bit definition */
-#define IIC_EXTSTS_XFRA 0x01
-#define IIC_EXTSTS_ICT 0x02
-#define IIC_EXTSTS_LA 0x04
-#define IIC_EXTSTS_BCS_MASK 0x70
-#define IIC_EXTSTS_BCS_FREE 0x40
-
-/* XTCNTLSS Register Bit definition */
-#define IIC_XTCNTLSS_SRST 0x01
-#define IIC_XTCNTLSS_EPI 0x02
-#define IIC_XTCNTLSS_SDBF 0x04
-#define IIC_XTCNTLSS_SBDD 0x08
-#define IIC_XTCNTLSS_SWS 0x10
-#define IIC_XTCNTLSS_SWC 0x20
-#define IIC_XTCNTLSS_SRS 0x40
-#define IIC_XTCNTLSS_SRC 0x80
-
-/* IICx_DIRECTCNTL register */
-#define IIC_DIRCNTL_SDAC 0x08
-#define IIC_DIRCNTL_SCC 0x04
-#define IIC_DIRCNTL_MSDA 0x02
-#define IIC_DIRCNTL_MSC 0x01
-
-#define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f)
-#endif
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC4xx_ISRAM_H_
-#define _PPC4xx_ISRAM_H_
-
-/*
- * Internal SRAM
- */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define ISRAM0_DCR_BASE 0x380
-#else
-#define ISRAM0_DCR_BASE 0x020
-#endif
-#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
-#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
-#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
-#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
-#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
-#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
-#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
-#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
-#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
-#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
-#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define ISRAM1_DCR_BASE 0x0B0
-#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
-#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
-#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */
-#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */
-#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */
-#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */
-#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */
-#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */
-#endif /* CONFIG_460EX || CONFIG_460GT */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define ISRAM1_SIZE 0x0984 /* OCM size 64k */
-#endif
-
-/*
- * L2 Cache
- */
-#if defined (CONFIG_440GX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
-#define L2_CACHE_BASE 0x030
-#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
-#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
-#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */
-#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */
-#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */
-#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
-#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
-#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
-#endif /* CONFIG_440GX */
-
-#endif /* _PPC4xx_ISRAM_H_ */
+++ /dev/null
-/* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*----------------------------------------------------------------------------+
-|
-| File Name: mal.h
-|
-| Function: Header file for the MAL (MADMAL) macro on the 405GP.
-|
-| Author: Mark Wisner
-|
-| Change Activity-
-|
-| Date Description of Change BY
-| --------- --------------------- ---
-| 29-Apr-99 Created MKW
-|
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-| 17-Nov-03 Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
-| Added register bit definitions to support multiple channels
-+----------------------------------------------------------------------------*/
-#ifndef _mal_h_
-#define _mal_h_
-
-#if !defined(MAL_DCR_BASE)
-#define MAL_DCR_BASE 0x180
-#endif
-#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */
-#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */
-#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
-#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
-#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
-#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/
-#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */
-#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/
-#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
-#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
-#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/
-#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */
-#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */
-#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */
-#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */
-#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */
-#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */
-#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */
-#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */
-#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */
-#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */
-#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */
-#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */
-#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/
-#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/
-#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */
-#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */
-#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */
-#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
-#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
-#endif /* CONFIG_440GX */
-
-/* MADMAL transmit and receive status/control bits */
-/* for COMMAC bits, refer to the COMMAC header file */
-
-#define MAL_TX_CTRL_READY 0x8000
-#define MAL_TX_CTRL_WRAP 0x4000
-#define MAL_TX_CTRL_CM 0x2000
-#define MAL_TX_CTRL_LAST 0x1000
-#define MAL_TX_CTRL_INTR 0x0400
-
-#define MAL_RX_CTRL_EMPTY 0x8000
-#define MAL_RX_CTRL_WRAP 0x4000
-#define MAL_RX_CTRL_CM 0x2000
-#define MAL_RX_CTRL_LAST 0x1000
-#define MAL_RX_CTRL_FIRST 0x0800
-#define MAL_RX_CTRL_INTR 0x0400
-
- /* Configuration Reg */
-#define MAL_CR_MMSR 0x80000000
-#define MAL_CR_PLBP_1 0x00400000 /* lowsest is 00 */
-#define MAL_CR_PLBP_2 0x00800000
-#define MAL_CR_PLBP_3 0x00C00000 /* highest */
-#define MAL_CR_GA 0x00200000
-#define MAL_CR_OA 0x00100000
-#define MAL_CR_PLBLE 0x00080000
-#define MAL_CR_PLBLT_1 0x00040000
-#define MAL_CR_PLBLT_2 0x00020000
-#define MAL_CR_PLBLT_3 0x00010000
-#define MAL_CR_PLBLT_4 0x00008000
-#define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
-#define MAL_CR_PLBB 0x00004000
-#define MAL_CR_OPBBL 0x00000080
-#define MAL_CR_EOPIE 0x00000004
-#define MAL_CR_LEA 0x00000002
-#define MAL_CR_MSD 0x00000001
-
- /* Error Status Reg */
-#define MAL_ESR_EVB 0x80000000
-#define MAL_ESR_CID 0x40000000
-#define MAL_ESR_DE 0x00100000
-#define MAL_ESR_ONE 0x00080000
-#define MAL_ESR_OTE 0x00040000
-#define MAL_ESR_OSE 0x00020000
-#define MAL_ESR_PEIN 0x00010000
- /* same bit position as the IER */
- /* VV VV */
-#define MAL_ESR_DEI 0x00000010
-#define MAL_ESR_ONEI 0x00000008
-#define MAL_ESR_OTEI 0x00000004
-#define MAL_ESR_OSEI 0x00000002
-#define MAL_ESR_PBEI 0x00000001
- /* ^^ ^^ */
- /* Mal IER */
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
-#define MAL_IER_PT 0x00000080
-#define MAL_IER_PRE 0x00000040
-#define MAL_IER_PWE 0x00000020
-#define MAL_IER_DE 0x00000010
-#define MAL_IER_OTE 0x00000004
-#define MAL_IER_OE 0x00000002
-#define MAL_IER_PE 0x00000001
-#else
-#define MAL_IER_DE 0x00000010
-#define MAL_IER_NE 0x00000008
-#define MAL_IER_TE 0x00000004
-#define MAL_IER_OPBE 0x00000002
-#define MAL_IER_PLBE 0x00000001
-#endif
-
-/* MAL Channel Active Set and Reset Registers */
-#define MAL_TXRX_CASR (0x80000000)
-
-#define MAL_TXRX_CASR_V(__x) (__x) /* Channel 0 shifts 0, channel 1 shifts 1, etc */
-
-
-/* MAL Buffer Descriptor structure */
-typedef struct {
- short ctrl; /* MAL / Commac status control bits */
- short data_len; /* Max length is 4K-1 (12 bits) */
- char *data_ptr; /* pointer to actual data buffer */
-} mal_desc_t;
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC4xx_SDRAM_H_
-#define _PPC4xx_SDRAM_H_
-
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM)
-
-/*
- * SDRAM Controller
- */
-
-#ifndef CONFIG_405EP
-#define SDRAM0_BESR0 0x00 /* bus error syndrome reg a */
-#define SDRAM0_BESRS0 0x04 /* bus error syndrome reg set a */
-#define SDRAM0_BESR1 0x08 /* bus error syndrome reg b */
-#define SDRAM0_BESRS1 0x0c /* bus error syndrome reg set b */
-#define SDRAM0_BEAR 0x10 /* bus error address reg */
-#endif
-#define SDRAM0_CFG 0x20 /* memory controller options 1 */
-#define SDRAM0_STATUS 0x24 /* memory status */
-#define SDRAM0_RTR 0x30 /* refresh timer reg */
-#define SDRAM0_PMIT 0x34 /* power management idle timer */
-#define SDRAM0_B0CR 0x40 /* memory bank 0 configuration */
-#define SDRAM0_B1CR 0x44 /* memory bank 1 configuration */
-#ifndef CONFIG_405EP
-#define SDRAM0_B2CR 0x48 /* memory bank 2 configuration */
-#define SDRAM0_B3CR 0x4c /* memory bank 3 configuration */
-#endif
-#define SDRAM0_TR 0x80 /* timing reg 1 */
-#ifndef CONFIG_405EP
-#define SDRAM0_ECCCFG 0x94 /* ECC configuration */
-#define SDRAM0_ECCESR 0x98 /* ECC error status */
-#endif
-
-#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
-
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
-
-/*
- * Memory controller registers
- */
-#define SDRAM_CFG0 0x20 /* memory controller options 0 */
-#define SDRAM_CFG1 0x21 /* memory controller options 1 */
-
-#define SDRAM0_BESR0 0x0000 /* bus error status reg 0 */
-#define SDRAM0_BESR1 0x0008 /* bus error status reg 1 */
-#define SDRAM0_BEAR 0x0010 /* bus error address reg */
-#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
-#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */
-#define SDRAM0_CFG1 0x0021 /* ddr sdram options 1 */
-#define SDRAM0_DEVOPT 0x0022 /* ddr sdram device options */
-#define SDRAM0_MCSTS 0x0024 /* memory controller status */
-#define SDRAM0_RTR 0x0030 /* refresh timer register */
-#define SDRAM0_PMIT 0x0034 /* power management idle timer */
-#define SDRAM0_UABBA 0x0038 /* plb UABus base address */
-#define SDRAM0_B0CR 0x0040 /* ddr sdram bank 0 configuration */
-#define SDRAM0_B1CR 0x0044 /* ddr sdram bank 1 configuration */
-#define SDRAM0_B2CR 0x0048 /* ddr sdram bank 2 configuration */
-#define SDRAM0_B3CR 0x004c /* ddr sdram bank 3 configuration */
-#define SDRAM0_TR0 0x0080 /* sdram timing register 0 */
-#define SDRAM0_TR1 0x0081 /* sdram timing register 1 */
-#define SDRAM0_CLKTR 0x0082 /* ddr clock timing register */
-#define SDRAM0_WDDCTR 0x0083 /* write data/dm/dqs clock timing reg */
-#define SDRAM0_DLYCAL 0x0084 /* delay line calibration register */
-#define SDRAM0_ECCESR 0x0098 /* ECC error status */
-
-/*
- * Memory Controller Options 0
- */
-#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
-#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
-#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
-#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
-#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
-#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
-#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
-#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
-#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
-#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
-#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
-#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
-
-/*
- * Memory Controller Options 1
- */
-#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
-#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
-
-/*
- * SDRAM DEVPOT Options
- */
-#define SDRAM_DEVOPT_DLL 0x80000000
-#define SDRAM_DEVOPT_DS 0x40000000
-
-/*
- * SDRAM MCSTS Options
- */
-#define SDRAM_MCSTS_MRSC 0x80000000
-#define SDRAM_MCSTS_SRMS 0x40000000
-#define SDRAM_MCSTS_CIS 0x20000000
-#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */
-
-/*
- * SDRAM Refresh Timer Register
- */
-#define SDRAM_RTR_RINT_MASK 0xFFFF0000
-#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
-
-/*
- * SDRAM UABus Base Address Reg
- */
-#define SDRAM_UABBA_UBBA_MASK 0x0000000F
-
-/*
- * Memory Bank 0-7 configuration
- */
-#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
-#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
-#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
-#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
-#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
-#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
-#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
-#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
-#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
-#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
-#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
-#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
-#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
-#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
-#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
-
-/*
- * SDRAM TR0 Options
- */
-#define SDRAM_TR0_SDWR_MASK 0x80000000
-#define SDRAM_TR0_SDWR_2_CLK 0x00000000
-#define SDRAM_TR0_SDWR_3_CLK 0x80000000
-#define SDRAM_TR0_SDWD_MASK 0x40000000
-#define SDRAM_TR0_SDWD_0_CLK 0x00000000
-#define SDRAM_TR0_SDWD_1_CLK 0x40000000
-#define SDRAM_TR0_SDCL_MASK 0x01800000
-#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
-#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
-#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
-#define SDRAM_TR0_SDPA_MASK 0x000C0000
-#define SDRAM_TR0_SDPA_2_CLK 0x00040000
-#define SDRAM_TR0_SDPA_3_CLK 0x00080000
-#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
-#define SDRAM_TR0_SDCP_MASK 0x00030000
-#define SDRAM_TR0_SDCP_2_CLK 0x00000000
-#define SDRAM_TR0_SDCP_3_CLK 0x00010000
-#define SDRAM_TR0_SDCP_4_CLK 0x00020000
-#define SDRAM_TR0_SDCP_5_CLK 0x00030000
-#define SDRAM_TR0_SDLD_MASK 0x0000C000
-#define SDRAM_TR0_SDLD_1_CLK 0x00000000
-#define SDRAM_TR0_SDLD_2_CLK 0x00004000
-#define SDRAM_TR0_SDRA_MASK 0x0000001C
-#define SDRAM_TR0_SDRA_6_CLK 0x00000000
-#define SDRAM_TR0_SDRA_7_CLK 0x00000004
-#define SDRAM_TR0_SDRA_8_CLK 0x00000008
-#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
-#define SDRAM_TR0_SDRA_10_CLK 0x00000010
-#define SDRAM_TR0_SDRA_11_CLK 0x00000014
-#define SDRAM_TR0_SDRA_12_CLK 0x00000018
-#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
-#define SDRAM_TR0_SDRD_MASK 0x00000003
-#define SDRAM_TR0_SDRD_2_CLK 0x00000001
-#define SDRAM_TR0_SDRD_3_CLK 0x00000002
-#define SDRAM_TR0_SDRD_4_CLK 0x00000003
-
-/*
- * SDRAM TR1 Options
- */
-#define SDRAM_TR1_RDSS_MASK 0xC0000000
-#define SDRAM_TR1_RDSS_TR0 0x00000000
-#define SDRAM_TR1_RDSS_TR1 0x40000000
-#define SDRAM_TR1_RDSS_TR2 0x80000000
-#define SDRAM_TR1_RDSS_TR3 0xC0000000
-#define SDRAM_TR1_RDSL_MASK 0x00C00000
-#define SDRAM_TR1_RDSL_STAGE1 0x00000000
-#define SDRAM_TR1_RDSL_STAGE2 0x00400000
-#define SDRAM_TR1_RDSL_STAGE3 0x00800000
-#define SDRAM_TR1_RDCD_MASK 0x00000800
-#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
-#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
-#define SDRAM_TR1_RDCT_MASK 0x000001FF
-#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
-#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
-#define SDRAM_TR1_RDCT_MIN 0x00000000
-#define SDRAM_TR1_RDCT_MAX 0x000001FF
-
-/*
- * SDRAM WDDCTR Options
- */
-#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
-#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
-#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
-#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
-#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
-
-/*
- * SDRAM CLKTR Options
- */
-#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
-#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
-#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
-#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
-#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
-
-/*
- * SDRAM DLYCAL Options
- */
-#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
-#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
-#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
-
-#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */
-
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
-
-#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
-#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
-#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
-
-#if !defined(CONFIG_405EX)
-/*
- * Memory queue defines
- */
-#define SDRAMQ_DCR_BASE 0x040
-
-#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
-#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
-#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
-#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
-#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
-#define SDRAM_CONF1HB_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */
-#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
-#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
-#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
-#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */
-#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
-#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
-#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */
-#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */
-
-#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
-#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
-#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
-#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
-#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
-#define SDRAM_CONF1LL_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */
-#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
-#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
-#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
-#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */
-#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
-#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
-#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */
-
-#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
-#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
-#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
-#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
-#define SDRAM_CONFPATHB_TPEN 0x08000000 /* Transaction Passing Enable - Bit 4 */
-
-#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
-
-/*
- * Memory Bank 0-7 configuration
- */
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
-#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
-#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
-#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
-#endif /* CONFIG_440SPE */
-#if defined(CONFIG_440SP)
-#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
-#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFF800000))
-#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFF800000))
-#endif /* CONFIG_440SP */
-#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
-#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((u32)(n))&0x3FF)<<6)
-#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((u32)(n))>>6)&0x3FF)
-#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
-#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
-#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
-#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
-#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
-#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
-#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
-#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
-#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
-#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
-#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
-#else /* CONFIG_405EX */
-/*
- * XXX - ToDo:
- * Revisit this file to check if all these 405EX defines are correct and
- * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02
- */
-#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF)
-#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0)
-#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1)
-#define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2)
-#define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3)
-#define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4)
-#define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5)
-#define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6)
-#define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7)
-#define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8)
-#define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9)
-#define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA)
-#define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB)
-#define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB
-#define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB
-#define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB
-#define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB
-#define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB
-#define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB
-#define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB
-#define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB
-#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB
-#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB
-#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB
-#endif /* CONFIG_405EX */
-
-/* The mode definitions are the same for all PPC4xx variants */
-#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0)
-#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1)
-#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2)
-#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3)
-#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4)
-#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5)
-#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6)
-#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7)
-#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8)
-#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9)
-#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0)
-#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1)
-
-/*
- * Memory controller registers
- */
-#if defined(CONFIG_405EX)
-#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
-#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
-#define SDRAM_BEARL 0x02 /* PLB bus error address low */
-#define SDRAM_BEARH 0x03 /* PLB bus error address high */
-#define SDRAM_WMIRQ 0x06 /* PLB write master interrupt (read/clear) */
-#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */
-#define SDRAM_PLBOPT 0x08 /* PLB slave options */
-#define SDRAM_PUABA 0x09 /* PLB upper address base */
-#define SDRAM_MCSTAT 0x1F /* memory controller status */
-#else /* CONFIG_405EX */
-#define SDRAM_MCSTAT 0x14 /* memory controller status */
-#endif /* CONFIG_405EX */
-#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
-#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
-#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
-#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
-#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
-#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
-#define SDRAM_CODT 0x26 /* on die termination for controller */
-#define SDRAM_VVPR 0x27 /* variable VRef programmming */
-#define SDRAM_OPARS 0x28 /* on chip driver control setup */
-#define SDRAM_OPART 0x29 /* on chip driver control trigger */
-#define SDRAM_RTR 0x30 /* refresh timer */
-#define SDRAM_PMIT 0x34 /* power management idle timer */
-#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
-#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
-#define SDRAM_MB2CF 0x48
-#define SDRAM_MB3CF 0x4C
-#define SDRAM_INITPLR0 0x50 /* manual initialization control */
-#define SDRAM_INITPLR1 0x51 /* manual initialization control */
-#define SDRAM_INITPLR2 0x52 /* manual initialization control */
-#define SDRAM_INITPLR3 0x53 /* manual initialization control */
-#define SDRAM_INITPLR4 0x54 /* manual initialization control */
-#define SDRAM_INITPLR5 0x55 /* manual initialization control */
-#define SDRAM_INITPLR6 0x56 /* manual initialization control */
-#define SDRAM_INITPLR7 0x57 /* manual initialization control */
-#define SDRAM_INITPLR8 0x58 /* manual initialization control */
-#define SDRAM_INITPLR9 0x59 /* manual initialization control */
-#define SDRAM_INITPLR10 0x5a /* manual initialization control */
-#define SDRAM_INITPLR11 0x5b /* manual initialization control */
-#define SDRAM_INITPLR12 0x5c /* manual initialization control */
-#define SDRAM_INITPLR13 0x5d /* manual initialization control */
-#define SDRAM_INITPLR14 0x5e /* manual initialization control */
-#define SDRAM_INITPLR15 0x5f /* manual initialization control */
-#define SDRAM_RQDC 0x70 /* read DQS delay control */
-#define SDRAM_RFDC 0x74 /* read feedback delay control */
-#define SDRAM_RDCC 0x78 /* read data capture control */
-#define SDRAM_DLCR 0x7A /* delay line calibration */
-#define SDRAM_CLKTR 0x80 /* DDR clock timing */
-#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
-#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
-#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
-#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
-#define SDRAM_MMODE 0x88 /* memory mode */
-#define SDRAM_MEMODE 0x89 /* memory extended mode */
-#define SDRAM_ECCES 0x98 /* ECC error status */
-#define SDRAM_CID 0xA4 /* core ID */
-#if !defined(CONFIG_405EX)
-#define SDRAM_RID 0xA8 /* revision ID */
-#endif
-#define SDRAM_FCSR 0xB0 /* feedback calibration status */
-#define SDRAM_RTSR 0xB1 /* run time status tracking */
-#if defined(CONFIG_405EX)
-#define SDRAM_RID 0xF8 /* revision ID */
-#endif
-
-/*
- * Memory Controller Bus Error Status
- */
-#define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF)
-#define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF)
-#define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, 0x0)
-#define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, 0x1)
-#define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, 0x2)
-#define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, 0x3)
-#define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, 0x4)
-#define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, 0x5)
-#define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, 0x6)
-#define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, 0x7)
-#define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7)
-#define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0x0)
-#define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 0x1)
-#define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0)
-#define SDRAM_BESR_M0RW_READ PPC_REG_VAL(8, 1)
-
-/*
- * Memory Controller Status
- */
-#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
-#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
-#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
-#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
-#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
-#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
-#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
-#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
-#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
-
-/*
- * Memory Controller Options 1
- */
-#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
-#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
-#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
-#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
-#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
-#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((u32)(n))>>28)&0x3)
-#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
-#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
-#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
-#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
-#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
-#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
-#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
-#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
-#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
-#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
-#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
-#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
-#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
-#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
-#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
-#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
-#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
-#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
-#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
-#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
-#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
-#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
-#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
-#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
-#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
-#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
-#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
-#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
-#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
-
-/*
- * Memory Controller Options 2
- */
-#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
-#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
-#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
-#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
-#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
-#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
-#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
-#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
-#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
-#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
-#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
-#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
-#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
-#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
-#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
-
-/*
- * SDRAM Refresh Timer Register
- */
-#define SDRAM_RTR_RINT_MASK 0xFFF80000
-#define SDRAM_RTR_RINT_ENCODE(n) ((((u32)(n))&0xFFF8)<<16)
-#define SDRAM_RTR_RINT_DECODE(n) ((((u32)(n))>>16)&0xFFF8)
-
-/*
- * SDRAM Read DQS Delay Control Register
- */
-#define SDRAM_RQDC_RQDE_MASK 0x80000000
-#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
-#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
-#define SDRAM_RQDC_RQFD_MASK 0x000001FF
-#define SDRAM_RQDC_RQFD_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
-
-#define SDRAM_RQDC_RQFD_MAX 0x1FF
-
-/*
- * SDRAM Read Data Capture Control Register
- */
-#define SDRAM_RDCC_RDSS_MASK 0xC0000000
-#define SDRAM_RDCC_RDSS_T1 0x00000000
-#define SDRAM_RDCC_RDSS_T2 0x40000000
-#define SDRAM_RDCC_RDSS_T3 0x80000000
-#define SDRAM_RDCC_RDSS_T4 0xC0000000
-#define SDRAM_RDCC_RSAE_MASK 0x00000001
-#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
-#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
-#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30)
-#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03)
-
-/*
- * SDRAM Read Feedback Delay Control Register
- */
-#define SDRAM_RFDC_ARSE_MASK 0x80000000
-#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
-#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
-#define SDRAM_RFDC_RFOS_MASK 0x007F0000
-#define SDRAM_RFDC_RFOS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define SDRAM_RFDC_RFFD_MASK 0x000007FF
-#define SDRAM_RFDC_RFFD_ENCODE(n) ((((u32)(n))&0x7FF)<<0)
-
-#define SDRAM_RFDC_RFFD_MAX 0x7FF
-
-/*
- * SDRAM Delay Line Calibration Register
- */
-#define SDRAM_DLCR_DCLM_MASK 0x80000000
-#define SDRAM_DLCR_DCLM_MANUAL 0x80000000
-#define SDRAM_DLCR_DCLM_AUTO 0x00000000
-#define SDRAM_DLCR_DLCR_MASK 0x08000000
-#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
-#define SDRAM_DLCR_DLCR_IDLE 0x00000000
-#define SDRAM_DLCR_DLCS_MASK 0x07000000
-#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
-#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
-#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
-#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
-#define SDRAM_DLCR_DLCS_ERROR 0x04000000
-#define SDRAM_DLCR_DLCV_MASK 0x000001FF
-#define SDRAM_DLCR_DLCV_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
-#define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF)
-
-/*
- * SDRAM Memory On Die Terimination Control Register
- */
-#define SDRAM_MODT_ODTON_DISABLE PPC_REG_VAL(0, 0)
-#define SDRAM_MODT_ODTON_ENABLE PPC_REG_VAL(0, 1)
-#define SDRAM_MODT_EB1W_DISABLE PPC_REG_VAL(1, 0)
-#define SDRAM_MODT_EB1W_ENABLE PPC_REG_VAL(1, 1)
-#define SDRAM_MODT_EB1R_DISABLE PPC_REG_VAL(2, 0)
-#define SDRAM_MODT_EB1R_ENABLE PPC_REG_VAL(2, 1)
-#define SDRAM_MODT_EB0W_DISABLE PPC_REG_VAL(7, 0)
-#define SDRAM_MODT_EB0W_ENABLE PPC_REG_VAL(7, 1)
-#define SDRAM_MODT_EB0R_DISABLE PPC_REG_VAL(8, 0)
-#define SDRAM_MODT_EB0R_ENABLE PPC_REG_VAL(8, 1)
-
-/*
- * SDRAM Controller On Die Termination Register
- */
-#define SDRAM_CODT_ODT_ON PPC_REG_VAL(0, 1)
-#define SDRAM_CODT_ODT_OFF PPC_REG_VAL(0, 0)
-#define SDRAM_CODT_RK1W_ON PPC_REG_VAL(1, 1)
-#define SDRAM_CODT_RK1W_OFF PPC_REG_VAL(1, 0)
-#define SDRAM_CODT_RK1R_ON PPC_REG_VAL(2, 1)
-#define SDRAM_CODT_RK1R_OFF PPC_REG_VAL(2, 0)
-#define SDRAM_CODT_RK0W_ON PPC_REG_VAL(7, 1)
-#define SDRAM_CODT_RK0W_OFF PPC_REG_VAL(7, 0)
-#define SDRAM_CODT_RK0R_ON PPC_REG_VAL(8, 1)
-#define SDRAM_CODT_RK0R_OFF PPC_REG_VAL(8, 0)
-#define SDRAM_CODT_ODTSH_NORMAL PPC_REG_VAL(10, 0)
-#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END PPC_REG_VAL(10, 1)
-#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START PPC_REG_VAL(10, 2)
-#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER PPC_REG_VAL(10, 3)
-#define SDRAM_CODT_CODTZ_75OHM PPC_REG_VAL(11, 0)
-#define SDRAM_CODT_CKEG_ON PPC_REG_VAL(12, 1)
-#define SDRAM_CODT_CKEG_OFF PPC_REG_VAL(12, 0)
-#define SDRAM_CODT_CTLG_ON PPC_REG_VAL(13, 1)
-#define SDRAM_CODT_CTLG_OFF PPC_REG_VAL(13, 0)
-#define SDRAM_CODT_FBDG_ON PPC_REG_VAL(14, 1)
-#define SDRAM_CODT_FBDG_OFF PPC_REG_VAL(14, 0)
-#define SDRAM_CODT_FBRG_ON PPC_REG_VAL(15, 1)
-#define SDRAM_CODT_FBRG_OFF PPC_REG_VAL(15, 0)
-#define SDRAM_CODT_CKLZ_36OHM PPC_REG_VAL(18, 1)
-#define SDRAM_CODT_CKLZ_18OHM PPC_REG_VAL(18, 0)
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK PPC_REG_VAL(26, 1)
-#define SDRAM_CODT_DQS_2_5_V_DDR1 PPC_REG_VAL(26, 0)
-#define SDRAM_CODT_DQS_1_8_V_DDR2 PPC_REG_VAL(26, 1)
-#define SDRAM_CODT_DQS_MASK PPC_REG_VAL(27, 1)
-#define SDRAM_CODT_DQS_DIFFERENTIAL PPC_REG_VAL(27, 0)
-#define SDRAM_CODT_DQS_SINGLE_END PPC_REG_VAL(27, 1)
-#define SDRAM_CODT_CKSE_DIFFERENTIAL PPC_REG_VAL(28, 0)
-#define SDRAM_CODT_CKSE_SINGLE_END PPC_REG_VAL(28, 1)
-#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END PPC_REG_VAL(29, 1)
-#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END PPC_REG_VAL(30, 1)
-#define SDRAM_CODT_IO_HIZ PPC_REG_VAL(31, 0)
-#define SDRAM_CODT_IO_NMODE PPC_REG_VAL(31, 1)
-
-/*
- * SDRAM Initialization Preload Register
- */
-#define SDRAM_INITPLR_ENABLE PPC_REG_VAL(0, 1)
-#define SDRAM_INITPLR_DISABLE PPC_REG_VAL(0, 0)
-#define SDRAM_INITPLR_IMWT_MASK PPC_REG_VAL(8, 0xFF)
-#define SDRAM_INITPLR_IMWT_ENCODE(n) PPC_REG_VAL(8, \
- (static_cast(u32, \
- n)) \
- & 0xFF)
-#define SDRAM_INITPLR_ICMD_MASK PPC_REG_VAL(12, 0x7)
-#define SDRAM_INITPLR_ICMD_ENCODE(n) PPC_REG_VAL(12, \
- (static_cast(u32, \
- n)) \
- & 0x7)
-#define SDRAM_INITPLR_IBA_MASK PPC_REG_VAL(15, 0x7)
-#define SDRAM_INITPLR_IBA_ENCODE(n) PPC_REG_VAL(15, \
- (static_cast(u32, \
- n)) \
- & 0x7)
-#define SDRAM_INITPLR_IMA_MASK PPC_REG_VAL(31, 0x7FFF)
-#define SDRAM_INITPLR_IMA_ENCODE(n) PPC_REG_VAL(31, \
- (static_cast(u32, \
- n)) \
- & 0x7FFF)
-
-/*
- * JEDEC DDR Initialization Commands
- */
-#define JEDEC_CMD_NOP 7
-#define JEDEC_CMD_PRECHARGE 2
-#define JEDEC_CMD_REFRESH 1
-#define JEDEC_CMD_EMR 0
-#define JEDEC_CMD_READ 5
-#define JEDEC_CMD_WRITE 4
-
-/*
- * JEDEC Precharge Command Memory Address Arguments
- */
-#define JEDEC_MA_PRECHARGE_ONE (0 << 10)
-#define JEDEC_MA_PRECHARGE_ALL (1 << 10)
-
-/*
- * JEDEC DDR EMR Command Bank Address Arguments
- */
-#define JEDEC_BA_MR 0
-#define JEDEC_BA_EMR 1
-#define JEDEC_BA_EMR2 2
-#define JEDEC_BA_EMR3 3
-
-/*
- * JEDEC DDR Mode Register
- */
-#define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12)
-#define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12)
-#define JEDEC_MA_MR_WR_MASK (0x7 << 9)
-#define JEDEC_MA_MR_WR_DDR1 (0x0 << 9)
-#define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9)
-#define JEDEC_MA_MR_WR_DDR2_3_CYC (0x2 << 9)
-#define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9)
-#define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9)
-#define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9)
-#define JEDEC_MA_MR_DLL_RESET (1 << 8)
-#define JEDEC_MA_MR_MODE_NORMAL (0 << 8)
-#define JEDEC_MA_MR_MODE_TEST (1 << 8)
-#define JEDEC_MA_MR_CL_MASK (0x7 << 4)
-#define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4)
-#define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4)
-#define JEDEC_MA_MR_CL_DDR1_3_0_CLK (0x3 << 4)
-#define JEDEC_MA_MR_CL_DDR2_2_0_CLK (0x2 << 4)
-#define JEDEC_MA_MR_CL_DDR2_3_0_CLK (0x3 << 4)
-#define JEDEC_MA_MR_CL_DDR2_4_0_CLK (0x4 << 4)
-#define JEDEC_MA_MR_CL_DDR2_5_0_CLK (0x5 << 4)
-#define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4)
-#define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4)
-#define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3)
-#define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3)
-#define JEDEC_MA_MR_BLEN_MASK (0x7 << 0)
-#define JEDEC_MA_MR_BLEN_4 (2 << 0)
-#define JEDEC_MA_MR_BLEN_8 (3 << 0)
-
-/*
- * JEDEC DDR Extended Mode Register
- */
-#define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12)
-#define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12)
-#define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12)
-#define JEDEC_MA_EMR_RQDS_MASK (1 << 11)
-#define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11)
-#define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11)
-#define JEDEC_MA_EMR_DQS_MASK (1 << 10)
-#define JEDEC_MA_EMR_DQS_DISABLE (1 << 10)
-#define JEDEC_MA_EMR_DQS_ENABLE (0 << 10)
-#define JEDEC_MA_EMR_OCD_MASK (0x7 << 7)
-#define JEDEC_MA_EMR_OCD_EXIT (0 << 7)
-#define JEDEC_MA_EMR_OCD_ENTER (7 << 7)
-#define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3)
-#define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3)
-#define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3)
-#define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3)
-#define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3)
-#define JEDEC_MA_EMR_RTT_MASK (0x11 << 2)
-#define JEDEC_MA_EMR_RTT_DISABLED (0x00 << 2)
-#define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2)
-#define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2)
-#define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2)
-#define JEDEC_MA_EMR_ODS_MASK (1 << 1)
-#define JEDEC_MA_EMR_ODS_NORMAL (0 << 1)
-#define JEDEC_MA_EMR_ODS_WEAK (1 << 1)
-#define JEDEC_MA_EMR_DLL_MASK (1 << 0)
-#define JEDEC_MA_EMR_DLL_ENABLE (0 << 0)
-#define JEDEC_MA_EMR_DLL_DISABLE (1 << 0)
-
-/*
- * JEDEC DDR Extended Mode Register 2
- */
-#define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7)
-#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7)
-
-/*
- * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register)
- */
-#define SDRAM_MMODE_WR_MASK JEDEC_MA_MR_WR_MASK
-#define SDRAM_MMODE_WR_DDR1 JEDEC_MA_MR_WR_DDR1
-#define SDRAM_MMODE_WR_DDR2_2_CYC JEDEC_MA_MR_WR_DDR2_2_CYC
-#define SDRAM_MMODE_WR_DDR2_3_CYC JEDEC_MA_MR_WR_DDR2_3_CYC
-#define SDRAM_MMODE_WR_DDR2_4_CYC JEDEC_MA_MR_WR_DDR2_4_CYC
-#define SDRAM_MMODE_WR_DDR2_5_CYC JEDEC_MA_MR_WR_DDR2_5_CYC
-#define SDRAM_MMODE_WR_DDR2_6_CYC JEDEC_MA_MR_WR_DDR2_6_CYC
-#define SDRAM_MMODE_DCL_MASK JEDEC_MA_MR_CL_MASK
-#define SDRAM_MMODE_DCL_DDR1_2_0_CLK JEDEC_MA_MR_CL_DDR1_2_0_CLK
-#define SDRAM_MMODE_DCL_DDR1_2_5_CLK JEDEC_MA_MR_CL_DDR1_2_5_CLK
-#define SDRAM_MMODE_DCL_DDR1_3_0_CLK JEDEC_MA_MR_CL_DDR1_3_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_2_0_CLK JEDEC_MA_MR_CL_DDR2_2_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_3_0_CLK JEDEC_MA_MR_CL_DDR2_3_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_4_0_CLK JEDEC_MA_MR_CL_DDR2_4_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_5_0_CLK JEDEC_MA_MR_CL_DDR2_5_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_6_0_CLK JEDEC_MA_MR_CL_DDR2_6_0_CLK
-#define SDRAM_MMODE_DCL_DDR2_7_0_CLK JEDEC_MA_MR_CL_DDR2_7_0_CLK
-#define SDRAM_MMODE_BTYP_SEQUENTIAL JEDEC_MA_MR_BTYP_SEQUENTIAL
-#define SDRAM_MMODE_BTYP_INTERLEAVED JEDEC_MA_MR_BTYP_INTERLEAVED
-#define SDRAM_MMODE_BLEN_MASK JEDEC_MA_MR_BLEN_MASK
-#define SDRAM_MMODE_BLEN_4 JEDEC_MA_MR_BLEN_4
-#define SDRAM_MMODE_BLEN_8 JEDEC_MA_MR_BLEN_8
-
-/*
- * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended
- * Mode Register)
- */
-#define SDRAM_MEMODE_QOFF_MASK JEDEC_MA_EMR_OUTPUT_MASK
-#define SDRAM_MEMODE_QOFF_DISABLE JEDEC_MA_EMR_OUTPUT_DISABLE
-#define SDRAM_MEMODE_QOFF_ENABLE JEDEC_MA_EMR_OUTPUT_ENABLE
-#define SDRAM_MEMODE_RDQS_MASK JEDEC_MA_EMR_RQDS_MASK
-#define SDRAM_MEMODE_RDQS_DISABLE JEDEC_MA_EMR_RDQS_DISABLE
-#define SDRAM_MEMODE_RDQS_ENABLE JEDEC_MA_EMR_RDQS_ENABLE
-#define SDRAM_MEMODE_DQS_MASK JEDEC_MA_EMR_DQS_MASK
-#define SDRAM_MEMODE_DQS_DISABLE JEDEC_MA_EMR_DQS_DISABLE
-#define SDRAM_MEMODE_DQS_ENABLE JEDEC_MA_EMR_DQS_ENABLE
-#define SDRAM_MEMODE_AL_DDR1_0_CYC JEDEC_MA_EMR_AL_DDR1_0_CYC
-#define SDRAM_MEMODE_AL_DDR2_1_CYC JEDEC_MA_EMR_AL_DDR2_1_CYC
-#define SDRAM_MEMODE_AL_DDR2_2_CYC JEDEC_MA_EMR_AL_DDR2_2_CYC
-#define SDRAM_MEMODE_AL_DDR2_3_CYC JEDEC_MA_EMR_AL_DDR2_3_CYC
-#define SDRAM_MEMODE_AL_DDR2_4_CYC JEDEC_MA_EMR_AL_DDR2_4_CYC
-#define SDRAM_MEMODE_RTT_MASK JEDEC_MA_EMR_RTT_MASK
-#define SDRAM_MEMODE_RTT_DISABLED JEDEC_MA_EMR_RTT_DISABLED
-#define SDRAM_MEMODE_RTT_75OHM JEDEC_MA_EMR_RTT_75OHM
-#define SDRAM_MEMODE_RTT_150OHM JEDEC_MA_EMR_RTT_150OHM
-#define SDRAM_MEMODE_RTT_50OHM JEDEC_MA_EMR_RTT_50OHM
-#define SDRAM_MEMODE_DIC_MASK JEDEC_MA_EMR_ODS_MASK
-#define SDRAM_MEMODE_DIC_NORMAL JEDEC_MA_EMR_ODS_NORMAL
-#define SDRAM_MEMODE_DIC_WEAK JEDEC_MA_EMR_ODS_WEAK
-#define SDRAM_MEMODE_DLL_MASK JEDEC_MA_EMR_DLL_MASK
-#define SDRAM_MEMODE_DLL_DISABLE JEDEC_MA_EMR_DLL_DISABLE
-#define SDRAM_MEMODE_DLL_ENABLE JEDEC_MA_EMR_DLL_ENABLE
-
-/*
- * SDRAM Clock Timing Register
- */
-#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
-#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
-#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
-#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000
-#define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000
-
-/*
- * SDRAM Write Timing Register
- */
-#define SDRAM_WRDTR_LLWP_MASK 0x10000000
-#define SDRAM_WRDTR_LLWP_DIS 0x10000000
-#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
-#define SDRAM_WRDTR_WTR_MASK 0x0E000000
-#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
-#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
-#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
-#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
-
-/*
- * SDRAM SDTR1 Options
- */
-#define SDRAM_SDTR1_LDOF_MASK 0x80000000
-#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
-#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
-#define SDRAM_SDTR1_RTW_MASK 0x00F00000
-#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
-#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
-#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
-#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
-#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
-#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
-#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
-#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
-
-/*
- * SDRAM SDTR2 Options
- */
-#define SDRAM_SDTR2_RCD_MASK 0xF0000000
-#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
-#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
-#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
-#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
-#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
-#define SDRAM_SDTR2_WTR_MASK 0x0F000000
-#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
-#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
-#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
-#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
-#define SDRAM_SDTR3_WTR_ENCODE(n) ((((u32)(n))&0xF)<<24)
-#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
-#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
-#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
-#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
-#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
-#define SDRAM_SDTR2_WPC_MASK 0x0000F000
-#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
-#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
-#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
-#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
-#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
-#define SDRAM_SDTR3_WPC_ENCODE(n) ((((u32)(n))&0xF)<<12)
-#define SDRAM_SDTR2_RPC_MASK 0x00000F00
-#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
-#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
-#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
-#define SDRAM_SDTR2_RP_MASK 0x000000F0
-#define SDRAM_SDTR2_RP_3_CLK 0x00000030
-#define SDRAM_SDTR2_RP_4_CLK 0x00000040
-#define SDRAM_SDTR2_RP_5_CLK 0x00000050
-#define SDRAM_SDTR2_RP_6_CLK 0x00000060
-#define SDRAM_SDTR2_RP_7_CLK 0x00000070
-#define SDRAM_SDTR2_RRD_MASK 0x0000000F
-#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
-#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
-
-/*
- * SDRAM SDTR3 Options
- */
-#define SDRAM_SDTR3_RAS_MASK 0x1F000000
-#define SDRAM_SDTR3_RAS_ENCODE(n) ((((u32)(n))&0x1F)<<24)
-#define SDRAM_SDTR3_RC_MASK 0x001F0000
-#define SDRAM_SDTR3_RC_ENCODE(n) ((((u32)(n))&0x1F)<<16)
-#define SDRAM_SDTR3_XCS_MASK 0x00001F00
-#define SDRAM_SDTR3_XCS 0x00000D00
-#define SDRAM_SDTR3_RFC_MASK 0x0000003F
-#define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0)
-
-/*
- * ECC Error Status
- */
-#define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF)
-#define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF)
-#define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1)
-#define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3)
-#define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0)
-#define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2)
-#define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1)
-#define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2)
-#define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3)
-#define SDRAM_ECCES_CE PPC_REG_VAL(18, 1)
-#define SDRAM_ECCES_UE PPC_REG_VAL(19, 1)
-#define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3)
-#define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1)
-#define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1)
-
-/*
- * Memory Bank 0-1 configuration
- */
-#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
-#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
-#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
-#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
-#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
-#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
-#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
-#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
-#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
-#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
-#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
-#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
-#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
-#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
-
-#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/
-#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */
-#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */
-#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */
-#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */
-
-#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
-
-#if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
-/*
- * SDRAM Controller
- */
-#define DDR0_00 0x00
-#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
-#define DDR0_00_INT_ACK_ALL 0x7F000000
-#define DDR0_00_INT_ACK_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_00_INT_ACK_DECODE(n) ((((u32)(n))>>24)&0x7F)
-/* Status */
-#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
-/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT0 0x00010000
-/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT1 0x00020000
-/* Bit2. Single correctable ECC event detected */
-#define DDR0_00_INT_STATUS_BIT2 0x00040000
-/* Bit3. Multiple correctable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT3 0x00080000
-/* Bit4. Single uncorrectable ECC event detected. */
-#define DDR0_00_INT_STATUS_BIT4 0x00100000
-/* Bit5. Multiple uncorrectable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT5 0x00200000
-/* Bit6. DRAM initialization complete. */
-#define DDR0_00_INT_STATUS_BIT6 0x00400000
-/* Bit7. Logical OR of all lower bits. */
-#define DDR0_00_INT_STATUS_BIT7 0x00800000
-
-#define DDR0_00_INT_STATUS_ENCODE(n) ((((u32)(n))&0xFF)<<16)
-#define DDR0_00_INT_STATUS_DECODE(n) ((((u32)(n))>>16)&0xFF)
-#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
-#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
-#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_01 0x01
-#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
-#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24)
-#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F)
-#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
-#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16)
-#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F)
-#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
-#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8)
-#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7)
-#define DDR0_01_INT_MASK_MASK 0x000000FF
-#define DDR0_01_INT_MASK_ENCODE(n) ((((u32)(n))&0xFF)<<0)
-#define DDR0_01_INT_MASK_DECODE(n) ((((u32)(n))>>0)&0xFF)
-#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
-#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
-
-#define DDR0_02 0x02
-#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
-#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((u32)(n))&0x2)<<24)
-#define DDR0_02_MAX_CS_REG_DECODE(n) ((((u32)(n))>>24)&0x2)
-#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
-#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((u32)(n))&0xF)<<16)
-#define DDR0_02_MAX_COL_REG_DECODE(n) ((((u32)(n))>>16)&0xF)
-#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
-#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((u32)(n))&0xF)<<8)
-#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((u32)(n))>>8)&0xF)
-#define DDR0_02_START_MASK 0x00000001
-#define DDR0_02_START_ENCODE(n) ((((u32)(n))&0x1)<<0)
-#define DDR0_02_START_DECODE(n) ((((u32)(n))>>0)&0x1)
-#define DDR0_02_START_OFF 0x00000000
-#define DDR0_02_START_ON 0x00000001
-
-#define DDR0_03 0x03
-#define DDR0_03_BSTLEN_MASK 0x07000000
-#define DDR0_03_BSTLEN_ENCODE(n) ((((u32)(n))&0x7)<<24)
-#define DDR0_03_BSTLEN_DECODE(n) ((((u32)(n))>>24)&0x7)
-#define DDR0_03_CASLAT_MASK 0x00070000
-#define DDR0_03_CASLAT_ENCODE(n) ((((u32)(n))&0x7)<<16)
-#define DDR0_03_CASLAT_DECODE(n) ((((u32)(n))>>16)&0x7)
-#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
-#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((u32)(n))&0xF)<<8)
-#define DDR0_03_CASLAT_LIN_DECODE(n) ((((u32)(n))>>8)&0xF)
-#define DDR0_03_INITAREF_MASK 0x0000000F
-#define DDR0_03_INITAREF_ENCODE(n) ((((u32)(n))&0xF)<<0)
-#define DDR0_03_INITAREF_DECODE(n) ((((u32)(n))>>0)&0xF)
-
-#define DDR0_04 0x04
-#define DDR0_04_TRC_MASK 0x1F000000
-#define DDR0_04_TRC_ENCODE(n) ((((u32)(n))&0x1F)<<24)
-#define DDR0_04_TRC_DECODE(n) ((((u32)(n))>>24)&0x1F)
-#define DDR0_04_TRRD_MASK 0x00070000
-#define DDR0_04_TRRD_ENCODE(n) ((((u32)(n))&0x7)<<16)
-#define DDR0_04_TRRD_DECODE(n) ((((u32)(n))>>16)&0x7)
-#define DDR0_04_TRTP_MASK 0x00000700
-#define DDR0_04_TRTP_ENCODE(n) ((((u32)(n))&0x7)<<8)
-#define DDR0_04_TRTP_DECODE(n) ((((u32)(n))>>8)&0x7)
-
-#define DDR0_05 0x05
-#define DDR0_05_TMRD_MASK 0x1F000000
-#define DDR0_05_TMRD_ENCODE(n) ((((u32)(n))&0x1F)<<24)
-#define DDR0_05_TMRD_DECODE(n) ((((u32)(n))>>24)&0x1F)
-#define DDR0_05_TEMRS_MASK 0x00070000
-#define DDR0_05_TEMRS_ENCODE(n) ((((u32)(n))&0x7)<<16)
-#define DDR0_05_TEMRS_DECODE(n) ((((u32)(n))>>16)&0x7)
-#define DDR0_05_TRP_MASK 0x00000F00
-#define DDR0_05_TRP_ENCODE(n) ((((u32)(n))&0xF)<<8)
-#define DDR0_05_TRP_DECODE(n) ((((u32)(n))>>8)&0xF)
-#define DDR0_05_TRAS_MIN_MASK 0x000000FF
-#define DDR0_05_TRAS_MIN_ENCODE(n) ((((u32)(n))&0xFF)<<0)
-#define DDR0_05_TRAS_MIN_DECODE(n) ((((u32)(n))>>0)&0xFF)
-
-#define DDR0_06 0x06
-#define DDR0_06_WRITEINTERP_MASK 0x01000000
-#define DDR0_06_WRITEINTERP_ENCODE(n) ((((u32)(n))&0x1)<<24)
-#define DDR0_06_WRITEINTERP_DECODE(n) ((((u32)(n))>>24)&0x1)
-#define DDR0_06_TWTR_MASK 0x00070000
-#define DDR0_06_TWTR_ENCODE(n) ((((u32)(n))&0x7)<<16)
-#define DDR0_06_TWTR_DECODE(n) ((((u32)(n))>>16)&0x7)
-#define DDR0_06_TDLL_MASK 0x0000FF00
-#define DDR0_06_TDLL_ENCODE(n) ((((u32)(n))&0xFF)<<8)
-#define DDR0_06_TDLL_DECODE(n) ((((u32)(n))>>8)&0xFF)
-#define DDR0_06_TRFC_MASK 0x0000007F
-#define DDR0_06_TRFC_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_06_TRFC_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_07 0x07
-#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
-#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((u32)(n))&0x1)<<24)
-#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((u32)(n))>>24)&0x1)
-#define DDR0_07_TFAW_MASK 0x001F0000
-#define DDR0_07_TFAW_ENCODE(n) ((((u32)(n))&0x1F)<<16)
-#define DDR0_07_TFAW_DECODE(n) ((((u32)(n))>>16)&0x1F)
-#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
-#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8)
-#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1)
-#define DDR0_07_AREFRESH_MASK 0x00000001
-#define DDR0_07_AREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<0)
-#define DDR0_07_AREFRESH_DECODE(n) ((((u32)(n))>>0)&0x1)
-
-#define DDR0_08 0x08
-#define DDR0_08_WRLAT_MASK 0x07000000
-#define DDR0_08_WRLAT_ENCODE(n) ((((u32)(n))&0x7)<<24)
-#define DDR0_08_WRLAT_DECODE(n) ((((u32)(n))>>24)&0x7)
-#define DDR0_08_TCPD_MASK 0x00FF0000
-#define DDR0_08_TCPD_ENCODE(n) ((((u32)(n))&0xFF)<<16)
-#define DDR0_08_TCPD_DECODE(n) ((((u32)(n))>>16)&0xFF)
-#define DDR0_08_DQS_N_EN_MASK 0x00000100
-#define DDR0_08_DQS_N_EN_ENCODE(n) ((((u32)(n))&0x1)<<8)
-#define DDR0_08_DQS_N_EN_DECODE(n) ((((u32)(n))>>8)&0x1)
-#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
-#define DDR0_08_DDRII_ENCODE(n) ((((u32)(n))&0x1)<<0)
-#define DDR0_08_DDRII_DECODE(n) ((((u32)(n))>>0)&0x1)
-
-#define DDR0_09 0x09
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24)
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F)
-#define DDR0_09_RTT_0_MASK 0x00030000
-#define DDR0_09_RTT_0_ENCODE(n) ((((u32)(n))&0x3)<<16)
-#define DDR0_09_RTT_0_DECODE(n) ((((u32)(n))>>16)&0x3)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
-#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_10 0x0A
-#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
-#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
-#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((u32)(n))>>16)&0x1)
-#define DDR0_10_CS_MAP_MASK 0x00000300
-#define DDR0_10_CS_MAP_NO_MEM 0x00000000
-#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
-#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
-#define DDR0_10_CS_MAP_ENCODE(n) ((((u32)(n))&0x3)<<8)
-#define DDR0_10_CS_MAP_DECODE(n) ((((u32)(n))>>8)&0x3)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<0)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((u32)(n))>>0)&0x1F)
-
-#define DDR0_11 0x0B
-#define DDR0_11_SREFRESH_MASK 0x01000000
-#define DDR0_11_SREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<24)
-#define DDR0_11_SREFRESH_DECODE(n) ((((u32)(n))>>24)&0x1F)
-#define DDR0_11_TXSNR_MASK 0x00FF0000
-#define DDR0_11_TXSNR_ENCODE(n) ((((u32)(n))&0xFF)<<16)
-#define DDR0_11_TXSNR_DECODE(n) ((((u32)(n))>>16)&0xFF)
-#define DDR0_11_TXSR_MASK 0x0000FF00
-#define DDR0_11_TXSR_ENCODE(n) ((((u32)(n))&0xFF)<<8)
-#define DDR0_11_TXSR_DECODE(n) ((((u32)(n))>>8)&0xFF)
-
-#define DDR0_12 0x0C
-#define DDR0_12_TCKE_MASK 0x0000007
-#define DDR0_12_TCKE_ENCODE(n) ((((u32)(n))&0x7)<<0)
-#define DDR0_12_TCKE_DECODE(n) ((((u32)(n))>>0)&0x7)
-
-#define DDR0_14 0x0E
-#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
-#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((u32)(n))&0x1)<<24)
-#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((u32)(n))>>24)&0x1)
-#define DDR0_14_REDUC_MASK 0x00010000
-#define DDR0_14_REDUC_64BITS 0x00000000
-#define DDR0_14_REDUC_32BITS 0x00010000
-#define DDR0_14_REDUC_ENCODE(n) ((((u32)(n))&0x1)<<16)
-#define DDR0_14_REDUC_DECODE(n) ((((u32)(n))>>16)&0x1)
-#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
-#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((u32)(n))&0x1)<<8)
-#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((u32)(n))>>8)&0x1)
-
-#define DDR0_17 0x11
-#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
-#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((u32)(n))>>24)&0x7F)
-#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
-#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
-#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
-#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
-#define DDR0_17_DLLLOCKREG_DECODE(n) ((((u32)(n))>>16)&0x1)
-#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
-#define DDR0_17_DLL_LOCK_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_17_DLL_LOCK_DECODE(n) ((((u32)(n))>>8)&0x7F)
-
-#define DDR0_18 0x12
-#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
-#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
-#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((u32)(n))>>24)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
-#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((u32)(n))>>16)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
-#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
-#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_19 0x13
-#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
-#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
-#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((u32)(n))>>24)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
-#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((u32)(n))>>16)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
-#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
-#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_20 0x14
-#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
-#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((u32)(n))>>24)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
-#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((u32)(n))>>16)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
-#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
-#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_21 0x15
-#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
-#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((u32)(n))&0x7F)<<24)
-#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((u32)(n))>>24)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
-#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((u32)(n))>>16)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
-#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
-#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_22 0x16
-#define DDR0_22_CTRL_RAW_MASK 0x03000000
-#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000
-#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000
-#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000
-#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000
-#define DDR0_22_CTRL_RAW_ENCODE(n) ((((u32)(n))&0x3)<<24)
-#define DDR0_22_CTRL_RAW_DECODE(n) ((((u32)(n))>>24)&0x3)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>16)&0x7F)
-#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
-#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
-#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((u32)(n))>>8)&0x7F)
-#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
-#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((u32)(n))&0x7F)<<0)
-#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((u32)(n))>>0)&0x7F)
-
-#define DDR0_23 0x17
-#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
-#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<24)
-#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((u32)(n))>>24)&0x3)
-#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
-#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<16)
-#define DDR0_23_ECC_C_SYND_DECODE(n) ((((u32)(n))>>16)&0xFF)
-#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
-#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<8)
-#define DDR0_23_ECC_U_SYND_DECODE(n) ((((u32)(n))>>8)&0xFF)
-#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
-#define DDR0_23_FWC_ENCODE(n) ((((u32)(n))&0x1)<<0)
-#define DDR0_23_FWC_DECODE(n) ((((u32)(n))>>0)&0x1)
-
-#define DDR0_24 0x18
-#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
-#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((u32)(n))&0x3)<<24)
-#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((u32)(n))>>24)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
-#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<16)
-#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((u32)(n))>>16)&0x3)
-#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
-#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<8)
-#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((u32)(n))>>8)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
-#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<0)
-#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((u32)(n))>>0)&0x3)
-
-#define DDR0_25 0x19
-#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
-#define DDR0_25_VERSION_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
-#define DDR0_25_VERSION_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
-#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((u32)(n))&0x3FF)<<0)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((u32)(n))>>0)&0x3FF)
-
-#define DDR0_26 0x1A
-#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
-#define DDR0_26_TRAS_MAX_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
-#define DDR0_26_TRAS_MAX_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
-#define DDR0_26_TREF_MASK 0x00003FFF
-#define DDR0_26_TREF_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
-#define DDR0_26_TREF_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
-
-#define DDR0_27 0x1B
-#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
-#define DDR0_27_EMRS_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
-#define DDR0_27_EMRS_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
-#define DDR0_27_TINIT_MASK 0x0000FFFF
-#define DDR0_27_TINIT_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
-#define DDR0_27_TINIT_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
-
-#define DDR0_28 0x1C
-#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
-#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
-#define DDR0_28_EMRS3_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
-#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
-#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
-#define DDR0_28_EMRS2_DATA_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
-
-#define DDR0_31 0x1F
-#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
-#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
-#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
-
-#define DDR0_32 0x20
-#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_33 0x21
-#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
-#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
-#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
-
-#define DDR0_34 0x22
-#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_35 0x23
-#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
-#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
-#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
-
-#define DDR0_36 0x24
-#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_36_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_37 0x25
-#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_37_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_38 0x26
-#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_39 0x27
-#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
-#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
-#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
-
-#define DDR0_40 0x28
-#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_40_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_41 0x29
-#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
-#define DDR0_41_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_42 0x2A
-#define DDR0_42_ADDR_PINS_MASK 0x07000000
-#define DDR0_42_ADDR_PINS_ENCODE(n) ((((u32)(n))&0x7)<<24)
-#define DDR0_42_ADDR_PINS_DECODE(n) ((((u32)(n))>>24)&0x7)
-#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
-#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((u32)(n))&0xF)<<0)
-#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((u32)(n))>>0)&0xF)
-
-#define DDR0_43 0x2B
-#define DDR0_43_TWR_MASK 0x07000000
-#define DDR0_43_TWR_ENCODE(n) ((((u32)(n))&0x7)<<24)
-#define DDR0_43_TWR_DECODE(n) ((((u32)(n))>>24)&0x7)
-#define DDR0_43_APREBIT_MASK 0x000F0000
-#define DDR0_43_APREBIT_ENCODE(n) ((((u32)(n))&0xF)<<16)
-#define DDR0_43_APREBIT_DECODE(n) ((((u32)(n))>>16)&0xF)
-#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
-#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((u32)(n))&0x7)<<8)
-#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((u32)(n))>>8)&0x7)
-#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
-#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((u32)(n))&0x1)<<0)
-#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((u32)(n))>>0)&0x1)
-
-#define DDR0_44 0x2C
-#define DDR0_44_TRCD_MASK 0x000000FF
-#define DDR0_44_TRCD_ENCODE(n) ((((u32)(n))&0xFF)<<0)
-#define DDR0_44_TRCD_DECODE(n) ((((u32)(n))>>0)&0xFF)
-
-#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
-
-#ifndef __ASSEMBLY__
-struct sdram_timing {
- u32 wrdtr;
- u32 clktr;
-};
-
-/*
- * Prototypes
- */
-void ppc4xx_ibm_ddr2_register_dump(void);
-u32 mfdcr_any(u32);
-void mtdcr_any(u32, u32);
-u32 ddr_wrdtr(u32);
-u32 ddr_clktr(u32);
-void spd_ddr_init_hang(void);
-u32 DQS_autocalibration(void);
-phys_size_t sdram_memsize(void);
-void dcbz_area(u32 start_address, u32 num_bytes);
-#endif /* __ASSEMBLY__ */
-
-#endif /* _PPC4xx_SDRAM_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PPC4xx_UIC_H_
-#define _PPC4xx_UIC_H_
-
-/*
- * Define the number of UIC's
- */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
-#define UIC_MAX 4
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EX)
-#define UIC_MAX 3
-#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define UIC_MAX 2
-#else
-#define UIC_MAX 1
-#endif
-
-#define IRQ_MAX (UIC_MAX * 32)
-
-/*
- * UIC register
- */
-#define UIC_SR 0x0 /* UIC status */
-#define UIC_ER 0x2 /* UIC enable */
-#define UIC_CR 0x3 /* UIC critical */
-#define UIC_PR 0x4 /* UIC polarity */
-#define UIC_TR 0x5 /* UIC triggering */
-#define UIC_MSR 0x6 /* UIC masked status */
-#define UIC_VR 0x7 /* UIC vector */
-#define UIC_VCR 0x8 /* UIC vector configuration */
-
-/*
- * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's
- * are cascaded on. With this trick we can use the common UIC code for 440GX
- * too.
- */
-#if defined(CONFIG_440GX)
-#define UIC0_DCR_BASE 0x200
-#define UIC1_DCR_BASE 0xc0
-#define UIC2_DCR_BASE 0xd0
-#define UIC3_DCR_BASE 0x210
-#else
-#define UIC0_DCR_BASE 0xc0
-#define UIC1_DCR_BASE 0xd0
-#define UIC2_DCR_BASE 0xe0
-#define UIC3_DCR_BASE 0xf0
-#endif
-
-#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */
-#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */
-#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */
-#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
-#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
-#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
-#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */
-#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
-
-#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */
-#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */
-#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */
-#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
-#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
-#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
-#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */
-#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
-
-#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
-#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */
-#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */
-#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
-#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
-#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
-#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */
-#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
-
-#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
-#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */
-#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */
-#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
-#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
-#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
-#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */
-#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
-
-/*
- * Now the interrupt vector definitions. They are different for most of
- * the 4xx variants, so we need some more #ifdef's here. No mask
- * definitions anymore here. For this please use the UIC_MASK macro below.
- *
- * Note: Please only define the interrupts really used in U-Boot here.
- * Those are the cascading and EMAC/MAL related interrupt.
- */
-
-#if defined(CONFIG_405EP) || defined(CONFIG_405GP)
-#define VECNUM_MAL_SERR 10
-#define VECNUM_MAL_TXEOB 11
-#define VECNUM_MAL_RXEOB 12
-#define VECNUM_MAL_TXDE 13
-#define VECNUM_MAL_RXDE 14
-#define VECNUM_ETH0 15
-#define VECNUM_ETH1_OFFS 2
-#define VECNUM_EIRQ6 29
-#endif /* defined(CONFIG_405EP) */
-
-#if defined(CONFIG_405EZ)
-#define VECNUM_USBDEV 15
-#define VECNUM_ETH0 16
-#define VECNUM_MAL_SERR 18
-#define VECNUM_MAL_TXDE 18
-#define VECNUM_MAL_RXDE 18
-#define VECNUM_MAL_TXEOB 19
-#define VECNUM_MAL_RXEOB 21
-#endif /* CONFIG_405EX */
-
-#if defined(CONFIG_405EX)
-/* UIC 0 */
-#define VECNUM_MAL_TXEOB 10
-#define VECNUM_MAL_RXEOB 11
-#define VECNUM_ETH0 24
-#define VECNUM_ETH1_OFFS 1
-#define VECNUM_UIC2NCI 28
-#define VECNUM_UIC2CI 29
-#define VECNUM_UIC1NCI 30
-#define VECNUM_UIC1CI 31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR (32 + 0)
-#define VECNUM_MAL_TXDE (32 + 1)
-#define VECNUM_MAL_RXDE (32 + 2)
-#endif /* CONFIG_405EX */
-
-#if defined(CONFIG_440GP) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR)
-/* UIC 0 */
-#define VECNUM_MAL_TXEOB 10
-#define VECNUM_MAL_RXEOB 11
-#define VECNUM_UIC1NCI 30
-#define VECNUM_UIC1CI 31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR (32 + 0)
-#define VECNUM_MAL_TXDE (32 + 1)
-#define VECNUM_MAL_RXDE (32 + 2)
-#define VECNUM_USBDEV (32 + 23)
-#define VECNUM_ETH0 (32 + 28)
-#define VECNUM_ETH1_OFFS 2
-#endif /* CONFIG_440GP */
-
-#if defined(CONFIG_440GX)
-/* UICB 0 (440GX only) */
-/*
- * All those defines below are off-by-one, so that the common UIC code
- * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc.
- */
-#define VECNUM_UIC1CI 0
-#define VECNUM_UIC1NCI 1
-#define VECNUM_UIC2CI 2
-#define VECNUM_UIC2NCI 3
-#define VECNUM_UIC3CI 4
-#define VECNUM_UIC3NCI 5
-
-/* UIC 0, used as UIC1 on 440GX because of UICB0 */
-#define VECNUM_MAL_TXEOB (32 + 10)
-#define VECNUM_MAL_RXEOB (32 + 11)
-
-/* UIC 1, used as UIC2 on 440GX because of UICB0 */
-#define VECNUM_MAL_SERR (64 + 0)
-#define VECNUM_MAL_TXDE (64 + 1)
-#define VECNUM_MAL_RXDE (64 + 2)
-#define VECNUM_ETH0 (64 + 28)
-#define VECNUM_ETH1_OFFS 2
-#endif /* CONFIG_440GX */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-/* UIC 0 */
-#define VECNUM_MAL_TXEOB 10
-#define VECNUM_MAL_RXEOB 11
-#define VECNUM_USBDEV 20
-#define VECNUM_ETH0 24
-#define VECNUM_ETH1_OFFS 1
-#define VECNUM_UIC2NCI 28
-#define VECNUM_UIC2CI 29
-#define VECNUM_UIC1NCI 30
-#define VECNUM_UIC1CI 31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR (32 + 0)
-#define VECNUM_MAL_TXDE (32 + 1)
-#define VECNUM_MAL_RXDE (32 + 2)
-
-/* UIC 2 */
-#define VECNUM_EIRQ2 (64 + 3)
-#endif /* CONFIG_440EPX */
-
-#if defined(CONFIG_440SP)
-/* UIC 0 */
-#define VECNUM_UIC1NCI 30
-#define VECNUM_UIC1CI 31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR (32 + 1)
-#define VECNUM_MAL_TXDE (32 + 2)
-#define VECNUM_MAL_RXDE (32 + 3)
-#define VECNUM_MAL_TXEOB (32 + 6)
-#define VECNUM_MAL_RXEOB (32 + 7)
-#define VECNUM_ETH0 (32 + 28)
-#endif /* CONFIG_440SP */
-
-#if defined(CONFIG_440SPE)
-/* UIC 0 */
-#define VECNUM_UIC2NCI 10
-#define VECNUM_UIC2CI 11
-#define VECNUM_UIC3NCI 16
-#define VECNUM_UIC3CI 17
-#define VECNUM_UIC1NCI 30
-#define VECNUM_UIC1CI 31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR (32 + 1)
-#define VECNUM_MAL_TXDE (32 + 2)
-#define VECNUM_MAL_RXDE (32 + 3)
-#define VECNUM_MAL_TXEOB (32 + 6)
-#define VECNUM_MAL_RXEOB (32 + 7)
-#define VECNUM_ETH0 (32 + 28)
-#endif /* CONFIG_440SPE */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-/* UIC 0 */
-#define VECNUM_UIC2NCI 10
-#define VECNUM_UIC2CI 11
-#define VECNUM_UIC3NCI 16
-#define VECNUM_UIC3CI 17
-#define VECNUM_UIC1NCI 30
-#define VECNUM_UIC1CI 31
-
-/* UIC 2 */
-#define VECNUM_MAL_SERR (64 + 3)
-#define VECNUM_MAL_TXDE (64 + 4)
-#define VECNUM_MAL_RXDE (64 + 5)
-#define VECNUM_MAL_TXEOB (64 + 6)
-#define VECNUM_MAL_RXEOB (64 + 7)
-#define VECNUM_ETH0 (64 + 16)
-#define VECNUM_ETH1_OFFS 1
-#endif /* CONFIG_460EX */
-
-#if defined(CONFIG_460SX)
-/* UIC 0 */
-#define VECNUM_UIC2NCI 10
-#define VECNUM_UIC2CI 11
-#define VECNUM_UIC3NCI 16
-#define VECNUM_UIC3CI 17
-#define VECNUM_ETH0 19
-#define VECNUM_ETH1_OFFS 1
-#define VECNUM_UIC1NCI 30
-#define VECNUM_UIC1CI 31
-
-/* UIC 1 */
-#define VECNUM_MAL_SERR (32 + 1)
-#define VECNUM_MAL_TXDE (32 + 2)
-#define VECNUM_MAL_RXDE (32 + 3)
-#define VECNUM_MAL_TXEOB (32 + 6)
-#define VECNUM_MAL_RXEOB (32 + 7)
-#endif /* CONFIG_460EX */
-
-#if !defined(VECNUM_ETH1_OFFS)
-#define VECNUM_ETH1_OFFS 1
-#endif
-
-/*
- * Mask definitions (used for example in 4xx_enet.c)
- */
-#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
-/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
-#define UIC_NR(vec) ((vec) >> 5)
-
-#endif /* _PPC4xx_UIC_H_ */
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-
-#ifndef __PPC4XX_H__
-#define __PPC4XX_H__
-
-/*
- * Include SoC specific headers
- */
-#if defined(CONFIG_405EP)
-#include <asm/ppc405ep.h>
-#endif
-
-#if defined(CONFIG_405EX)
-#include <asm/ppc405ex.h>
-#endif
-
-#if defined(CONFIG_405EZ)
-#include <asm/ppc405ez.h>
-#endif
-
-#if defined(CONFIG_405GP)
-#include <asm/ppc405gp.h>
-#endif
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#include <asm/ppc440ep_gr.h>
-#endif
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#include <asm/ppc440epx_grx.h>
-#endif
-
-#if defined(CONFIG_440GP)
-#include <asm/ppc440gp.h>
-#endif
-
-#if defined(CONFIG_440GX)
-#include <asm/ppc440gx.h>
-#endif
-
-#if defined(CONFIG_440SP)
-#include <asm/ppc440sp.h>
-#endif
-
-#if defined(CONFIG_440SPE)
-#include <asm/ppc440spe.h>
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#include <asm/ppc460ex_gt.h>
-#endif
-
-#if defined(CONFIG_460SX)
-#include <asm/ppc460sx.h>
-#endif
-
-/*
- * Common registers for all SoC's
- */
-/* DCR registers */
-#define PLB3A0_ACR 0x0077
-#define PLB4A0_ACR 0x0081
-#define PLB4A1_ACR 0x0089
-
-/* CPR register declarations */
-
-#define PLB4Ax_ACR_PPM_MASK 0xf0000000
-#define PLB4Ax_ACR_PPM_FIXED 0x00000000
-#define PLB4Ax_ACR_PPM_FAIR 0xd0000000
-#define PLB4Ax_ACR_HBU_MASK 0x08000000
-#define PLB4Ax_ACR_HBU_DISABLED 0x00000000
-#define PLB4Ax_ACR_HBU_ENABLED 0x08000000
-#define PLB4Ax_ACR_RDP_MASK 0x06000000
-#define PLB4Ax_ACR_RDP_DISABLED 0x00000000
-#define PLB4Ax_ACR_RDP_2DEEP 0x02000000
-#define PLB4Ax_ACR_RDP_3DEEP 0x04000000
-#define PLB4Ax_ACR_RDP_4DEEP 0x06000000
-#define PLB4Ax_ACR_WRP_MASK 0x01000000
-#define PLB4Ax_ACR_WRP_DISABLED 0x00000000
-#define PLB4Ax_ACR_WRP_2DEEP 0x01000000
-
-/*
- * External Bus Controller
- */
-/* Values for EBC0_CFGADDR register - indirect addressing of these regs */
-#define PB0CR 0x00 /* periph bank 0 config reg */
-#define PB1CR 0x01 /* periph bank 1 config reg */
-#define PB2CR 0x02 /* periph bank 2 config reg */
-#define PB3CR 0x03 /* periph bank 3 config reg */
-#define PB4CR 0x04 /* periph bank 4 config reg */
-#define PB5CR 0x05 /* periph bank 5 config reg */
-#define PB6CR 0x06 /* periph bank 6 config reg */
-#define PB7CR 0x07 /* periph bank 7 config reg */
-#define PB0AP 0x10 /* periph bank 0 access parameters */
-#define PB1AP 0x11 /* periph bank 1 access parameters */
-#define PB2AP 0x12 /* periph bank 2 access parameters */
-#define PB3AP 0x13 /* periph bank 3 access parameters */
-#define PB4AP 0x14 /* periph bank 4 access parameters */
-#define PB5AP 0x15 /* periph bank 5 access parameters */
-#define PB6AP 0x16 /* periph bank 6 access parameters */
-#define PB7AP 0x17 /* periph bank 7 access parameters */
-#define PBEAR 0x20 /* periph bus error addr reg */
-#define PBESR0 0x21 /* periph bus error status reg 0 */
-#define PBESR1 0x22 /* periph bus error status reg 1 */
-#define EBC0_CFG 0x23 /* external bus configuration reg */
-
-/*
- * GPIO macro register defines
- */
-/* todo: merge with gpio.h header */
-#define GPIO_BASE GPIO0_BASE
-
-#define GPIO0_OR (GPIO0_BASE + 0x0)
-#define GPIO0_TCR (GPIO0_BASE + 0x4)
-#define GPIO0_OSRL (GPIO0_BASE + 0x8)
-#define GPIO0_OSRH (GPIO0_BASE + 0xC)
-#define GPIO0_TSRL (GPIO0_BASE + 0x10)
-#define GPIO0_TSRH (GPIO0_BASE + 0x14)
-#define GPIO0_ODR (GPIO0_BASE + 0x18)
-#define GPIO0_IR (GPIO0_BASE + 0x1C)
-#define GPIO0_RR1 (GPIO0_BASE + 0x20)
-#define GPIO0_RR2 (GPIO0_BASE + 0x24)
-#define GPIO0_RR3 (GPIO0_BASE + 0x28)
-#define GPIO0_ISR1L (GPIO0_BASE + 0x30)
-#define GPIO0_ISR1H (GPIO0_BASE + 0x34)
-#define GPIO0_ISR2L (GPIO0_BASE + 0x38)
-#define GPIO0_ISR2H (GPIO0_BASE + 0x3C)
-#define GPIO0_ISR3L (GPIO0_BASE + 0x40)
-#define GPIO0_ISR3H (GPIO0_BASE + 0x44)
-
-#define GPIO1_OR (GPIO1_BASE + 0x0)
-#define GPIO1_TCR (GPIO1_BASE + 0x4)
-#define GPIO1_OSRL (GPIO1_BASE + 0x8)
-#define GPIO1_OSRH (GPIO1_BASE + 0xC)
-#define GPIO1_TSRL (GPIO1_BASE + 0x10)
-#define GPIO1_TSRH (GPIO1_BASE + 0x14)
-#define GPIO1_ODR (GPIO1_BASE + 0x18)
-#define GPIO1_IR (GPIO1_BASE + 0x1C)
-#define GPIO1_RR1 (GPIO1_BASE + 0x20)
-#define GPIO1_RR2 (GPIO1_BASE + 0x24)
-#define GPIO1_RR3 (GPIO1_BASE + 0x28)
-#define GPIO1_ISR1L (GPIO1_BASE + 0x30)
-#define GPIO1_ISR1H (GPIO1_BASE + 0x34)
-#define GPIO1_ISR2L (GPIO1_BASE + 0x38)
-#define GPIO1_ISR2H (GPIO1_BASE + 0x3C)
-#define GPIO1_ISR3L (GPIO1_BASE + 0x40)
-#define GPIO1_ISR3H (GPIO1_BASE + 0x44)
-
-/* General Purpose Timer (GPT) Register Offsets */
-#define GPT0_TBC 0x00000000
-#define GPT0_IM 0x00000018
-#define GPT0_ISS 0x0000001C
-#define GPT0_ISC 0x00000020
-#define GPT0_IE 0x00000024
-#define GPT0_COMP0 0x00000080
-#define GPT0_COMP1 0x00000084
-#define GPT0_COMP2 0x00000088
-#define GPT0_COMP3 0x0000008C
-#define GPT0_COMP4 0x00000090
-#define GPT0_COMP5 0x00000094
-#define GPT0_COMP6 0x00000098
-#define GPT0_MASK0 0x000000C0
-#define GPT0_MASK1 0x000000C4
-#define GPT0_MASK2 0x000000C8
-#define GPT0_MASK3 0x000000CC
-#define GPT0_MASK4 0x000000D0
-#define GPT0_MASK5 0x000000D4
-#define GPT0_MASK6 0x000000D8
-#define GPT0_DCT0 0x00000110
-#define GPT0_DCIS 0x0000011C
-
-#if defined(CONFIG_440)
-#include <asm/ppc440.h>
-#else
-#include <asm/ppc405.h>
-#endif
-
-#include <asm/ppc4xx-sdram.h>
-#include <asm/ppc4xx-ebc.h>
-#if !defined(CONFIG_XILINX_440)
-#include <asm/ppc4xx-uic.h>
-#endif
-
-/*
- * Macro for generating register field mnemonics
- */
-#define PPC_REG_BITS 32
-#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
-
-/*
- * Elide casts when assembling register mnemonics
- */
-#ifndef __ASSEMBLY__
-#define static_cast(type, val) (type)(val)
-#else
-#define static_cast(type, val) (val)
-#endif
-
-/*
- * Common stuff for 4xx (405 and 440)
- */
-
-#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
-#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
-
-#define RESET_VECTOR 0xfffffffc
-#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
- cache line aligned data. */
-
-#define CPR0_DCR_BASE 0x0C
-#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
-#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
-
-#define SDR_DCR_BASE 0x0E
-#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
-#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
-
-#define SDRAM_DCR_BASE 0x10
-#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
-#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
-
-#define EBC_DCR_BASE 0x12
-#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
-#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
-
-/*
- * Macros for indirect DCR access
- */
-#define mtcpr(reg, d) \
- do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
-#define mfcpr(reg, d) \
- do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
-
-#define mtebc(reg, d) \
- do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
-#define mfebc(reg, d) \
- do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
-
-#define mtsdram(reg, d) \
- do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
-#define mfsdram(reg, d) \
- do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
-
-#define mtsdr(reg, d) \
- do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
-#define mfsdr(reg, d) \
- do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
-
-#ifndef __ASSEMBLY__
-
-typedef struct
-{
- unsigned long freqDDR;
- unsigned long freqEBC;
- unsigned long freqOPB;
- unsigned long freqPCI;
- unsigned long freqPLB;
- unsigned long freqTmrClk;
- unsigned long freqUART;
- unsigned long freqProcessor;
- unsigned long freqVCOHz;
- unsigned long freqVCOMhz; /* in MHz */
- unsigned long pciClkSync; /* PCI clock is synchronous */
- unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
- unsigned long pllExtBusDiv;
- unsigned long pllFbkDiv;
- unsigned long pllFwdDiv;
- unsigned long pllFwdDivA;
- unsigned long pllFwdDivB;
- unsigned long pllOpbDiv;
- unsigned long pllPciDiv;
- unsigned long pllPlbDiv;
-} PPC4xx_SYS_INFO;
-
-static inline u32 get_mcsr(void)
-{
- u32 val;
-
- asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
- return val;
-}
-
-static inline void set_mcsr(u32 val)
-{
- asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
-int ppc4xx_pci_sync_clock_config(u32 async);
-
-unsigned long get_OPB_freq(void);
-unsigned long get_PCI_freq(void);
-
-typedef PPC4xx_SYS_INFO sys_info_t;
-int ppc440spe_revB(void);
-void get_sys_info(sys_info_t *);
-
-#endif /* __ASSEMBLY__ */
-
-/* for multi-cpu support */
-#define NA_OR_UNKNOWN_CPU -1
-
-#endif /* __PPC4XX_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2009
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PPC4xx_CONFIG_H
-#define __PPC4xx_CONFIG_H
-
-#include <common.h>
-
-struct ppc4xx_config {
- char label[16];
- char description[64];
- u8 val[CONFIG_4xx_CONFIG_BLOCKSIZE];
-};
-
-extern struct ppc4xx_config ppc4xx_config_val[];
-extern int ppc4xx_config_count;
-
-#endif /* __PPC4xx_CONFIG_H */
/* Special Purpose Registers (SPRNs)*/
-/* PPC440 Architecture is BOOK-E */
-#ifdef CONFIG_440
-#define CONFIG_BOOKE
-#endif
-
#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
#ifdef CONFIG_BOOKE
#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
#define SPRN_MCAR 0x23d /* Machine Check Address register */
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
-#if defined(CONFIG_440)
-#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
-#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
-#else
#define MCSR_DB 0x20000000 /* Data PLB Error */
-#endif /* defined(CONFIG_440) */
#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
#define MAS7 SPRN_MAS7
#define MAS8 SPRN_MAS8
-#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85xx)
#define DAR_DEAR DEAR
#else
#define DAR_DEAR DAR
#endif
#endif /* CONFIG_MACH_SPECIFIC */
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
+#if defined(CONFIG_MPC85xx)
#define EPAPR_MAGIC (0x45504150)
#else
#define EPAPR_MAGIC (0x65504150)
endif
endif
-obj-$(CONFIG_SYS_EXTBDINFO) += setup.o
ifdef MINIMAL
obj-y += cache.o time.o
obj-y += ticks.o
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
+++ /dev/null
-/*
- * Copyright (c) 2017 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <version.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int setup_board_extra(void)
-{
- bd_t *bd = gd->bd;
-
- strncpy((char *)bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
- strncpy((char *)bd->bi_r_version, U_BOOT_VERSION,
- sizeof(bd->bi_r_version));
-
- bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
- bd->bi_plb_busfreq = gd->bus_clk;
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
- bd->bi_pci_busfreq = get_PCI_freq();
- bd->bi_opbfreq = get_OPB_freq();
-#elif defined(CONFIG_XILINX_405)
- bd->bi_pci_busfreq = get_PCI_freq();
-#endif
-
- return 0;
-}
+++ /dev/null
-if TARGET_ACADIA
-
-config SYS_BOARD
- default "acadia"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "acadia"
-
-endif
+++ /dev/null
-ACADIA BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/amcc/acadia/
-F: include/configs/acadia.h
-F: configs/acadia_defconfig
+++ /dev/null
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = acadia.o cmd_acadia.o memory.o pll.o
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-extern void board_pll_init_f(void);
-
-static void acadia_gpio_init(void)
-{
- /*
- * GPIO0 setup (select GPIO or alternate function)
- */
- out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
- out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
- out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
- out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
- out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
- out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
- out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
-
- /*
- * Ultra (405EZ) was nice enough to add another GPIO controller
- */
- out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */
- out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
- out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */
- out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
- out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */
- out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
- out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */
-}
-
-int board_early_init_f(void)
-{
- unsigned int reg;
-
- /* don't reinit PLL when booting via I2C bootstrap option */
- mfsdr(SDR0_PINSTP, reg);
- if (reg != 0xf0000000)
- board_pll_init_f();
-
- acadia_gpio_init();
-
- /* Configure 405EZ for NAND usage */
- mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
- mfsdr(SDR0_ULTRA0, reg);
- reg &= ~SDR_ULTRA0_CSN_MASK;
- reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
- SDR_ULTRA0_NDGPIOBP |
- SDR_ULTRA0_EBCRDYEN |
- SDR_ULTRA0_NFSRSTEN;
- mtsdr(SDR0_ULTRA0, reg);
-
- /* USB Host core needs this bit set */
- mfsdr(SDR0_ULTRA1, reg);
- mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
-
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000010);
- mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */
- mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- return 0;
-}
-
-int misc_init_f(void)
-{
- /* Set EPLD to take PHY out of reset */
- out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
- udelay(100000);
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
- u8 rev;
-
- rev = in8(CONFIG_SYS_CPLD_BASE + 0);
- printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-
-static u8 boot_267_nor[] = {
- 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00,
- 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
-};
-
-static u8 boot_267_nand[] = {
- 0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00,
- 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
-};
-
-static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u8 chip;
- u8 *buf;
- int cpu_freq;
-
- if (argc < 3)
- return cmd_usage(cmdtp);
-
- cpu_freq = simple_strtol(argv[1], NULL, 10);
- if (cpu_freq != 267) {
- printf("Unsupported cpu-frequency - only 267 supported\n");
- return 1;
- }
-
- /* use 0x50 as I2C EEPROM address for now */
- chip = 0x50;
-
- if ((strcmp(argv[2], "nor") != 0) &&
- (strcmp(argv[2], "nand") != 0)) {
- printf("Unsupported boot-device - only nor|nand support\n");
- return 1;
- }
-
- if (strcmp(argv[2], "nand") == 0) {
- switch (cpu_freq) {
- case 267:
- buf = boot_267_nand;
- break;
- default:
- break;
- }
- } else {
- switch (cpu_freq) {
- case 267:
- buf = boot_267_nor;
- break;
- default:
- break;
- }
- }
-
- if (i2c_write(chip, 0, 1, buf, 16) != 0)
- printf("Error writing to EEPROM at address 0x%x\n", chip);
- udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
- if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0)
- printf("Error2 writing to EEPROM at address 0x%x\n", chip);
-
- printf("Done\n");
- printf("Please power-cycle the board for the changes to take effect\n");
-
- return 0;
-}
-
-U_BOOT_CMD(
- bootstrap, 3, 0, do_bootstrap,
- "program the I2C bootstrap EEPROM",
- "<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM"
-);
+++ /dev/null
-#
-# (C) Copyright 2007-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# AMCC 405EZ Reference Platform (Acadia) board
-#
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void board_pll_init_f(void);
-
-static void cram_bcr_write(u32 wr_val)
-{
- wr_val <<= 2;
-
- /* set CRAM_CRE to 1 */
- gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
-
- /* Write BCR to CRAM on CS1 */
- out32(wr_val + 0x00200000, 0);
- debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
-
- /* Write BCR to CRAM on CS2 */
- out32(wr_val + 0x02200000, 0);
- debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
-
- sync();
- eieio();
-
- /* set CRAM_CRE back to 0 (normal operation) */
- gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
-
- return;
-}
-
-int dram_init(void)
-{
- int i;
- u32 val;
-
- /* 1. EBC need to program READY, CLK, ADV for ASync mode */
- gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
- gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
- gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
- gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
-
- /* 2. EBC in Async mode */
- mtebc(PB1AP, 0x078F1EC0);
- mtebc(PB2AP, 0x078F1EC0);
- mtebc(PB1CR, 0x000BC000);
- mtebc(PB2CR, 0x020BC000);
-
- /* 3. Set CRAM in Sync mode */
- cram_bcr_write(0x7012); /* CRAM burst setting */
-
- /* 4. EBC in Sync mode */
- mtebc(PB1AP, 0x9C0201C0);
- mtebc(PB2AP, 0x9C0201C0);
-
- /* Set GPIO pins back to alternate function */
- gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
- gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
-
- /* Config EBC to use RDY */
- mfsdr(SDR0_ULTRA0, val);
- mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
-
- /* Wait a short while, since for NAND booting this is too fast */
- for (i=0; i<200000; i++)
- ;
-
- gd->ram_size = CONFIG_SYS_MBYTES_RAM << 20;
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc405.h>
-
-/* test-only: move into cpu directory!!! */
-
-#if defined(PLLMR0_200_133_66)
-void board_pll_init_f(void)
-{
- /*
- * set PLL clocks based on input sysclk is 33M
- *
- * ----------------------------------
- * | CLK | FREQ (MHz) | DIV RATIO |
- * ----------------------------------
- * | CPU | 200.0 | 4 (0x02)|
- * | PLB | 133.3 | 6 (0x06)|
- * | OPB | 66.6 | 12 (0x0C)|
- * | EBC | 66.6 | 12 (0x0C)|
- * | SPI | 66.6 | 12 (0x0C)|
- * | UART0 | 10.0 | 40 (0x28)|
- * | UART1 | 10.0 | 40 (0x28)|
- * | DAC | 2.0 | 200 (0xC8)|
- * | ADC | 2.0 | 200 (0xC8)|
- * | PWM | 100.0 | 4 (0x04)|
- * | EMAC | 25.0 | 16 (0x10)|
- * -----------------------------------
- */
-
- /* Initialize PLL */
- mtcpr(CPR0_PLLC, 0x0000033c);
- mtcpr(CPR0_PLLD, 0x0c010200);
- mtcpr(CPR0_PRIMAD, 0x04060c0c);
- mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
- mtcpr(CPR0_CLKUPD, 0x40000000);
-}
-
-#elif defined(PLLMR0_266_160_80)
-
-void board_pll_init_f(void)
-{
- /*
- * set PLL clocks based on input sysclk is 33M
- *
- * ----------------------------------
- * | CLK | FREQ (MHz) | DIV RATIO |
- * ----------------------------------
- * | CPU | 266.64 | 3 |
- * | PLB | 159.98 | 5 (0x05)|
- * | OPB | 79.99 | 10 (0x0A)|
- * | EBC | 79.99 | 10 (0x0A)|
- * | SPI | 79.99 | 10 (0x0A)|
- * | UART0 | 28.57 | 7 (0x07)|
- * | UART1 | 28.57 | 7 (0x07)|
- * | DAC | 28.57 | 7 (0xA7)|
- * | ADC | 4 | 50 (0x32)|
- * | PWM | 28.57 | 7 (0x07)|
- * | EMAC | 4 | 50 (0x32)|
- * -----------------------------------
- */
-
- /* Initialize PLL */
- mtcpr(CPR0_PLLC, 0x20000238);
- mtcpr(CPR0_PLLD, 0x03010400);
- mtcpr(CPR0_PRIMAD, 0x03050a0a);
- mtcpr(CPR0_PERC0, 0x00000000);
- mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
- mtcpr(CPR0_PERD1, 0x07323200);
- mtcpr(CPR0_CLKUP, 0x40000000);
-}
-
-#elif defined(PLLMR0_333_166_83)
-
-void board_pll_init_f(void)
-{
- /*
- * set PLL clocks based on input sysclk is 33M
- *
- * ----------------------------------
- * | CLK | FREQ (MHz) | DIV RATIO |
- * ----------------------------------
- * | CPU | 333.33 | 2 |
- * | PLB | 166.66 | 4 (0x04)|
- * | OPB | 83.33 | 8 (0x08)|
- * | EBC | 83.33 | 8 (0x08)|
- * | SPI | 83.33 | 8 (0x08)|
- * | UART0 | 16.66 | 5 (0x05)|
- * | UART1 | 16.66 | 5 (0x05)|
- * | DAC | ???? | 166 (0xA6)|
- * | ADC | ???? | 166 (0xA6)|
- * | PWM | 41.66 | 3 (0x03)|
- * | EMAC | ???? | 3 (0x03)|
- * -----------------------------------
- */
-
- /* Initialize PLL */
- mtcpr(CPR0_PLLC, 0x0000033C);
- mtcpr(CPR0_PLLD, 0x0a010000);
- mtcpr(CPR0_PRIMAD, 0x02040808);
- mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
- mtcpr(CPR0_PERD1, 0xA6A60300);
- mtcpr(CPR0_CLKUP, 0x40000000);
-}
-
-#elif defined(PLLMR0_100_100_12)
-
-void board_pll_init_f(void)
-{
- /*
- * set PLL clocks based on input sysclk is 33M
- *
- * ----------------------
- * | CLK | FREQ (MHz) |
- * ----------------------
- * | CPU | 100.00 |
- * | PLB | 100.00 |
- * | OPB | 12.00 |
- * | EBC | 49.00 |
- * ----------------------
- */
-
- /* Initialize PLL */
- mtcpr(CPR0_PLLC, 0x000003BC);
- mtcpr(CPR0_PLLD, 0x06060600);
- mtcpr(CPR0_PRIMAD, 0x02020004);
- mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
- mtcpr(CPR0_PERD1, 0xC8C81600);
- mtcpr(CPR0_CLKUP, 0x40000000);
-}
-#endif /* CPU_<speed>_405EZ */
+++ /dev/null
-if TARGET_BAMBOO
-
-config SYS_BOARD
- default "bamboo"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "bamboo"
-
-endif
+++ /dev/null
-BAMBOO BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/amcc/bamboo/
-F: include/configs/bamboo.h
-F: configs/bamboo_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = bamboo.o flash.o
-extra-y += init.o
+++ /dev/null
-The 2 important dipswitches are configured as shown below:
-
-SW1 (for 33MHz SysClk)
-----------------------
-S1 S2 S3 S4 S5 S6 S7 S8
-OFF OFF OFF OFF OFF OFF OFF ON
-
-SW7 (for Op-Code Flash and Boot Option H)
------------------------------------------
-S1 S2 S3 S4 S5 S6 S7 S8
-OFF OFF OFF ON OFF OFF OFF OFF
-
-The EEPROM at location 0x52 is loaded with these 16 bytes:
-C47042A6 05D7A190 40082350 0d050000
-
-SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors
-SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB
-SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output
-SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz
-SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor
-SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A
-SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B
-SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B
-SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor
-SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor
-SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0
-SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0
-SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0
-SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer
-SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit
-SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC
-SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled
-SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled
-SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100
-SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled
-SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1
-SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled
-SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC
-SDR0_SDSTP0[NE]: 0 : NDFC: disabled
-SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit
-SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection
-SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size)
-SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled
-SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready
-SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter
-SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC
-SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC
-SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC
-SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC
-SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count
-
-PPC440EP Clocking Configuration
-
-SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz
-OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz
-
-The above information is reported by Eugene O'Brien
-<Eugene.O'Brien@advantechamt.com>. Thanks a lot.
-
-2007-08-06, Stefan Roese <sr@denx.de>
----------------------------------------------------------------------
-
-The configuration for the AMCC 440EP eval board "Bamboo" was changed
-to only use 384 kbytes of FLASH for the U-Boot image. This way the
-redundant environment can be saved in the remaining 2 sectors of the
-same flash chip.
-
-Caution: With an upgrade from an earlier U-Boot version the current
-environment will be erased since the environment is now saved in
-different sectors. By using the following command the environment can
-be saved after upgrading the U-Boot image and *before* resetting the
-board:
-
-setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \
- 'cp.b FFF60000 FFF80000 20000'
-
-2006-07-27, Stefan Roese <sr@denx.de>
+++ /dev/null
-/*
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <spd_sdram.h>
-#include <asm/ppc440.h>
-#include "bamboo.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void ext_bus_cntlr_init(void);
-void configure_ppc440ep_pins(void);
-int is_nand_selected(void);
-
-/*************************************************************************
- *
- * Bamboo has one bank onboard sdram (plus DIMM)
- *
- * Fixed memory is composed of :
- * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
- * 13 row add bits, 10 column add bits (but 12 row used only).
- * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
- * 12 row add bits, 10 column add bits.
- * Prepare a subset (only the used ones) of SPD data
- *
- * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
- * the corresponding bank is divided by 2 due to number of Row addresses
- * 12 in the ECC module
- *
- * Assumes: 64 MB, ECC, non-registered
- * PLB @ 133 MHz
- *
- ************************************************************************/
-const unsigned char cfg_simulate_spd_eeprom[128] = {
- 0x80, /* number of SPD bytes used: 128 */
- 0x08, /* total number bytes in SPD device = 256 */
- 0x07, /* DDR ram */
-#ifdef CONFIG_DDR_ECC
- 0x0C, /* num Row Addr: 12 */
-#else
- 0x0D, /* num Row Addr: 13 */
-#endif
- 0x09, /* numColAddr: 9 */
- 0x01, /* numBanks: 1 */
- 0x20, /* Module data width: 32 bits */
- 0x00, /* Module data width continued: +0 */
- 0x04, /* 2.5 Volt */
- 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
- 0x00, /* SDRAM Access from clock */
-#ifdef CONFIG_DDR_ECC
- 0x02, /* ECC ON : 02 OFF : 00 */
-#else
- 0x00, /* ECC ON : 02 OFF : 00 */
-#endif
- 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
- 0,
- 0,
- 0x01, /* wcsbc = 1 */
- 0,
- 0,
- 0x0C, /* casBit (2,2.5) */
- 0,
- 0,
- 0x00, /* not registered: 0 registered : 0x02*/
- 0,
- 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
- 0,
- 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
- 0,
- 0x50, /* tRpNs = 20 ns */
- 0,
- 0x50, /* tRcdNs = 20 ns */
- 45, /* tRasNs */
-#ifdef CONFIG_DDR_ECC
- 0x08, /* bankSizeID: 32MB */
-#else
- 0x10, /* bankSizeID: 64MB */
-#endif
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
-};
-
-#if 0
-{ /* GPIO Alternate1 Alternate2 Alternate3 */
- {
- /* GPIO Core 0 */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
- { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
- { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
- },
- {
- /* GPIO Core 1 */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
- }
-};
-#endif
-
-/*----------------------------------------------------------------------------+
- | EBC Devices Characteristics
- | Peripheral Bank Access Parameters - EBC0_BnAP
- | Peripheral Bank Configuration Register - EBC0_BnCR
- +----------------------------------------------------------------------------*/
-/* Small Flash */
-#define EBC0_BNAP_SMALL_FLASH \
- EBC0_BNAP_BME_DISABLED | \
- EBC0_BNAP_TWT_ENCODE(6) | \
- EBC0_BNAP_CSN_ENCODE(0) | \
- EBC0_BNAP_OEN_ENCODE(1) | \
- EBC0_BNAP_WBN_ENCODE(1) | \
- EBC0_BNAP_WBF_ENCODE(3) | \
- EBC0_BNAP_TH_ENCODE(1) | \
- EBC0_BNAP_RE_ENABLED | \
- EBC0_BNAP_SOR_DELAYED | \
- EBC0_BNAP_BEM_WRITEONLY | \
- EBC0_BNAP_PEN_DISABLED
-
-#define EBC0_BNCR_SMALL_FLASH_CS0 \
- EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_8BIT
-
-#define EBC0_BNCR_SMALL_FLASH_CS4 \
- EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_8BIT
-
-/* Large Flash or SRAM */
-#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
- EBC0_BNAP_BME_DISABLED | \
- EBC0_BNAP_TWT_ENCODE(8) | \
- EBC0_BNAP_CSN_ENCODE(0) | \
- EBC0_BNAP_OEN_ENCODE(1) | \
- EBC0_BNAP_WBN_ENCODE(1) | \
- EBC0_BNAP_WBF_ENCODE(1) | \
- EBC0_BNAP_TH_ENCODE(2) | \
- EBC0_BNAP_SOR_DELAYED | \
- EBC0_BNAP_BEM_RW | \
- EBC0_BNAP_PEN_DISABLED
-
-#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
- EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
- EBC0_BNCR_BS_8MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_16BIT
-
-
-#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
- EBC0_BNCR_BAS_ENCODE(0x87800000) | \
- EBC0_BNCR_BS_8MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_16BIT
-
-/* NVRAM - FPGA */
-#define EBC0_BNAP_NVRAM_FPGA \
- EBC0_BNAP_BME_DISABLED | \
- EBC0_BNAP_TWT_ENCODE(9) | \
- EBC0_BNAP_CSN_ENCODE(0) | \
- EBC0_BNAP_OEN_ENCODE(1) | \
- EBC0_BNAP_WBN_ENCODE(1) | \
- EBC0_BNAP_WBF_ENCODE(0) | \
- EBC0_BNAP_TH_ENCODE(2) | \
- EBC0_BNAP_RE_ENABLED | \
- EBC0_BNAP_SOR_DELAYED | \
- EBC0_BNAP_BEM_WRITEONLY | \
- EBC0_BNAP_PEN_DISABLED
-
-#define EBC0_BNCR_NVRAM_FPGA_CS5 \
- EBC0_BNCR_BAS_ENCODE(0x80000000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_8BIT
-
-/* Nand Flash */
-#define EBC0_BNAP_NAND_FLASH \
- EBC0_BNAP_BME_DISABLED | \
- EBC0_BNAP_TWT_ENCODE(3) | \
- EBC0_BNAP_CSN_ENCODE(0) | \
- EBC0_BNAP_OEN_ENCODE(0) | \
- EBC0_BNAP_WBN_ENCODE(0) | \
- EBC0_BNAP_WBF_ENCODE(0) | \
- EBC0_BNAP_TH_ENCODE(1) | \
- EBC0_BNAP_RE_ENABLED | \
- EBC0_BNAP_SOR_NOT_DELAYED | \
- EBC0_BNAP_BEM_RW | \
- EBC0_BNAP_PEN_DISABLED
-
-
-#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
-
-/* NAND0 */
-#define EBC0_BNCR_NAND_FLASH_CS1 \
- EBC0_BNCR_BAS_ENCODE(0x90000000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_32BIT
-/* NAND1 - Bank2 */
-#define EBC0_BNCR_NAND_FLASH_CS2 \
- EBC0_BNCR_BAS_ENCODE(0x94000000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_32BIT
-
-/* NAND1 - Bank3 */
-#define EBC0_BNCR_NAND_FLASH_CS3 \
- EBC0_BNCR_BAS_ENCODE(0x94000000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_32BIT
-
-int board_early_init_f(void)
-{
- ext_bus_cntlr_init();
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
- mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- /*--------------------------------------------------------------------
- * Setup the GPIO pins
- *-------------------------------------------------------------------*/
- out32(GPIO0_OSRL, 0x00000400);
- out32(GPIO0_OSRH, 0x00000000);
- out32(GPIO0_TSRL, 0x00000400);
- out32(GPIO0_TSRH, 0x00000000);
- out32(GPIO0_ISR1L, 0x00000000);
- out32(GPIO0_ISR1H, 0x00000000);
- out32(GPIO0_ISR2L, 0x00000000);
- out32(GPIO0_ISR2H, 0x00000000);
- out32(GPIO0_ISR3L, 0x00000000);
- out32(GPIO0_ISR3H, 0x00000000);
-
- out32(GPIO1_OSRL, 0x0C380000);
- out32(GPIO1_OSRH, 0x00000000);
- out32(GPIO1_TSRL, 0x0C380000);
- out32(GPIO1_TSRH, 0x00000000);
- out32(GPIO1_ISR1L, 0x0FC30000);
- out32(GPIO1_ISR1H, 0x00000000);
- out32(GPIO1_ISR2L, 0x0C010000);
- out32(GPIO1_ISR2H, 0x00000000);
- out32(GPIO1_ISR3L, 0x01400000);
- out32(GPIO1_ISR3H, 0x00000000);
-
- configure_ppc440ep_pins();
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-
-int dram_init(void)
-{
- gd->ram_size = spd_sdram();
-
- return 0;
-}
-
-/*----------------------------------------------------------------------------+
- | is_powerpc440ep_pass1.
- +----------------------------------------------------------------------------*/
-int is_powerpc440ep_pass1(void)
-{
- unsigned long pvr;
-
- pvr = get_pvr();
-
- if (pvr == PVR_POWERPC_440EP_PASS1)
- return true;
- else if (pvr == PVR_POWERPC_440EP_PASS2)
- return false;
- else {
- printf("brdutil error 3\n");
- for (;;)
- ;
- }
-
- return false;
-}
-
-/*----------------------------------------------------------------------------+
- | is_nand_selected.
- +----------------------------------------------------------------------------*/
-int is_nand_selected(void)
-{
-#ifdef CONFIG_BAMBOO_NAND
- return true;
-#else
- return false;
-#endif
-}
-
-/*----------------------------------------------------------------------------+
- | config_on_ebc_cs4_is_small_flash => from EPLD
- +----------------------------------------------------------------------------*/
-unsigned char config_on_ebc_cs4_is_small_flash(void)
-{
- /* Not implemented yet => returns constant value */
- return true;
-}
-
-/*----------------------------------------------------------------------------+
- | Ext_bus_cntlr_init.
- | Initialize the external bus controller
- +----------------------------------------------------------------------------*/
-void ext_bus_cntlr_init(void)
-{
- unsigned long sdr0_pstrp0, sdr0_sdstp1;
- unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
- int computed_boot_device = BOOT_DEVICE_UNKNOWN;
- unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
- unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
- unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
- unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
- unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
-
-
- /*-------------------------------------------------------------------------+
- |
- | PART 1 : Initialize EBC Bank 5
- | ==============================
- | Bank5 is always associated to the NVRAM/EPLD.
- | It has to be initialized prior to other banks settings computation since
- | some board registers values may be needed
- |
- +-------------------------------------------------------------------------*/
- /* NVRAM - FPGA */
- mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
- mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
-
- /*-------------------------------------------------------------------------+
- |
- | PART 2 : Determine which boot device was selected
- | =========================================
- |
- | Read Pin Strap Register in PPC440EP
- | In case of boot from IIC, read Serial Device Strap Register1
- |
- | Result can either be :
- | - Boot from EBC 8bits => SMALL FLASH
- | - Boot from EBC 16bits => Large Flash or SRAM
- | - Boot from NAND Flash
- | - Boot from PCI
- |
- +-------------------------------------------------------------------------*/
- /* Read Pin Strap Register in PPC440EP */
- mfsdr(SDR0_PINSTP, sdr0_pstrp0);
- bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
-
- /*-------------------------------------------------------------------------+
- | PPC440EP Pass1
- +-------------------------------------------------------------------------*/
- if (is_powerpc440ep_pass1() == true) {
- switch(bootstrap_settings) {
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
- /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
- /* Boot from Small Flash */
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
- /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
- /* Boot from PCI */
- computed_boot_device = BOOT_FROM_PCI;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
- /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
- /* Boot from Nand Flash */
- computed_boot_device = BOOT_FROM_NAND_FLASH0;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
- /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
- /* Boot from Small Flash */
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
- case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
- /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
- /* Read Serial Device Strap Register1 in PPC440EP */
- mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
- boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
- ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
- switch(boot_selection) {
- case SDR0_SDSTP1_BOOT_SEL_EBC:
- switch(ebc_boot_size) {
- case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
- computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
- break;
- case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
- }
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_PCI:
- computed_boot_device = BOOT_FROM_PCI;
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_NDFC:
- computed_boot_device = BOOT_FROM_NAND_FLASH0;
- break;
- }
- break;
- }
- }
-
- /*-------------------------------------------------------------------------+
- | PPC440EP Pass2
- +-------------------------------------------------------------------------*/
- else {
- switch(bootstrap_settings) {
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
- /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
- /* Boot from Small Flash */
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
- /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
- /* Boot from PCI */
- computed_boot_device = BOOT_FROM_PCI;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
- /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
- /* Boot from Nand Flash */
- computed_boot_device = BOOT_FROM_NAND_FLASH0;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
- /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
- /* Boot from Large Flash or SRAM */
- computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
- /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
- /* Boot from Large Flash or SRAM */
- computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
- /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
- /* Boot from PCI */
- computed_boot_device = BOOT_FROM_PCI;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
- case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
- /* Default Strap Settings 5-7 */
- /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
- /* Read Serial Device Strap Register1 in PPC440EP */
- mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
- boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
- ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
- switch(boot_selection) {
- case SDR0_SDSTP1_BOOT_SEL_EBC:
- switch(ebc_boot_size) {
- case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
- computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
- break;
- case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
- }
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_PCI:
- computed_boot_device = BOOT_FROM_PCI;
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_NDFC:
- computed_boot_device = BOOT_FROM_NAND_FLASH0;
- break;
- }
- break;
- }
- }
-
- /*-------------------------------------------------------------------------+
- |
- | PART 3 : Compute EBC settings depending on selected boot device
- | ====== ======================================================
- |
- | Resulting EBC init will be among following configurations :
- |
- | - Boot from EBC 8bits => boot from SMALL FLASH selected
- | EBC-CS0 = Small Flash
- | EBC-CS1,2,3 = NAND Flash or
- | Exp.Slot depending on Soft Config
- | EBC-CS4 = SRAM/Large Flash or
- | Large Flash/SRAM depending on jumpers
- | EBC-CS5 = NVRAM / EPLD
- |
- | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
- | EBC-CS0 = SRAM/Large Flash or
- | Large Flash/SRAM depending on jumpers
- | EBC-CS1,2,3 = NAND Flash or
- | Exp.Slot depending on Software Configuration
- | EBC-CS4 = Small Flash
- | EBC-CS5 = NVRAM / EPLD
- |
- | - Boot from NAND Flash
- | EBC-CS0 = NAND Flash0
- | EBC-CS1,2,3 = NAND Flash1
- | EBC-CS4 = SRAM/Large Flash or
- | Large Flash/SRAM depending on jumpers
- | EBC-CS5 = NVRAM / EPLD
- |
- | - Boot from PCI
- | EBC-CS0 = ...
- | EBC-CS1,2,3 = NAND Flash or
- | Exp.Slot depending on Software Configuration
- | EBC-CS4 = SRAM/Large Flash or
- | Large Flash/SRAM or
- | Small Flash depending on jumpers
- | EBC-CS5 = NVRAM / EPLD
- |
- +-------------------------------------------------------------------------*/
-
- switch(computed_boot_device) {
- /*------------------------------------------------------------------------- */
- case BOOT_FROM_SMALL_FLASH:
- /*------------------------------------------------------------------------- */
- ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
- ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
- if ((is_nand_selected()) == true) {
- /* NAND Flash */
- ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
- ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
- ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
- ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- } else {
- /* Expansion Slot */
- ebc0_cs1_bnap_value = 0;
- ebc0_cs1_bncr_value = 0;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- }
- ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
- ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
-
- break;
-
- /*------------------------------------------------------------------------- */
- case BOOT_FROM_LARGE_FLASH_OR_SRAM:
- /*------------------------------------------------------------------------- */
- ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
- ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
- if ((is_nand_selected()) == true) {
- /* NAND Flash */
- ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
- ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- } else {
- /* Expansion Slot */
- ebc0_cs1_bnap_value = 0;
- ebc0_cs1_bncr_value = 0;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- }
- ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
- ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
-
- break;
-
- /*------------------------------------------------------------------------- */
- case BOOT_FROM_NAND_FLASH0:
- /*------------------------------------------------------------------------- */
- ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
- ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
-
- ebc0_cs1_bnap_value = 0;
- ebc0_cs1_bncr_value = 0;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
-
- /* Large Flash or SRAM */
- ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
- ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
-
- break;
-
- /*------------------------------------------------------------------------- */
- case BOOT_FROM_PCI:
- /*------------------------------------------------------------------------- */
- ebc0_cs0_bnap_value = 0;
- ebc0_cs0_bncr_value = 0;
-
- if ((is_nand_selected()) == true) {
- /* NAND Flash */
- ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
- ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- } else {
- /* Expansion Slot */
- ebc0_cs1_bnap_value = 0;
- ebc0_cs1_bncr_value = 0;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- }
-
- if ((config_on_ebc_cs4_is_small_flash()) == true) {
- /* Small Flash */
- ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
- ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
- } else {
- /* Large Flash or SRAM */
- ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
- ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
- }
-
- break;
-
- /*------------------------------------------------------------------------- */
- case BOOT_DEVICE_UNKNOWN:
- /*------------------------------------------------------------------------- */
- /* Error */
- break;
-
- }
-
-
- /*-------------------------------------------------------------------------+
- | Initialize EBC CONFIG
- +-------------------------------------------------------------------------*/
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
- EBC0_CFG_PTD_ENABLED |
- EBC0_CFG_RTC_2048PERCLK |
- EBC0_CFG_EMPL_LOW |
- EBC0_CFG_EMPH_LOW |
- EBC0_CFG_CSTC_DRIVEN |
- EBC0_CFG_BPF_ONEDW |
- EBC0_CFG_EMS_8BIT |
- EBC0_CFG_PME_DISABLED |
- EBC0_CFG_PMT_ENCODE(0) );
-
- /*-------------------------------------------------------------------------+
- | Initialize EBC Bank 0-4
- +-------------------------------------------------------------------------*/
- /* EBC Bank0 */
- mtebc(PB0AP, ebc0_cs0_bnap_value);
- mtebc(PB0CR, ebc0_cs0_bncr_value);
- /* EBC Bank1 */
- mtebc(PB1AP, ebc0_cs1_bnap_value);
- mtebc(PB1CR, ebc0_cs1_bncr_value);
- /* EBC Bank2 */
- mtebc(PB2AP, ebc0_cs2_bnap_value);
- mtebc(PB2CR, ebc0_cs2_bncr_value);
- /* EBC Bank3 */
- mtebc(PB3AP, ebc0_cs3_bnap_value);
- mtebc(PB3CR, ebc0_cs3_bncr_value);
- /* EBC Bank4 */
- mtebc(PB4AP, ebc0_cs4_bnap_value);
- mtebc(PB4CR, ebc0_cs4_bncr_value);
-
- return;
-}
-
-
-/*----------------------------------------------------------------------------+
- | get_uart_configuration.
- +----------------------------------------------------------------------------*/
-uart_config_nb_t get_uart_configuration(void)
-{
- return (L4);
-}
-
-/*----------------------------------------------------------------------------+
- | set_phy_configuration_through_fpga => to EPLD
- +----------------------------------------------------------------------------*/
-void set_phy_configuration_through_fpga(zmii_config_t config)
-{
-
- unsigned long fpga_selection_reg;
-
- fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
-
- switch(config)
- {
- case ZMII_CONFIGURATION_IS_MII:
- fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
- break;
- case ZMII_CONFIGURATION_IS_RMII:
- fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
- break;
- case ZMII_CONFIGURATION_IS_SMII:
- fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
- break;
- case ZMII_CONFIGURATION_UNKNOWN:
- default:
- break;
- }
- out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
-
-}
-
-/*----------------------------------------------------------------------------+
- | scp_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void scp_selection_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
- fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | iic1_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void iic1_selection_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
- fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | dma_a_b_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void dma_a_b_selection_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | dma_a_b_unselect_in_fpga.
- +----------------------------------------------------------------------------*/
-void dma_a_b_unselect_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | dma_c_d_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void dma_c_d_selection_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | dma_c_d_unselect_in_fpga.
- +----------------------------------------------------------------------------*/
-void dma_c_d_unselect_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | usb2_device_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void usb2_device_selection_in_fpga(void)
-{
- unsigned long fpga_selection_1_reg;
-
- fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
- out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | usb2_device_reset_through_fpga.
- +----------------------------------------------------------------------------*/
-void usb2_device_reset_through_fpga(void)
-{
- /* Perform soft Reset pulse */
- unsigned long fpga_reset_reg;
- int i;
-
- fpga_reset_reg = in8(FPGA_RESET_REG);
- out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
- for (i=0; i<500; i++)
- udelay(1000);
- out8(FPGA_RESET_REG,fpga_reset_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | usb2_host_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void usb2_host_selection_in_fpga(void)
-{
- unsigned long fpga_selection_1_reg;
-
- fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
- out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | ndfc_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void ndfc_selection_in_fpga(void)
-{
- unsigned long fpga_selection_1_reg;
-
- fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
- fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
- fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
- out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | uart_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void uart_selection_in_fpga(uart_config_nb_t uart_config)
-{
- /* FPGA register */
- unsigned char fpga_selection_3_reg;
-
- /* Read FPGA Reagister */
- fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
-
- switch (uart_config)
- {
- case L1:
- /* ----------------------------------------------------------------------- */
- /* L1 configuration: UART0 = 8 pins */
- /* ----------------------------------------------------------------------- */
- /* Configure FPGA */
- fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
- fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
- out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
-
- break;
-
- case L2:
- /* ----------------------------------------------------------------------- */
- /* L2 configuration: UART0 = 4 pins */
- /* UART1 = 4 pins */
- /* ----------------------------------------------------------------------- */
- /* Configure FPGA */
- fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
- fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
- out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
-
- break;
-
- case L3:
- /* ----------------------------------------------------------------------- */
- /* L3 configuration: UART0 = 4 pins */
- /* UART1 = 2 pins */
- /* UART2 = 2 pins */
- /* ----------------------------------------------------------------------- */
- /* Configure FPGA */
- fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
- fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
- out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
- break;
-
- case L4:
- /* Configure FPGA */
- fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
- fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
- out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
-
- break;
-
- default:
- /* Unsupported UART configuration number */
- for (;;)
- ;
- break;
-
- }
-}
-
-
-/*----------------------------------------------------------------------------+
- | init_default_gpio
- +----------------------------------------------------------------------------*/
-void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- int i;
-
- /* Init GPIO0 */
- for(i=0; i<GPIO_MAX; i++)
- {
- gpio_tab[GPIO0][i].add = GPIO0_BASE;
- gpio_tab[GPIO0][i].in_out = GPIO_DIS;
- gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
- }
-
- /* Init GPIO1 */
- for(i=0; i<GPIO_MAX; i++)
- {
- gpio_tab[GPIO1][i].add = GPIO1_BASE;
- gpio_tab[GPIO1][i].in_out = GPIO_DIS;
- gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
- }
-
- /* EBC_CS_N(5) - GPIO0_10 */
- gpio_tab[GPIO0][10].in_out = GPIO_OUT;
- gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
-
- /* EBC_CS_N(4) - GPIO0_9 */
- gpio_tab[GPIO0][9].in_out = GPIO_OUT;
- gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
- | update_uart_ios
- +------------------------------------------------------------------------------
- |
- | Set UART Configuration in PowerPC440EP
- |
- | +---------------------------------------------------------------------+
- | | Configuartion | Connector | Nb of pins | Pins | Associated |
- | | Number | Port Name | available | naming | CORE |
- | +-----------------+---------------+------------+--------+-------------+
- | | L1 | Port_A | 8 | UART | UART core 0 |
- | +-----------------+---------------+------------+--------+-------------+
- | | L2 | Port_A | 4 | UART1 | UART core 0 |
- | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
- | +-----------------+---------------+------------+--------+-------------+
- | | L3 | Port_A | 4 | UART1 | UART core 0 |
- | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
- | | | Port_C | 2 | UART3 | UART core 2 |
- | +-----------------+---------------+------------+--------+-------------+
- | | | Port_A | 2 | UART1 | UART core 0 |
- | | L4 | Port_B | 2 | UART2 | UART core 1 |
- | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
- | | | Port_D | 2 | UART4 | UART core 3 |
- | +-----------------+---------------+------------+--------+-------------+
- |
- | Involved GPIOs
- |
- | +------------------------------------------------------------------------------+
- | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
- | +---------+------------------+-----+-----------------+-----+-------------+-----+
- | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
- | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
- | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
- | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
- | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
- | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
- | +------------------------------------------------------------------------------+
- |
- |
- +----------------------------------------------------------------------------*/
-
-void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- switch (uart_config)
- {
- case L1:
- /* ----------------------------------------------------------------------- */
- /* L1 configuration: UART0 = 8 pins */
- /* ----------------------------------------------------------------------- */
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO1][2].in_out = GPIO_IN;
- gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][3].in_out = GPIO_IN;
- gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][4].in_out = GPIO_IN;
- gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][5].in_out = GPIO_OUT;
- gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][6].in_out = GPIO_OUT;
- gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][7].in_out = GPIO_IN;
- gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
-
- break;
-
- case L2:
- /* ----------------------------------------------------------------------- */
- /* L2 configuration: UART0 = 4 pins */
- /* UART1 = 4 pins */
- /* ----------------------------------------------------------------------- */
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO1][2].in_out = GPIO_IN;
- gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][3].in_out = GPIO_OUT;
- gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][4].in_out = GPIO_IN;
- gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][5].in_out = GPIO_OUT;
- gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][6].in_out = GPIO_OUT;
- gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][7].in_out = GPIO_IN;
- gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
-
- break;
-
- case L3:
- /* ----------------------------------------------------------------------- */
- /* L3 configuration: UART0 = 4 pins */
- /* UART1 = 2 pins */
- /* UART2 = 2 pins */
- /* ----------------------------------------------------------------------- */
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO1][2].in_out = GPIO_OUT;
- gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][3].in_out = GPIO_IN;
- gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][4].in_out = GPIO_IN;
- gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][5].in_out = GPIO_OUT;
- gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][6].in_out = GPIO_OUT;
- gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][7].in_out = GPIO_IN;
- gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
-
- break;
-
- case L4:
- /* ----------------------------------------------------------------------- */
- /* L4 configuration: UART0 = 2 pins */
- /* UART1 = 2 pins */
- /* UART2 = 2 pins */
- /* UART3 = 2 pins */
- /* ----------------------------------------------------------------------- */
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO1][2].in_out = GPIO_OUT;
- gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][3].in_out = GPIO_IN;
- gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][4].in_out = GPIO_IN;
- gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][5].in_out = GPIO_OUT;
- gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][6].in_out = GPIO_OUT;
- gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][7].in_out = GPIO_IN;
- gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
-
- break;
-
- default:
- /* Unsupported UART configuration number */
- printf("ERROR - Unsupported UART configuration number.\n\n");
- for (;;)
- ;
- break;
-
- }
-
- /* Set input Selection Register on Alt_Receive for UART Input Core */
- out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
- out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
- out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
-}
-
-/*----------------------------------------------------------------------------+
- | update_ndfc_ios(void).
- +----------------------------------------------------------------------------*/
-void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
- gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
- gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
-
-#if 0
- gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
- gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
-#endif
-}
-
-/*----------------------------------------------------------------------------+
- | update_zii_ios(void).
- +----------------------------------------------------------------------------*/
-void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
- gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
- gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
- gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
- gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
- gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
- gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
- gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
- gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
- gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
- gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
- gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
- gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
- gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
- gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
-
-}
-
-/*----------------------------------------------------------------------------+
- | update_uic_0_3_irq_ios().
- +----------------------------------------------------------------------------*/
-void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
- gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
- gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
- gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
- gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
- | update_uic_4_9_irq_ios().
- +----------------------------------------------------------------------------*/
-void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
- gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
- gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
- gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
- gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
- gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
- | update_dma_a_b_ios().
- +----------------------------------------------------------------------------*/
-void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
- gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
- gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
- gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
- gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
- gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
-}
-
-/*----------------------------------------------------------------------------+
- | update_dma_c_d_ios().
- +----------------------------------------------------------------------------*/
-void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
- gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
- gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
- gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
- gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
- gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
- gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
-
-}
-
-/*----------------------------------------------------------------------------+
- | update_ebc_master_ios().
- +----------------------------------------------------------------------------*/
-void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
- gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
- gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
- gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
- gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
- | update_usb2_device_ios().
- +----------------------------------------------------------------------------*/
-void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
- gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
- gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
- gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
- gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
- gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
- gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
- gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
- gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
-
-}
-
-/*----------------------------------------------------------------------------+
- | update_pci_patch_ios().
- +----------------------------------------------------------------------------*/
-void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
- gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
- | set_chip_gpio_configuration(unsigned char gpio_core,
- | gpio_param_s (*gpio_tab)[GPIO_MAX])
- | Put the core impacted by clock modification and sharing in reset.
- | Config the select registers to resolve the sharing depending of the config.
- | Configure the GPIO registers.
- |
- +----------------------------------------------------------------------------*/
-void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- unsigned char i=0, j=0, reg_offset = 0;
- unsigned long gpio_reg, gpio_core_add;
-
- /* GPIO config of the GPIOs 0 to 31 */
- for (i=0; i<GPIO_MAX; i++, j++)
- {
- if (i == GPIO_MAX/2)
- {
- reg_offset = 4;
- j = i-16;
- }
-
- gpio_core_add = gpio_tab[gpio_core][i].add;
-
- if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
- (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
- {
- switch (gpio_tab[gpio_core][i].alt_nb)
- {
- case GPIO_SEL:
- break;
-
- case GPIO_ALT1:
- gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
- out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
- break;
-
- case GPIO_ALT2:
- gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
- out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
- break;
-
- case GPIO_ALT3:
- gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
- out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
- break;
- }
- }
- if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
- (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
- {
-
- switch (gpio_tab[gpio_core][i].alt_nb)
- {
- case GPIO_SEL:
- break;
- case GPIO_ALT1:
- gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
- out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
- gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
- out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
- break;
- case GPIO_ALT2:
- gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
- out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
- gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
- out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
- break;
- case GPIO_ALT3:
- gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
- out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
- gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
- out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
- break;
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------+
- | force_bup_core_selection.
- +----------------------------------------------------------------------------*/
-void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
-{
- /* Pointer invalid */
- if (core_select_P == NULL)
- {
- printf("Configuration invalid pointer 1\n");
- for (;;)
- ;
- }
-
- /* L4 Selection */
- *(core_select_P+UART_CORE0) = CORE_SELECTED;
- *(core_select_P+UART_CORE1) = CORE_SELECTED;
- *(core_select_P+UART_CORE2) = CORE_SELECTED;
- *(core_select_P+UART_CORE3) = CORE_SELECTED;
-
- /* RMII Selection */
- *(core_select_P+RMII_SEL) = CORE_SELECTED;
-
- /* External Interrupt 0-9 selection */
- *(core_select_P+UIC_0_3) = CORE_SELECTED;
- *(core_select_P+UIC_4_9) = CORE_SELECTED;
-
- *(core_select_P+SCP_CORE) = CORE_SELECTED;
- *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
- *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
- *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
-
- if (is_nand_selected()) {
- *(core_select_P+NAND_FLASH) = CORE_SELECTED;
- }
-
- *config_val_P = CONFIG_IS_VALID;
-
-}
-
-/*----------------------------------------------------------------------------+
- | configure_ppc440ep_pins.
- +----------------------------------------------------------------------------*/
-void configure_ppc440ep_pins(void)
-{
- uart_config_nb_t uart_configuration;
- config_validity_t config_val = CONFIG_IS_INVALID;
-
- /* Create Core Selection Table */
- core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
- {
- CORE_NOT_SELECTED, /* IIC_CORE, */
- CORE_NOT_SELECTED, /* SPC_CORE, */
- CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
- CORE_NOT_SELECTED, /* UIC_4_9, */
- CORE_NOT_SELECTED, /* USB2_HOST, */
- CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
- CORE_NOT_SELECTED, /* USB2_DEVICE, */
- CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
- CORE_NOT_SELECTED, /* USB1_DEVICE, */
- CORE_NOT_SELECTED, /* EBC_MASTER, */
- CORE_NOT_SELECTED, /* NAND_FLASH, */
- CORE_NOT_SELECTED, /* UART_CORE0, */
- CORE_NOT_SELECTED, /* UART_CORE1, */
- CORE_NOT_SELECTED, /* UART_CORE2, */
- CORE_NOT_SELECTED, /* UART_CORE3, */
- CORE_NOT_SELECTED, /* MII_SEL, */
- CORE_NOT_SELECTED, /* RMII_SEL, */
- CORE_NOT_SELECTED, /* SMII_SEL, */
- CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
- CORE_NOT_SELECTED, /* UIC_0_3 */
- CORE_NOT_SELECTED, /* USB1_HOST */
- CORE_NOT_SELECTED /* PCI_PATCH */
- };
-
- gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
-
- /* Table Default Initialisation + FPGA Access */
- init_default_gpio(gpio_tab);
- set_chip_gpio_configuration(GPIO0, gpio_tab);
- set_chip_gpio_configuration(GPIO1, gpio_tab);
-
- /* Update Table */
- force_bup_core_selection(ppc440ep_core_selection, &config_val);
-#if 0 /* test-only */
- /* If we are running PIBS 1, force known configuration */
- update_core_selection_table(ppc440ep_core_selection, &config_val);
-#endif
-
- /*----------------------------------------------------------------------------+
- | SDR + ios table update + fpga initialization
- +----------------------------------------------------------------------------*/
- unsigned long sdr0_pfc1 = 0;
- unsigned long sdr0_usb0 = 0;
- unsigned long sdr0_mfr = 0;
-
- /* PCI Always selected */
-
- /* I2C Selection */
- if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
- iic1_selection_in_fpga();
- }
-
- /* SCP Selection */
- if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
- scp_selection_in_fpga();
- }
-
- /* UIC 0:3 Selection */
- if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
- {
- update_uic_0_3_irq_ios(gpio_tab);
- dma_a_b_unselect_in_fpga();
- }
-
- /* UIC 4:9 Selection */
- if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
- update_uic_4_9_irq_ios(gpio_tab);
- }
-
- /* DMA AB Selection */
- if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
- update_dma_a_b_ios(gpio_tab);
- dma_a_b_selection_in_fpga();
- }
-
- /* DMA CD Selection */
- if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
- {
- update_dma_c_d_ios(gpio_tab);
- dma_c_d_selection_in_fpga();
- }
-
- /* EBC Master Selection */
- if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
- update_ebc_master_ios(gpio_tab);
- }
-
- /* PCI Patch Enable */
- if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
- update_pci_patch_ios(gpio_tab);
- }
-
- /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
- if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
- {
- /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
- printf("Invalid configuration => USB2 Host selected\n");
- for (;;)
- ;
- /*usb2_host_selection_in_fpga(); */
- }
-
- /* USB2.0 Device Selection */
- if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
- {
- update_usb2_device_ios(gpio_tab);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
-
- mfsdr(SDR0_USB0, sdr0_usb0);
- sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
- sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
- mtsdr(SDR0_USB0, sdr0_usb0);
-
- usb2_device_selection_in_fpga();
- }
-
- /* USB1.1 Device Selection */
- if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
- {
- mfsdr(SDR0_USB0, sdr0_usb0);
- sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
- sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
- mtsdr(SDR0_USB0, sdr0_usb0);
- }
-
- /* USB1.1 Host Selection */
- if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
- {
- mfsdr(SDR0_USB0, sdr0_usb0);
- sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
- sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
- mtsdr(SDR0_USB0, sdr0_usb0);
- }
-
- /* NAND Flash Selection */
- if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
- {
- update_ndfc_ios(gpio_tab);
- mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- SDR0_CUST0_CHIPSELGAT_EN1 |
- SDR0_CUST0_CHIPSELGAT_EN2);
- ndfc_selection_in_fpga();
- }
- else
- {
- /* Set Mux on EMAC */
- mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
- }
-
- /* MII Selection */
- if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
- {
- update_zii_ios(gpio_tab);
- mfsdr(SDR0_MFR, sdr0_mfr);
- sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
- mtsdr(SDR0_MFR, sdr0_mfr);
-
- set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
- }
-
- /* RMII Selection */
- if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
- {
- update_zii_ios(gpio_tab);
- mfsdr(SDR0_MFR, sdr0_mfr);
- sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
- mtsdr(SDR0_MFR, sdr0_mfr);
-
- set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
- }
-
- /* SMII Selection */
- if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
- {
- update_zii_ios(gpio_tab);
- mfsdr(SDR0_MFR, sdr0_mfr);
- sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
- mtsdr(SDR0_MFR, sdr0_mfr);
-
- set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
- }
-
- /* UART Selection */
- uart_configuration = get_uart_configuration();
- switch (uart_configuration)
- {
- case L1: /* L1 Selection */
- /* UART0 8 pins Only */
- /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
- break;
- case L2: /* L2 Selection */
- /* UART0 and UART1 4 pins */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
- break;
- case L3: /* L3 Selection */
- /* UART0 4 pins, UART1 and UART2 2 pins */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
- break;
- case L4: /* L4 Selection */
- /* UART0, UART1, UART2 and UART3 2 pins */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
- break;
- }
- update_uart_ios(uart_configuration, gpio_tab);
-
- /* UART Selection in all cases */
- uart_selection_in_fpga(uart_configuration);
-
- /* Packet Reject Function Available */
- if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
- {
- /* Set UPR Bit in SDR0_PFC1 Register */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
- }
-
- /* Packet Reject Function Enable */
- if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
- {
- mfsdr(SDR0_MFR, sdr0_mfr);
- sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;
- mtsdr(SDR0_MFR, sdr0_mfr);
- }
-
- /* Perform effective access to hardware */
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- set_chip_gpio_configuration(GPIO0, gpio_tab);
- set_chip_gpio_configuration(GPIO1, gpio_tab);
-
- /* USB2.0 Device Reset must be done after GPIO setting */
- if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
- usb2_device_reset_through_fpga();
-
-}
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*----------------------------------------------------------------------------+
- | FPGA registers and bit definitions
- +----------------------------------------------------------------------------*/
-/*
- * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
- * TLB initialization makes it correspond to logical address 0x80001FF0.
- * => Done init_chip.s in bootlib
- */
-#define FPGA_BASE_ADDR 0x80002000
-
-/*----------------------------------------------------------------------------+
- | Board Jumpers Setting Register
- | Board Settings provided by jumpers
- +----------------------------------------------------------------------------*/
-#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
-/* Boot from small flash */
-#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
-/* Operational Flash versus SRAM position in Memory Map */
-#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
-#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
-#define FPGA_SET_REG_SRAM_ABOVE 0x00
-/* Boot From NAND Flash */
-#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
-#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
-/* On Board PCI Arbiter Select */
-#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
-#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
-
-/*----------------------------------------------------------------------------+
- | Functions Selection Register 1
- +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
-#define FPGA_SEL_1_REG_PHY_MASK 0xE0
-#define FPGA_SEL_1_REG_MII 0x80
-#define FPGA_SEL_1_REG_RMII 0x40
-#define FPGA_SEL_1_REG_SMII 0x20
-#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
-#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
-#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
-#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
-#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
-#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
-
-/*----------------------------------------------------------------------------+
- | Functions Selection Register 2
- +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
-#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
-#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
-#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
-#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
-#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
-#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
-#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
- /* 1 = TC - output from 440EP */
-#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
- /* 1 = TC (output from 440EP) */
-#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
-#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
-#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
-
-/*----------------------------------------------------------------------------+
- | Functions Selection Register 3
- +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
-#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
-#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
-#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
-#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
-#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
-#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
-#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
-#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
-
-/*----------------------------------------------------------------------------+
- | Soft Reset Register
- +----------------------------------------------------------------------------*/
-#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
-#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
-#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
-#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
-#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
-#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
-#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
-
-
-/*----------------------------------------------------------------------------+
-| SDR Configuration registers
-+----------------------------------------------------------------------------*/
-#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
-#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
-#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
-#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
-
-#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
-#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
-#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
-#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
-
-/* Serial Device Enabled - Addr = 0xA8 */
-#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
-/* Serial Device Enabled - Addr = 0xA4 */
-#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
-
-/* Pin Straps Reg */
-#define SDR0_PSTRP0 0x0040
-#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
-
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
-
-/*----------------------------------------------------------------------------+
-| EBC Configuration Register - EBC0_CFG
-+----------------------------------------------------------------------------*/
-/* External Bus Three-State Control */
-#define EBC0_CFG_EBTC_DRIVEN 0x80000000
-/* Device-Paced Time-out Disable */
-#define EBC0_CFG_PTD_ENABLED 0x00000000
-/* Ready Timeout Count */
-#define EBC0_CFG_RTC_MASK 0x38000000
-#define EBC0_CFG_RTC_16PERCLK 0x00000000
-#define EBC0_CFG_RTC_32PERCLK 0x08000000
-#define EBC0_CFG_RTC_64PERCLK 0x10000000
-#define EBC0_CFG_RTC_128PERCLK 0x18000000
-#define EBC0_CFG_RTC_256PERCLK 0x20000000
-#define EBC0_CFG_RTC_512PERCLK 0x28000000
-#define EBC0_CFG_RTC_1024PERCLK 0x30000000
-#define EBC0_CFG_RTC_2048PERCLK 0x38000000
-/* External Master Priority Low */
-#define EBC0_CFG_EMPL_LOW 0x00000000
-#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
-#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
-#define EBC0_CFG_EMPL_HIGH 0x06000000
-/* External Master Priority High */
-#define EBC0_CFG_EMPH_LOW 0x00000000
-#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
-#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
-#define EBC0_CFG_EMPH_HIGH 0x01800000
-/* Chip Select Three-State Control */
-#define EBC0_CFG_CSTC_DRIVEN 0x00400000
-/* Burst Prefetch */
-#define EBC0_CFG_BPF_ONEDW 0x00000000
-#define EBC0_CFG_BPF_TWODW 0x00100000
-#define EBC0_CFG_BPF_FOURDW 0x00200000
-/* External Master Size */
-#define EBC0_CFG_EMS_8BIT 0x00000000
-/* Power Management Enable */
-#define EBC0_CFG_PME_DISABLED 0x00000000
-#define EBC0_CFG_PME_ENABLED 0x00020000
-/* Power Management Timer */
-#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
-
-/*----------------------------------------------------------------------------+
-| Peripheral Bank Configuration Register - EBC0_BnCR
-+----------------------------------------------------------------------------*/
-/* BAS - Base Address Select */
-#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
-/* BS - Bank Size */
-#define EBC0_BNCR_BS_MASK 0x000E0000
-#define EBC0_BNCR_BS_1MB 0x00000000
-#define EBC0_BNCR_BS_2MB 0x00020000
-#define EBC0_BNCR_BS_4MB 0x00040000
-#define EBC0_BNCR_BS_8MB 0x00060000
-#define EBC0_BNCR_BS_16MB 0x00080000
-#define EBC0_BNCR_BS_32MB 0x000A0000
-#define EBC0_BNCR_BS_64MB 0x000C0000
-#define EBC0_BNCR_BS_128MB 0x000E0000
-/* BU - Bank Usage */
-#define EBC0_BNCR_BU_MASK 0x00018000
-#define EBC0_BNCR_BU_RO 0x00008000
-#define EBC0_BNCR_BU_WO 0x00010000
-#define EBC0_BNCR_BU_RW 0x00018000
-/* BW - Bus Width */
-#define EBC0_BNCR_BW_MASK 0x00006000
-#define EBC0_BNCR_BW_8BIT 0x00000000
-#define EBC0_BNCR_BW_16BIT 0x00002000
-#define EBC0_BNCR_BW_32BIT 0x00004000
-
-/*----------------------------------------------------------------------------+
-| Peripheral Bank Access Parameters - EBC0_BnAP
-+----------------------------------------------------------------------------*/
-/* Burst Mode Enable */
-#define EBC0_BNAP_BME_ENABLED 0x80000000
-#define EBC0_BNAP_BME_DISABLED 0x00000000
-/* Transfert Wait */
-#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
-/* Chip Select On Timing */
-#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
-/* Output Enable On Timing */
-#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
-/* Write Back Enable On Timing */
-#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
-/* Write Back Enable Off Timing */
-#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
-/* Transfert Hold */
-#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
-/* PerReady Enable */
-#define EBC0_BNAP_RE_ENABLED 0x00000100
-#define EBC0_BNAP_RE_DISABLED 0x00000000
-/* Sample On Ready */
-#define EBC0_BNAP_SOR_DELAYED 0x00000000
-#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
-/* Byte Enable Mode */
-#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
-#define EBC0_BNAP_BEM_RW 0x00000040
-/* Parity Enable */
-#define EBC0_BNAP_PEN_DISABLED 0x00000000
-#define EBC0_BNAP_PEN_ENABLED 0x00000020
-
-/*----------------------------------------------------------------------------+
-| Define Boot devices
-+----------------------------------------------------------------------------*/
-/* */
-#define BOOT_FROM_SMALL_FLASH 0x00
-#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
-#define BOOT_FROM_NAND_FLASH0 0x02
-#define BOOT_FROM_PCI 0x03
-#define BOOT_DEVICE_UNKNOWN 0x04
-
-
-#define PVR_POWERPC_440EP_PASS1 0x42221850
-#define PVR_POWERPC_440EP_PASS2 0x422218D3
-
-#define GPIO0 0
-#define GPIO1 1
-
-/*#define MAX_SELECTION_NB CORE_NB */
-#define MAX_CORE_SELECT_NB 22
-
-/*----------------------------------------------------------------------------+
- | PPC440EP GPIOs addresses.
- +----------------------------------------------------------------------------*/
-#define GPIO0_REAL 0xEF600B00
-
-#define GPIO1_REAL 0xEF600C00
-
-/* Offsets */
-#define GPIOx_OR 0x00 /* GPIO Output Register */
-#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
-#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
-#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
-#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
-#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
-#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
-#define GPIOx_IR 0x1C /* GPIO Input Register */
-#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
-#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
-#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
-#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
-#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
-#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
-#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
-#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
-#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
-
-/* GPIO0 */
-#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
-#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
-#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
-#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
-#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
-#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
-
-/* GPIO1 */
-#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
-#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
-#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
-#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
-#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
-#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
-
-#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
-#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
-#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
-#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
-#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
-
-
-/*----------------------------------------------------------------------------+
- | XX XX
- |
- | XXXXXX XXX XX XXX XXX
- | XX XX X XX XX XX
- | XX XX X XX XX XX
- | XX XX XX XX XX
- | XXXXXX XXX XXX XXXX XXXX
- +----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
- | Defines
- +----------------------------------------------------------------------------*/
-typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
- ZMII_CONFIGURATION_IS_MII,
- ZMII_CONFIGURATION_IS_RMII,
- ZMII_CONFIGURATION_IS_SMII
-} zmii_config_t;
-
-/*----------------------------------------------------------------------------+
- | Declare Configuration values
- +----------------------------------------------------------------------------*/
-typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
-typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
-typedef enum config_list { IIC_CORE,
- SCP_CORE,
- DMA_CHANNEL_AB,
- UIC_4_9,
- USB2_HOST,
- DMA_CHANNEL_CD,
- USB2_DEVICE,
- PACKET_REJ_FUNC_AVAIL,
- USB1_DEVICE,
- EBC_MASTER,
- NAND_FLASH,
- UART_CORE0,
- UART_CORE1,
- UART_CORE2,
- UART_CORE3,
- MII_SEL,
- RMII_SEL,
- SMII_SEL,
- PACKET_REJ_FUNC_EN,
- UIC_0_3,
- USB1_HOST,
- PCI_PATCH,
- CORE_NB
-} core_list_t;
-
-typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
- B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
- B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
- B3_V16, B3_VALUE_UNKNOWN
-} block3_value_t;
-
-typedef enum config_validity { CONFIG_IS_VALID,
- CONFIG_IS_INVALID
-} config_validity_t;
+++ /dev/null
-#
-# (C) Copyright 2002-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2004-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/ppc440.h>
-#include "bamboo.h"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*
- * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
- */
-static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
- {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
- {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
- {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */
- {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
- {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
- {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
- {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
- {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
- {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
-};
-
-/*
- * include common flash code (for amcc boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- unsigned long total_b = 0;
- unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
- unsigned short index = 0;
- int i;
- unsigned long val;
- unsigned long ebc_boot_size;
- unsigned long boot_selection;
-
- mfsdr(SDR0_PINSTP, val);
- index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
-
- if ((index == 5) || (index == 7)) {
- /*
- * Boot Settings in IIC EEprom address 0xA8 or 0xA4
- * Read Serial Device Strap Register1 in PPC440EP
- */
- mfsdr(SDR0_SDSTP1, val);
- boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
- ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
- switch(boot_selection) {
- case SDR0_SDSTP1_BOOT_SEL_EBC:
- switch(ebc_boot_size) {
- case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
- index = 3;
- break;
- case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
- index = 0;
- break;
- }
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_PCI:
- index = 1;
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_NDFC:
- index = 2;
- break;
- }
- } else if (index == 0) {
- if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
- index = 8; /* sram below op code flash -> new index 8 */
- }
- }
-
- DEBUGF("\n");
- DEBUGF("FLASH: Index: %d\n", index);
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
-
- /* check whether the address is 0 */
- if (flash_addr_table[index][i] == 0)
- continue;
-
- DEBUGF("Detection bank %d...\n", i);
- /* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
- &flash_info[i]);
- flash_info[i].size = size_b[i];
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i] << 20);
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
- }
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH)
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND)
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[i]);
-#endif
-#endif
-
- total_b += flash_info[i].size;
- }
-
- return total_b;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
-
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-
- /* PCI base & peripherals */
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
- tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
-
- /* PCI */
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
-
- /* USB 2.0 Device */
- tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
-
- tlbtab_end
+++ /dev/null
-if TARGET_BUBINGA
-
-config SYS_BOARD
- default "bubinga"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "bubinga"
-
-endif
+++ /dev/null
-BUBINGA BOARD
-#M: -
-S: Maintained
-F: board/amcc/bubinga/
-F: include/configs/bubinga.h
-F: configs/bubinga_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = bubinga.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-long int spd_sdram(void);
-
-int board_early_init_f(void)
-{
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000010);
- mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */
- mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * Configure CPC0_PCI to enable PerWE as output
- * and enable the internal PCI arbiter if selected
- */
- if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
- mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
- else
- mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN);
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-/* -------------------------------------------------------------------------
- dram_init() reads EEPROM via I2c. EEPROM contains all of
- the necessary info for SDRAM controller configuration
- ------------------------------------------------------------------------- */
-int dram_init(void)
-{
- gd->ram_size = spd_sdram();
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-/*
- * include common flash code (for amcc boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-unsigned long flash_init(void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 =
- flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- /* Only one bank */
- if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
- /* Setup offsets */
- flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- &flash_info[0]);
-#ifdef CONFIG_ENV_IS_IN_FLASH
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- size_b1 = 0;
- flash_info[0].size = size_b0;
- }
-
- /* 2 banks */
- else {
- size_b1 =
- flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
- &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
-
- if (size_b1) {
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b1 = -size_b1;
- pbcr = (pbcr & 0x0001ffff) | base_b1 |
- (((size_b1 / 1024 / 1024) - 1) << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
- /* printf("PB1CR = %x\n", pbcr); */
- }
-
- if (size_b0) {
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB1CR);
- base_b0 = base_b1 - size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 |
- (((size_b0 / 1024 / 1024) - 1) << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
- /* printf("PB0CR = %x\n", pbcr); */
- }
-
- size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
-
- flash_get_offsets(base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
- base_b0 + size_b0 - 1, &flash_info[0]);
- /* Also protect sector containing initial power-up instruction */
- /* (flash_protect() checks address range - other call ignored) */
- (void)flash_protect(FLAG_PROTECT_SET,
- 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
- (void)flash_protect(FLAG_PROTECT_SET,
- 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 =
- flash_get_size((vu_long *) base_b1, &flash_info[1]);
-
- flash_get_offsets(base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- base_b1 + size_b1 - CONFIG_SYS_MONITOR_LEN,
- base_b1 + size_b1 - 1,
- &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- (void)flash_protect(FLAG_PROTECT_CLEAR,
- base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
- base_b0 + size_b0 - 1,
- &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- } /* else 2 banks */
- return (size_b0 + size_b1);
-}
-
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-}
+++ /dev/null
-if TARGET_CANYONLANDS
-
-config SYS_BOARD
- default "canyonlands"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "canyonlands"
-
-choice BOARD_TYPE
- prompt "Select which board to build for"
- optional
-
-config CANYONLANDS
- bool "Glacier"
- help
- Select this to build for the Canyonlands 460EX board.
-
-config GLACIER
- bool "Glacier"
- help
- Select this to build for the Glacier 460GT board.
-
-config ARCHES
- bool "Arches"
- help
- Select this to build for the Arches dual 460GT board.
-
-endchoice
-
-endif
+++ /dev/null
-CANYONLANDS BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/amcc/canyonlands/
-F: include/configs/canyonlands.h
-F: configs/arches_defconfig
-F: configs/canyonlands_defconfig
-F: configs/glacier_defconfig
-F: configs/glacier_ramboot_defconfig
+++ /dev/null
-#
-# (C) Copyright 2008
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := canyonlands.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc440.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/4xx_pcie.h>
-#include <asm/ppc4xx-gpio.h>
-#include <linux/errno.h>
-#include <usb.h>
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct board_bcsr {
- u8 board_id;
- u8 cpld_rev;
- u8 led_user;
- u8 board_status;
- u8 reset_ctrl;
- u8 flash_ctrl;
- u8 eth_ctrl;
- u8 usb_ctrl;
- u8 irq_ctrl;
-};
-
-#define BOARD_CANYONLANDS_PCIE 1
-#define BOARD_CANYONLANDS_SATA 2
-#define BOARD_GLACIER 3
-#define BOARD_ARCHES 4
-
-/*
- * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-#if defined(CONFIG_ARCHES)
-u32 ddr_wrdtr(u32 default_val) {
- return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
-}
-#else
-u32 ddr_wrdtr(u32 default_val) {
- return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
-}
-
-u32 ddr_clktr(u32 default_val) {
- return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
-}
-#endif
-
-#if defined(CONFIG_ARCHES)
-/*
- * FPGA read/write helper macros
- */
-static inline int board_fpga_read(int offset)
-{
- return in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
-}
-
-static inline void board_fpga_write(int offset, int data)
-{
- out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
-}
-
-/*
- * CPLD read/write helper macros
- */
-static inline int board_cpld_read(int offset)
-{
- int data;
-
- out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
- data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
-
- return data;
-}
-
-static inline void board_cpld_write(int offset, int data)
-{
- out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
- out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
-}
-#else
-static int pvr_460ex(void)
-{
- u32 pvr = get_pvr();
-
- if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
- (pvr == PVR_460EX_RB))
- return 1;
-
- return 0;
-}
-#endif /* defined(CONFIG_ARCHES) */
-
-int board_early_init_f(void)
-{
-#if !defined(CONFIG_ARCHES)
- u32 sdr0_cust0;
- struct board_bcsr *bcsr_data =
- (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
-
-#endif
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC3SR, 0xffffffff); /* clear all */
- mtdcr(UIC3ER, 0x00000000); /* disable all */
- mtdcr(UIC3CR, 0x00000000); /* all non-critical */
- mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC3SR, 0xffffffff); /* clear all */
-
-#if !defined(CONFIG_ARCHES)
- /* SDR Setting - enable NDFC */
- mfsdr(SDR0_CUST0, sdr0_cust0);
- sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- SDR0_CUST0_NDFC_BAC_ENCODE(3) |
- (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
- mtsdr(SDR0_CUST0, sdr0_cust0);
-#endif
-
- /*
- * Configure PFC (Pin Function Control) registers
- * UART0: 4 pins
- */
- mtsdr(SDR0_PFC1, 0x00040000);
-
- /* Enable PCI host functionality in SDR0_PCI0 */
- mtsdr(SDR0_PCI0, 0xe0000000);
-
-#if !defined(CONFIG_ARCHES)
- /* Enable ethernet and take out of reset */
- out_8(&bcsr_data->eth_ctrl, 0) ;
-
- /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
- out_8(&bcsr_data->flash_ctrl, 0) ;
- mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
-
- /* Setup PLB4-AHB bridge based on the system address map */
- mtdcr(AHB_TOP, 0x8000004B);
- mtdcr(AHB_BOT, 0x8000004B);
-
-#endif
-
- return 0;
-}
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int board_usb_init(int index, enum usb_init_type init)
-{
- struct board_bcsr *bcsr_data =
- (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
- u8 val;
-
- /* Enable USB host & USB-OTG */
- val = in_8(&bcsr_data->usb_ctrl);
- val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
- out_8(&bcsr_data->usb_ctrl, val);
-
- /*
- * Configure USB-STP pins as alternate and not GPIO
- * It seems to be neccessary to configure the STP pins as GPIO
- * input at powerup (perhaps while USB reset is asserted). So
- * we configure those pins to their "real" function now.
- */
- gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
- gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-
- return 0;
-}
-
-int usb_board_stop(void)
-{
- struct board_bcsr *bcsr_data =
- (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
- u8 val;
-
- /* Disable USB host & USB-OTG */
- val = in_8(&bcsr_data->usb_ctrl);
- val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
- out_8(&bcsr_data->usb_ctrl, val);
-
- /* Reconfigure USB-STP pins as input */
- gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
- gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return usb_board_stop();
-}
-#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
-
-#if !defined(CONFIG_ARCHES)
-static void canyonlands_sata_init(int board_type)
-{
- u32 reg;
-
- if (board_type == BOARD_CANYONLANDS_SATA) {
- /* Put SATA in reset */
- SDR_WRITE(SDR0_SRST1, 0x00020001);
-
- /* Set the phy for SATA, not PCI-E port 0 */
- reg = SDR_READ(PESDR0_PHY_CTL_RST);
- SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
- reg = SDR_READ(PESDR0_L0CLK);
- SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
- SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
- SDR_WRITE(PESDR0_L0DRV, 0x00000104);
-
- /* Bring SATA out of reset */
- SDR_WRITE(SDR0_SRST1, 0x00000000);
- }
-}
-#endif /* !defined(CONFIG_ARCHES) */
-
-int get_cpu_num(void)
-{
- int cpu = NA_OR_UNKNOWN_CPU;
-
-#if defined(CONFIG_ARCHES)
- int cpu_num;
-
- cpu_num = board_fpga_read(0x3);
-
- /* sanity check; assume cpu numbering starts and increments from 0 */
- if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
- cpu = cpu_num;
-#endif
-
- return cpu;
-}
-
-#if !defined(CONFIG_ARCHES)
-int checkboard(void)
-{
- struct board_bcsr *bcsr_data =
- (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- if (pvr_460ex()) {
- printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
- if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
- gd->board_type = BOARD_CANYONLANDS_PCIE;
- else
- gd->board_type = BOARD_CANYONLANDS_SATA;
- } else {
- printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
- gd->board_type = BOARD_GLACIER;
- }
-
- switch (gd->board_type) {
- case BOARD_CANYONLANDS_PCIE:
- case BOARD_GLACIER:
- puts(", 2*PCIe");
- break;
-
- case BOARD_CANYONLANDS_SATA:
- puts(", 1*PCIe/1*SATA");
- break;
- }
-
- printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- canyonlands_sata_init(gd->board_type);
-
- return (0);
-}
-
-#else /* defined(CONFIG_ARCHES) */
-
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
- printf(" Revision %02x.%02x ",
- board_fpga_read(0x0), board_fpga_read(0x1));
-
- gd->board_type = BOARD_ARCHES;
-
- /* Only CPU0 has access to CPLD registers */
- if (get_cpu_num() == 0) {
- u8 cfg_sw = board_cpld_read(0x1);
- printf("(FPGA=%02x, CPLD=%02x)\n",
- board_fpga_read(0x2), board_cpld_read(0x0));
- printf(" Configuration Switch %d%d%d%d\n",
- ((cfg_sw >> 3) & 0x01),
- ((cfg_sw >> 2) & 0x01),
- ((cfg_sw >> 1) & 0x01),
- ((cfg_sw >> 0) & 0x01));
- } else
- printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
-
-
- if (s != NULL)
- printf(" Serial# %s\n", s);
-
- return 0;
-}
-#endif /* !defined(CONFIG_ARCHES) */
-
-#if defined(CONFIG_PCI)
-int board_pcie_first(void)
-{
- /*
- * Canyonlands with SATA enabled has only one PCIe slot
- * (2nd one).
- */
- if (gd->board_type == BOARD_CANYONLANDS_SATA)
- return 1;
-
- return 0;
-}
-#endif /* CONFIG_PCI */
-
-int board_early_init_r (void)
-{
- /*
- * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
- * boot EBC mapping only supports a maximum of 16MBytes
- * (4.ff00.0000 - 4.ffff.ffff).
- * To solve this problem, the FLASH has to get remapped to another
- * EBC address which accepts bigger regions:
- *
- * 0xfc00.0000 -> 4.cc00.0000
- */
-
- /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
- mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-
- /* Remove TLB entry of boot EBC mapping */
- remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
-
- /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
- program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
- TLB_WORD2_I_ENABLE);
-
- /*
- * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
- * 0xfc00.0000 is possible
- */
-
- /*
- * Clear potential errors resulting from auto-calibration.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- return 0;
-}
-
-#if !defined(CONFIG_ARCHES)
-int misc_init_r(void)
-{
- u32 sdr0_srst1 = 0;
- u32 eth_cfg;
- u8 val;
-
- /*
- * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
- * This is board specific, so let's do it here.
- */
- mfsdr(SDR0_ETH_CFG, eth_cfg);
- /* disable SGMII mode */
- eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
- SDR0_ETH_CFG_SGMII1_ENABLE |
- SDR0_ETH_CFG_SGMII0_ENABLE);
- /* Set the for 2 RGMII mode */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
- eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
- if (pvr_460ex())
- eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
- else
- eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
- mtsdr(SDR0_ETH_CFG, eth_cfg);
-
- /*
- * The AHB Bridge core is held in reset after power-on or reset
- * so enable it now
- */
- mfsdr(SDR0_SRST1, sdr0_srst1);
- sdr0_srst1 &= ~SDR0_SRST1_AHB;
- mtsdr(SDR0_SRST1, sdr0_srst1);
-
- /*
- * RTC/M41T62:
- * Disable square wave output: Batterie will be drained
- * quickly, when this output is not disabled
- */
- val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
- val &= ~0x40;
- i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
-
- return 0;
-}
-
-#else /* defined(CONFIG_ARCHES) */
-
-int misc_init_r(void)
-{
- u32 eth_cfg = 0;
- u32 eth_pll;
- u32 reg;
-
- /*
- * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
- * This is board specific, so let's do it here.
- */
-
- /* enable SGMII mode */
- eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
- SDR0_ETH_CFG_SGMII1_ENABLE |
- SDR0_ETH_CFG_SGMII2_ENABLE);
-
- /* Set EMAC for MDIO */
- eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
-
- /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
- eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
-
- mtsdr(SDR0_ETH_CFG, eth_cfg);
-
- /* reset all SGMII interfaces */
- mfsdr(SDR0_SRST1, reg);
- reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
- mtsdr(SDR0_SRST1, reg);
- mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
- mtsdr(SDR0_SRST1, 0x00000000);
-
- do {
- mfsdr(SDR0_ETH_PLL, eth_pll);
- } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
-
- return 0;
-}
-#endif /* !defined(CONFIG_ARCHES) */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-extern int __ft_board_setup(void *blob, bd_t *bd);
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- __ft_board_setup(blob, bd);
-
- if (gd->board_type == BOARD_CANYONLANDS_SATA) {
- /*
- * When SATA is selected we need to disable the first PCIe
- * node in the device tree, so that Linux doesn't initialize
- * it.
- */
- fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
- "disabled", sizeof("disabled"), 1);
- }
-
- if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
- /*
- * When PCIe is selected we need to disable the SATA
- * node in the device tree, so that Linux doesn't initialize
- * it.
- */
- fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
- "disabled", sizeof("disabled"), 1);
- }
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
+++ /dev/null
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
- {
- "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88",
- {
- 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
-#if !defined(CONFIG_ARCHES)
- {
- "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
- 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
- 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
- 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88",
- {
- 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
- 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
-#endif
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-#
-# (C) Copyright 2008-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 460EX/460GT Evaluation Board (Canyonlands) board
-#
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
- * use the speed up boot process. It is patched after relocation to
- * enable SA_I
- */
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-#endif
-
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
-
- /* PCIe UTL register */
- tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG)
-
-#if !defined(CONFIG_ARCHES)
- /* TLB-entry for NAND */
- tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
-
- /* TLB-entry for CPLD */
- tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
-#else
- /* TLB-entry for FPGA */
- tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG)
-#endif
-
- /* TLB-entry for OCM */
- tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I)
-
- /* TLB-entry for Local Configuration registers => peripherals */
- tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
-
- /* AHB: Internal USB Peripherals (USB, SATA) */
- tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG)
-
-#if defined(CONFIG_RAPIDIO)
- /* TLB-entries for RapidIO (SRIO) */
- tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
- 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
- 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
- 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000,
- 0x4, AC_RW | SA_IG)
-#endif
-
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- _image_copy_start = .;
- arch/powerpc/cpu/ppc4xx/start.o (.text*)
- board/amcc/canyonlands/init.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : {
- *(.data.init)
- . = ALIGN(256);
- LONG(0) LONG(0) /* Extend u-boot.bin to here */
- }
- __init_end = .;
- _end = .;
- _image_binary_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2004-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word_1(flash_info_t * info, ulong dest, ulong data);
-static int write_word_2(flash_info_t * info, ulong dest, ulong data);
-static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
-static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
-static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
-static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
-#endif
-
-void flash_print_info(flash_info_t * info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_STM:
- printf("STM ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- case FLASH_MAN_SST:
- printf("SST ");
- break;
- case FLASH_MAN_MX:
- printf ("MACRONIX ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AMD016:
- printf("AM29F016D (16 Mbit, uniform sector size)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AM033C:
- printf("AM29LV033C (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A:
- printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A:
- printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- case FLASH_STMW320DT:
- printf ("M29W320DT (32 M, top sector)\n");
- break;
- case FLASH_MXLV320T:
- printf ("MXLV320T (32 Mbit, top sector)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ", info->protect[i] ? "RO " : " ");
- }
- printf("\n");
- return;
-}
-
-
-/*
- * The following code cannot be run from FLASH!
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
- /* bit 0 used for big flash marking */
- if ((ulong)addr & 0x1) {
- return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
- } else {
- return flash_get_size_1(addr, info);
- }
-}
-
-static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
-#else
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-#endif
-{
- short i;
- CONFIG_SYS_FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
- DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
-
- /* Write auto select command: read Manufacturer ID */
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
- udelay(1000);
-
- value = addr2[0];
- DEBUGF("FLASH MANUFACT: %x\n", value);
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr2[1]; /* device ID */
- DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 KiB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 KiB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 KiB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
- info->flash_id += FLASH_AMD016;
- info->sector_count = 32;
- info->size = 0x00200000; /* => 2 MiB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
- info->flash_id += FLASH_AMDLV033C;
- info->sector_count = 64;
- info->size = 0x00400000; /* => 4 MiB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000; /* => 512 KiB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000; /* => 512 KiB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000; /* => 1 MiB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000; /* => 1 MiB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000; /* => 2 MiB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000; /* => 2 MiB */
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
- /* For AMD29033C flash we need to resend the command of *
- * reading flash protection for upper 8 Mb of flash */
- if (i == 32) {
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /* issue bank reset to return to read mode */
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
- return (info->size);
-}
-
-static int wait_for_DQ7_1(flash_info_t * info, int sect)
-{
- ulong start, now, last;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
- (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
- start = get_timer(0);
- last = start;
- while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
- (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
- return 0;
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
- return flash_erase_2(info, s_first, s_last);
- } else {
- return flash_erase_1(info, s_first, s_last);
- }
-}
-
-static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
-#else
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-#endif
-{
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("- missing\n");
- } else {
- printf("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
- for (i = 0; i < 50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7_1(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /* reset to read mode */
- addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-{
- if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
- return write_word_2(info, dest, data);
- } else {
- return write_word_1(info, dest, data);
- }
-}
-
-static int write_word_1(flash_info_t * info, ulong dest, ulong data)
-#else
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-#endif
-{
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-
-#undef CONFIG_SYS_FLASH_WORD_SIZE
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
-{
- short i;
- int n;
- CONFIG_SYS_FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
- DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
-
- /* Write auto select command: read Manufacturer ID */
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
- udelay(1000);
-
- value = addr2[0];
- DEBUGF("FLASH MANUFACT: %x\n", value);
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
- info->flash_id = FLASH_MAN_MX;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr2[1]; /* device ID */
-
- DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
- switch (value) {
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MiB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MiB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
- info->flash_id += FLASH_STMW320DT;
- info->sector_count = 67;
- info->size = 0x00400000; break; /* => 4 MiB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
- info->flash_id += FLASH_MXLV320T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
- /* set sector offsets for top boot block type */
- base += info->size;
- i = info->sector_count;
- /* 1 x 16k boot sector */
- base -= 16 << 10;
- --i;
- info->start[i] = base;
- /* 2 x 8k boot sectors */
- for (n=0; n<2; ++n) {
- base -= 8 << 10;
- --i;
- info->start[i] = base;
- }
- /* 1 x 32k boot sector */
- base -= 32 << 10;
- --i;
- info->start[i] = base;
-
- while (i > 0) { /* 64k regular sectors */
- base -= 64 << 10;
- --i;
- info->start[i] = base;
- }
- } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00002000;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000a000;
- info->start[i--] = base + info->size - 0x0000c000;
- info->start[i--] = base + info->size - 0x0000e000;
- info->start[i--] = base + info->size - 0x00010000;
-
- for (; i >= 0; i--)
- info->start[i] = base + i * 0x00010000;
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00002000;
- info->start[2] = base + 0x00004000;
- info->start[3] = base + 0x00006000;
- info->start[4] = base + 0x00008000;
- info->start[5] = base + 0x0000a000;
- info->start[6] = base + 0x0000c000;
- info->start[7] = base + 0x0000e000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] =
- base + ((i-7) * 0x00010000);
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00002000;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000a000;
- info->start[i--] = base + info->size - 0x0000c000;
- info->start[i--] = base + info->size - 0x0000e000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
- /* For AMD29033C flash we need to resend the command of *
- * reading flash protection for upper 8 Mb of flash */
- if (i == 32) {
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /* issue bank reset to return to read mode */
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
- return (info->size);
-}
-
-static int wait_for_DQ7_2(flash_info_t * info, int sect)
-{
- ulong start, now, last;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
- (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
- start = get_timer(0);
- last = start;
- while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
- (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
- return 0;
-}
-
-static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
-{
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("- missing\n");
- } else {
- printf("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
- for (i = 0; i < 50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7_2(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /* reset to read mode */
- addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-static int write_word_2(flash_info_t * info, ulong dest, ulong data)
-{
- ulong *data_ptr = &data;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
+++ /dev/null
-if TARGET_KATMAI
-
-config SYS_BOARD
- default "katmai"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "katmai"
-
-endif
+++ /dev/null
-KATMAI BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/amcc/katmai/
-F: include/configs/katmai.h
-F: configs/katmai_defconfig
+++ /dev/null
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := katmai.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
- {
- "400-133","CPU: 400 PLB: 133 OPB: 66 EBC: 66",
- { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
- },
- {
- "500-166","CPU: 500 PLB: 166 OPB: 83 EBC: 83",
- { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
- },
- {
- "533-133","CPU: 533 PLB: 133 OPB: 66 EBC: 66",
- { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
- },
- {
- "667-133","CPU: 667 PLB: 133 OPB: 66 EBC: 66",
- { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
- },
- {
- "667-166","CPU: 667 PLB: 166 OPB: 83 EBC: 83",
- { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
- },
- {
- "800-160","CPU: 800 PLB: 160 OPB: 53 EBC: 17",
- { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
- },
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# AMCC 440SPe Evaluation (Katmai) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
-
-/**************************************************************************
- * TLB table for revA
- *************************************************************************/
- .globl tlbtabA
-tlbtabA:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
- tlbtab_end
-
-/**************************************************************************
- * TLB table for revB
- *
- * Notice: revB of the 440SPe chip is very strict about PLB real addresses
- * and ranges to be mapped for config space: it seems to only work with
- * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
- * set otherwise) while revA uses c_nnnn_nnnn.
- *************************************************************************/
- .globl tlbtabB
-tlbtabB:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
-
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2007-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <i2c.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/4xx_pcie.h>
-#include <linux/errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f (void)
-{
- unsigned long mfr;
-
- /*----------------------------------------------------------------------+
- * Interrupt controller setup for the Katmai 440SPe Evaluation board.
- *-----------------------------------------------------------------------+
- *-----------------------------------------------------------------------+
- * Interrupt | Source | Pol. | Sensi.| Crit. |
- *-----------+-----------------------------------+-------+-------+-------+
- * IRQ 00 | UART0 | High | Level | Non |
- * IRQ 01 | UART1 | High | Level | Non |
- * IRQ 02 | IIC0 | High | Level | Non |
- * IRQ 03 | IIC1 | High | Level | Non |
- * IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
- * IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
- * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
- * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
- * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
- * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
- * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
- * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
- * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
- * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
- * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
- * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
- * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
- * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
- * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
- * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
- * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
- * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
- * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
- * IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
- * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
- * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
- * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
- * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
- * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
- * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
- * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
- * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
- *------------------------------------------------------------------------
- * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
- * IRQ 33 | MAL Serr | High | Level | Non |
- * IRQ 34 | MAL Txde | High | Level | Non |
- * IRQ 35 | MAL Rxde | High | Level | Non |
- * IRQ 36 | DMC CE or DMC UE | High | Level | Non |
- * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
- * IRQ 38 | MAL TX EOB | High | Level | Non |
- * IRQ 39 | MAL RX EOB | High | Level | Non |
- * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
- * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
- * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
- * IRQ 43 | L2 Cache | Risin | Edge | Non |
- * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
- * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
- * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
- * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
- * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
- * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
- * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
- * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
- * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
- * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
- * IRQ 54 | DMA Error | High | Level | Non |
- * IRQ 55 | DMA I2O Error | High | Level | Non |
- * IRQ 56 | Serial ROM | High | Level | Non |
- * IRQ 57 | PCIX0 Error | High | Edge | Non |
- * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
- * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
- * IRQ 60 | EMAC0 Interrupt | High | Level | Non |
- * IRQ 61 | EMAC0 Wake-up | High | Level | Non |
- * IRQ 62 | Reserved | High | Level | Non |
- * IRQ 63 | XOR | High | Level | Non |
- *-----------------------------------------------------------------------
- * IRQ 64 | PE0 AL | High | Level | Non |
- * IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
- * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
- * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
- * IRQ 68 | PE0 TCR | High | Level | Non |
- * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
- * IRQ 70 | PE0 DCR Error | High | Level | Non |
- * IRQ 71 | Reserved | N/A | N/A | Non |
- * IRQ 72 | PE1 AL | High | Level | Non |
- * IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
- * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
- * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
- * IRQ 76 | PE1 TCR | High | Level | Non |
- * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
- * IRQ 78 | PE1 DCR Error | High | Level | Non |
- * IRQ 79 | Reserved | N/A | N/A | Non |
- * IRQ 80 | PE2 AL | High | Level | Non |
- * IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
- * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
- * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
- * IRQ 84 | PE2 TCR | High | Level | Non |
- * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
- * IRQ 86 | PE2 DCR Error | High | Level | Non |
- * IRQ 87 | Reserved | N/A | N/A | Non |
- * IRQ 88 | External IRQ(5) | Progr | Progr | Non |
- * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
- * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
- * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
- * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
- * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
- * IRQ 94 | Reserved | N/A | N/A | Non |
- * IRQ 95 | Reserved | N/A | N/A | Non |
- *-----------------------------------------------------------------------
- * IRQ 96 | PE0 INTA | High | Level | Non |
- * IRQ 97 | PE0 INTB | High | Level | Non |
- * IRQ 98 | PE0 INTC | High | Level | Non |
- * IRQ 99 | PE0 INTD | High | Level | Non |
- * IRQ 100 | PE1 INTA | High | Level | Non |
- * IRQ 101 | PE1 INTB | High | Level | Non |
- * IRQ 102 | PE1 INTC | High | Level | Non |
- * IRQ 103 | PE1 INTD | High | Level | Non |
- * IRQ 104 | PE2 INTA | High | Level | Non |
- * IRQ 105 | PE2 INTB | High | Level | Non |
- * IRQ 106 | PE2 INTC | High | Level | Non |
- * IRQ 107 | PE2 INTD | Risin | Edge | Non |
- * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
- * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
- * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
- * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
- * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
- * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
- * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
- * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
- * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
- * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
- * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
- * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
- * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
- * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
- * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
- * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
- * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
- * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
- * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
- * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
- *-----------+-----------------------------------+-------+-------+-------+ */
- /*-------------------------------------------------------------------------+
- * Put UICs in PowerPC440SPemode.
- * Initialise UIC registers. Clear all interrupts. Disable all interrupts.
- * Set critical interrupt values. Set interrupt polarities. Set interrupt
- * trigger levels. Make bit 0 High priority. Clear all interrupts again.
- *------------------------------------------------------------------------*/
- mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
- mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */
- mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
- mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
- mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/
- mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/
-
-
- mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/
- mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
- mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
- mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
- mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/
- mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/
- mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
- mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
- mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/
- mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/
-
- mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */
- mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/
- mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
- mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
- mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/
- mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/
-
- mfsdr(SDR0_MFR, mfr);
- mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
- mtsdr(SDR0_MFR, mfr);
-
- mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
-
- out32(GPIO0_OR, CONFIG_SYS_GPIO_OR);
- out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
- out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
-
- return 0;
-}
-
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: Katmai - AMCC 440SPe Evaluation Board");
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-/*
- * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-u32 ddr_wrdtr(u32 default_val) {
- return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
-}
-
-u32 ddr_clktr(u32 default_val) {
- return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
-}
-
-#if defined(CONFIG_PCI)
-int board_pcie_card_present(int port)
-{
- u32 val;
-
- val = in32(GPIO0_IR);
- switch (port) {
- case 0:
- return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0));
- case 1:
- return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1));
- case 2:
- return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2));
- default:
- return 0;
- }
-}
-#endif /* defined(CONFIG_PCI) */
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis);
- return pci_eth_init(bis);
-}
+++ /dev/null
-if TARGET_KILAUEA
-
-config SYS_BOARD
- default "kilauea"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "kilauea"
-
-endif
+++ /dev/null
-KILAUEA BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/amcc/kilauea/
-F: include/configs/kilauea.h
-F: configs/haleakala_defconfig
-F: configs/kilauea_defconfig
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := kilauea.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
-
-struct ppc4xx_config ppc4xx_config_val[] = {
- {
- "333-nor","NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
- {
- 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
- {
- 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
- {
- 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
- {
- 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
- 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
- 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
- {
- 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-#
-# (C) Copyright 2007-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc405.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#include <asm/4xx_pcie.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static int board_cpld_version(void)
-{
- u32 cpld;
-
- cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
- if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
- /*
- * Magic not found -> "old" CPLD revision which needs
- * the "old" EBC configuration
- */
- mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
- EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
- EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
- EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
- EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
- EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
- EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
-
- /*
- * Return 0 for "old" CPLD version
- */
- return 0;
- }
-
- /*
- * Magic found -> "new" CPLD revision which needs no new
- * EBC configuration
- */
- return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
-}
-
-/*
- * Board early initialization function
- */
-int board_early_init_f (void)
-{
- u32 val;
-
- /*--------------------------------------------------------------------+
- | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
- +--------------------------------------------------------------------+
- +---------------------------------------------------------------------+
- |Interrupt| Source | Pol. | Sensi.| Crit. |
- +---------+-----------------------------------+-------+-------+-------+
- | IRQ 00 | UART0 | High | Level | Non |
- | IRQ 01 | UART1 | High | Level | Non |
- | IRQ 02 | IIC0 | High | Level | Non |
- | IRQ 03 | TBD | High | Level | Non |
- | IRQ 04 | TBD | High | Level | Non |
- | IRQ 05 | EBM | High | Level | Non |
- | IRQ 06 | BGI | High | Level | Non |
- | IRQ 07 | IIC1 | Rising| Edge | Non |
- | IRQ 08 | SPI | High | Lvl/ed| Non |
- | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
- | IRQ 10 | MAL TX EOB | High | Level | Non |
- | IRQ 11 | MAL RX EOB | High | Level | Non |
- | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
- | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
- | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
- | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
- | IRQ 16 | PCIE0 AL | high | Level | Non |
- | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
- | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
- | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
- | IRQ 20 | PCIE0 TCR | High | Level | Non |
- | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
- | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
- | IRQ 23 | Security EIP-94 | High | Level | Non |
- | IRQ 24 | EMAC0 interrupt | High | Level | Non |
- | IRQ 25 | EMAC1 interrupt | High | Level | Non |
- | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
- | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
- | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
- | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
- | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
- | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
- |----------------------------------------------------------------------
- | IRQ 32 | MAL Serr | High | Level | Non |
- | IRQ 33 | MAL Txde | High | Level | Non |
- | IRQ 34 | MAL Rxde | High | Level | Non |
- | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
- | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
- | IRQ 37 | EBC | High |Lvl Edg| Non |
- | IRQ 38 | NDFC | High | Level | Non |
- | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
- | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
- | IRQ 41 | PCIE1 AL | high | Level | Non |
- | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
- | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
- | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
- | IRQ 45 | PCIE1 TCR | High | Level | Non |
- | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
- | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
- | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
- | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
- | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
- | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
- | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
- | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
- | IRQ 55 | Serial ROM | High | Level | Non |
- | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
- | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
- | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
- |----------------------------------------------------------------------
- | IRQ 64 | PE0 AL | High | Level | Non |
- | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
- | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
- | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
- | IRQ 68 | PE0 TCR | High | Level | Non |
- | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
- | IRQ 70 | PE0 DCR Error | High | Level | Non |
- | IRQ 71 | Reserved | N/A | N/A | Non |
- | IRQ 72 | PE1 AL | High | Level | Non |
- | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
- | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
- | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
- | IRQ 76 | PE1 TCR | High | Level | Non |
- | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
- | IRQ 78 | PE1 DCR Error | High | Level | Non |
- | IRQ 79 | Reserved | N/A | N/A | Non |
- | IRQ 80 | PE2 AL | High | Level | Non |
- | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
- | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
- | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
- | IRQ 84 | PE2 TCR | High | Level | Non |
- | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
- | IRQ 86 | PE2 DCR Error | High | Level | Non |
- | IRQ 87 | Reserved | N/A | N/A | Non |
- | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
- | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
- | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
- | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
- | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
- | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
- | IRQ 94 | Reserved | N/A | N/A | Non |
- | IRQ 95 | Reserved | N/A | N/A | Non |
- |---------------------------------------------------------------------
- +---------+-----------------------------------+-------+-------+------*/
- /*--------------------------------------------------------------------+
- | Initialise UIC registers. Clear all interrupts. Disable all
- | interrupts.
- | Set critical interrupt values. Set interrupt polarities. Set
- | interrupt trigger levels. Make bit 0 High priority. Clear all
- | interrupts again.
- +-------------------------------------------------------------------*/
-
- mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
- mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
- mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
- mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
- mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
- mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
- mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
- /* Except cascade UIC0 and UIC1 */
- mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
- mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
- mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
-
- /*
- * Note: Some cores are still in reset when the chip starts, so
- * take them out of reset
- */
- mtsdr(SDR0_SRST, 0);
-
- /* Configure 405EX for NAND usage */
- val = SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NRB_BUSY |
- (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
- mtsdr(SDR0_CUST0, val);
-
- /*
- * Configure PFC (Pin Function Control) registers
- * -> Enable USB
- */
- val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
- mtsdr(SDR0_PFC1, val);
-
- /*
- * The CPLD version detection has to be the first access to
- * the CPLD, so we need to make this access this early and
- * save the CPLD version for later.
- */
- gd->board_type = board_cpld_version();
-
- /*
- * Configure FPGA register with PCIe reset
- */
- out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
- mdelay(50);
- out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
-
- return 0;
-}
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* Monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-#endif
-
- return 0;
-}
-
-static int is_405exr(void)
-{
- u32 pvr = get_pvr();
-
- if (pvr & 0x00000004)
- return 0; /* bit 2 set -> 405EX */
-
- return 1; /* bit 2 cleared -> 405EXr */
-}
-
-int board_emac_count(void)
-{
- /*
- * 405EXr only has one EMAC interface, 405EX has two
- */
- if (is_405exr())
- return 1;
- else
- return 2;
-}
-
-/*
- * Override the weak default implementation and return the
- * last PCIe slot number (max number - 1).
- */
-int board_pcie_last(void)
-{
- /*
- * 405EXr only has one EMAC interface, 405EX has two
- */
- if (is_405exr())
- return 1 - 1;
- else
- return 2 - 1;
-}
-
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- if (is_405exr())
- printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
- else
- printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- printf(" (CPLD rev. %ld)\n", gd->board_type);
-
- return (0);
-}
+++ /dev/null
-if TARGET_LUAN
-
-config SYS_BOARD
- default "luan"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "luan"
-
-endif
+++ /dev/null
-LUAN BOARD
-M: John Otken <jotken@softadvances.com>
-S: Maintained
-F: board/amcc/luan/
-F: include/configs/luan.h
-F: configs/luan_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = luan.o flash.o
-extra-y += init.o
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-#define EPLD0_FSEL_FB2 0x80
-#define EPLD0_BOOT_SMALL_FLASH 0x40 /* 0 boot from large flash, 1 from small flash */
-#define EPLD0_RAW_CARD_BIT0 0x20 /* raw card EC level */
-#define EPLD0_RAW_CARD_BIT1 0x10
-#define EPLD0_RAW_CARD_BIT2 0x08
-#define EPLD0_EXT_ARB_SEL_N 0x04 /* 0 select on-board ext PCI-X, 1 internal arbiter */
-#define EPLD0_FLASH_ONBRD_N 0x02 /* 0 small flash/SRAM active, 1 block access */
-#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */
-
-#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */
-#define EPLD1_PCIL0_CNTL1 0x40 /* S*0 of 9531 */
-#define EPLD1_PCIL0_CNTL2 0x20 /* S*1 of 9531 */
-#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */
-#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */
-#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */
-#define EPLD1_MASTER_CLOCK7 0x02 /* clock source select 7 */
-#define EPLD1_MASTER_CLOCK8 0x01 /* clock source select 8 */
-
-#define EPLD2_ETH_MODE_10 0x80 /* Ethernet mode 10 (default = 1) */
-#define EPLD2_ETH_MODE_100 0x40 /* Ethernet mode 100 (default = 1) */
-#define EPLD2_ETH_MODE_1000 0x20 /* Ethernet mode 1000 (default = 1) */
-#define EPLD2_ETH_DUPLEX_MODE 0x10 /* Ethernet force full duplex mode */
-#define EPLD2_RESET_ETH_N 0x08 /* Ethernet reset (default = 1) */
-#define EPLD2_ETH_AUTO_NEGO 0x04 /* Ethernet auto negotiation */
-#define EPLD2_DEFAULT_UART_N 0x01 /* 0 select DSR DTR for UART1 */
-
-#define EPLD3_STATUS_LED4 0x08 /* status LED 8 (1 = LED on) */
-#define EPLD3_STATUS_LED3 0x04 /* status LED 4 (1 = LED on) */
-#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */
-#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */
-
-#define EPLD4_PCIL0_VTH1 0x80 /* PCI-X 0 VTH1 status */
-#define EPLD4_PCIL0_VTH2 0x40 /* PCI-X 0 VTH2 status */
-#define EPLD4_PCIL0_VTH3 0x20 /* PCI-X 0 VTH3 status */
-#define EPLD4_PCIL0_VTH4 0x10 /* PCI-X 0 VTH4 status */
-#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */
-#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */
-#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */
-#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */
-
-#define EPLD5_PCIL0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
-#define EPLD5_PCIL0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
-#define EPLD5_PCIL0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
-#define EPLD5_PCIL0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
-#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */
-#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */
-#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */
-#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */
-
-#define EPLD6_PCIL0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
-#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */
-#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */
-#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */
-#define EPLD6_PCI1_CLKCNTL1 0x80 /* PCI1 clock control S*0 of 9531 */
-#define EPLD6_PCI1_CLKCNTL2 0x40 /* PCI1 clock control S*1 of 9531 */
-#define EPLD6_PCI2_CLKCNTL1 0x20 /* PCI2 clock control S*0 of 9531 */
-#define EPLD6_PCI2_CLKCNTL2 0x10 /* PCI2 clock control S*1 of 9531 */
-
-#define EPLD7_VTH1 0x80 /* PCI2 VTH1 status */
-#define EPLD7_VTH2 0x40 /* PCI2 VTH2 status */
-#define EPLD7_VTH3 0x20 /* PCI2 VTH3 status */
-#define EPLD7_VTH4 0x10 /* PCI2 VTH4 status */
-#define EPLD7_INTA_MODE 0x80 /* see S5 on SW2 for details */
-#define EPLD7_PCI_INT_MODE_N 0x40 /* see S1 on SW2 for details */
-#define EPLD7_WRITE_ENABLE_GPIO 0x20 /* see S2 on SW2 for details */
-#define EPLD7_WRITE_ENABLE_INT 0x10 /* see S3 on SW2 for details */
-
-
-typedef struct {
- unsigned char status; /* misc status */
- unsigned char clock; /* clock status, PCI-X clock control */
- unsigned char ethuart; /* Ethernet, UART status */
- unsigned char leds; /* LED register */
- unsigned char vth01; /* PCI0, PCI1 VTH register */
- unsigned char pciints; /* PCI0, PCI1 interrupts */
- unsigned char pci2; /* PCI2 interrupts, clock control */
- unsigned char vth2; /* PCI2 VTH register */
- unsigned char filler1[4096-8];
- unsigned char gpio00; /* GPIO bits 0-7 */
- unsigned char gpio08; /* GPIO bits 8-15 */
- unsigned char gpio16; /* GPIO bits 16-23 */
- unsigned char gpio24; /* GPIO bits 24-31 */
- unsigned char filler2[4096-4];
- unsigned char version; /* EPLD version */
-} epld_t;
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = {
- {0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */
-};
-
-/*
- * include common flash code (for amcc boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-
-unsigned long flash_init(void)
-{
- unsigned long total_b = 0;
- unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
- unsigned short index = 0;
- int i;
-
- /* read FPGA base register FPGA_REG0 */
-
- DEBUGF("\n");
- DEBUGF("FLASH: Index: %d\n", index);
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
-
- /* check whether the address is 0 */
- if (flash_addr_table[index][i] == 0) {
- continue;
- }
-
- /* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size((vu_long *)
- flash_addr_table[index][i],
- &flash_info[i]);
- flash_info[i].size = size_b[i];
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i] << 20);
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
- }
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- &flash_info[2]);
-#ifdef CONFIG_ENV_IS_IN_FLASH
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[2]);
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[2]);
-#endif
-
- total_b += flash_info[i].size;
- }
-
- return total_b;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
-
- tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
- tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
- tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
- tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
- tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
- /* internal ram (l2 cache) */
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
-
- /* peripherals at f0000000 */
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
-
- /* PCI */
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2005
- * John Otken, jotken@softadvances.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-isram.h>
-#include <spd_sdram.h>
-#include "epld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-
-/*************************************************************************
- * int board_early_init_f()
- *
- ************************************************************************/
-int board_early_init_f(void)
-{
- u32 mfr;
-
- mtebc( PB0AP, 0x03800000 ); /* set chip selects */
- mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
- mtebc( PB1AP, 0x03800000 );
- mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
- mtebc( PB2AP, 0x03800000 );
- mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
-
- mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */
- mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */
- mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */
- mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */
- mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */
- mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
- mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */
- mtdcr( UIC1SR, 0xffffffff );
-
- mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */
- mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */
- mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */
- mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */
- mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */
- mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
- mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */
- mtdcr( UIC0SR, 0xffffffff );
-
- mfsdr(SDR0_MFR, mfr);
- mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
- mtsdr(SDR0_MFR, mfr);
-
- return 0;
-}
-
-
-/*************************************************************************
- * int misc_init_r()
- *
- ************************************************************************/
-int misc_init_r(void)
-{
- volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
-
- /* set modes of operation */
- x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
- EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
- /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
- x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
-
- /* put Ethernet+PHY in reset */
- x->ethuart &= ~EPLD2_RESET_ETH_N;
- udelay(10000);
- /* take Ethernet+PHY out of reset */
- x->ethuart |= EPLD2_RESET_ETH_N;
-
- return 0;
-}
-
-
-/*************************************************************************
- * int checkboard()
- *
- ************************************************************************/
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: Luan - AMCC PPC440SP Evaluation Board");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-/*
- * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-u32 ddr_clktr(u32 default_val) {
- return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
-}
-
-/*************************************************************************
- * hw_watchdog_reset
- *
- * This routine is called to reset (keep alive) the watchdog timer
- *
- ************************************************************************/
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
-}
-#endif
-
-
-/*************************************************************************
- * int on_off()
- *
- ************************************************************************/
-static int on_off( const char *s )
-{
- if (strcmp(s, "on") == 0) {
- return 1;
- } else if (strcmp(s, "off") == 0) {
- return 0;
- }
- return -1;
-}
-
-
-/*************************************************************************
- * void l2cache_disable()
- *
- ************************************************************************/
-static void l2cache_disable(void)
-{
- mtdcr( L2_CACHE_CFG, 0 );
-}
-
-
-/*************************************************************************
- * void l2cache_enable()
- *
- ************************************************************************/
-static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
-{
- mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
-
- mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */
-
- mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
-
- while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ; /* poll L2_SR for completion */
-
- mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
-
- mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
-
- mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */
- mtdcr( L2_CACHE_SNP1, 0 );
-
- __asm__ volatile ("sync"); /* msync */
-
- mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */
-
- __asm__ volatile ("sync");
-}
-
-
-/*************************************************************************
- * int l2cache_status()
- *
- ************************************************************************/
-static int l2cache_status(void)
-{
- return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
-}
-
-
-/*************************************************************************
- * int do_l2cache()
- *
- ************************************************************************/
-int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
-{
- switch (argc) {
- case 2: /* on / off */
- switch (on_off(argv[1])) {
- case 0: l2cache_disable();
- break;
- case 1: l2cache_enable();
- break;
- }
- /* FALL TROUGH */
- case 1: /* get status */
- printf ("L2 Cache is %s\n",
- l2cache_status() ? "ON" : "OFF");
- return 0;
- default:
- return cmd_usage(cmdtp);
- }
-
- return 0;
-}
-
-
-U_BOOT_CMD(
- l2cache, 2, 1, do_l2cache,
- "enable or disable L2 cache",
- "[on, off]\n"
- " - enable or disable L2 cache"
-);
+++ /dev/null
-if TARGET_MAKALU
-
-config SYS_BOARD
- default "makalu"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "makalu"
-
-endif
+++ /dev/null
-MAKALU BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/amcc/makalu/
-F: include/configs/makalu.h
-F: configs/makalu_defconfig
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = makalu.o cmd_pll.o
-obj-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * ehnus: change pll frequency.
- * Wed Sep 5 11:45:17 CST 2007
- * hsun@udtech.com.cn
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <i2c.h>
-
-#ifdef CONFIG_CMD_EEPROM
-
-#define EEPROM_CONF_OFFSET 0
-#define EEPROM_TEST_OFFSET 16
-#define EEPROM_SDSTP_PARAM 16
-
-#define PLL_NAME_MAX 12
-#define BUF_STEP 8
-
-/* eeprom_wirtes 8Byte per op. */
-#define EEPROM_ALTER_FREQ(freq) \
- do { \
- int __i; \
- for (__i = 0; __i < 2; __i++) \
- eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \
- EEPROM_CONF_OFFSET + __i*BUF_STEP, \
- pll_select[freq], \
- BUF_STEP + __i*BUF_STEP); \
- } while (0)
-
-#define PDEBUG
-#ifdef PDEBUG
-#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET)
-#else
-#define PLL_DEBUG
-#endif
-
-typedef enum {
- PLL_ebc20,
- PLL_333,
- PLL_4001,
- PLL_4002,
- PLL_533,
- PLL_600,
- PLL_666, /* For now, kilauea can't support */
- RCONF,
- WTEST,
- PLL_TOTAL
-} pll_freq_t;
-
-static const char
-pll_name[][PLL_NAME_MAX] = {
- "PLL_ebc20",
- "PLL_333",
- "PLL_400@1",
- "PLL_400@2",
- "PLL_533",
- "PLL_600",
- "PLL_666",
- "RCONF",
- "WTEST",
- ""
-};
-
-/*
- * ehnus:
- */
-static uchar
-pll_select[][EEPROM_SDSTP_PARAM] = {
- /* 0: CPU 333MHz EBC 20MHz, for test only */
- {
- 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 0: 333 */
- {
- 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 1: 400_266 */
- {
- 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 2: 400 */
- {
- 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 3: 533 */
- {
- 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 4: 600 */
- {
- 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- /* 5: 666 */
- {
- 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- },
-
- {}
-};
-
-static uchar
-testbuf[EEPROM_SDSTP_PARAM] = {
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
-};
-
-static void
-pll_debug(int off)
-{
- int i;
- uchar buffer[EEPROM_SDSTP_PARAM];
-
- memset(buffer, 0, sizeof(buffer));
- eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
- buffer, EEPROM_SDSTP_PARAM);
-
- printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
- for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
- printf("%02x ", buffer[i]);
- printf("\n");
-}
-
-static void
-test_write(void)
-{
- printf("Debug: test eeprom_write ... ");
-
- /*
- * Write twice, 8 bytes per write
- */
- eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
- testbuf, 8);
- eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
- testbuf, 16);
- printf("done\n");
-
- pll_debug(EEPROM_TEST_OFFSET);
-}
-
-int
-do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char c = '\0';
- pll_freq_t pll_freq;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) {
- if (!strcmp(pll_name[pll_freq], argv[1]))
- break;
- }
-
- switch (pll_freq) {
- case PLL_ebc20:
- case PLL_333:
- case PLL_4001:
- case PLL_4002:
- case PLL_533:
- case PLL_600:
- EEPROM_ALTER_FREQ(pll_freq);
- break;
-
- case PLL_666: /* not support */
- printf("Choose this option will result in a boot failure."
- "\nContinue? (Y/N): ");
-
- c = getc(); putc('\n');
-
- if ((c == 'y') || (c == 'Y')) {
- EEPROM_ALTER_FREQ(pll_freq);
- break;
- }
- goto ret;
-
- case RCONF:
- pll_debug(EEPROM_CONF_OFFSET);
- goto ret;
- case WTEST:
- printf("DEBUG: write test\n");
- test_write();
- goto ret;
-
- default:
- printf("Invalid options\n\n");
- return cmd_usage(cmdtp);
- }
-
- printf("PLL set to %s, "
- "reset the board to take effect\n", pll_name[pll_freq]);
-
- PLL_DEBUG;
-ret:
- return 0;
-}
-
-U_BOOT_CMD(
- pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter,
- "change pll frequence",
- "pllalter <selection> - change pll frequence \n\n\
- ** New freq take effect after reset. ** \n\
- ----------------------------------------------\n\
- PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
- \t Same as PLL_333 \n\
- \t except \n\
- \t EBC: 20 MHz \n\
- ----------------------------------------------\n\
- PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 666 MHz \n\
- \t CPU: 333 MHz \n\
- \t PLB: 166 MHz \n\
- \t OPB: 83 MHz \n\
- \t DDR: 83 MHz \n\
- ------------------------------------------------\n\
- PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 800 MHz \n\
- \t CPU: 400 MHz \n\
- \t PLB: 133 MHz \n\
- \t OPB: 66 MHz \n\
- \t DDR: 133 MHz \n\
- ------------------------------------------------\n\
- PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 800 MHz \n\
- \t CPU: 400 MHz \n\
- \t PLB: 200 MHz \n\
- \t OPB: 100 MHz \n\
- \t DDR: 200 MHz \n\
- ----------------------------------------------\n\
- PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 1066 MHz \n\
- \t CPU: 533 MHz \n\
- \t PLB: 177 MHz \n\
- \t OPB: 88 MHz \n\
- \t DDR: 177 MHz \n\
- ----------------------------------------------\n\
- PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 1200 MHz \n\
- \t CPU: 600 MHz \n\
- \t PLB: 200 MHz \n\
- \t OPB: 100 MHz \n\
- \t DDR: 200 MHz \n\
- ----------------------------------------------\n\
- PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
- \t VCO: 1333 MHz \n\
- \t CPU: 666 MHz \n\
- \t PLB: 166 MHz \n\
- \t OPB: 83 MHz \n\
- \t DDR: 166 MHz \n\
- -----------------------------------------------\n\
- RCONF: Read current eeprom configuration. \n\
- -----------------------------------------------\n\
- WTEST: Test EEPROM write with predefined values\n\
- -----------------------------------------------"
-);
-
-#endif /* CONFIG_CMD_EEPROM */
+++ /dev/null
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- * Grant Erickson <gerickson@nuovations.com>
- *
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Originally based on code provided from Senao and AMCC
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- blr
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc405.h>
-#include <libfdt.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <linux/errno.h>
-
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#include <asm/4xx_pcie.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*
- * Board early initialization function
- */
-int board_early_init_f (void)
-{
- u32 val;
-
- /*--------------------------------------------------------------------+
- | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
- +--------------------------------------------------------------------+
- +---------------------------------------------------------------------+
- |Interrupt| Source | Pol. | Sensi.| Crit. |
- +---------+-----------------------------------+-------+-------+-------+
- | IRQ 00 | UART0 | High | Level | Non |
- | IRQ 01 | UART1 | High | Level | Non |
- | IRQ 02 | IIC0 | High | Level | Non |
- | IRQ 03 | TBD | High | Level | Non |
- | IRQ 04 | TBD | High | Level | Non |
- | IRQ 05 | EBM | High | Level | Non |
- | IRQ 06 | BGI | High | Level | Non |
- | IRQ 07 | IIC1 | Rising| Edge | Non |
- | IRQ 08 | SPI | High | Lvl/ed| Non |
- | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
- | IRQ 10 | MAL TX EOB | High | Level | Non |
- | IRQ 11 | MAL RX EOB | High | Level | Non |
- | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
- | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
- | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
- | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
- | IRQ 16 | PCIE0 AL | high | Level | Non |
- | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
- | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
- | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
- | IRQ 20 | PCIE0 TCR | High | Level | Non |
- | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
- | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
- | IRQ 23 | Security EIP-94 | High | Level | Non |
- | IRQ 24 | EMAC0 interrupt | High | Level | Non |
- | IRQ 25 | EMAC1 interrupt | High | Level | Non |
- | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
- | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
- | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
- | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
- | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
- | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
- |----------------------------------------------------------------------
- | IRQ 32 | MAL Serr | High | Level | Non |
- | IRQ 33 | MAL Txde | High | Level | Non |
- | IRQ 34 | MAL Rxde | High | Level | Non |
- | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
- | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
- | IRQ 37 | EBC | High |Lvl Edg| Non |
- | IRQ 38 | NDFC | High | Level | Non |
- | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
- | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
- | IRQ 41 | PCIE1 AL | high | Level | Non |
- | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
- | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
- | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
- | IRQ 45 | PCIE1 TCR | High | Level | Non |
- | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
- | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
- | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
- | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
- | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
- | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
- | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
- | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
- | IRQ 55 | Serial ROM | High | Level | Non |
- | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
- | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
- | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
- |----------------------------------------------------------------------
- | IRQ 64 | PE0 AL | High | Level | Non |
- | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
- | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
- | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
- | IRQ 68 | PE0 TCR | High | Level | Non |
- | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
- | IRQ 70 | PE0 DCR Error | High | Level | Non |
- | IRQ 71 | Reserved | N/A | N/A | Non |
- | IRQ 72 | PE1 AL | High | Level | Non |
- | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
- | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
- | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
- | IRQ 76 | PE1 TCR | High | Level | Non |
- | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
- | IRQ 78 | PE1 DCR Error | High | Level | Non |
- | IRQ 79 | Reserved | N/A | N/A | Non |
- | IRQ 80 | PE2 AL | High | Level | Non |
- | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
- | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
- | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
- | IRQ 84 | PE2 TCR | High | Level | Non |
- | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
- | IRQ 86 | PE2 DCR Error | High | Level | Non |
- | IRQ 87 | Reserved | N/A | N/A | Non |
- | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
- | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
- | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
- | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
- | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
- | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
- | IRQ 94 | Reserved | N/A | N/A | Non |
- | IRQ 95 | Reserved | N/A | N/A | Non |
- |---------------------------------------------------------------------
- +---------+-----------------------------------+-------+-------+------*/
- /*--------------------------------------------------------------------+
- | Initialise UIC registers. Clear all interrupts. Disable all
- | interrupts.
- | Set critical interrupt values. Set interrupt polarities. Set
- | interrupt trigger levels. Make bit 0 High priority. Clear all
- | interrupts again.
- +-------------------------------------------------------------------*/
-
- mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
- mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
- mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
- mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
- mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
- mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
- mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
- /* Except cascade UIC0 and UIC1 */
- mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
- mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
- mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
-
- /*
- * Note: Some cores are still in reset when the chip starts, so
- * take them out of reset
- */
- mtsdr(SDR0_SRST, 0);
-
- /* Reset PCIe slots */
- gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
- udelay(100);
- gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);
-
- /*
- * Configure PFC (Pin Function Control) registers
- * -> Enable USB
- */
- val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
- mtsdr(SDR0_PFC1, val);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* Monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-#endif
-
- return 0;
-}
-
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
+++ /dev/null
-if TARGET_REDWOOD
-
-config SYS_BOARD
- default "redwood"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "redwood"
-
-endif
+++ /dev/null
-REDWOOD BOARD
-M: Feng Kan <fkan@amcc.com>
-S: Maintained
-F: board/amcc/redwood/
-F: include/configs/redwood.h
-F: configs/redwood_defconfig
+++ /dev/null
-#
-# (C) Copyright 2008
-# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = redwood.o
-extra-y += init.o
+++ /dev/null
-#
-# (C) Copyright 2008
-# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# AMCC 460SX Reference Platform (redwood) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
- /* Although 512 KB, map 256k at a time */
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
- tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I)
-
- tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
-
- /*
- * Peripheral base
- */
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG)
- tlbtab_end
+++ /dev/null
-/*
- * This is the main board level file for the Redwood AMCC board.
- *
- * (C) Copyright 2008
- * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include "redwood.h"
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <asm/io.h>
-
-int compare_to_true(char *str);
-char *remove_l_w_space(char *in_str);
-char *remove_t_w_space(char *in_str);
-int get_console_port(void);
-
-static void early_init_EBC(void);
-static int bootdevice_selected(void);
-static void early_reinit_EBC(int);
-static void early_init_UIC(void);
-
-/*
- * Define Boot devices
- */
-#define BOOT_FROM_8BIT_SRAM 0x00
-#define BOOT_FROM_16BIT_SRAM 0x01
-#define BOOT_FROM_32BIT_SRAM 0x02
-#define BOOT_FROM_8BIT_NAND 0x03
-#define BOOT_FROM_16BIT_NOR 0x04
-#define BOOT_DEVICE_UNKNOWN 0xff
-
-/*
- * EBC Devices Characteristics
- * Peripheral Bank Access Parameters - EBC_BxAP
- * Peripheral Bank Configuration Register - EBC_BxCR
- */
-
-/*
- * 8 bit width SRAM
- * BU Value
- * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
- * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
- * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
- */
-#define EBC_BXAP_8BIT_SRAM \
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED
-
-#define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM
-#define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM
-
-/*
- * NAND flash
- * BU Value
- * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
- * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
- * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
-*/
-#define EBC_BXAP_NAND \
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED
-
-/*
- * NOR flash
- * BU Value
- * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
- * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
- * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
-*/
-#define EBC_BXAP_NOR \
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED
-
-/*
- * FPGA
- * BU value :
- * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
- * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
- */
-#define EBC_BXAP_FPGA \
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(11) | \
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1) | \
- EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | \
- EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_RW | \
- EBC_BXAP_PEN_DISABLED
-
-#define EBC_BXCR_8BIT_SRAM_CS0 \
- EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
-
-#define EBC_BXCR_32BIT_SRAM_CS0 \
- EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
-
-#define EBC_BXCR_NAND_CS0 \
- EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
-
-#define EBC_BXCR_16BIT_SRAM_CS0 \
- EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
-
-#define EBC_BXCR_NOR_CS0 \
- EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
-
-#define EBC_BXCR_NOR_CS1 \
- EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
-
-#define EBC_BXCR_NAND_CS1 \
- EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
-
-#define EBC_BXCR_NAND_CS2 \
- EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
-
-#define EBC_BXCR_SRAM_CS2 \
- EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
-
-#define EBC_BXCR_LARGE_FLASH_CS2 \
- EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
-
-#define EBC_BXCR_FPGA_CS3 \
- EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
-
-/*****************************************************************************
- * UBOOT initiated board specific function calls
- ****************************************************************************/
-
-int board_early_init_f(void)
-{
- int computed_boot_device = BOOT_DEVICE_UNKNOWN;
-
- /*
- * Initialise EBC
- */
- early_init_EBC();
-
- /*
- * Determine which boot device was selected
- */
- computed_boot_device = bootdevice_selected();
-
- /*
- * Reinit EBC based on selected boot device
- */
- early_reinit_EBC(computed_boot_device);
-
- /*
- * Setup for UIC on 460SX redwood board
- */
- early_init_UIC();
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: Redwood - AMCC 460SX Reference Board");
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-static void early_init_EBC(void)
-{
- /*
- * Initialize EBC CONFIG -
- * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
- * default value :
- * 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
- */
- mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
- EBC_CFG_PTD_ENABLE |
- EBC_CFG_RTC_16PERCLK |
- EBC_CFG_ATC_PREVIOUS |
- EBC_CFG_DTC_PREVIOUS |
- EBC_CFG_CTC_PREVIOUS |
- EBC_CFG_OEO_PREVIOUS |
- EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
-
- /*
- * PART 1 : Initialize EBC Bank 3
- * ==============================
- * Bank1 is always associated to the EPLD.
- * It has to be initialized prior to other banks settings computation
- * since some board registers values may be needed to determine the
- * boot type
- */
- mtebc(PB1AP, EBC_BXAP_FPGA);
- mtebc(PB1CR, EBC_BXCR_FPGA_CS3);
-
-}
-
-static int bootdevice_selected(void)
-{
- unsigned long sdr0_pinstp;
- unsigned long bootstrap_settings;
- int computed_boot_device = BOOT_DEVICE_UNKNOWN;
-
- /*
- * Determine which boot device was selected
- * =================================================
- *
- * Read Pin Strap Register in PPC460SX
- * Result can either be :
- * - Boot strap = boot from EBC 8bits => Small Flash
- * - Boot strap = boot from PCI
- * - Boot strap = IIC
- * In case of boot from IIC, read Serial Device Strap Register1
- *
- * Result can either be :
- * - Boot from EBC - EBC Bus Width = 8bits => Small Flash
- * - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
- * - Boot from PCI
- */
-
- /* Read Pin Strap Register in PPC460SX */
- mfsdr(SDR0_PINSTP, sdr0_pinstp);
- bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
-
- switch (bootstrap_settings) {
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
- /*
- * Boot from SRAM, 8bit width
- */
- computed_boot_device = BOOT_FROM_8BIT_SRAM;
- break;
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
- /*
- * Boot from SRAM, 32bit width
- */
- computed_boot_device = BOOT_FROM_32BIT_SRAM;
- break;
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
- /*
- * Boot from NAND, 8bit width
- */
- computed_boot_device = BOOT_FROM_8BIT_NAND;
- break;
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
- /*
- * Boot from SRAM, 16bit width
- * Boot setting in IIC EEPROM 0x50
- */
- computed_boot_device = BOOT_FROM_16BIT_SRAM;
- break;
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
- /*
- * Boot from NOR, 16bit width
- * Boot setting in IIC EEPROM 0x54
- */
- computed_boot_device = BOOT_FROM_16BIT_NOR;
- break;
- default:
- /* should not be */
- computed_boot_device = BOOT_DEVICE_UNKNOWN;
- break;
- }
-
- return computed_boot_device;
-}
-
-static void early_reinit_EBC(int computed_boot_device)
-{
- /*
- * Compute EBC settings depending on selected boot device
- * ======================================================
- *
- * Resulting EBC init will be among following configurations :
- *
- * - Boot from EBC 8bits => boot from Small Flash selected
- * EBC-CS0 = Small Flash
- * EBC-CS2 = Large Flash and SRAM
- *
- * - Boot from EBC 16bits => boot from Large Flash or SRAM
- * EBC-CS0 = Large Flash or SRAM
- * EBC-CS2 = Small Flash
- *
- * - Boot from PCI
- * EBC-CS0 = not initialized to avoid address contention
- * EBC-CS2 = same as boot from Small Flash selected
- */
-
- unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
- unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
- unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
-
- switch (computed_boot_device) {
- /*-------------------------------------------------------------------*/
- case BOOT_FROM_8BIT_SRAM:
- /*-------------------------------------------------------------------*/
- ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
- ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
- ebc0_cs1_bxap_value = EBC_BXAP_NOR;
- ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
- ebc0_cs2_bxap_value = EBC_BXAP_NAND;
- ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
- break;
-
- /*-------------------------------------------------------------------*/
- case BOOT_FROM_16BIT_SRAM:
- /*-------------------------------------------------------------------*/
- ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
- ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
- ebc0_cs1_bxap_value = EBC_BXAP_NOR;
- ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
- ebc0_cs2_bxap_value = EBC_BXAP_NAND;
- ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
- break;
-
- /*-------------------------------------------------------------------*/
- case BOOT_FROM_32BIT_SRAM:
- /*-------------------------------------------------------------------*/
- ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
- ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
- ebc0_cs1_bxap_value = EBC_BXAP_NOR;
- ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
- ebc0_cs2_bxap_value = EBC_BXAP_NAND;
- ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
- break;
-
- /*-------------------------------------------------------------------*/
- case BOOT_FROM_16BIT_NOR:
- /*-------------------------------------------------------------------*/
- ebc0_cs0_bxap_value = EBC_BXAP_NOR;
- ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
- ebc0_cs1_bxap_value = EBC_BXAP_NAND;
- ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
- ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
- ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
- break;
-
- /*-------------------------------------------------------------------*/
- case BOOT_FROM_8BIT_NAND:
- /*-------------------------------------------------------------------*/
- ebc0_cs0_bxap_value = EBC_BXAP_NAND;
- ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
- ebc0_cs1_bxap_value = EBC_BXAP_NOR;
- ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
- ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
- ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
- break;
-
- /*-------------------------------------------------------------------*/
- default:
- /*-------------------------------------------------------------------*/
- /* BOOT_DEVICE_UNKNOWN */
- break;
- }
-
- mtebc(PB0AP, ebc0_cs0_bxap_value);
- mtebc(PB0CR, ebc0_cs0_bxcr_value);
- mtebc(PB1AP, ebc0_cs1_bxap_value);
- mtebc(PB1CR, ebc0_cs1_bxcr_value);
- mtebc(PB2AP, ebc0_cs2_bxap_value);
- mtebc(PB2CR, ebc0_cs2_bxcr_value);
-}
-
-static void early_init_UIC(void)
-{
- /*
- * Initialise UIC registers. Clear all interrupts. Disable all
- * interrupts.
- * Set critical interrupt values. Set interrupt polarities. Set
- * interrupt trigger levels. Make bit 0 High priority. Clear all
- * interrupts again.
- */
- mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
- mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
- mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical
- * interrupts */
- mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
- mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
- mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
- mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical
- * interrupts */
- mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
- mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
- mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
- mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical
- * interrupts */
- mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
- mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted
- * cascade to be checked */
- mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical
- * interrupts */
- mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
-
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __REDWOOD_H_
-#define __REDWOOD_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*----------------------------------------------------------------------------+
-| Defines
-+----------------------------------------------------------------------------*/
-/* Pin Straps Reg */
-#define SDR0_PSTRP0 0x0040
-#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
-
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __REDWOOD_H_ */
+++ /dev/null
-if TARGET_SEQUOIA
-
-config SYS_BOARD
- default "sequoia"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "sequoia"
-
-endif
+++ /dev/null
-SEQUOIA BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/amcc/sequoia/
-F: include/configs/sequoia.h
-F: configs/rainier_defconfig
-F: configs/rainier_ramboot_defconfig
-F: configs/sequoia_defconfig
-F: configs/sequoia_ramboot_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = sequoia.o sdram.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
- {
- "333-133-nor", "NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66",
- {
- 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "333-166-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55",
- {
- 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "333-166-nand", "NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55",
- {
- 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30,
- 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
- {
- 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "400-160-nor", "NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53",
- {
- 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "416-166-nor", "NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55",
- {
- 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "416-166-nand", "NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55",
- {
- 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10,
- 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "500-166-nor", "NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55",
- {
- 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "500-166-nand", "NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55",
- {
- 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30,
- 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "533-133-nor", "NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66",
- {
- 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "667-133-nor", "NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66",
- {
- 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "667-166-nor", "NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55",
- {
- 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "667-166-nand", "NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55",
- {
- 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30,
- 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-#
-# (C) Copyright 2002-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 440EPx Reference Platform (Sequoia) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- */
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /* vxWorks needs this as first entry for the Machine Check interrupt */
- tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
-
- /*
- * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
- * entry is already configured for SDRAM via the JTAG debugger and mustn't
- * be re-initialized by this RAM-booting U-Boot version.
- */
-#ifndef CONFIG_SYS_RAMBOOT
- /* TLB-entry for DDR SDRAM (Up to 2GB) */
-#ifdef CONFIG_4xx_DCACHE
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G)
-#else
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
-#endif
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /* TLB-entry for EBC */
- tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG )
-
- /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
-#endif
-
- /* TLB-entry for PCI Memory */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
-
- /* TLB-entry for NAND */
- tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for Internal Registers & OCM */
- tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
-
- /*TLB-entry PCI registers*/
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
- /* TLB-entry PCI IO Space - from sr@denx.de */
- tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
-
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debug output */
-#undef DEBUG
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc440.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*-----------------------------------------------------------------------------+
- * Prototypes
- *-----------------------------------------------------------------------------*/
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-
-/*************************************************************************
- *
- * dram_init -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-int dram_init(void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
- ulong speed = get_bus_freq(0);
-
- mtsdram(DDR0_02, 0x00000000);
-
- mtsdram(DDR0_00, 0x0000190A);
- mtsdram(DDR0_01, 0x01000000);
- mtsdram(DDR0_03, 0x02030602);
- mtsdram(DDR0_04, 0x0A020200);
- mtsdram(DDR0_05, 0x02020308);
- mtsdram(DDR0_06, 0x0102C812);
- mtsdram(DDR0_07, 0x000D0100);
- mtsdram(DDR0_08, 0x02430001);
- mtsdram(DDR0_09, 0x00011D5F);
- mtsdram(DDR0_10, 0x00000100);
- mtsdram(DDR0_11, 0x0027C800);
- mtsdram(DDR0_12, 0x00000003);
- mtsdram(DDR0_14, 0x00000000);
- mtsdram(DDR0_17, 0x19000000);
- mtsdram(DDR0_18, 0x19191919);
- mtsdram(DDR0_19, 0x19191919);
- mtsdram(DDR0_20, 0x0B0B0B0B);
- mtsdram(DDR0_21, 0x0B0B0B0B);
- mtsdram(DDR0_22, 0x00267F0B);
- mtsdram(DDR0_23, 0x00000000);
- mtsdram(DDR0_24, 0x01010002);
- if (speed > 133333334)
- mtsdram(DDR0_26, 0x5B26050C);
- else
- mtsdram(DDR0_26, 0x5B260408);
- mtsdram(DDR0_27, 0x0000682B);
- mtsdram(DDR0_28, 0x00000000);
- mtsdram(DDR0_31, 0x00000000);
- mtsdram(DDR0_42, 0x01000006);
- mtsdram(DDR0_43, 0x030A0200);
- mtsdram(DDR0_44, 0x00000003);
- mtsdram(DDR0_02, 0x00000001);
-
- denali_wait_for_dlllock();
-#endif /* #ifndef CONFIG_SYS_RAMBOOT */
-
-#ifdef CONFIG_DDR_DATA_EYE
- /* -----------------------------------------------------------+
- * Perform data eye search if requested.
- * ----------------------------------------------------------*/
- denali_core_search_data_eye();
-#endif
-
- /*
- * Clear possible errors resulting from data-eye-search.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2006-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/bitops.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_MTD_NOR_FLASH)
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-#endif
-
-extern void __ft_board_setup(void *blob, bd_t *bd);
-ulong flash_get_size(ulong base, int banknum);
-
-static inline u32 get_async_pci_freq(void)
-{
- if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
- CONFIG_SYS_BCSR5_PCI66EN)
- return 66666666;
- else
- return 33333333;
-}
-
-int board_early_init_f(void)
-{
- u32 sdr0_cust0;
- u32 sdr0_pfc1, sdr0_pfc2;
- u32 reg;
-
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, 0xb8400000);
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- /* Check and reconfigure the PCI sync clock if necessary */
- ppc4xx_pci_sync_clock_config(get_async_pci_freq());
-
- /* 50MHz tmrclk */
- out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
-
- /* clear write protects */
- out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
-
- /* enable Ethernet */
- out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
-
- /* enable USB device */
- out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
-
- /* select Ethernet (and optionally IIC1) pins */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_4;
-#ifdef CONFIG_I2C_MULTI_BUS
- sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
-#endif
- /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
-
- mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_4;
- mtsdr(SDR0_PFC2, sdr0_pfc2);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* PCI arbiter enabled */
- mfsdr(SDR0_PCI0, reg);
- mtsdr(SDR0_PCI0, 0x80000000 | reg);
-
- /* setup NAND FLASH */
- mfsdr(SDR0_CUST0, sdr0_cust0);
- sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
- mtsdr(SDR0_CUST0, sdr0_cust0);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
-#if defined(CONFIG_MTD_NOR_FLASH)
- uint pbcr;
- int size_val = 0;
-#endif
-#ifdef CONFIG_440EPX
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1;
- char *act = getenv("usbact");
-#endif
- u32 reg;
-
-#if defined(CONFIG_MTD_NOR_FLASH)
- /* Re-do flash sizing to get full correct info */
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
-#if defined(CONFIG_SYS_RAMBOOT)
- mtdcr(EBC0_CFGADDR, PB3CR);
-#else
- mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
- pbcr = mfdcr(EBC0_CFGDATA);
- size_val = ffs(gd->bd->bi_flashsize) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_SYS_RAMBOOT)
- mtdcr(EBC0_CFGADDR, PB3CR);
-#else
- mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- /* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-#endif /* CONFIG_MTD_NOR_FLASH */
-
- /*
- * USB suff...
- */
-#ifdef CONFIG_440EPX
- if (act == NULL || strcmp(act, "hostdev") == 0) {
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-
- /*
- * An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
-
- /*
- * To enable the USB 2.0 Device function
- * through the UTMI interface
- */
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /*clear resets*/
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay (1000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Host(int phy) Device(ext phy)\n");
-
- } else if (strcmp(act, "dev") == 0) {
- /*-------------------PATCH-------------------------------*/
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x672c6000);
-
- udelay (1000);
- mtsdr(SDR0_SRST0, 0x00000080);
-
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x60206000);
-
- *(unsigned int *)(0xe0000350) = 0x00000001;
-
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x60306000);
- /*-------------------PATCH-------------------------------*/
-
- /* SDR Setting */
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_PFC1, sdr0_pfc1);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
-
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
-
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
-
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* clear resets */
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay (1000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Device(int phy)\n");
- }
-#endif /* CONFIG_440EPX */
-
- mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
- reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
- mtsdr(SDR0_SRST1, reg);
-
- /*
- * Clear PLB4A0_ACR[WRP]
- * This fix will make the MAL burst disabling patch for the Linux
- * EMAC driver obsolete.
- */
- reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
- mtdcr(PLB4A0_ACR, reg);
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
- u8 rev;
- u32 clock = get_async_pci_freq();
-
-#ifdef CONFIG_440EPX
- printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
-#else
- printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
-#endif
-
- rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
- printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- /*
- * Reconfiguration of the PCI sync clock is already done,
- * now check again if everything is in range:
- */
- if (ppc4xx_pci_sync_clock_config(clock)) {
- printf("ERROR: PCI clocking incorrect (async=%d "
- "sync=%ld)!\n", clock, get_PCI_freq());
- }
-
- return (0);
-}
-
-#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
-/*
- * Assign interrupts to PCI devices.
- */
-void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
-}
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-/*
- * On NAND-booting sequoia, we need to patch the chips select numbers
- * in the dtb (CS0 - NAND, CS3 - NOR)
- */
-int ft_board_setup(void *blob, bd_t *bd)
-{
- int rc;
- int len;
- int nodeoffset;
- struct fdt_property *prop;
- u32 *reg;
- char path[32];
-
- /* First do common fdt setup */
- __ft_board_setup(blob, bd);
-
- /* And now configure NOR chip select to 3 instead of 0 */
- strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
- nodeoffset = fdt_path_offset(blob, path);
- prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
- if (prop == NULL) {
- printf("Unable to update NOR chip select for NAND booting\n");
- return -FDT_ERR_NOTFOUND;
- }
- reg = (u32 *)&prop->data[0];
- reg[0] = 3;
- rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
- if (rc) {
- printf("Unable to update property NOR mappings\n");
- return rc;
- }
-
- /* And now configure NAND chip select to 0 instead of 3 */
- strcpy(path, "/plb/opb/ebc/ndfc@3,0");
- nodeoffset = fdt_path_offset(blob, path);
- prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
- if (prop == NULL) {
- printf("Unable to update NDFC chip select for NAND booting\n");
- return len;
- }
- reg = (u32 *)&prop->data[0];
- reg[0] = 0;
- rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
- if (rc) {
- printf("Unable to update property NDFC mapping\n");
- return rc;
- }
-
- return 0;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/ppc4xx/start.o (.text*)
- board/amcc/sequoia/init.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-if TARGET_WALNUT
-
-config SYS_BOARD
- default "walnut"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "walnut"
-
-endif
+++ /dev/null
-WALNUT BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/amcc/walnut/
-F: include/configs/walnut.h
-F: configs/sycamore_defconfig
-F: configs/walnut_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = walnut.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-/*
- * include common flash code (for amcc boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-unsigned long flash_init(void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 =
- flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- /* Only one bank */
- if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
- /* Setup offsets */
- flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- &flash_info[0]);
-#ifdef CONFIG_ENV_IS_IN_FLASH
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- size_b1 = 0;
- flash_info[0].size = size_b0;
- } else {
- /* 2 banks */
- size_b1 =
- flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
- &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
-
- if (size_b1) {
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b1 = -size_b1;
- pbcr =
- (pbcr & 0x0001ffff) | base_b1 |
- (((size_b1 / 1024 / 1024) - 1) << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
- /* printf("PB1CR = %x\n", pbcr); */
- }
-
- if (size_b0) {
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB1CR);
- base_b0 = base_b1 - size_b0;
- pbcr =
- (pbcr & 0x0001ffff) | base_b0 |
- (((size_b0 / 1024 / 1024) - 1) << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
- /* printf("PB0CR = %x\n", pbcr); */
- }
-
- size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
-
- flash_get_offsets(base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- base_b0 + size_b0 - monitor_flash_len,
- base_b0 + size_b0 - 1, &flash_info[0]);
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 =
- flash_get_size((vu_long *) base_b1, &flash_info[1]);
-
- flash_get_offsets(base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- base_b1 + size_b1 -
- monitor_flash_len,
- base_b1 + size_b1 - 1,
- &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- (void)flash_protect(FLAG_PROTECT_CLEAR,
- base_b0 + size_b0 -
- monitor_flash_len,
- base_b0 + size_b0 - 1,
- &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- } /* else 2 banks */
- return (size_b0 + size_b1);
-}
-
-
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <spd_sdram.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the Walnut/Sycamore board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
- | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
- | IRQ 27 (EXT IRQ 2) Not Used
- | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
- | Note for Walnut board:
- | An interrupt taken for the FPGA (IRQ 25) indicates that either
- | the Mouse, Keyboard, IRDA, or External Expansion caused the
- | interrupt. The FPGA must be read to determine which device
- | caused the interrupt. The default setting of the FPGA clears
- |
- +-------------------------------------------------------------------------*/
-
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
- mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /* set UART1 control to select CTS/RTS */
-#define FPGA_BRDC 0xF0300004
- *(volatile char *)(FPGA_BRDC) |= 0x1;
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
- uint pvr = get_pvr();
-
- if (pvr == PVR_405GPR_RB) {
- puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
- } else {
- puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
- }
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-/*
- * dram_init() reads EEPROM via I2c. EEPROM contains all of
- * the necessary info for SDRAM controller configuration
- */
-int dram_init(void)
-{
- gd->ram_size = spd_sdram();
-
- return 0;
-}
+++ /dev/null
-if TARGET_YOSEMITE
-
-config SYS_BOARD
- default "yosemite"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "yosemite"
-
-endif
+++ /dev/null
-YOSEMITE BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/amcc/yosemite/
-F: include/configs/yosemite.h
-F: configs/yellowstone_defconfig
-F: configs/yosemite_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = yosemite.o
-extra-y += init.o
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
-
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
-
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I )
-
- /* PCI */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
-
- /* USB 2.0 Device */
- tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
-
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static inline u32 get_async_pci_freq(void)
-{
- if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
- CONFIG_SYS_BCSR5_PCI66EN)
- return 66666666;
- else
- return 33333333;
-}
-
-int board_early_init_f(void)
-{
- register uint reg;
-
- /*--------------------------------------------------------------------
- * Setup the external bus controller/chip selects
- *-------------------------------------------------------------------*/
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- reg = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
-
- /*--------------------------------------------------------------------
- * Setup the GPIO pins
- *-------------------------------------------------------------------*/
- /*CPLD cs */
- /*setup Address lines for flash size 64Meg. */
- out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
-
- /*setup emac */
- out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
- out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
- out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
-
- /*UART1 */
- out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
- out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
- out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
-
- /* external interrupts IRQ0...3 */
- out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
- out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
- out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
-
-#ifdef CONFIG_440EP
- /*setup USB 2.0 */
- out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
- out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
- out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
- out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
- out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
-#endif
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
- mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- /*--------------------------------------------------------------------
- * Setup other serial configuration
- *-------------------------------------------------------------------*/
- mfsdr(SDR0_PCI0, reg);
- mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
- mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
- mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
-
- /* Check and reconfigure the PCI sync clock if necessary */
- ppc4xx_pci_sync_clock_config(get_async_pci_freq());
-
- /*clear tmrclk divisor */
- *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
-
- /*enable ethernet */
- *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
-
-#ifdef CONFIG_440EP
- /*enable usb 1.1 fs device and remove usb 2.0 reset */
- *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
-#endif
-
- /*get rid of flash write protect */
- *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- uint pbcr;
- int size_val = 0;
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- switch (gd->bd->bi_flashsize) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- case 32 << 20:
- size_val = 5;
- break;
- case 64 << 20:
- size_val = 6;
- break;
- case 128 << 20:
- size_val = 7;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
- u8 rev;
- u32 clock = get_async_pci_freq();
-
-#ifdef CONFIG_440EP
- printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
-#else
- printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
-#endif
-
- rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
- printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- /*
- * Reconfiguration of the PCI sync clock is already done,
- * now check again if everything is in range:
- */
- if (ppc4xx_pci_sync_clock_config(clock)) {
- printf("ERROR: PCI clocking incorrect (async=%d "
- "sync=%ld)!\n", clock, get_PCI_freq());
- }
-
- return (0);
-}
-
-/*************************************************************************
- * dram_init -- doesn't use serial presence detect.
- *
- * Assumes: 256 MB, ECC, non-registered
- * PLB @ 133 MHz
- *
- ************************************************************************/
-#define NUM_TRIES 64
-#define NUM_READS 10
-
-void sdram_tr1_set(int ram_address, int* tr1_value)
-{
- int i;
- int j, k;
- volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
- int first_good = -1, last_bad = 0x1ff;
-
- unsigned long test[NUM_TRIES] = {
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
- 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
-
- /* go through all possible SDRAM0_TR1[RDCT] values */
- for (i=0; i<=0x1ff; i++) {
- /* set the current value for TR1 */
- mtsdram(SDRAM0_TR1, (0x80800800 | i));
-
- /* write values */
- for (j=0; j<NUM_TRIES; j++) {
- ram_pointer[j] = test[j];
-
- /* clear any cache at ram location */
- __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
- }
-
- /* read values back */
- for (j=0; j<NUM_TRIES; j++) {
- for (k=0; k<NUM_READS; k++) {
- /* clear any cache at ram location */
- __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-
- if (ram_pointer[j] != test[j])
- break;
- }
-
- /* read error */
- if (k != NUM_READS) {
- break;
- }
- }
-
- /* we have a SDRAM0_TR1[RDCT] that is part of the window */
- if (j == NUM_TRIES) {
- if (first_good == -1)
- first_good = i; /* found beginning of window */
- } else { /* bad read */
- /* if we have not had a good read then don't care */
- if(first_good != -1) {
- /* first failure after a good read */
- last_bad = i-1;
- break;
- }
- }
- }
-
- /* return the current value for TR1 */
- *tr1_value = (first_good + last_bad) / 2;
-}
-
-int dram_init(void)
-{
- register uint reg;
- int tr1_bank1, tr1_bank2;
-
- /*--------------------------------------------------------------------
- * Setup some default
- *------------------------------------------------------------------*/
- mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
- mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */
- mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */
-
- /*clear this first, if the DDR is enabled by a debugger
- then you can not make changes. */
- mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */
-
- /*--------------------------------------------------------------------
- * Setup for board-specific specific mem
- *------------------------------------------------------------------*/
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
-
- mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */
- mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */
- mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
- mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */
- udelay(400); /* Delay 200 usecs (min) */
-
- /*--------------------------------------------------------------------
- * Enable the controller, then wait for DCEN to complete
- *------------------------------------------------------------------*/
- mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */
-
- for (;;) {
- mfsdram(SDRAM0_MCSTS, reg);
- if (reg & 0x80000000)
- break;
- }
-
- sdram_tr1_set(0x00000000, &tr1_bank1);
- sdram_tr1_set(0x08000000, &tr1_bank2);
- mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
-
- gd->ram_size = CONFIG_SYS_SDRAM_BANKS *
- (CONFIG_SYS_KBYTES_SDRAM * 1024); /* set bytes */
-
- return 0;
-}
-
-/*************************************************************************
- * hw_watchdog_reset
- *
- * This routine is called to reset (keep alive) the watchdog timer
- *
- ************************************************************************/
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
-
-}
-#endif
-
-void board_reset(void)
-{
- /* give reset to BCSR */
- *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
-}
+++ /dev/null
-if TARGET_YUCCA
-
-config SYS_BOARD
- default "yucca"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "yucca"
-
-endif
+++ /dev/null
-YUCCA BOARD
-#M: -
-S: Maintained
-F: board/amcc/yucca/
-F: include/configs/yucca.h
-F: configs/yucca_defconfig
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = yucca.o flash.o cmd_yucca.o
-extra-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * hacked for evb440spe
- */
-
-#include <common.h>
-#include <cli.h>
-#include <command.h>
-#include <console.h>
-#include "yucca.h"
-#include <i2c.h>
-#include <asm/byteorder.h>
-
-extern void print_evb440spe_info(void);
-static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
- int flag, int argc, char * const argv[]);
-
-/* ------------------------------------------------------------------------- */
-int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- return setBootStrapClock (cmdtp, 1, flag, argc, argv);
-}
-
-/* ------------------------------------------------------------------------- */
-/* Modify memory.
- *
- * Syntax:
- * evb440spe wrclk prom0,prom1
- */
-static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
- int argc, char * const argv[])
-{
- uchar chip;
- ulong data;
- int nbytes;
-
- char sysClock[4];
- char cpuClock[4];
- char plbClock[4];
- char pcixClock[4];
-
- if (argc < 3)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[2], "prom0") == 0)
- chip = IIC0_BOOTPROM_ADDR;
- else
- chip = IIC0_ALT_BOOTPROM_ADDR;
-
- do {
- printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n");
- nbytes = cli_readline(" ? ");
-
- if (strcmp(console_buffer, "quit") == 0)
- return 0;
-
- if ((strcmp(console_buffer, "33") != 0) &
- (strcmp(console_buffer, "66") != 0))
- nbytes=0;
-
- strcpy(sysClock, console_buffer);
-
- } while (nbytes == 0);
-
- do {
- if (strcmp(sysClock, "66") == 0) {
- printf("enter cpu clock frequency 400, 533 MHz or quit to abort\n");
- } else {
-#ifdef CONFIG_STRESS
- printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n");
-#else
- printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n");
-#endif
- }
- nbytes = cli_readline(" ? ");
-
- if (strcmp(console_buffer, "quit") == 0)
- return 0;
-
- if (strcmp(sysClock, "66") == 0) {
- if ((strcmp(console_buffer, "400") != 0) &
- (strcmp(console_buffer, "533") != 0)
-#ifdef CONFIG_STRESS
- & (strcmp(console_buffer, "667") != 0)
-#endif
- ) {
- nbytes = 0;
- }
- } else {
- if ((strcmp(console_buffer, "400") != 0) &
- (strcmp(console_buffer, "500") != 0) &
- (strcmp(console_buffer, "533") != 0)
-#ifdef CONFIG_STRESS
- & (strcmp(console_buffer, "667") != 0)
-#endif
- ) {
- nbytes = 0;
- }
- }
-
- strcpy(cpuClock, console_buffer);
-
- } while (nbytes == 0);
-
- if (strcmp(cpuClock, "500") == 0){
- strcpy(plbClock, "166");
- } else if (strcmp(cpuClock, "533") == 0){
- strcpy(plbClock, "133");
- } else {
- do {
- if (strcmp(cpuClock, "400") == 0)
- printf("enter plb clock frequency 100, 133 MHz or quit to abort\n");
-
-#ifdef CONFIG_STRESS
- if (strcmp(cpuClock, "667") == 0)
- printf("enter plb clock frequency 133, 166 MHz or quit to abort\n");
-
-#endif
- nbytes = cli_readline(" ? ");
-
- if (strcmp(console_buffer, "quit") == 0)
- return 0;
-
- if (strcmp(cpuClock, "400") == 0) {
- if ((strcmp(console_buffer, "100") != 0) &
- (strcmp(console_buffer, "133") != 0))
- nbytes = 0;
- }
-#ifdef CONFIG_STRESS
- if (strcmp(cpuClock, "667") == 0) {
- if ((strcmp(console_buffer, "133") != 0) &
- (strcmp(console_buffer, "166") != 0))
- nbytes = 0;
- }
-#endif
- strcpy(plbClock, console_buffer);
-
- } while (nbytes == 0);
- }
-
- do {
- printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n");
- nbytes = cli_readline(" ? ");
-
- if (strcmp(console_buffer, "quit") == 0)
- return 0;
-
- if ((strcmp(console_buffer, "33") != 0) &
- (strcmp(console_buffer, "66") != 0) &
- (strcmp(console_buffer, "100") != 0) &
- (strcmp(console_buffer, "133") != 0)) {
- nbytes = 0;
- }
- strcpy(pcixClock, console_buffer);
-
- } while (nbytes == 0);
-
- printf("\nsys clk = %s MHz\n", sysClock);
- printf("cpu clk = %s MHz\n", cpuClock);
- printf("plb clk = %s MHz\n", plbClock);
- printf("Pci-X clk = %s MHz\n", pcixClock);
-
- do {
- printf("\npress [y] to write I2C bootstrap\n");
- printf("or [n] to abort.\n");
- printf("Don't forget to set board switches\n");
- printf("according to your choice before re-starting\n");
- printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n");
-
- nbytes = cli_readline(" ? ");
- if (strcmp(console_buffer, "n") == 0)
- return 0;
-
- } while (nbytes == 0);
-
- if (strcmp(sysClock, "33") == 0) {
- if ((strcmp(cpuClock, "400") == 0) &
- (strcmp(plbClock, "100") == 0))
- data = 0x8678c206;
-
- if ((strcmp(cpuClock, "400") == 0) &
- (strcmp(plbClock, "133") == 0))
- data = 0x8678c2c6;
-
- if ((strcmp(cpuClock, "500") == 0))
- data = 0x8778f2c6;
-
- if ((strcmp(cpuClock, "533") == 0))
- data = 0x87790252;
-
-#ifdef CONFIG_STRESS
- if ((strcmp(cpuClock, "667") == 0) &
- (strcmp(plbClock, "133") == 0))
- data = 0x87794256;
-
- if ((strcmp(cpuClock, "667") == 0) &
- (strcmp(plbClock, "166") == 0))
- data = 0x87794206;
-
-#endif
- }
- if (strcmp(sysClock, "66") == 0) {
- if ((strcmp(cpuClock, "400") == 0) &
- (strcmp(plbClock, "100") == 0))
- data = 0x84706206;
-
- if ((strcmp(cpuClock, "400") == 0) &
- (strcmp(plbClock, "133") == 0))
- data = 0x847062c6;
-
- if ((strcmp(cpuClock, "533") == 0))
- data = 0x85708206;
-
-#ifdef CONFIG_STRESS
- if ((strcmp(cpuClock, "667") == 0) &
- (strcmp(plbClock, "133") == 0))
- data = 0x8570a256;
-
- if ((strcmp(cpuClock, "667") == 0) &
- (strcmp(plbClock, "166") == 0))
- data = 0x8570a206;
-
-#endif
- }
-
-#ifdef DEBUG
- printf(" pin strap0 to write in i2c = %x\n", data);
-#endif /* DEBUG */
-
- if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
- printf("Error writing strap0 in %s\n", argv[2]);
-
- if (strcmp(pcixClock, "33") == 0)
- data = 0x00000701;
-
- if (strcmp(pcixClock, "66") == 0)
- data = 0x00000601;
-
- if (strcmp(pcixClock, "100") == 0)
- data = 0x00000501;
-
- if (strcmp(pcixClock, "133") == 0)
- data = 0x00000401;
-
- if (strcmp(plbClock, "166") == 0)
- data = data | 0x05950000;
- else
- data = data | 0x05A50000;
-
-#ifdef DEBUG
- printf(" pin strap1 to write in i2c = %x\n", data);
-#endif /* DEBUG */
-
- udelay(1000);
- if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
- printf("Error writing strap1 in %s\n", argv[2]);
-
- return 0;
-}
-
-U_BOOT_CMD(
- evb440spe, 3, 1, do_evb440spe,
- "program the serial device strap",
- "wrclk [prom0|prom1] - program the serial device strap"
-);
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# AMCC 440SPe Reference Platform (yucca) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/ppc440.h>
-#include "yucca.h"
-
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*
- * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
- */
-static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
- {0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */
- {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
- {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */
- {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
- {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
- {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
- {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
- {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
- {0xfff00000, 0xfff80000, 0xe7c00001}, /* 8:boot from small flash */
-};
-
-/*
- * include common flash code (for amcc boards)
- */
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word_1(flash_info_t * info, ulong dest, ulong data);
-static int write_word_2(flash_info_t * info, ulong dest, ulong data);
-static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
-static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
-static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
-static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
-#endif
-
-void flash_print_info(flash_info_t * info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_STM:
- printf("STM ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- case FLASH_MAN_SST:
- printf("SST ");
- break;
- case FLASH_MAN_MX:
- printf("MIXC ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AMD016:
- printf("AM29F016D (16 Mbit, uniform sector size)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AM033C:
- printf("AM29LV033C (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A:
- printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A:
- printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- case FLASH_STMW320DT:
- printf ("M29W320DT (32 M, top sector)\n");
- break;
- case FLASH_MXLV320T:
- printf ("MXLV320T (32 Mbit, top sector)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
- }
- printf("\n");
- return;
-}
-
-
-/*
- * The following code cannot be run from FLASH!
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
- /* bit 0 used for big flash marking */
- if ((ulong)addr & 0x1)
- return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
- else
- return flash_get_size_1(addr, info);
-}
-
-static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
-#else
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-#endif
-{
- short i;
- CONFIG_SYS_FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
- DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
-
- /* Write auto select command: read Manufacturer ID */
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
- udelay(1000);
-
- value = addr2[0];
- DEBUGF("FLASH MANUFACT: %x\n", value);
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr2[1]; /* device ID */
- DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
- info->flash_id += FLASH_AMD016;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
- info->flash_id += FLASH_AMDLV033C;
- info->sector_count = 64;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
- /* For AMD29033C flash we need to resend the command of *
- * reading flash protection for upper 8 Mb of flash */
- if (i == 32) {
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /* issue bank reset to return to read mode */
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
- return (info->size);
-}
-
-static int wait_for_DQ7_1(flash_info_t * info, int sect)
-{
- ulong start, now, last;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
- (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
- start = get_timer(0);
- last = start;
- while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
- (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
- return 0;
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
- return flash_erase_2(info, s_first, s_last);
- } else {
- return flash_erase_1(info, s_first, s_last);
- }
-}
-
-static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
-#else
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-#endif
-{
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf("- missing\n");
- else
- printf("- no sectors to erase\n");
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot)
- printf("- Warning: %d protected sectors will not be erased!", prot);
-
- printf("\n");
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
- for (i = 0; i < 50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7_1(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /* reset to read mode */
- addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
-
- for (; cnt == 0 && i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- if ((rc = write_word(info, wp, data)) != 0)
- return (rc);
-
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i)
- data = (data << 8) | *src++;
-
- if ((rc = write_word(info, wp, data)) != 0)
- return (rc);
-
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0)
- return (0);
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-{
- if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
- return write_word_2(info, dest, data);
- } else {
- return write_word_1(info, dest, data);
- }
-}
-
-static int write_word_1(flash_info_t * info, ulong dest, ulong data)
-#else
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-#endif
-{
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
- ulong start;
- int i, flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data)
- return (2);
-
- for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return (1);
- }
- }
-
- return (0);
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-
-#undef CONFIG_SYS_FLASH_WORD_SIZE
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
-{
- short i;
- int n;
- CONFIG_SYS_FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
- DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
-
- /* issue bank reset to return to read mode */
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
- /* Write auto select command: read Manufacturer ID */
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
- udelay(1000);
-
- value = addr2[0];
- DEBUGF("FLASH MANUFACT: %x\n", value);
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
- info->flash_id = FLASH_MAN_MX;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr2[1]; /* device ID */
- DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 4 MB */
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 4 MB */
- case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
- info->flash_id += FLASH_STMW320DT;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
- case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
- info->flash_id += FLASH_MXLV320T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 4 MB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
- /* set sector offsets for top boot block type */
- base += info->size;
- i = info->sector_count;
- /* 1 x 16k boot sector */
- base -= 16 << 10;
- --i;
- info->start[i] = base;
- /* 2 x 8k boot sectors */
- for (n = 0; n < 2; ++n) {
- base -= 8 << 10;
- --i;
- info->start[i] = base;
- }
- /* 1 x 32k boot sector */
- base -= 32 << 10;
- --i;
- info->start[i] = base;
-
- while (i > 0) { /* 64k regular sectors */
- base -= 64 << 10;
- --i;
- info->start[i] = base;
- }
- } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00002000;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000a000;
- info->start[i--] = base + info->size - 0x0000c000;
- info->start[i--] = base + info->size - 0x0000e000;
- info->start[i--] = base + info->size - 0x00010000;
-
- for (; i >= 0; i--)
- info->start[i] = base + i * 0x00010000;
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
-
- for (i = 4; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
-
- for (; i >= 0; i--)
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
- /* For AMD29033C flash we need to resend the command of *
- * reading flash protection for upper 8 Mb of flash */
- if (i == 32) {
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /* issue bank reset to return to read mode */
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
- return (info->size);
-}
-
-static int wait_for_DQ7_2(flash_info_t * info, int sect)
-{
- ulong start, now, last;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
- (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
- start = get_timer(0);
- last = start;
- while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
- (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
- return 0;
-}
-
-static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
-{
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf("- missing\n");
- else
- printf("- no sectors to erase\n");
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot)
- printf("- Warning: %d protected sectors will not be erased!", prot);
-
- printf("\n");
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
- for (i = 0; i < 50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7_2(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /* reset to read mode */
- addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-static int write_word_2(flash_info_t * info, ulong dest, ulong data)
-{
- ulong *data_ptr = &data;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data)
- return (2);
-
- for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return (1);
- }
- }
-
- return (0);
-}
-#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- unsigned long total_b = 0;
- unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
- unsigned short index = 0;
- int i;
- unsigned long val;
- unsigned long ebc_boot_size;
- unsigned long boot_selection;
-
- mfsdr(sdr_pstrp0, val);
- index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 28;
-
- if ((index == 0xc) || (index == 8)) {
- /*
- * Boot Settings in IIC EEprom address 0xA8 or 0xA0
- * Read Serial Device Strap Register1 in PPC440SPe
- */
- mfsdr(SDR0_SDSTP1, val);
- boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
- ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
- switch(boot_selection) {
- case SDR0_SDSTP1_BOOT_SEL_EBC:
- switch(ebc_boot_size) {
- case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
- index = 3;
- break;
- case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
- index = 0;
- break;
- }
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_PCI:
- index = 1;
- break;
-
- }
- } /*else if (index == 0) {*/
-/* if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
-/* index = 8;*/ /* sram below op code flash -> new index 8*/
-/* }*/
-
- DEBUGF("\n");
- DEBUGF("FLASH: Index: %d\n", index);
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
-
- /* check whether the address is 0 */
- if (flash_addr_table[index][i] == 0)
- continue;
-
- /* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
- &flash_info[i]);
-
- flash_info[i].size = size_b[i];
-
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i] << 20);
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
- }
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH)
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[i]);
-#if defined(CONFIG_ENV_ADDR_REDUND)
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[i]);
-#endif
-#endif
- total_b += flash_info[i].size;
- }
-
- return total_b;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
-
-/**************************************************************************
- * TLB table for revA
- *************************************************************************/
- .globl tlbtabA
-tlbtabA:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
- tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
-
- tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
- tlbtab_end
-
-/**************************************************************************
- * TLB table for revB
- *
- * Notice: revB of the 440SPe chip is very strict about PLB real addresses
- * and ranges to be mapped for config space: it seems to only work with
- * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
- * set otherwise) while revA uses c_nnnn_nnnn.
- *************************************************************************/
- .globl tlbtabB
-tlbtabB:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
- tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
-
- tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Port to AMCC-440SPE Evaluation Board SOP - April 2005
- *
- * PCIe supporting routines derived from Linux 440SPe PCIe driver.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <i2c.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/4xx_pcie.h>
-#include <linux/errno.h>
-
-#include "yucca.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fpga_init (void);
-
-#define DEBUG_ENV
-#ifdef DEBUG_ENV
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-
-int board_early_init_f (void)
-{
-/*----------------------------------------------------------------------------+
-| Define Boot devices
-+----------------------------------------------------------------------------*/
-#define BOOT_FROM_SMALL_FLASH 0x00
-#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
-#define BOOT_FROM_PCI 0x02
-#define BOOT_DEVICE_UNKNOWN 0x03
-
-/*----------------------------------------------------------------------------+
-| EBC Devices Characteristics
-| Peripheral Bank Access Parameters - EBC_BxAP
-| Peripheral Bank Configuration Register - EBC_BxCR
-+----------------------------------------------------------------------------*/
-
-/*
- * Small Flash and FRAM
- * BU Value
- * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
- * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
- * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
- */
-#define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(7) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(0) | \
- EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(0) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED
-
-#define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
- EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_8BIT
-
-#define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \
- EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_8BIT
-
-/*
- * Large Flash and SRAM
- * BU Value
- * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
- * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
- * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
-*/
-#define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(7) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(0) | \
- EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(0) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED
-
-#define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
- EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT
-
-#define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \
- EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT
-
-/*
- * FPGA
- * BU value :
- * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
- * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
- */
-#define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(11) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(10) | \
- EBC_BXAP_OEN_ENCODE(1) | \
- EBC_BXAP_WBN_ENCODE(1) | \
- EBC_BXAP_WBF_ENCODE(1) | \
- EBC_BXAP_TH_ENCODE(1) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_RW | \
- EBC_BXAP_PEN_DISABLED
-
-#define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \
- EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT
-
- unsigned long mfr;
- /*
- * Define Variables for EBC initialization depending on BOOTSTRAP option
- */
- unsigned long sdr0_pinstp, sdr0_sdstp1 ;
- unsigned long bootstrap_settings, ebc_data_width, boot_selection;
- int computed_boot_device = BOOT_DEVICE_UNKNOWN;
-
- /*-------------------------------------------------------------------+
- | Initialize EBC CONFIG -
- | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
- | default value :
- | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
- |
- +-------------------------------------------------------------------*/
- mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
- EBC_CFG_PTD_ENABLE |
- EBC_CFG_RTC_16PERCLK |
- EBC_CFG_ATC_PREVIOUS |
- EBC_CFG_DTC_PREVIOUS |
- EBC_CFG_CTC_PREVIOUS |
- EBC_CFG_OEO_PREVIOUS |
- EBC_CFG_EMC_DEFAULT |
- EBC_CFG_PME_DISABLE |
- EBC_CFG_PR_16);
-
- /*-------------------------------------------------------------------+
- |
- | PART 1 : Initialize EBC Bank 1
- | ==============================
- | Bank1 is always associated to the EPLD.
- | It has to be initialized prior to other banks settings computation
- | since some board registers values may be needed to determine the
- | boot type
- |
- +-------------------------------------------------------------------*/
- mtebc(PB1AP, EBC_BXAP_FPGA);
- mtebc(PB1CR, EBC_BXCR_FPGA_CS1);
-
- /*-------------------------------------------------------------------+
- |
- | PART 2 : Determine which boot device was selected
- | =================================================
- |
- | Read Pin Strap Register in PPC440SPe
- | Result can either be :
- | - Boot strap = boot from EBC 8bits => Small Flash
- | - Boot strap = boot from PCI
- | - Boot strap = IIC
- | In case of boot from IIC, read Serial Device Strap Register1
- |
- | Result can either be :
- | - Boot from EBC - EBC Bus Width = 8bits => Small Flash
- | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
- | - Boot from PCI
- |
- +-------------------------------------------------------------------*/
- /* Read Pin Strap Register in PPC440SP */
- mfsdr(SDR0_PINSTP, sdr0_pinstp);
- bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
-
- switch (bootstrap_settings) {
- case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
- /*
- * Strapping Option A
- * Boot from EBC - 8 bits , Small Flash
- */
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
- case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
- /*
- * Strappping Option B
- * Boot from PCI
- */
- computed_boot_device = BOOT_FROM_PCI;
- break;
- case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
- case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
- /*
- * Strapping Option C or D
- * Boot Settings in IIC EEprom address 0x50 or 0x54
- * Read Serial Device Strap Register1 in PPC440SPe
- */
- mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
- boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
- ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
-
- switch (boot_selection) {
- case SDR0_SDSTP1_ERPN_EBC:
- switch (ebc_data_width) {
- case SDR0_SDSTP1_EBCW_16_BITS:
- computed_boot_device =
- BOOT_FROM_LARGE_FLASH_OR_SRAM;
- break;
- case SDR0_SDSTP1_EBCW_8_BITS :
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
- }
- break;
-
- case SDR0_SDSTP1_ERPN_PCI:
- computed_boot_device = BOOT_FROM_PCI;
- break;
- default:
- /* should not occure */
- computed_boot_device = BOOT_DEVICE_UNKNOWN;
- }
- break;
- default:
- /* should not be */
- computed_boot_device = BOOT_DEVICE_UNKNOWN;
- break;
- }
-
- /*-------------------------------------------------------------------+
- |
- | PART 3 : Compute EBC settings depending on selected boot device
- | ====== ======================================================
- |
- | Resulting EBC init will be among following configurations :
- |
- | - Boot from EBC 8bits => boot from Small Flash selected
- | EBC-CS0 = Small Flash
- | EBC-CS2 = Large Flash and SRAM
- |
- | - Boot from EBC 16bits => boot from Large Flash or SRAM
- | EBC-CS0 = Large Flash or SRAM
- | EBC-CS2 = Small Flash
- |
- | - Boot from PCI
- | EBC-CS0 = not initialized to avoid address contention
- | EBC-CS2 = same as boot from Small Flash selected
- |
- +-------------------------------------------------------------------*/
- unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
- unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
-
- switch (computed_boot_device) {
- /*-------------------------------------------------------------------*/
- case BOOT_FROM_PCI:
- /*-------------------------------------------------------------------*/
- /*
- * By Default CS2 is affected to LARGE Flash
- * do not initialize SMALL FLASH to avoid address contention
- * Large Flash
- */
- ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
- ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
- break;
-
- /*-------------------------------------------------------------------*/
- case BOOT_FROM_SMALL_FLASH:
- /*-------------------------------------------------------------------*/
- ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
- ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
-
- /*
- * Large Flash or SRAM
- */
- /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
- ebc0_cs2_bxap_value = 0x048ff240;
- ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
- break;
-
- /*-------------------------------------------------------------------*/
- case BOOT_FROM_LARGE_FLASH_OR_SRAM:
- /*-------------------------------------------------------------------*/
- ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
- ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
-
- /* Small flash */
- ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
- ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
- break;
-
- /*-------------------------------------------------------------------*/
- default:
- /*-------------------------------------------------------------------*/
- /* BOOT_DEVICE_UNKNOWN */
- break;
- }
-
- mtebc(PB0AP, ebc0_cs0_bxap_value);
- mtebc(PB0CR, ebc0_cs0_bxcr_value);
- mtebc(PB2AP, ebc0_cs2_bxap_value);
- mtebc(PB2CR, ebc0_cs2_bxcr_value);
-
- /*--------------------------------------------------------------------+
- | Interrupt controller setup for the AMCC 440SPe Evaluation board.
- +--------------------------------------------------------------------+
- +---------------------------------------------------------------------+
- |Interrupt| Source | Pol. | Sensi.| Crit. |
- +---------+-----------------------------------+-------+-------+-------+
- | IRQ 00 | UART0 | High | Level | Non |
- | IRQ 01 | UART1 | High | Level | Non |
- | IRQ 02 | IIC0 | High | Level | Non |
- | IRQ 03 | IIC1 | High | Level | Non |
- | IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
- | IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
- | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
- | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
- | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
- | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
- | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
- | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
- | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
- | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
- | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
- | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
- | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
- | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
- | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
- | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
- | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
- | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
- | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
- | IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
- | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
- | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
- | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
- | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
- | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
- | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
- | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
- | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
- |----------------------------------------------------------------------
- | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
- | IRQ 33 | MAL Serr | High | Level | Non |
- | IRQ 34 | MAL Txde | High | Level | Non |
- | IRQ 35 | MAL Rxde | High | Level | Non |
- | IRQ 36 | DMC CE or DMC UE | High | Level | Non |
- | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
- | IRQ 38 | MAL TX EOB | High | Level | Non |
- | IRQ 39 | MAL RX EOB | High | Level | Non |
- | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
- | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
- | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
- | IRQ 43 | L2 Cache | Risin | Edge | Non |
- | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
- | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
- | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
- | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
- | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
- | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
- | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
- | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
- | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
- | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
- | IRQ 54 | DMA Error | High | Level | Non |
- | IRQ 55 | DMA I2O Error | High | Level | Non |
- | IRQ 56 | Serial ROM | High | Level | Non |
- | IRQ 57 | PCIX0 Error | High | Edge | Non |
- | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
- | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
- | IRQ 60 | EMAC0 Interrupt | High | Level | Non |
- | IRQ 61 | EMAC0 Wake-up | High | Level | Non |
- | IRQ 62 | Reserved | High | Level | Non |
- | IRQ 63 | XOR | High | Level | Non |
- |----------------------------------------------------------------------
- | IRQ 64 | PE0 AL | High | Level | Non |
- | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
- | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
- | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
- | IRQ 68 | PE0 TCR | High | Level | Non |
- | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
- | IRQ 70 | PE0 DCR Error | High | Level | Non |
- | IRQ 71 | Reserved | N/A | N/A | Non |
- | IRQ 72 | PE1 AL | High | Level | Non |
- | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
- | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
- | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
- | IRQ 76 | PE1 TCR | High | Level | Non |
- | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
- | IRQ 78 | PE1 DCR Error | High | Level | Non |
- | IRQ 79 | Reserved | N/A | N/A | Non |
- | IRQ 80 | PE2 AL | High | Level | Non |
- | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
- | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
- | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
- | IRQ 84 | PE2 TCR | High | Level | Non |
- | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
- | IRQ 86 | PE2 DCR Error | High | Level | Non |
- | IRQ 87 | Reserved | N/A | N/A | Non |
- | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
- | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
- | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
- | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
- | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
- | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
- | IRQ 94 | Reserved | N/A | N/A | Non |
- | IRQ 95 | Reserved | N/A | N/A | Non |
- |---------------------------------------------------------------------
- | IRQ 96 | PE0 INTA | High | Level | Non |
- | IRQ 97 | PE0 INTB | High | Level | Non |
- | IRQ 98 | PE0 INTC | High | Level | Non |
- | IRQ 99 | PE0 INTD | High | Level | Non |
- | IRQ 100 | PE1 INTA | High | Level | Non |
- | IRQ 101 | PE1 INTB | High | Level | Non |
- | IRQ 102 | PE1 INTC | High | Level | Non |
- | IRQ 103 | PE1 INTD | High | Level | Non |
- | IRQ 104 | PE2 INTA | High | Level | Non |
- | IRQ 105 | PE2 INTB | High | Level | Non |
- | IRQ 106 | PE2 INTC | High | Level | Non |
- | IRQ 107 | PE2 INTD | Risin | Edge | Non |
- | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
- | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
- | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
- | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
- | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
- | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
- | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
- | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
- | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
- | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
- | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
- | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
- | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
- | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
- | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
- | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
- | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
- | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
- | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
- | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
- +---------+-----------------------------------+-------+-------+------*/
- /*--------------------------------------------------------------------+
- | Put UICs in PowerPC440SPemode.
- | Initialise UIC registers. Clear all interrupts. Disable all
- | interrupts.
- | Set critical interrupt values. Set interrupt polarities. Set
- | interrupt trigger levels. Make bit 0 High priority. Clear all
- | interrupts again.
- +-------------------------------------------------------------------*/
- mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
- mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical
- * interrupts */
- mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
- mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest
- * priority */
- mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
- mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical
- * interrupts */
- mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
- mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
- mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest
- * priority */
- mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
- mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical
- * interrupts */
- mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */
- mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest
- * priority */
- mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
- mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted
- * cascade to be checked */
- mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical
- * interrupts */
- mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
- mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest
- * priority */
- mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
- mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
-
- mfsdr(SDR0_MFR, mfr);
- mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
- mtsdr(SDR0_MFR, mfr);
-
- fpga_init();
-
- return 0;
-}
-
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: Yucca - AMCC 440SPe Evaluation Board");
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-/*
- * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-static int ppc440spe_rev_a(void)
-{
- if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
- return 1;
- else
- return 0;
-}
-
-u32 ddr_wrdtr(u32 default_val) {
- /*
- * Yucca boards with 440SPe rev. A need a slightly different setup
- * for the MCIF0_WRDTR register.
- */
- if (ppc440spe_rev_a())
- return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
-
- return default_val;
-}
-
-u32 ddr_clktr(u32 default_val) {
- /*
- * Yucca boards with 440SPe rev. A need a slightly different setup
- * for the MCIF0_CLKTR register.
- */
- if (ppc440spe_rev_a())
- return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
-
- return default_val;
-}
-
-#if defined(CONFIG_PCI)
-int board_pcie_card_present(int port)
-{
- u16 reg;
-
- reg = in_be16((u16 *)FPGA_REG1C);
- switch(port) {
- case 0:
- return !(reg & FPGA_REG1C_PE0_PRSNT);
- case 1:
- return !(reg & FPGA_REG1C_PE1_PRSNT);
- case 2:
- return !(reg & FPGA_REG1C_PE2_PRSNT);
- default:
- return 0;
- }
-}
-
-/*
- * For the given slot, set endpoint mode, send power to the slot,
- * turn on the green LED and turn off the yellow LED, enable the
- * clock. In endpoint mode reset bit is read only.
- */
-void board_pcie_setup_port(int port, int rootpoint)
-{
- u16 power, clock, green_led, yellow_led,
- reset_off, rp, ep;
-
- switch (port) {
- case 0:
- rp = FPGA_REG1C_PE0_ROOTPOINT;
- ep = 0;
- break;
- case 1:
- rp = 0;
- ep = FPGA_REG1C_PE1_ENDPOINT;
- break;
- case 2:
- rp = 0;
- ep = FPGA_REG1C_PE2_ENDPOINT;
- break;
-
- default:
- return;
- }
-
- power = FPGA_REG1A_PWRON_ENCODE(port);
- green_led = FPGA_REG1A_GLED_ENCODE(port);
- clock = FPGA_REG1A_REFCLK_ENCODE(port);
- yellow_led = FPGA_REG1A_YLED_ENCODE(port);
- reset_off = FPGA_REG1C_PERST_ENCODE(port);
-
- out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) &
- (yellow_led | in_be16((u16 *)FPGA_REG1A)));
-
- out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) &
- (rp | in_be16((u16 *)FPGA_REG1C)));
-
- if (rootpoint) {
- /*
- * Leave device in reset for a while after powering on the
- * slot to give it a chance to initialize.
- */
- udelay(250 * 1000);
-
- out_be16((u16 *)FPGA_REG1C,
- reset_off | in_be16((u16 *)FPGA_REG1C));
- }
-}
-#endif /* defined(CONFIG_PCI) */
-
-int misc_init_f (void)
-{
- uint reg;
-
- out16(FPGA_REG10, (in16(FPGA_REG10) &
- ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
- FPGA_REG10_10MHZ_ENABLE |
- FPGA_REG10_100MHZ_ENABLE |
- FPGA_REG10_GIGABIT_ENABLE |
- FPGA_REG10_FULL_DUPLEX );
-
- udelay(10000); /* wait 10ms */
-
- out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
-
- /* minimal init for PCIe */
- /* pci express 0 Endpoint Mode */
- mfsdr(SDRN_PESDR_DLPSET(0), reg);
- reg &= (~0x00400000);
- mtsdr(SDRN_PESDR_DLPSET(0), reg);
- /* pci express 1 Rootpoint Mode */
- mfsdr(SDRN_PESDR_DLPSET(1), reg);
- reg |= 0x00400000;
- mtsdr(SDRN_PESDR_DLPSET(1), reg);
- /* pci express 2 Rootpoint Mode */
- mfsdr(SDRN_PESDR_DLPSET(2), reg);
- reg |= 0x00400000;
- mtsdr(SDRN_PESDR_DLPSET(2), reg);
-
- out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
- ~FPGA_REG1C_PE0_ROOTPOINT &
- ~FPGA_REG1C_PE1_ENDPOINT &
- ~FPGA_REG1C_PE2_ENDPOINT));
-
- return 0;
-}
-
-void fpga_init(void)
-{
- /*
- * by default sdram access is disabled by fpga
- */
- out16(FPGA_REG10, (in16 (FPGA_REG10) |
- FPGA_REG10_SDRAM_ENABLE |
- FPGA_REG10_ENABLE_DISPLAY ));
-
- return;
-}
-
-/*---------------------------------------------------------------------------+
- | onboard_pci_arbiter_selected => from EPLD
- +---------------------------------------------------------------------------*/
-int onboard_pci_arbiter_selected(int core_pci)
-{
-#if 0
- unsigned long onboard_pci_arbiter_sel;
-
- onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
-
- if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
- return (BOARD_OPTION_SELECTED);
- else
-#endif
- return (BOARD_OPTION_NOT_SELECTED);
-}
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis);
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __YUCCA_H_
-#define __YUCCA_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*----------------------------------------------------------------------------+
-| Defines
-+----------------------------------------------------------------------------*/
-
-#define TMR_FREQ_EXT 25000000
-#define BOARD_UART_CLOCK 11059200
-
-#define BOARD_OPTION_SELECTED 1
-#define BOARD_OPTION_NOT_SELECTED 0
-
-#define ENGINEERING_CLOCK_CHECKING "clk_chk"
-#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
-
-#define ENGINEERING_CLOCK_CHECKING_DATA 1
-#define ENGINEERING_EXTERNAL_CLOCK_DATA 2
-
-/* ethernet definition */
-#define MAX_ENETMODE_PARM 3
-#define ENETMODE_NEG 0
-#define ENETMODE_SPEED 1
-#define ENETMODE_DUPLEX 2
-
-#define ENETMODE_AUTONEG 0
-#define ENETMODE_NO_AUTONEG 1
-#define ENETMODE_10 2
-#define ENETMODE_100 3
-#define ENETMODE_1000 4
-#define ENETMODE_HALF 5
-#define ENETMODE_FULL 6
-
-#define NUM_TLB_ENTRIES 64
-
-/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */
-#define MICRON_SPD_JEDEC_ID 0x2c
-
-/*----------------------------------------------------------------------------+
-| TLB specific defines.
-+----------------------------------------------------------------------------*/
-#define TLB_256MB_ALIGN_MASK 0xF0000000
-#define TLB_16MB_ALIGN_MASK 0xFF000000
-#define TLB_1MB_ALIGN_MASK 0xFFF00000
-#define TLB_256KB_ALIGN_MASK 0xFFFC0000
-#define TLB_64KB_ALIGN_MASK 0xFFFF0000
-#define TLB_16KB_ALIGN_MASK 0xFFFFC000
-#define TLB_4KB_ALIGN_MASK 0xFFFFF000
-#define TLB_1KB_ALIGN_MASK 0xFFFFFC00
-#define TLB_256MB_SIZE 0x10000000
-#define TLB_16MB_SIZE 0x01000000
-#define TLB_1MB_SIZE 0x00100000
-#define TLB_256KB_SIZE 0x00040000
-#define TLB_64KB_SIZE 0x00010000
-#define TLB_16KB_SIZE 0x00004000
-#define TLB_4KB_SIZE 0x00001000
-#define TLB_1KB_SIZE 0x00000400
-
-#define TLB_WORD0_EPN_MASK 0xFFFFFC00
-#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD0_V_MASK 0x00000200
-#define TLB_WORD0_V_ENABLE 0x00000200
-#define TLB_WORD0_V_DISABLE 0x00000000
-#define TLB_WORD0_TS_MASK 0x00000100
-#define TLB_WORD0_TS_1 0x00000100
-#define TLB_WORD0_TS_0 0x00000000
-#define TLB_WORD0_SIZE_MASK 0x000000F0
-#define TLB_WORD0_SIZE_1KB 0x00000000
-#define TLB_WORD0_SIZE_4KB 0x00000010
-#define TLB_WORD0_SIZE_16KB 0x00000020
-#define TLB_WORD0_SIZE_64KB 0x00000030
-#define TLB_WORD0_SIZE_256KB 0x00000040
-#define TLB_WORD0_SIZE_1MB 0x00000050
-#define TLB_WORD0_SIZE_16MB 0x00000070
-#define TLB_WORD0_SIZE_256MB 0x00000090
-#define TLB_WORD0_TPAR_MASK 0x0000000F
-#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
-#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
-
-#define TLB_WORD1_RPN_MASK 0xFFFFFC00
-#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD1_PAR1_MASK 0x00000300
-#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
-#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
-#define TLB_WORD1_PAR1_0 0x00000000
-#define TLB_WORD1_PAR1_1 0x00000100
-#define TLB_WORD1_PAR1_2 0x00000200
-#define TLB_WORD1_PAR1_3 0x00000300
-#define TLB_WORD1_ERPN_MASK 0x0000000F
-#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
-#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
-
-#define TLB_WORD2_PAR2_MASK 0xC0000000
-#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
-#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
-#define TLB_WORD2_PAR2_0 0x00000000
-#define TLB_WORD2_PAR2_1 0x40000000
-#define TLB_WORD2_PAR2_2 0x80000000
-#define TLB_WORD2_PAR2_3 0xC0000000
-#define TLB_WORD2_U0_MASK 0x00008000
-#define TLB_WORD2_U0_ENABLE 0x00008000
-#define TLB_WORD2_U0_DISABLE 0x00000000
-#define TLB_WORD2_U1_MASK 0x00004000
-#define TLB_WORD2_U1_ENABLE 0x00004000
-#define TLB_WORD2_U1_DISABLE 0x00000000
-#define TLB_WORD2_U2_MASK 0x00002000
-#define TLB_WORD2_U2_ENABLE 0x00002000
-#define TLB_WORD2_U2_DISABLE 0x00000000
-#define TLB_WORD2_U3_MASK 0x00001000
-#define TLB_WORD2_U3_ENABLE 0x00001000
-#define TLB_WORD2_U3_DISABLE 0x00000000
-#define TLB_WORD2_W_MASK 0x00000800
-#define TLB_WORD2_W_ENABLE 0x00000800
-#define TLB_WORD2_W_DISABLE 0x00000000
-#define TLB_WORD2_I_MASK 0x00000400
-#define TLB_WORD2_I_ENABLE 0x00000400
-#define TLB_WORD2_I_DISABLE 0x00000000
-#define TLB_WORD2_M_MASK 0x00000200
-#define TLB_WORD2_M_ENABLE 0x00000200
-#define TLB_WORD2_M_DISABLE 0x00000000
-#define TLB_WORD2_G_MASK 0x00000100
-#define TLB_WORD2_G_ENABLE 0x00000100
-#define TLB_WORD2_G_DISABLE 0x00000000
-#define TLB_WORD2_E_MASK 0x00000080
-#define TLB_WORD2_E_ENABLE 0x00000080
-#define TLB_WORD2_E_DISABLE 0x00000000
-#define TLB_WORD2_UX_MASK 0x00000020
-#define TLB_WORD2_UX_ENABLE 0x00000020
-#define TLB_WORD2_UX_DISABLE 0x00000000
-#define TLB_WORD2_UW_MASK 0x00000010
-#define TLB_WORD2_UW_ENABLE 0x00000010
-#define TLB_WORD2_UW_DISABLE 0x00000000
-#define TLB_WORD2_UR_MASK 0x00000008
-#define TLB_WORD2_UR_ENABLE 0x00000008
-#define TLB_WORD2_UR_DISABLE 0x00000000
-#define TLB_WORD2_SX_MASK 0x00000004
-#define TLB_WORD2_SX_ENABLE 0x00000004
-#define TLB_WORD2_SX_DISABLE 0x00000000
-#define TLB_WORD2_SW_MASK 0x00000002
-#define TLB_WORD2_SW_ENABLE 0x00000002
-#define TLB_WORD2_SW_DISABLE 0x00000000
-#define TLB_WORD2_SR_MASK 0x00000001
-#define TLB_WORD2_SR_ENABLE 0x00000001
-#define TLB_WORD2_SR_DISABLE 0x00000000
-
-/*----------------------------------------------------------------------------+
-| Board specific defines.
-+----------------------------------------------------------------------------*/
-#define NONCACHE_MEMORY_SIZE (64*1024)
-#define NONCACHE_AREA0_ENDOFFSET (64*1024)
-#define NONCACHE_AREA1_ENDOFFSET (32*1024)
-
-#define FLASH_SECTORSIZE 0x00010000
-
-/* SDRAM MICRON */
-#define SDRAM_MICRON 0x2C
-
-#define SDRAM_TRUE 1
-#define SDRAM_FALSE 0
-#define SDRAM_DDR1 1
-#define SDRAM_DDR2 2
-#define SDRAM_NONE 0
-#define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */
-#define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */
-#define MAXBANKSPERDIMM 2
-#define MAXRANKSPERDIMM 2
-#define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */
-#define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */
-#define ERROR_STR_LENGTH 256
-#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
-
-/*----------------------------------------------------------------------------+
-| SDR Configuration registers
-+----------------------------------------------------------------------------*/
-/* Serial Device Strap Reg 0 */
-#define sdr_pstrp0 0x0040
-
-#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */
-#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */
-#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
-
-#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */
-#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
-#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */
-
-#define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */
-#define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */
-#define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */
-#define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */
-#define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */
-
-/* Serial Device Enabled - Addr = 0xA8 */
-#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
-/* Serial Device Enabled - Addr = 0xA4 */
-#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
-
-/* Pin Straps Reg */
-#define SDR0_PSTRP0 0x0040
-#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
-
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
-
-/* fpgareg - defines are in include/config/YUCCA.h */
-
-#define SDR0_CUST0_ENET3_MASK 0x00000080
-#define SDR0_CUST0_ENET3_COPPER 0x00000000
-#define SDR0_CUST0_ENET3_FIBER 0x00000080
-#define SDR0_CUST0_RGMII3_MASK 0x00000070
-#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
-#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
-#define SDR0_CUST0_RGMII3_DISAB 0x00000000
-#define SDR0_CUST0_RGMII3_RTBI 0x00000040
-#define SDR0_CUST0_RGMII3_RGMII 0x00000050
-#define SDR0_CUST0_RGMII3_TBI 0x00000060
-#define SDR0_CUST0_RGMII3_GMII 0x00000070
-#define SDR0_CUST0_ENET2_MASK 0x00000008
-#define SDR0_CUST0_ENET2_COPPER 0x00000000
-#define SDR0_CUST0_ENET2_FIBER 0x00000008
-#define SDR0_CUST0_RGMII2_MASK 0x00000007
-#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
-#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
-#define SDR0_CUST0_RGMII2_DISAB 0x00000000
-#define SDR0_CUST0_RGMII2_RTBI 0x00000004
-#define SDR0_CUST0_RGMII2_RGMII 0x00000005
-#define SDR0_CUST0_RGMII2_TBI 0x00000006
-#define SDR0_CUST0_RGMII2_GMII 0x00000007
-
-#define ONE_MILLION 1000000
-#define ONE_BILLION 1000000000
-
-/*----------------------------------------------------------------------------+
-| X
-| XX
-| XX XXX XXXXX XX XXX XXXXX
-| XX XX X XXX XX XX
-| XX XX XXXXXX XX XX
-| XX XX X XX XX XX XX
-| XXX XX XXXXX X XXXX XXX
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-| Declare Configuration values
-+----------------------------------------------------------------------------*/
-
-typedef enum config_selection {
- CONFIG_NOT_SELECTED,
- CONFIG_SELECTED
-} config_selection_t;
-
-typedef enum config_list {
- UART2_IN_SERVICE_MODE,
- CPU_TRACE_MODE,
- UART1_CTS_RTS,
- CONFIG_NB
-} config_list_t;
-
-#define MAX_CONFIG_SELECT_NB 3
-
-#define BOARD_INFO_UART2_IN_SERVICE_MODE 1
-#define BOARD_INFO_CPU_TRACE_MODE 2
-#define BOARD_INFO_UART1_CTS_RTS_MODE 4
-
-void force_bup_config_selection(config_selection_t *confgi_select_P);
-void update_config_selection_table(config_selection_t *config_select_P);
-void display_config_selection(config_selection_t *config_select_P);
-
-/*----------------------------------------------------------------------------+
-| XX
-|
-| XXXX XX XXX XXX XXXX
-| XX XX XX XX XX XX
-| XX XXX XX XX XX XX XX
-| XX XX XXXXX XX XX XX
-| XXXX XX XXXX XXXX
-| XXXX
-|
-|
-|
-| +------------------------------------------------------------------+
-| | GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
-| +----------------------+------------------+-----+------------+-----+
-| | | | | | |
-| | GPIO0_0 | PCIX0REQ2_N | I/O | TRCCLK | |
-| | GPIO0_1 | PCIX0REQ3_N | I/O | TRCBS0 | |
-| | GPIO0_2 | PCIX0GNT2_N | I/O | TRCBS1 | |
-| | GPIO0_3 | PCIX0GNT3_N | I/O | TRCBS2 | |
-| | GPIO0_4 | PCIX1REQ2_N | I/O | TRCES0 | |
-| | GPIO0_5 | PCIX1REQ3_N | I/O | TRCES1 | |
-| | GPIO0_6 | PCIX1GNT2_N | I/O | TRCES2 | NA |
-| | GPIO0_7 | PCIX1GNT3_N | I/O | TRCES3 | NA |
-| | GPIO0_8 | PERREADY | I | TRCES4 | NA |
-| | GPIO0_9 | PERCS1_N | O | TRCTS0 | NA |
-| | GPIO0_10 | PERCS2_N | O | TRCTS1 | NA |
-| | GPIO0_11 | IRQ0 | I | TRCTS2 | NA |
-| | GPIO0_12 | IRQ1 | I | TRCTS3 | NA |
-| | GPIO0_13 | IRQ2 | I | TRCTS4 | NA |
-| | GPIO0_14 | IRQ3 | I | TRCTS5 | NA |
-| | GPIO0_15 | IRQ4 | I | TRCTS6 | NA |
-| | GPIO0_16 | IRQ5 | I | UART2RX | I |
-| | GPIO0_17 | PERBE0_N | O | UART2TX | O |
-| | GPIO0_18 | PCI0GNT0_N | I/O | NA | NA |
-| | GPIO0_19 | PCI0GNT1_N | I/O | NA | NA |
-| | GPIO0_20 | PCI0REQ0_N | I/O | NA | NA |
-| | GPIO0_21 | PCI0REQ1_N | I/O | NA | NA |
-| | GPIO0_22 | PCI1GNT0_N | I/O | NA | NA |
-| | GPIO0_23 | PCI1GNT1_N | I/O | NA | NA |
-| | GPIO0_24 | PCI1REQ0_N | I/O | NA | NA |
-| | GPIO0_25 | PCI1REQ1_N | I/O | NA | NA |
-| | GPIO0_26 | PCI2GNT0_N | I/O | NA | NA |
-| | GPIO0_27 | PCI2GNT1_N | I/O | NA | NA |
-| | GPIO0_28 | PCI2REQ0_N | I/O | NA | NA |
-| | GPIO0_29 | PCI2REQ1_N | I/O | NA | NA |
-| | GPIO0_30 | UART1RX | I | NA | NA |
-| | GPIO0_31 | UART1TX | O | NA | NA |
-| | | | | | |
-| +----------------------+------------------+-----+------------+-----+
-|
-+----------------------------------------------------------------------------*/
-
-unsigned long auto_calc_speed(void);
-/*----------------------------------------------------------------------------+
-| Prototypes
-+----------------------------------------------------------------------------*/
-void print_evb440spe_info(void);
-
-int onboard_pci_arbiter_selected(int core_pci);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __YUCCA_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2005-2008
- * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#if !defined(CONFIG_440)
-#include <asm/4xx_pci.h>
-#endif
-
-#if defined(CONFIG_CMD_BSP)
-#define ADDRMASK 0xfffff000
-
-/*
- * Command loadpci: wait for signal from host and boot image.
- */
-int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 *ptr = 0;
- int count = 0;
- int count2 = 0;
- char addr[16];
- char str[] = "\\|/-";
- u32 la, ptm1la;
-
-#if defined(CONFIG_440)
- ptm1la = in32r(PCIL0_PTM1LA);
-#else
- ptm1la = in32r(PTM1LA);
-#endif
- while(1) {
- /*
- * Mark sync address
- */
- ptr = (u32 *)ptm1la;
- memset(ptr, 0, 0x20);
-
- *ptr = 0xffffffff;
- puts("\nWaiting for action from pci host -");
-
- /*
- * Wait for host to write the start address
- */
- while (*ptr == 0xffffffff) {
- count++;
- if (!(count % 100)) {
- count2++;
- putc(0x08); /* backspace */
- putc(str[count2 % 4]);
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- udelay(1000);
- }
-
- printf("\nGot bootcode %08x: ", *ptr);
- la = ptm1la + (*ptr & ADDRMASK);
- sprintf(addr, "%08x", la);
-
- switch (*ptr & ~ADDRMASK) {
- case 0:
- /*
- * Boot image via bootm
- */
- printf("booting image at addr 0x%s ...\n", addr);
- setenv("loadaddr", addr);
- do_bootm(cmdtp, 0, 0, NULL);
- break;
-
- case 1:
- /*
- * Boot image via "source" command
- */
- printf("executing script at addr 0x%s ...\n", addr);
- source(la, NULL);
- break;
-
- case 2:
- /*
- * Call run_cmd
- */
- printf("running command at addr 0x%s ...\n", addr);
- run_command((char *)la, 0);
- break;
-
- default:
- printf("unhandled boot method\n");
- break;
- }
- }
-}
-
-U_BOOT_CMD(
- loadpci, 1, 1, do_loadpci,
- "Wait for pci bootcmd and boot it",
- ""
-);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-#include <asm/io.h>
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- */
-static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
- else
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);
- if ( ctrl & NAND_ALE )
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE);
- else
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);
- if ( ctrl & NAND_NCE )
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE);
- else
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-
-/*
- * read device ready pin
- */
-static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
-{
- if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY)
- return 1;
- return 0;
-}
-
-
-int board_nand_init(struct nand_chip *nand)
-{
- /*
- * Set NAND-FLASH GPIO signals to defaults
- */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
-
- /*
- * Initialize nand_chip structure
- */
- nand->cmd_ctrl = esd405ep_nand_hwcontrol;
- nand->dev_ready = esd405ep_nand_device_ready;
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->chip_delay = NAND_BIG_DELAY_US;
- nand->options = NAND_SAMSUNG_LP_OPTIONS;
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#ifdef __PPC__
-#include <asm/ppc4xx.h>
-#endif
-#include <asm/processor.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
- short n;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
- /* set sector offsets for bottom boot block type */
- for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- }
- while (i < info->sector_count) { /* 64k regular sectors */
- info->start[i] = base;
- base += 64 << 10;
- ++i;
- }
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
- /* set sector offsets for top boot block type */
- base += info->size;
- i = info->sector_count;
- for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
- base -= 8 << 10;
- --i;
- info->start[i] = base;
- }
- while (i > 0) { /* 64k regular sectors */
- base -= 64 << 10;
- --i;
- info->start[i] = base;
- }
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
- break;
- case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
- break;
- case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
- break;
- case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
- break;
- case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
- break;
- case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n");
- break;
- case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST320: printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST640: printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
-#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- /* print empty and read-only info */
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
-#else
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
-#endif
-
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- short n;
- CONFIG_SYS_FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
-
- value = addr2[CONFIG_SYS_FLASH_READ0];
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
- info->flash_id = FLASH_MAN_EXCEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
- info->flash_id += FLASH_AMDL322B;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
- info->flash_id += FLASH_AMDL323T;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
- info->flash_id += FLASH_AM640U;
- info->sector_count = 128;
- info->size = 0x00800000; break; /* => 8 MB */
-
-#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM))
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601:
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201:
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202:
- info->flash_id += FLASH_SST320;
- info->sector_count = 64;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401:
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402:
- info->flash_id += FLASH_SST640;
- info->sector_count = 128;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
- /* set sector offsets for bottom boot block type */
- for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- }
- while (i < info->sector_count) { /* 64k regular sectors */
- info->start[i] = base;
- base += 64 << 10;
- ++i;
- }
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
- /* set sector offsets for top boot block type */
- base += info->size;
- i = info->sector_count;
- for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
- base -= 8 << 10;
- --i;
- info->start[i] = base;
- }
- while (i > 0) { /* 64k regular sectors */
- base -= 64 << 10;
- --i;
- info->start[i] = base;
- }
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */
- for (i=0; i<50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- if (sect == s_first) {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- }
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
- while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- ulong *data_ptr = &data;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
- ulong start;
- int flag;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
- {
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2001-2004
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef FPGA_DEBUG
-#define DBG(x...) printf(x)
-#else
-#define DBG(x...)
-#endif /* DEBUG */
-
-#define MAX_ONES 226
-
-#ifdef CONFIG_SYS_FPGA_PRG
-# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output) */
-# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
-# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
-# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
-# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
-#else
-# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
-# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
-#endif
-
-#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
-#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
-#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
-
-#ifndef SET_FPGA
-# define SET_FPGA(data) out_be32((void *)GPIO0_OR, data)
-#endif
-
-#ifdef FPGA_PROG_ACTIVE_HIGH
-# define FPGA_PRG_LOW FPGA_PRG
-# define FPGA_PRG_HIGH 0
-#else
-# define FPGA_PRG_LOW 0
-# define FPGA_PRG_HIGH FPGA_PRG
-#endif
-
-#define FPGA_CLK_LOW 0
-#define FPGA_CLK_HIGH FPGA_CLK
-
-#define FPGA_DATA_LOW 0
-#define FPGA_DATA_HIGH FPGA_DATA
-
-#define FPGA_WRITE_1 { \
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
-
-#define FPGA_WRITE_0 { \
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
-
-#ifndef FPGA_DONE_STATE
-# define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE)
-#endif
-#ifndef FPGA_INIT_STATE
-# define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT)
-#endif
-
-
-static int fpga_boot (const unsigned char *fpgadata, int size)
-{
- int i, index, len;
- int count;
- unsigned char b;
-
-#ifdef CONFIG_SYS_FPGA_SPARTAN2
- int j;
-#else
- int bit;
-#endif
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = fpgadata[index];
- DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
- index += len + 3;
- }
-
-#ifdef CONFIG_SYS_FPGA_SPARTAN2
- /* search for preamble 0xFFFFFFFF */
- while (1) {
- if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
- && (fpgadata[index + 2] == 0xff)
- && (fpgadata[index + 3] == 0xff))
- break; /* preamble found */
- else
- index++;
- }
-#else
- /* search for preamble 0xFF2X */
- for (index = 0; index < size - 1; index++) {
- if ((fpgadata[index] == 0xff)
- && ((fpgadata[index + 1] & 0xf0) == 0x30))
- break;
- }
- index += 2;
-#endif
-
- DBG ("FPGA: configdata starts at position 0x%x\n", index);
- DBG ("FPGA: length of fpga-data %d\n", size - index);
-
- /*
- * Setup port pins for fpga programming
- */
-#ifndef CONFIG_M5249
- out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
- /* setup for output */
- out_be32 ((void *)GPIO0_TCR,
- in_be32 ((void *)GPIO0_TCR) |
- FPGA_PRG | FPGA_CLK | FPGA_DATA);
-#endif
- SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */
-
- DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
- DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
-
- /*
- * Init fpga by asserting and deasserting PROGRAM*
- */
- SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */
-
- /* Wait for FPGA init line low */
- count = 0;
- while (FPGA_INIT_STATE) {
- udelay (1000); /* wait 1ms */
- /* Check for timeout - 100us max, so use 3ms */
- if (count++ > 3) {
- DBG ("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_INIT_LOW;
- }
- }
-
- DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
- DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
-
- /* deassert PROGRAM* */
- SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */
-
- /* Wait for FPGA end of init period . */
- count = 0;
- while (!(FPGA_INIT_STATE)) {
- udelay (1000); /* wait 1ms */
- /* Check for timeout */
- if (count++ > 3) {
- DBG ("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_INIT_HIGH;
- }
- }
-
- DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
- DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
-
- DBG ("write configuration data into fpga\n");
- /* write configuration-data into fpga... */
-
-#ifdef CONFIG_SYS_FPGA_SPARTAN2
- /*
- * Load uncompressed image into fpga
- */
- for (i = index; i < size; i++) {
- b = fpgadata[i];
- for (j = 0; j < 8; j++) {
- if ((b & 0x80) == 0x80) {
- FPGA_WRITE_1;
- } else {
- FPGA_WRITE_0;
- }
- b <<= 1;
- }
- }
-#else
- /* send 0xff 0x20 */
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_0;
- FPGA_WRITE_0;
- FPGA_WRITE_1;
- FPGA_WRITE_0;
- FPGA_WRITE_0;
- FPGA_WRITE_0;
- FPGA_WRITE_0;
- FPGA_WRITE_0;
-
- /*
- ** Bit_DeCompression
- ** Code 1 .. maxOnes : n '1's followed by '0'
- ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
- ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
- ** 255 : '1'
- */
-
- for (i = index; i < size; i++) {
- b = fpgadata[i];
- if ((b >= 1) && (b <= MAX_ONES)) {
- for (bit = 0; bit < b; bit++) {
- FPGA_WRITE_1;
- }
- FPGA_WRITE_0;
- } else if (b == (MAX_ONES + 1)) {
- for (bit = 1; bit < b; bit++) {
- FPGA_WRITE_1;
- }
- } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
- for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
- FPGA_WRITE_0;
- }
- FPGA_WRITE_1;
- } else if (b == 255) {
- FPGA_WRITE_1;
- }
- }
-#endif
-
- DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
- DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
-
- /*
- * Check if fpga's DONE signal - correctly booted ?
- */
-
- /* Wait for FPGA end of programming period . */
- count = 0;
- while (!(FPGA_DONE_STATE)) {
- udelay (1000); /* wait 1ms */
- /* Check for timeout */
- if (count++ > 3) {
- DBG ("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_DONE;
- }
- }
-
- DBG ("FPGA: Booting successful!\n");
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2003-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/io.h>
-#include "lcd.h"
-
-
-extern int video_display_bitmap (ulong, int, int);
-
-
-int palette_index;
-int palette_value;
-int lcd_depth;
-unsigned char *glob_lcd_reg;
-unsigned char *glob_lcd_mem;
-
-#if defined(CONFIG_SYS_LCD_ENDIAN)
-void lcd_setup(int lcd, int config)
-{
- if (lcd == 0) {
- /*
- * Set endianess and reset lcd controller 0 (small)
- */
-
- /* set reset to low */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST);
- udelay(10); /* wait 10us */
- if (config == 1) {
- /* big-endian */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
- } else {
- /* little-endian */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
- }
- udelay(10); /* wait 10us */
- /* set reset to high */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST);
- } else {
- /*
- * Set endianess and reset lcd controller 1 (big)
- */
-
- /* set reset to low */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST);
- udelay(10); /* wait 10us */
- if (config == 1) {
- /* big-endian */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
- } else {
- /* little-endian */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
- }
- udelay(10); /* wait 10us */
- /* set reset to high */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST);
- }
-
- /*
- * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive
- */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
-}
-#endif /* CONFIG_SYS_LCD_ENDIAN */
-
-
-int lcd_bmp(uchar *logo_bmp)
-{
- int i;
- uchar *ptr;
- ushort *ptr2;
- ushort val;
- unsigned char *dst = NULL;
- int x, y;
- int width, height, bpp, colors, line_size;
- int header_size;
- unsigned char *bmp;
- unsigned char r, g, b;
- BITMAPINFOHEADER *bm_info;
- ulong len;
-
- /*
- * Check for bmp mark 'BM'
- */
- if (*(ushort *)logo_bmp != 0x424d) {
- /*
- * Decompress bmp image
- */
- len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
- dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
- if (dst == NULL) {
- printf("Error: malloc for gunzip failed!\n");
- return 1;
- }
- if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
- (uchar *)logo_bmp, &len) != 0) {
- free(dst);
- return 1;
- }
- if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
- printf("Image could be truncated"
- " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
- }
-
- /*
- * Check for bmp mark 'BM'
- */
- if (*(ushort *)dst != 0x424d) {
- printf("LCD: Unknown image format!\n");
- free(dst);
- return 1;
- }
- } else {
- /*
- * Uncompressed BMP image, just use this pointer
- */
- dst = (uchar *)logo_bmp;
- }
-
- /*
- * Get image info from bmp-header
- */
- bm_info = (BITMAPINFOHEADER *)(dst + 14);
- bpp = LOAD_SHORT(bm_info->biBitCount);
- width = LOAD_LONG(bm_info->biWidth);
- height = LOAD_LONG(bm_info->biHeight);
- switch (bpp) {
- case 1:
- colors = 1;
- line_size = width >> 3;
- break;
- case 4:
- colors = 16;
- line_size = width >> 1;
- break;
- case 8:
- colors = 256;
- line_size = width;
- break;
- case 24:
- colors = 0;
- line_size = width * 3;
- break;
- default:
- printf("LCD: Unknown bpp (%d) im image!\n", bpp);
- if ((dst != NULL) && (dst != (uchar *)logo_bmp))
- free(dst);
- return 1;
- }
- printf(" (%d*%d, %dbpp)\n", width, height, bpp);
-
- /*
- * Write color palette
- */
- if ((colors <= 256) && (lcd_depth <= 8)) {
- ptr = (unsigned char *)(dst + 14 + 40);
- for (i = 0; i < colors; i++) {
- b = *ptr++;
- g = *ptr++;
- r = *ptr++;
- ptr++;
- S1D_WRITE_PALETTE(glob_lcd_reg, i, r, g, b);
- }
- }
-
- /*
- * Write bitmap data into framebuffer
- */
- ptr = glob_lcd_mem;
- ptr2 = (ushort *)glob_lcd_mem;
- header_size = 14 + 40 + 4*colors; /* skip bmp header */
- for (y = 0; y < height; y++) {
- bmp = &dst[(height-1-y)*line_size + header_size];
- if (lcd_depth == 16) {
- if (bpp == 24) {
- for (x = 0; x < width; x++) {
- /*
- * Generate epson 16bpp fb-format
- * from 24bpp image
- */
- b = *bmp++ >> 3;
- g = *bmp++ >> 2;
- r = *bmp++ >> 3;
- val = ((r & 0x1f) << 11) |
- ((g & 0x3f) << 5) |
- (b & 0x1f);
- *ptr2++ = val;
- }
- } else if (bpp == 8) {
- for (x = 0; x < line_size; x++) {
- /* query rgb value from palette */
- ptr = (unsigned char *)(dst + 14 + 40);
- ptr += (*bmp++) << 2;
- b = *ptr++ >> 3;
- g = *ptr++ >> 2;
- r = *ptr++ >> 3;
- val = ((r & 0x1f) << 11) |
- ((g & 0x3f) << 5) |
- (b & 0x1f);
- *ptr2++ = val;
- }
- }
- } else {
- for (x = 0; x < line_size; x++)
- *ptr++ = *bmp++;
- }
- }
-
- if ((dst != NULL) && (dst != (uchar *)logo_bmp))
- free(dst);
- return 0;
-}
-
-
-int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
- uchar *logo_bmp, ulong len)
-{
- int i;
- ushort s1dReg;
- uchar s1dValue;
- int reg_byte_swap;
-
- /*
- * Detect epson
- */
- out_8(&lcd_reg[0], 0x00);
- out_8(&lcd_reg[1], 0x00);
-
- if (in_8(&lcd_reg[0]) == 0x1c) {
- /*
- * Big epson detected
- */
- reg_byte_swap = false;
- palette_index = 0x1e2;
- palette_value = 0x1e4;
- lcd_depth = 16;
- puts("LCD: S1D13806");
- } else if (in_8(&lcd_reg[1]) == 0x1c) {
- /*
- * Big epson detected (with register swap bug)
- */
- reg_byte_swap = true;
- palette_index = 0x1e3;
- palette_value = 0x1e5;
- lcd_depth = 16;
- puts("LCD: S1D13806S");
- } else if (in_8(&lcd_reg[0]) == 0x18) {
- /*
- * Small epson detected (704)
- */
- reg_byte_swap = false;
- palette_index = 0x15;
- palette_value = 0x17;
- lcd_depth = 8;
- puts("LCD: S1D13704");
- } else if (in_8(&lcd_reg[0x10000]) == 0x24) {
- /*
- * Small epson detected (705)
- */
- reg_byte_swap = false;
- palette_index = 0x15;
- palette_value = 0x17;
- lcd_depth = 8;
- lcd_reg += 0x10000; /* add offset for 705 regs */
- puts("LCD: S1D13705");
- } else {
- out_8(&lcd_reg[0x1a], 0x00);
- udelay(1000);
- if (in_8(&lcd_reg[1]) == 0x0c) {
- /*
- * S1D13505 detected
- */
- reg_byte_swap = true;
- palette_index = 0x25;
- palette_value = 0x27;
- lcd_depth = 16;
-
- puts("LCD: S1D13505");
- } else {
- puts("LCD: No controller detected!\n");
- return 1;
- }
- }
-
- /*
- * Setup lcd controller regs
- */
- for (i = 0; i < reg_count; i++) {
- s1dReg = regs[i].Index;
- if (reg_byte_swap) {
- if ((s1dReg & 0x0001) == 0)
- s1dReg |= 0x0001;
- else
- s1dReg &= ~0x0001;
- }
- s1dValue = regs[i].Value;
- out_8(&lcd_reg[s1dReg], s1dValue);
- }
-
- /*
- * Save reg & mem pointer for later usage (e.g. bmp command)
- */
- glob_lcd_reg = lcd_reg;
- glob_lcd_mem = lcd_mem;
-
- /*
- * Display bmp image
- */
- return lcd_bmp(logo_bmp);
-}
-
-int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr;
-#ifdef CONFIG_VIDEO_SM501
- char *str;
-#endif
- if (argc != 2)
- return cmd_usage(cmdtp);
-
- addr = simple_strtoul(argv[1], NULL, 16);
-
-#ifdef CONFIG_VIDEO_SM501
- str = getenv("bd_type");
- if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) {
- /*
- * SM501 available, use standard bmp command
- */
- return video_display_bitmap(addr, 0, 0);
- } else {
- /*
- * No SM501 available, use esd epson bmp command
- */
- return lcd_bmp((uchar *)addr);
- }
-#else
- return lcd_bmp((uchar *)addr);
-#endif
-}
-
-U_BOOT_CMD(
- esdbmp, 2, 1, do_esdbmp,
- "display BMP image",
- "<imageAddr> - display image"
-);
+++ /dev/null
-/*
- * (C) Copyright 2003-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Neutralize little endians.
- */
-#define SWAP_LONG(data) ((unsigned long) \
- (((unsigned long)(data) >> 24) | \
- ((unsigned long)(data) << 24) | \
- (((unsigned long)(data) >> 8) & 0x0000ff00 ) | \
- (((unsigned long)(data) << 8) & 0x00ff0000 )))
-#define SWAP_SHORT(data) ((unsigned short) \
- (((unsigned short)(data) >> 8 ) | \
- ((unsigned short)(data) << 8 )))
-#define LOAD_LONG(data) SWAP_LONG(data)
-#define LOAD_SHORT(data) SWAP_SHORT(data)
-
-#define S1D_WRITE_PALETTE(p,i,r,g,b) \
- { \
- out_8(&((uchar*)(p))[palette_index], (uchar)(i)); \
- out_8(&((uchar*)(p))[palette_index], (uchar)(r)); \
- out_8(&((uchar*)(p))[palette_index], (uchar)(g)); \
- out_8(&((uchar*)(p))[palette_index], (uchar)(b)); \
- }
-
-typedef struct
-{
- ushort Index;
- uchar Value;
-} S1D_REGS;
-
-typedef struct /**** BMP file info structure ****/
-{
- unsigned int biSize; /* Size of info header */
- int biWidth; /* Width of image */
- int biHeight; /* Height of image */
- unsigned short biPlanes; /* Number of color planes */
- unsigned short biBitCount; /* Number of bits per pixel */
- unsigned int biCompression; /* Type of compression to use */
- unsigned int biSizeImage; /* Size of image data */
- int biXPelsPerMeter; /* X pixels per meter */
- int biYPelsPerMeter; /* Y pixels per meter */
- unsigned int biClrUsed; /* Number of colors used */
- unsigned int biClrImportant; /* Number of important colors */
-} BITMAPINFOHEADER;
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#ifdef CONFIG_LXT971_NO_SLEEP
-#include <miiphy.h>
-#endif
-
-
-#ifdef CONFIG_LXT971_NO_SLEEP
-void lxt971_no_sleep(void)
-{
- unsigned short reg;
-
- miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, ®);
- reg &= ~0x0040; /* disable sleep mode */
- miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
-}
-#endif /* CONFIG_LXT971_NO_SLEEP */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <pci.h>
-
-
-u_long pci9054_iobase;
-
-
-#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */
-#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */
-
-
-/*-----------------------------------------------------------------------------+
-| Subroutine: pci9054_read_config_dword
-| Description: Read a PCI configuration register
-| Inputs:
-| hose PCI Controller
-| dev PCI Bus+Device+Function number
-| offset Configuration register number
-| value Address of the configuration register value
-| Return value:
-| 0 Successful
-+-----------------------------------------------------------------------------*/
-int pci9054_read_config_dword(struct pci_controller *hose,
- pci_dev_t dev, int offset, u32* value)
-{
- unsigned long conAdrVal;
- unsigned long val;
-
- /* generate coded value for CON_ADR register */
- conAdrVal = dev | (offset & 0xfc) | 0x80000000;
-
- /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
- *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
-
- /* Note: *pResult comes back as -1 if machine check happened */
- val = in32r(PCI_PRIMARY_CDR);
-
- *value = (unsigned long) val;
-
- out32r(PCI_PRIMARY_CAR, 0);
-
- if ((*(unsigned long *)0x50000304) & 0x60000000)
- {
- /* clear pci master/target abort bits */
- *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
- }
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------------+
-| Subroutine: pci9054_write_config_dword
-| Description: Write a PCI configuration register.
-| Inputs:
-| hose PCI Controller
-| dev PCI Bus+Device+Function number
-| offset Configuration register number
-| Value Configuration register value
-| Return value:
-| 0 Successful
-| Updated for pass2 errata #6. Need to disable interrupts and clear the
-| PCICFGADR reg after writing the PCICFGDATA reg.
-+-----------------------------------------------------------------------------*/
-int pci9054_write_config_dword(struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 value)
-{
- unsigned long conAdrVal;
-
- conAdrVal = dev | (offset & 0xfc) | 0x80000000;
-
- *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
-
- out32r(PCI_PRIMARY_CDR, value);
-
- out32r(PCI_PRIMARY_CAR, 0);
-
- /* clear pci master/target abort bits */
- *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-#ifdef CONFIG_DASA_SIM
-static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *_)
-{
- unsigned int iobase;
- unsigned short status = 0;
- unsigned char timer;
-
- /*
- * Configure PLX PCI9054
- */
- pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
- status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
- pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
-
- /* Check the latency timer for values >= 0x60.
- */
- pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
- if (timer < 0x60)
- {
- pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
- }
-
- /* Set I/O base register.
- */
- pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
- pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
-
- pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
-
- if (pci9054_iobase == 0xffffffff)
- {
- printf("Error: Can not set I/O base register.\n");
- return;
- }
-}
-#endif
-
-static struct pci_config_table pci9054_config_table[] = {
-#ifndef CONFIG_PCI_PNP
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
- pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
- CONFIG_SYS_ETH_IOBASE,
- PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
-#ifdef CONFIG_DASA_SIM
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
- pci_dasa_sim_config_pci9054 },
-#endif
-#endif
- { }
-};
-
-static struct pci_controller pci9054_hose = {
- config_table: pci9054_config_table,
-};
-
-void pci_init_board(void)
-{
- struct pci_controller *hose = &pci9054_hose;
-
- /*
- * Register the hose
- */
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* System memory space */
- pci_set_region(hose->regions + 0,
- 0x00000000, 0x00000000, 0x01000000,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI Memory space */
- pci_set_region(hose->regions + 1,
- 0x00000000, 0xc0000000, 0x10000000,
- PCI_REGION_MEM);
-
- pci_set_ops(hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- pci9054_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- pci9054_write_config_dword);
-
- hose->region_count = 2;
-
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz)
- * Memory: DRAM (MCLK=40.000 MHz)
- */
-static S1D_REGS regs_13505_640_480_16bpp[] =
-{
- {0x1B,0x00}, /* Miscellaneous Register */
- {0x23,0x20}, /* Performance Enhancement Register 1 */
- {0x01,0x30}, /* Memory Configuration Register */
- {0x22,0x24}, /* Performance Enhancement Register 0 */
- {0x02,0x25}, /* Panel Type Register */
- {0x03,0x00}, /* MOD Rate Register */
- {0x04,0x4F}, /* Horizontal Display Width Register */
- {0x05,0x0c}, /* Horizontal Non-Display Period Register */
- {0x06,0x00}, /* HRTC/FPLINE Start Position Register */
- {0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */
- {0x08,0xDF}, /* Vertical Display Height Register 0 */
- {0x09,0x01}, /* Vertical Display Height Register 1 */
- {0x0A,0x3E}, /* Vertical Non-Display Period Register */
- {0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */
- {0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */
- {0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */
- {0x0F,0x03}, /* Screen 1 Line Compare Register 1 */
- {0x10,0x00}, /* Screen 1 Display Start Address Register 0 */
- {0x11,0x00}, /* Screen 1 Display Start Address Register 1 */
- {0x12,0x00}, /* Screen 1 Display Start Address Register 2 */
- {0x13,0x00}, /* Screen 2 Display Start Address Register 0 */
- {0x14,0x00}, /* Screen 2 Display Start Address Register 1 */
- {0x15,0x00}, /* Screen 2 Display Start Address Register 2 */
- {0x16,0x80}, /* Memory Address Offset Register 0 */
- {0x17,0x02}, /* Memory Address Offset Register 1 */
- {0x18,0x00}, /* Pixel Panning Register */
- {0x19,0x01}, /* Clock Configuration Register */
- {0x1A,0x00}, /* Power Save Configuration Register */
- {0x1C,0x00}, /* MD Configuration Readback Register 0 */
- {0x1E,0x06}, /* General IO Pins Configuration Register 0 */
- {0x1F,0x00}, /* General IO Pins Configuration Register 1 */
- {0x20,0x00}, /* General IO Pins Control Register 0 */
- {0x21,0x00}, /* General IO Pins Control Register 1 */
- {0x23,0x20}, /* Performance Enhancement Register 1 */
- {0x0D,0x15}, /* Display Mode Register */
-};
+++ /dev/null
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Generic Header information generated by 13704CFG.EXE (Build 10)
- * Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
- */
-
-static S1D_REGS regs_13704_320_240_4bpp[] =
-{
- { 0x00, 0x00 }, /* Revision Code Register */
- { 0x01, 0x04 }, /*00*/ /* Mode Register 0 Register */
- { 0x02, 0xA4 }, /*a0*/ /* Mode Register 1 Register */
- { 0x03, 0x83 }, /*03*/ /* Mode Register 2 Register - bit7 is LUT bypass */
- { 0x04, 0x27 }, /* Horizontal Panel Size Register */
- { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */
- { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */
- { 0x07, 0x00 }, /* FPLINE Start Position Register */
- { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */
- { 0x09, 0x00 }, /* FPFRAME Start Position Register */
- { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */
- { 0x0B, 0x00 }, /* MOD Rate Register */
- { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */
- { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */
- { 0x0E, 0x00 }, /* Not Used */
- { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */
- { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */
- { 0x11, 0x00 }, /* Not Used */
- { 0x12, 0x00 }, /* Memory Address Offset Register */
- { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */
- { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */
- { 0x15, 0x00 }, /* Look-Up Table Address Register */
- { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */
- { 0x17, 0x00 }, /* Look-Up Table Data Register */
- { 0x18, 0x01 }, /* GPIO Configuration Control Register */
- { 0x19, 0x01 }, /* GPIO Status/Control Register */
- { 0x1A, 0x00 }, /* Scratch Pad Register */
- { 0x1B, 0x00 }, /* SwivelView Mode Register */
- { 0x1C, 0xA0 }, /* Line Byte Count Register */
- { 0x1D, 0x00 }, /* Not Used */
- { 0x1E, 0x00 }, /* Not Used */
- { 0x1F, 0x00 }, /* Not Used */
-};
+++ /dev/null
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Generic Header information generated by 13704CFG.EXE (Build 10)
- * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
- */
-
-static S1D_REGS regs_13705_320_240_8bpp[] =
-{
- { 0x00, 0x00 }, /* Revision Code Register */
- { 0x01, 0x23 }, /* Mode Register 0 Register */
- { 0x02, 0xE0 }, /* Mode Register 1 Register */
- { 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */
- { 0x04, 0x27 }, /* Horizontal Panel Size Register */
- { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */
- { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */
- { 0x07, 0x00 }, /* FPLINE Start Position Register */
- { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */
- { 0x09, 0x01 }, /* FPFRAME Start Position Register */
- { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */
- { 0x0B, 0x00 }, /* MOD Rate Register */
- { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */
- { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */
- { 0x0E, 0x00 }, /* Not Used */
- { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */
- { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */
- { 0x11, 0x00 }, /* Not Used */
- { 0x12, 0x00 }, /* Memory Address Offset Register */
- { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */
- { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */
- { 0x15, 0x00 }, /* Look-Up Table Address Register */
- { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */
- { 0x17, 0x00 }, /* Look-Up Table Data Register */
- { 0x18, 0x01 }, /* GPIO Configuration Control Register */
- { 0x19, 0x01 }, /* GPIO Status/Control Register */
- { 0x1A, 0x00 }, /* Scratch Pad Register */
- { 0x1B, 0x00 }, /* SwivelView Mode Register */
- { 0x1C, 0xFF }, /* Line Byte Count Register */
- { 0x1D, 0x00 }, /* Not Used */
- { 0x1E, 0x00 }, /* Not Used */
- { 0x1F, 0x00 }, /* Not Used */
-};
+++ /dev/null
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * File generated by S1D13806CFG.EXE
- * Panel: (active) 1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
- */
-
-static S1D_REGS regs_13806_1024_768_8bpp[] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x00}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
- {0x0008,0x00}, /* General IO Pins Control Register 0 */
- {0x0009,0x00}, /* General IO Pins Control Register 1 */
- {0x0010,0x00}, /* Memory Clock Configuration Register */
- {0x0014,0x01}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x03}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x55}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x7F}, /* LCD Horizontal Display Width Register */
- {0x0034,0x12}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x01}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xFF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x02}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x03}, /* LCD Display Mode Register */
- {0x0041,0x00}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x00}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x10}, /* TV Output Control Register */
- {0x0060,0x03}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01F0,0x10}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
-};
+++ /dev/null
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * File generated by S1D13806CFG.EXE
- * Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz)
- */
-
-static S1D_REGS regs_13806_320_240_4bpp[] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x08}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x08}, /* General IO Pins Configuration Register 1 */
- {0x0008,0x08}, /* General IO Pins Control Register 0 */
- {0x0009,0x00}, /* General IO Pins Control Register 1 */
- {0x0010,0x00}, /* Memory Clock Configuration Register */
- {0x0014,0x32}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x03}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x00}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x27}, /* LCD Horizontal Display Width Register */
- {0x0034,0x03}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x01}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xEF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x00}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x02}, /* LCD Display Mode Register */
- {0x0041,0x00}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x50}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x00}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x10}, /* TV Output Control Register */
- {0x0060,0x03}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01F0,0x10}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
-};
+++ /dev/null
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * File generated by S1D13806CFG.EXE
- * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
- */
-
-static S1D_REGS regs_13806_640_480_16bpp[] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x18}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
- {0x0008,0x18}, /* General IO Pins Control Register 0 */
- {0x0009,0x00}, /* General IO Pins Control Register 1 */
- {0x0010,0x00}, /* Memory Clock Configuration Register */
- {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x03}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x25}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
- {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x00}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x00}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x05}, /* LCD Display Mode Register */
- {0x0041,0x00}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x10}, /* TV Output Control Register */
- {0x0060,0x05}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01F0,0x10}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
-};
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*******************************************************/
-/* file: lenval.c */
-/* abstract: This file contains routines for using */
-/* the lenVal data structure. */
-/*******************************************************/
-
-#include <common.h>
-#include <asm/processor.h>
-
-#include "lenval.h"
-#include "ports.h"
-
-
-/*****************************************************************************
- * Function: value
- * Description: Extract the long value from the lenval array.
- * Parameters: plvValue - ptr to lenval.
- * Returns: long - the extracted value.
- *****************************************************************************/
-long value( lenVal* plvValue )
-{
- long lValue; /* result to hold the accumulated result */
- short sIndex;
-
- lValue = 0;
- for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex )
- {
- lValue <<= 8; /* shift the accumulated result */
- lValue |= plvValue->val[ sIndex]; /* get the last byte first */
- }
-
- return( lValue );
-}
-
-/*****************************************************************************
- * Function: initLenVal
- * Description: Initialize the lenval array with the given value.
- * Assumes lValue is less than 256.
- * Parameters: plv - ptr to lenval.
- * lValue - the value to set.
- * Returns: void.
- *****************************************************************************/
-void initLenVal( lenVal* plv,
- long lValue )
-{
- plv->len = 1;
- plv->val[0] = (unsigned char)lValue;
-}
-
-/*****************************************************************************
- * Function: EqualLenVal
- * Description: Compare two lenval arrays with an optional mask.
- * Parameters: plvTdoExpected - ptr to lenval #1.
- * plvTdoCaptured - ptr to lenval #2.
- * plvTdoMask - optional ptr to mask (=0 if no mask).
- * Returns: short - 0 = mismatch; 1 = equal.
- *****************************************************************************/
-short EqualLenVal( lenVal* plvTdoExpected,
- lenVal* plvTdoCaptured,
- lenVal* plvTdoMask )
-{
- short sEqual;
- short sIndex;
- unsigned char ucByteVal1;
- unsigned char ucByteVal2;
- unsigned char ucByteMask;
-
- sEqual = 1;
- sIndex = plvTdoExpected->len;
-
- while ( sEqual && sIndex-- )
- {
- ucByteVal1 = plvTdoExpected->val[ sIndex ];
- ucByteVal2 = plvTdoCaptured->val[ sIndex ];
- if ( plvTdoMask )
- {
- ucByteMask = plvTdoMask->val[ sIndex ];
- ucByteVal1 &= ucByteMask;
- ucByteVal2 &= ucByteMask;
- }
- if ( ucByteVal1 != ucByteVal2 )
- {
- sEqual = 0;
- }
- }
-
- return( sEqual );
-}
-
-
-/*****************************************************************************
- * Function: RetBit
- * Description: return the (byte, bit) of lv (reading from left to right).
- * Parameters: plv - ptr to lenval.
- * iByte - the byte to get the bit from.
- * iBit - the bit number (0=msb)
- * Returns: short - the bit value.
- *****************************************************************************/
-short RetBit( lenVal* plv,
- int iByte,
- int iBit )
-{
- /* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
- /* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
- return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) );
-}
-
-/*****************************************************************************
- * Function: SetBit
- * Description: set the (byte, bit) of lv equal to val
- * Example: SetBit("00000000",byte, 1) equals "01000000".
- * Parameters: plv - ptr to lenval.
- * iByte - the byte to get the bit from.
- * iBit - the bit number (0=msb).
- * sVal - the bit value to set.
- * Returns: void.
- *****************************************************************************/
-void SetBit( lenVal* plv,
- int iByte,
- int iBit,
- short sVal )
-{
- unsigned char ucByteVal;
- unsigned char ucBitMask;
-
- ucBitMask = (unsigned char)(1 << ( 7 - iBit ));
- ucByteVal = (unsigned char)(plv->val[ iByte ] & (~ucBitMask));
-
- if ( sVal )
- {
- ucByteVal |= ucBitMask;
- }
- plv->val[ iByte ] = ucByteVal;
-}
-
-/*****************************************************************************
- * Function: AddVal
- * Description: add val1 to val2 and store in resVal;
- * assumes val1 and val2 are of equal length.
- * Parameters: plvResVal - ptr to result.
- * plvVal1 - ptr of addendum.
- * plvVal2 - ptr of addendum.
- * Returns: void.
- *****************************************************************************/
-void addVal( lenVal* plvResVal,
- lenVal* plvVal1,
- lenVal* plvVal2 )
-{
- unsigned char ucCarry;
- unsigned short usSum;
- unsigned short usVal1;
- unsigned short usVal2;
- short sIndex;
-
- plvResVal->len = plvVal1->len; /* set up length of result */
-
- /* start at least significant bit and add bytes */
- ucCarry = 0;
- sIndex = plvVal1->len;
- while ( sIndex-- )
- {
- usVal1 = plvVal1->val[ sIndex ]; /* i'th byte of val1 */
- usVal2 = plvVal2->val[ sIndex ]; /* i'th byte of val2 */
-
- /* add the two bytes plus carry from previous addition */
- usSum = (unsigned short)( usVal1 + usVal2 + ucCarry );
-
- /* set up carry for next byte */
- ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 );
-
- /* set the i'th byte of the result */
- plvResVal->val[ sIndex ] = (unsigned char)usSum;
- }
-}
-
-/*****************************************************************************
- * Function: readVal
- * Description: read from XSVF numBytes bytes of data into x.
- * Parameters: plv - ptr to lenval in which to put the bytes read.
- * sNumBytes - the number of bytes to read.
- * Returns: void.
- *****************************************************************************/
-void readVal( lenVal* plv,
- short sNumBytes )
-{
- unsigned char* pucVal;
-
- plv->len = sNumBytes; /* set the length of the lenVal */
- for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal )
- {
- /* read a byte of data into the lenVal */
- readByte( pucVal );
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*******************************************************/
-/* file: lenval.h */
-/* abstract: This file contains a description of the */
-/* data structure "lenval". */
-/*******************************************************/
-
-#ifndef lenval_dot_h
-#define lenval_dot_h
-
-/* the lenVal structure is a byte oriented type used to store an */
-/* arbitrary length binary value. As an example, the hex value */
-/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes */
-/* and val[0]=0e and val[1]=3d. val[2-MAX_LEN] are undefined */
-
-/* maximum length (in bytes) of value to read in */
-/* this needs to be at least 4, and longer than the */
-/* length of the longest SDR instruction. If there is, */
-/* only 1 device in the chain, MAX_LEN must be at least */
-/* ceil(27/8) == 4. For 6 devices in a chain, MAX_LEN */
-/* must be 5, for 14 devices MAX_LEN must be 6, for 20 */
-/* devices MAX_LEN must be 7, etc.. */
-/* You can safely set MAX_LEN to a smaller number if you*/
-/* know how many devices will be in your chain. */
-#define MAX_LEN 7000
-
-
-typedef struct var_len_byte
-{
- short len; /* number of chars in this value */
- unsigned char val[MAX_LEN+1]; /* bytes of data */
-} lenVal;
-
-
-/* return the long representation of a lenVal */
-extern long value(lenVal *x);
-
-/* set lenVal equal to value */
-extern void initLenVal(lenVal *x, long value);
-
-/* check if expected equals actual (taking the mask into account) */
-extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask);
-
-/* add val1+val2 and put the result in resVal */
-extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2);
-
-/* return the (byte, bit) of lv (reading from left to right) */
-extern short RetBit(lenVal *lv, int byte, int bit);
-
-/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1)
- equals "01000000" */
-extern void SetBit(lenVal *lv, int byte, int bit, short val);
-
-/* read from XSVF numBytes bytes of data into x */
-extern void readVal(lenVal *x, short numBytes);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*****************************************************************************
- * file: micro.c
- * abstract: This file contains the function, xsvfExecute(),
- * call for interpreting the XSVF commands.
- * Usage: Call xsvfExecute() to process XSVF data.
- * The XSVF data is retrieved by readByte() in ports.c
- * Remove the main function if you already have one.
- * Options: XSVF_SUPPORT_COMPRESSION
- * This define supports the XC9500/XL compression scheme.
- * This define adds support for XSDRINC and XSETSDRMASKS.
- * XSVF_SUPPORT_ERRORCODES
- * This define causes the xsvfExecute function to return
- * an error code for specific errors. See error codes below.
- * If this is not defined, the return value defaults to the
- * legacy values for backward compatibility:
- * 1 = success; 0 = failure.
- * Debugging: DEBUG_MODE (Legacy name)
- * Define DEBUG_MODE to compile with debugging features.
- * Both micro.c and ports.c must be compiled with the DEBUG_MODE
- * defined to enable the standalone main implementation in
- * micro.c that reads XSVF from a file.
- * History: v2.00 - Original XSVF implementation.
- * v4.04 - Added delay at end of XSIR for XC18v00 support.
- * Added new commands for CoolRunner support:
- * XSTATE, XENDIR, XENDDR
- * v4.05 - Cleanup micro.c but leave ports.c intact.
- * v4.06 - Fix xsvfGotoTapState for retry transition.
- * v4.07 - Update example waitTime implementations for
- * compatibility with Virtex-II.
- * v4.10 - Add new XSIR2 command that supports a 2-byte
- * IR-length parameter for IR shifts > 255 bits.
- * v4.11 - No change. Update version to match SVF2XSVF xlator.
- * v4.14 - Added XCOMMENT.
- * v5.00 - Improve XSTATE support.
- * Added XWAIT.
- *****************************************************************************/
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-
-#include "micro.h"
-#include "lenval.h"
-#include "ports.h"
-
-const unsigned char *xsvfdata;
-
-/*============================================================================
- * XSVF #define
- ============================================================================*/
-
-#define XSVF_VERSION "5.00"
-
-/*****************************************************************************
- * Define: XSVF_SUPPORT_COMPRESSION
- * Description: Define this to support the XC9500/XL XSVF data compression
- * scheme.
- * Code size can be reduced by NOT supporting this feature.
- * However, you must use the -nc (no compress) option when
- * translating SVF to XSVF using the SVF2XSVF translator.
- * Corresponding, uncompressed XSVF may be larger.
- *****************************************************************************/
-#ifndef XSVF_SUPPORT_COMPRESSION
-#define XSVF_SUPPORT_COMPRESSION 1
-#endif
-
-/*****************************************************************************
- * Define: XSVF_SUPPORT_ERRORCODES
- * Description: Define this to support the new XSVF error codes.
- * (The original XSVF player just returned 1 for success and
- * 0 for an unspecified failure.)
- *****************************************************************************/
-#ifndef XSVF_SUPPORT_ERRORCODES
-#define XSVF_SUPPORT_ERRORCODES 1
-#endif
-
-#ifdef XSVF_SUPPORT_ERRORCODES
-#define XSVF_ERRORCODE(errorCode) errorCode
-#else /* Use legacy error code */
-#define XSVF_ERRORCODE(errorCode) ((errorCode==XSVF_ERROR_NONE)?1:0)
-#endif /* XSVF_SUPPORT_ERRORCODES */
-
-
-/*============================================================================
- * DEBUG_MODE #define
- ============================================================================*/
-#define DEBUG_MODE
-
-#ifdef DEBUG_MODE
-#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat ); }
-#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat, arg1 ); }
-#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat, arg1, arg2 ); }
-#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat, arg1, arg2, arg3 ); }
-#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- xsvfPrintLenVal(plenVal); }
-#else /* !DEBUG_MODE */
-#define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
-#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
-#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2)
-#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3)
-#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal)
-#endif /* DEBUG_MODE */
-
-
-/*============================================================================
- * XSVF Type Declarations
- ============================================================================*/
-
-/*****************************************************************************
- * Struct: SXsvfInfo
- * Description: This structure contains all of the data used during the
- * execution of the XSVF. Some data is persistent, predefined
- * information (e.g. lRunTestTime). The bulk of this struct's
- * size is due to the lenVal structs (defined in lenval.h)
- * which contain buffers for the active shift data. The MAX_LEN
- * #define in lenval.h defines the size of these buffers.
- * These buffers must be large enough to store the longest
- * shift data in your XSVF file. For example:
- * MAX_LEN >= ( longest_shift_data_in_bits / 8 )
- * Because the lenVal struct dominates the space usage of this
- * struct, the rough size of this struct is:
- * sizeof( SXsvfInfo ) ~= MAX_LEN * 7 (number of lenVals)
- * xsvfInitialize() contains initialization code for the data
- * in this struct.
- * xsvfCleanup() contains cleanup code for the data in this
- * struct.
- *****************************************************************************/
-typedef struct tagSXsvfInfo
-{
- /* XSVF status information */
- unsigned char ucComplete; /* 0 = running; 1 = complete */
- unsigned char ucCommand; /* Current XSVF command byte */
- long lCommandCount; /* Number of commands processed */
- int iErrorCode; /* An error code. 0 = no error. */
-
- /* TAP state/sequencing information */
- unsigned char ucTapState; /* Current TAP state */
- unsigned char ucEndIR; /* ENDIR TAP state (See SVF) */
- unsigned char ucEndDR; /* ENDDR TAP state (See SVF) */
-
- /* RUNTEST information */
- unsigned char ucMaxRepeat; /* Max repeat loops (for xc9500/xl) */
- long lRunTestTime; /* Pre-specified RUNTEST time (usec) */
-
- /* Shift Data Info and Buffers */
- long lShiftLengthBits; /* Len. current shift data in bits */
- short sShiftLengthBytes; /* Len. current shift data in bytes */
-
- lenVal lvTdi; /* Current TDI shift data */
- lenVal lvTdoExpected; /* Expected TDO shift data */
- lenVal lvTdoCaptured; /* Captured TDO shift data */
- lenVal lvTdoMask; /* TDO mask: 0=dontcare; 1=compare */
-
-#ifdef XSVF_SUPPORT_COMPRESSION
- /* XSDRINC Data Buffers */
- lenVal lvAddressMask; /* Address mask for XSDRINC */
- lenVal lvDataMask; /* Data mask for XSDRINC */
- lenVal lvNextData; /* Next data for XSDRINC */
-#endif /* XSVF_SUPPORT_COMPRESSION */
-} SXsvfInfo;
-
-/* Declare pointer to functions that perform XSVF commands */
-typedef int (*TXsvfDoCmdFuncPtr)( SXsvfInfo* );
-
-/*============================================================================
- * XSVF Command Bytes
- ============================================================================*/
-
-/* encodings of xsvf instructions */
-#define XCOMPLETE 0
-#define XTDOMASK 1
-#define XSIR 2
-#define XSDR 3
-#define XRUNTEST 4
-/* Reserved 5 */
-/* Reserved 6 */
-#define XREPEAT 7
-#define XSDRSIZE 8
-#define XSDRTDO 9
-#define XSETSDRMASKS 10
-#define XSDRINC 11
-#define XSDRB 12
-#define XSDRC 13
-#define XSDRE 14
-#define XSDRTDOB 15
-#define XSDRTDOC 16
-#define XSDRTDOE 17
-#define XSTATE 18 /* 4.00 */
-#define XENDIR 19 /* 4.04 */
-#define XENDDR 20 /* 4.04 */
-#define XSIR2 21 /* 4.10 */
-#define XCOMMENT 22 /* 4.14 */
-#define XWAIT 23 /* 5.00 */
-/* Insert new commands here */
-/* and add corresponding xsvfDoCmd function to xsvf_pfDoCmd below. */
-#define XLASTCMD 24 /* Last command marker */
-
-
-/*============================================================================
- * XSVF Command Parameter Values
- ============================================================================*/
-
-#define XSTATE_RESET 0 /* 4.00 parameter for XSTATE */
-#define XSTATE_RUNTEST 1 /* 4.00 parameter for XSTATE */
-
-#define XENDXR_RUNTEST 0 /* 4.04 parameter for XENDIR/DR */
-#define XENDXR_PAUSE 1 /* 4.04 parameter for XENDIR/DR */
-
-/* TAP states */
-#define XTAPSTATE_RESET 0x00
-#define XTAPSTATE_RUNTEST 0x01 /* a.k.a. IDLE */
-#define XTAPSTATE_SELECTDR 0x02
-#define XTAPSTATE_CAPTUREDR 0x03
-#define XTAPSTATE_SHIFTDR 0x04
-#define XTAPSTATE_EXIT1DR 0x05
-#define XTAPSTATE_PAUSEDR 0x06
-#define XTAPSTATE_EXIT2DR 0x07
-#define XTAPSTATE_UPDATEDR 0x08
-#define XTAPSTATE_IRSTATES 0x09 /* All IR states begin here */
-#define XTAPSTATE_SELECTIR 0x09
-#define XTAPSTATE_CAPTUREIR 0x0A
-#define XTAPSTATE_SHIFTIR 0x0B
-#define XTAPSTATE_EXIT1IR 0x0C
-#define XTAPSTATE_PAUSEIR 0x0D
-#define XTAPSTATE_EXIT2IR 0x0E
-#define XTAPSTATE_UPDATEIR 0x0F
-
-/*============================================================================
- * XSVF Function Prototypes
- ============================================================================*/
-
-int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo ); /* Illegal command function */
-int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo );
-int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSIR( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDR( SXsvfInfo* pXsvfInfo );
-int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo );
-int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo );
-int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo );
-int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo );
-int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo );
-/* Insert new command functions here */
-
-/*============================================================================
- * XSVF Global Variables
- ============================================================================*/
-
-/* Array of XSVF command functions. Must follow command byte value order! */
-/* If your compiler cannot take this form, then convert to a switch statement*/
-TXsvfDoCmdFuncPtr xsvf_pfDoCmd[] =
-{
- xsvfDoXCOMPLETE, /* 0 */
- xsvfDoXTDOMASK, /* 1 */
- xsvfDoXSIR, /* 2 */
- xsvfDoXSDR, /* 3 */
- xsvfDoXRUNTEST, /* 4 */
- xsvfDoIllegalCmd, /* 5 */
- xsvfDoIllegalCmd, /* 6 */
- xsvfDoXREPEAT, /* 7 */
- xsvfDoXSDRSIZE, /* 8 */
- xsvfDoXSDRTDO, /* 9 */
-#ifdef XSVF_SUPPORT_COMPRESSION
- xsvfDoXSETSDRMASKS, /* 10 */
- xsvfDoXSDRINC, /* 11 */
-#else
- xsvfDoIllegalCmd, /* 10 */
- xsvfDoIllegalCmd, /* 11 */
-#endif /* XSVF_SUPPORT_COMPRESSION */
- xsvfDoXSDRBCE, /* 12 */
- xsvfDoXSDRBCE, /* 13 */
- xsvfDoXSDRBCE, /* 14 */
- xsvfDoXSDRTDOBCE, /* 15 */
- xsvfDoXSDRTDOBCE, /* 16 */
- xsvfDoXSDRTDOBCE, /* 17 */
- xsvfDoXSTATE, /* 18 */
- xsvfDoXENDXR, /* 19 */
- xsvfDoXENDXR, /* 20 */
- xsvfDoXSIR2, /* 21 */
- xsvfDoXCOMMENT, /* 22 */
- xsvfDoXWAIT /* 23 */
-/* Insert new command functions here */
-};
-
-#ifdef DEBUG_MODE
-char* xsvf_pzCommandName[] =
-{
- "XCOMPLETE",
- "XTDOMASK",
- "XSIR",
- "XSDR",
- "XRUNTEST",
- "Reserved5",
- "Reserved6",
- "XREPEAT",
- "XSDRSIZE",
- "XSDRTDO",
- "XSETSDRMASKS",
- "XSDRINC",
- "XSDRB",
- "XSDRC",
- "XSDRE",
- "XSDRTDOB",
- "XSDRTDOC",
- "XSDRTDOE",
- "XSTATE",
- "XENDIR",
- "XENDDR",
- "XSIR2",
- "XCOMMENT",
- "XWAIT"
-};
-
-char* xsvf_pzErrorName[] =
-{
- "No error",
- "ERROR: Unknown",
- "ERROR: TDO mismatch",
- "ERROR: TDO mismatch and exceeded max retries",
- "ERROR: Unsupported XSVF command",
- "ERROR: Illegal state specification",
- "ERROR: Data overflows allocated MAX_LEN buffer size"
-};
-
-char* xsvf_pzTapState[] =
-{
- "RESET", /* 0x00 */
- "RUNTEST/IDLE", /* 0x01 */
- "DRSELECT", /* 0x02 */
- "DRCAPTURE", /* 0x03 */
- "DRSHIFT", /* 0x04 */
- "DREXIT1", /* 0x05 */
- "DRPAUSE", /* 0x06 */
- "DREXIT2", /* 0x07 */
- "DRUPDATE", /* 0x08 */
- "IRSELECT", /* 0x09 */
- "IRCAPTURE", /* 0x0A */
- "IRSHIFT", /* 0x0B */
- "IREXIT1", /* 0x0C */
- "IRPAUSE", /* 0x0D */
- "IREXIT2", /* 0x0E */
- "IRUPDATE" /* 0x0F */
-};
-#endif /* DEBUG_MODE */
-
-/*#ifdef DEBUG_MODE */
-/* FILE* in; /XXX* Legacy DEBUG_MODE file pointer */
-int xsvf_iDebugLevel;
-/*#endif /XXX* DEBUG_MODE */
-
-/*============================================================================
- * Utility Functions
- ============================================================================*/
-
-/*****************************************************************************
- * Function: xsvfPrintLenVal
- * Description: Print the lenval value in hex.
- * Parameters: plv - ptr to lenval.
- * Returns: void.
- *****************************************************************************/
-#ifdef DEBUG_MODE
-void xsvfPrintLenVal( lenVal *plv )
-{
- int i;
-
- if ( plv )
- {
- printf( "0x" );
- for ( i = 0; i < plv->len; ++i )
- {
- printf( "%02x", ((unsigned int)(plv->val[ i ])) );
- }
- }
-}
-#endif /* DEBUG_MODE */
-
-
-/*****************************************************************************
- * Function: xsvfInfoInit
- * Description: Initialize the xsvfInfo data.
- * Parameters: pXsvfInfo - ptr to the XSVF info structure.
- * Returns: int - 0 = success; otherwise error.
- *****************************************************************************/
-int xsvfInfoInit( SXsvfInfo* pXsvfInfo )
-{
- XSVFDBG_PRINTF1( 4, " sizeof( SXsvfInfo ) = %d bytes\n",
- sizeof( SXsvfInfo ) );
-
- pXsvfInfo->ucComplete = 0;
- pXsvfInfo->ucCommand = XCOMPLETE;
- pXsvfInfo->lCommandCount = 0;
- pXsvfInfo->iErrorCode = XSVF_ERROR_NONE;
- pXsvfInfo->ucMaxRepeat = 0;
- pXsvfInfo->ucTapState = XTAPSTATE_RESET;
- pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST;
- pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST;
- pXsvfInfo->lShiftLengthBits = 0L;
- pXsvfInfo->sShiftLengthBytes= 0;
- pXsvfInfo->lRunTestTime = 0L;
-
- return( 0 );
-}
-
-/*****************************************************************************
- * Function: xsvfInfoCleanup
- * Description: Cleanup the xsvfInfo data.
- * Parameters: pXsvfInfo - ptr to the XSVF info structure.
- * Returns: void.
- *****************************************************************************/
-void xsvfInfoCleanup( SXsvfInfo* pXsvfInfo )
-{
-}
-
-/*****************************************************************************
- * Function: xsvfGetAsNumBytes
- * Description: Calculate the number of bytes the given number of bits
- * consumes.
- * Parameters: lNumBits - the number of bits.
- * Returns: short - the number of bytes to store the number of bits.
- *****************************************************************************/
-short xsvfGetAsNumBytes( long lNumBits )
-{
- return( (short)( ( lNumBits + 7L ) / 8L ) );
-}
-
-/*****************************************************************************
- * Function: xsvfTmsTransition
- * Description: Apply TMS and transition TAP controller by applying one TCK
- * cycle.
- * Parameters: sTms - new TMS value.
- * Returns: void.
- *****************************************************************************/
-void xsvfTmsTransition( short sTms )
-{
- setPort( TMS, sTms );
- setPort( TCK, 0 );
- setPort( TCK, 1 );
-}
-
-/*****************************************************************************
- * Function: xsvfGotoTapState
- * Description: From the current TAP state, go to the named TAP state.
- * A target state of RESET ALWAYS causes TMS reset sequence.
- * All SVF standard stable state paths are supported.
- * All state transitions are supported except for the following
- * which cause an XSVF_ERROR_ILLEGALSTATE:
- * - Target==DREXIT2; Start!=DRPAUSE
- * - Target==IREXIT2; Start!=IRPAUSE
- * Parameters: pucTapState - Current TAP state; returns final TAP state.
- * ucTargetState - New target TAP state.
- * Returns: int - 0 = success; otherwise error.
- *****************************************************************************/
-int xsvfGotoTapState( unsigned char* pucTapState,
- unsigned char ucTargetState )
-{
- int i;
- int iErrorCode;
-
- iErrorCode = XSVF_ERROR_NONE;
- if ( ucTargetState == XTAPSTATE_RESET )
- {
- /* If RESET, always perform TMS reset sequence to reset/sync TAPs */
- xsvfTmsTransition( 1 );
- for ( i = 0; i < 5; ++i )
- {
- setPort( TCK, 0 );
- setPort( TCK, 1 );
- }
- *pucTapState = XTAPSTATE_RESET;
- XSVFDBG_PRINTF( 3, " TMS Reset Sequence -> Test-Logic-Reset\n" );
- XSVFDBG_PRINTF1( 3, " TAP State = %s\n",
- xsvf_pzTapState[ *pucTapState ] );
- } else if ( ( ucTargetState != *pucTapState ) &&
- ( ( ( ucTargetState == XTAPSTATE_EXIT2DR ) && ( *pucTapState != XTAPSTATE_PAUSEDR ) ) ||
- ( ( ucTargetState == XTAPSTATE_EXIT2IR ) && ( *pucTapState != XTAPSTATE_PAUSEIR ) ) ) )
- {
- /* Trap illegal TAP state path specification */
- iErrorCode = XSVF_ERROR_ILLEGALSTATE;
- } else {
- if ( ucTargetState == *pucTapState )
- {
- /* Already in target state. Do nothing except when in DRPAUSE
- or in IRPAUSE to comply with SVF standard */
- if ( ucTargetState == XTAPSTATE_PAUSEDR )
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_EXIT2DR;
- XSVFDBG_PRINTF1( 3, " TAP State = %s\n",
- xsvf_pzTapState[ *pucTapState ] );
- }
- else if ( ucTargetState == XTAPSTATE_PAUSEIR )
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_EXIT2IR;
- XSVFDBG_PRINTF1( 3, " TAP State = %s\n",
- xsvf_pzTapState[ *pucTapState ] );
- }
- }
-
- /* Perform TAP state transitions to get to the target state */
- while ( ucTargetState != *pucTapState )
- {
- switch ( *pucTapState )
- {
- case XTAPSTATE_RESET:
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_RUNTEST;
- break;
- case XTAPSTATE_RUNTEST:
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_SELECTDR;
- break;
- case XTAPSTATE_SELECTDR:
- if ( ucTargetState >= XTAPSTATE_IRSTATES )
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_SELECTIR;
- }
- else
- {
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_CAPTUREDR;
- }
- break;
- case XTAPSTATE_CAPTUREDR:
- if ( ucTargetState == XTAPSTATE_SHIFTDR )
- {
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_SHIFTDR;
- }
- else
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_EXIT1DR;
- }
- break;
- case XTAPSTATE_SHIFTDR:
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_EXIT1DR;
- break;
- case XTAPSTATE_EXIT1DR:
- if ( ucTargetState == XTAPSTATE_PAUSEDR )
- {
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_PAUSEDR;
- }
- else
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_UPDATEDR;
- }
- break;
- case XTAPSTATE_PAUSEDR:
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_EXIT2DR;
- break;
- case XTAPSTATE_EXIT2DR:
- if ( ucTargetState == XTAPSTATE_SHIFTDR )
- {
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_SHIFTDR;
- }
- else
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_UPDATEDR;
- }
- break;
- case XTAPSTATE_UPDATEDR:
- if ( ucTargetState == XTAPSTATE_RUNTEST )
- {
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_RUNTEST;
- }
- else
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_SELECTDR;
- }
- break;
- case XTAPSTATE_SELECTIR:
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_CAPTUREIR;
- break;
- case XTAPSTATE_CAPTUREIR:
- if ( ucTargetState == XTAPSTATE_SHIFTIR )
- {
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_SHIFTIR;
- }
- else
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_EXIT1IR;
- }
- break;
- case XTAPSTATE_SHIFTIR:
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_EXIT1IR;
- break;
- case XTAPSTATE_EXIT1IR:
- if ( ucTargetState == XTAPSTATE_PAUSEIR )
- {
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_PAUSEIR;
- }
- else
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_UPDATEIR;
- }
- break;
- case XTAPSTATE_PAUSEIR:
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_EXIT2IR;
- break;
- case XTAPSTATE_EXIT2IR:
- if ( ucTargetState == XTAPSTATE_SHIFTIR )
- {
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_SHIFTIR;
- }
- else
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_UPDATEIR;
- }
- break;
- case XTAPSTATE_UPDATEIR:
- if ( ucTargetState == XTAPSTATE_RUNTEST )
- {
- xsvfTmsTransition( 0 );
- *pucTapState = XTAPSTATE_RUNTEST;
- }
- else
- {
- xsvfTmsTransition( 1 );
- *pucTapState = XTAPSTATE_SELECTDR;
- }
- break;
- default:
- iErrorCode = XSVF_ERROR_ILLEGALSTATE;
- *pucTapState = ucTargetState; /* Exit while loop */
- break;
- }
- XSVFDBG_PRINTF1( 3, " TAP State = %s\n",
- xsvf_pzTapState[ *pucTapState ] );
- }
- }
-
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfShiftOnly
- * Description: Assumes that starting TAP state is SHIFT-DR or SHIFT-IR.
- * Shift the given TDI data into the JTAG scan chain.
- * Optionally, save the TDO data shifted out of the scan chain.
- * Last shift cycle is special: capture last TDO, set last TDI,
- * but does not pulse TCK. Caller must pulse TCK and optionally
- * set TMS=1 to exit shift state.
- * Parameters: lNumBits - number of bits to shift.
- * plvTdi - ptr to lenval for TDI data.
- * plvTdoCaptured - ptr to lenval for storing captured TDO data.
- * iExitShift - 1=exit at end of shift; 0=stay in Shift-DR.
- * Returns: void.
- *****************************************************************************/
-void xsvfShiftOnly( long lNumBits,
- lenVal* plvTdi,
- lenVal* plvTdoCaptured,
- int iExitShift )
-{
- unsigned char* pucTdi;
- unsigned char* pucTdo;
- unsigned char ucTdiByte;
- unsigned char ucTdoByte;
- unsigned char ucTdoBit;
- int i;
-
- /* assert( ( ( lNumBits + 7 ) / 8 ) == plvTdi->len ); */
-
- /* Initialize TDO storage len == TDI len */
- pucTdo = 0;
- if ( plvTdoCaptured )
- {
- plvTdoCaptured->len = plvTdi->len;
- pucTdo = plvTdoCaptured->val + plvTdi->len;
- }
-
- /* Shift LSB first. val[N-1] == LSB. val[0] == MSB. */
- pucTdi = plvTdi->val + plvTdi->len;
- while ( lNumBits )
- {
- /* Process on a byte-basis */
- ucTdiByte = (*(--pucTdi));
- ucTdoByte = 0;
- for ( i = 0; ( lNumBits && ( i < 8 ) ); ++i )
- {
- --lNumBits;
- if ( iExitShift && !lNumBits )
- {
- /* Exit Shift-DR state */
- setPort( TMS, 1 );
- }
-
- /* Set the new TDI value */
- setPort( TDI, (short)(ucTdiByte & 1) );
- ucTdiByte >>= 1;
-
- /* Set TCK low */
- setPort( TCK, 0 );
-
- if ( pucTdo )
- {
- /* Save the TDO value */
- ucTdoBit = readTDOBit();
- ucTdoByte |= ( ucTdoBit << i );
- }
-
- /* Set TCK high */
- setPort( TCK, 1 );
- }
-
- /* Save the TDO byte value */
- if ( pucTdo )
- {
- (*(--pucTdo)) = ucTdoByte;
- }
- }
-}
-
-/*****************************************************************************
- * Function: xsvfShift
- * Description: Goes to the given starting TAP state.
- * Calls xsvfShiftOnly to shift in the given TDI data and
- * optionally capture the TDO data.
- * Compares the TDO captured data against the TDO expected
- * data.
- * If a data mismatch occurs, then executes the exception
- * handling loop upto ucMaxRepeat times.
- * Parameters: pucTapState - Ptr to current TAP state.
- * ucStartState - Starting shift state: Shift-DR or Shift-IR.
- * lNumBits - number of bits to shift.
- * plvTdi - ptr to lenval for TDI data.
- * plvTdoCaptured - ptr to lenval for storing TDO data.
- * plvTdoExpected - ptr to expected TDO data.
- * plvTdoMask - ptr to TDO mask.
- * ucEndState - state in which to end the shift.
- * lRunTestTime - amount of time to wait after the shift.
- * ucMaxRepeat - Maximum number of retries on TDO mismatch.
- * Returns: int - 0 = success; otherwise TDO mismatch.
- * Notes: XC9500XL-only Optimization:
- * Skip the waitTime() if plvTdoMask->val[0:plvTdoMask->len-1]
- * is NOT all zeros and sMatch==1.
- *****************************************************************************/
-int xsvfShift( unsigned char* pucTapState,
- unsigned char ucStartState,
- long lNumBits,
- lenVal* plvTdi,
- lenVal* plvTdoCaptured,
- lenVal* plvTdoExpected,
- lenVal* plvTdoMask,
- unsigned char ucEndState,
- long lRunTestTime,
- unsigned char ucMaxRepeat )
-{
- int iErrorCode;
- int iMismatch;
- unsigned char ucRepeat;
- int iExitShift;
-
- iErrorCode = XSVF_ERROR_NONE;
- iMismatch = 0;
- ucRepeat = 0;
- iExitShift = ( ucStartState != ucEndState );
-
- XSVFDBG_PRINTF1( 3, " Shift Length = %ld\n", lNumBits );
- XSVFDBG_PRINTF( 4, " TDI = ");
- XSVFDBG_PRINTLENVAL( 4, plvTdi );
- XSVFDBG_PRINTF( 4, "\n");
- XSVFDBG_PRINTF( 4, " TDO Expected = ");
- XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
- XSVFDBG_PRINTF( 4, "\n");
-
- if ( !lNumBits )
- {
- /* Compatibility with XSVF2.00: XSDR 0 = no shift, but wait in RTI */
- if ( lRunTestTime )
- {
- /* Wait for prespecified XRUNTEST time */
- xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
- XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime );
- waitTime( lRunTestTime );
- }
- }
- else
- {
- do
- {
- /* Goto Shift-DR or Shift-IR */
- xsvfGotoTapState( pucTapState, ucStartState );
-
- /* Shift TDI and capture TDO */
- xsvfShiftOnly( lNumBits, plvTdi, plvTdoCaptured, iExitShift );
-
- if ( plvTdoExpected )
- {
- /* Compare TDO data to expected TDO data */
- iMismatch = !EqualLenVal( plvTdoExpected,
- plvTdoCaptured,
- plvTdoMask );
- }
-
- if ( iExitShift )
- {
- /* Update TAP state: Shift->Exit */
- ++(*pucTapState);
- XSVFDBG_PRINTF1( 3, " TAP State = %s\n",
- xsvf_pzTapState[ *pucTapState ] );
-
- if ( iMismatch && lRunTestTime && ( ucRepeat < ucMaxRepeat ) )
- {
- XSVFDBG_PRINTF( 4, " TDO Expected = ");
- XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
- XSVFDBG_PRINTF( 4, "\n");
- XSVFDBG_PRINTF( 4, " TDO Captured = ");
- XSVFDBG_PRINTLENVAL( 4, plvTdoCaptured );
- XSVFDBG_PRINTF( 4, "\n");
- XSVFDBG_PRINTF( 4, " TDO Mask = ");
- XSVFDBG_PRINTLENVAL( 4, plvTdoMask );
- XSVFDBG_PRINTF( 4, "\n");
- XSVFDBG_PRINTF1( 3, " Retry #%d\n", ( ucRepeat + 1 ) );
- /* Do exception handling retry - ShiftDR only */
- xsvfGotoTapState( pucTapState, XTAPSTATE_PAUSEDR );
- /* Shift 1 extra bit */
- xsvfGotoTapState( pucTapState, XTAPSTATE_SHIFTDR );
- /* Increment RUNTEST time by an additional 25% */
- lRunTestTime += ( lRunTestTime >> 2 );
- }
- else
- {
- /* Do normal exit from Shift-XR */
- xsvfGotoTapState( pucTapState, ucEndState );
- }
-
- if ( lRunTestTime )
- {
- /* Wait for prespecified XRUNTEST time */
- xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
- XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime );
- waitTime( lRunTestTime );
- }
- }
- } while ( iMismatch && ( ucRepeat++ < ucMaxRepeat ) );
- }
-
- if ( iMismatch )
- {
- XSVFDBG_PRINTF( 1, " TDO Expected = ");
- XSVFDBG_PRINTLENVAL( 1, plvTdoExpected );
- XSVFDBG_PRINTF( 1, "\n");
- XSVFDBG_PRINTF( 1, " TDO Captured = ");
- XSVFDBG_PRINTLENVAL( 1, plvTdoCaptured );
- XSVFDBG_PRINTF( 1, "\n");
- XSVFDBG_PRINTF( 1, " TDO Mask = ");
- XSVFDBG_PRINTLENVAL( 1, plvTdoMask );
- XSVFDBG_PRINTF( 1, "\n");
- if ( ucMaxRepeat && ( ucRepeat > ucMaxRepeat ) )
- {
- iErrorCode = XSVF_ERROR_MAXRETRIES;
- }
- else
- {
- iErrorCode = XSVF_ERROR_TDOMISMATCH;
- }
- }
-
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfBasicXSDRTDO
- * Description: Get the XSDRTDO parameters and execute the XSDRTDO command.
- * This is the common function for all XSDRTDO commands.
- * Parameters: pucTapState - Current TAP state.
- * lShiftLengthBits - number of bits to shift.
- * sShiftLengthBytes - number of bytes to read.
- * plvTdi - ptr to lenval for TDI data.
- * lvTdoCaptured - ptr to lenval for storing TDO data.
- * iEndState - state in which to end the shift.
- * lRunTestTime - amount of time to wait after the shift.
- * ucMaxRepeat - maximum xc9500/xl retries.
- * Returns: int - 0 = success; otherwise TDO mismatch.
- *****************************************************************************/
-int xsvfBasicXSDRTDO( unsigned char* pucTapState,
- long lShiftLengthBits,
- short sShiftLengthBytes,
- lenVal* plvTdi,
- lenVal* plvTdoCaptured,
- lenVal* plvTdoExpected,
- lenVal* plvTdoMask,
- unsigned char ucEndState,
- long lRunTestTime,
- unsigned char ucMaxRepeat )
-{
- readVal( plvTdi, sShiftLengthBytes );
- if ( plvTdoExpected )
- {
- readVal( plvTdoExpected, sShiftLengthBytes );
- }
- return( xsvfShift( pucTapState, XTAPSTATE_SHIFTDR, lShiftLengthBits,
- plvTdi, plvTdoCaptured, plvTdoExpected, plvTdoMask,
- ucEndState, lRunTestTime, ucMaxRepeat ) );
-}
-
-/*****************************************************************************
- * Function: xsvfDoSDRMasking
- * Description: Update the data value with the next XSDRINC data and address.
- * Example: dataVal=0x01ff, nextData=0xab, addressMask=0x0100,
- * dataMask=0x00ff, should set dataVal to 0x02ab
- * Parameters: plvTdi - The current TDI value.
- * plvNextData - the next data value.
- * plvAddressMask - the address mask.
- * plvDataMask - the data mask.
- * Returns: void.
- *****************************************************************************/
-#ifdef XSVF_SUPPORT_COMPRESSION
-void xsvfDoSDRMasking( lenVal* plvTdi,
- lenVal* plvNextData,
- lenVal* plvAddressMask,
- lenVal* plvDataMask )
-{
- int i;
- unsigned char ucTdi;
- unsigned char ucTdiMask;
- unsigned char ucDataMask;
- unsigned char ucNextData;
- unsigned char ucNextMask;
- short sNextData;
-
- /* add the address Mask to dataVal and return as a new dataVal */
- addVal( plvTdi, plvTdi, plvAddressMask );
-
- ucNextData = 0;
- ucNextMask = 0;
- sNextData = plvNextData->len;
- for ( i = plvDataMask->len - 1; i >= 0; --i )
- {
- /* Go through data mask in reverse order looking for mask (1) bits */
- ucDataMask = plvDataMask->val[ i ];
- if ( ucDataMask )
- {
- /* Retrieve the corresponding TDI byte value */
- ucTdi = plvTdi->val[ i ];
-
- /* For each bit in the data mask byte, look for 1's */
- ucTdiMask = 1;
- while ( ucDataMask )
- {
- if ( ucDataMask & 1 )
- {
- if ( !ucNextMask )
- {
- /* Get the next data byte */
- ucNextData = plvNextData->val[ --sNextData ];
- ucNextMask = 1;
- }
-
- /* Set or clear the data bit according to the next data */
- if ( ucNextData & ucNextMask )
- {
- ucTdi |= ucTdiMask; /* Set bit */
- }
- else
- {
- ucTdi &= ( ~ucTdiMask ); /* Clear bit */
- }
-
- /* Update the next data */
- ucNextMask <<= 1;
- }
- ucTdiMask <<= 1;
- ucDataMask >>= 1;
- }
-
- /* Update the TDI value */
- plvTdi->val[ i ] = ucTdi;
- }
- }
-}
-#endif /* XSVF_SUPPORT_COMPRESSION */
-
-/*============================================================================
- * XSVF Command Functions (type = TXsvfDoCmdFuncPtr)
- * These functions update pXsvfInfo->iErrorCode only on an error.
- * Otherwise, the error code is left alone.
- * The function returns the error code from the function.
- ============================================================================*/
-
-/*****************************************************************************
- * Function: xsvfDoIllegalCmd
- * Description: Function place holder for illegal/unsupported commands.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo )
-{
- XSVFDBG_PRINTF2( 0, "ERROR: Encountered unsupported command #%d (%s)\n",
- ((unsigned int)(pXsvfInfo->ucCommand)),
- ((pXsvfInfo->ucCommand < XLASTCMD)
- ? (xsvf_pzCommandName[pXsvfInfo->ucCommand])
- : "Unknown") );
- pXsvfInfo->iErrorCode = XSVF_ERROR_ILLEGALCMD;
- return( pXsvfInfo->iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXCOMPLETE
- * Description: XCOMPLETE (no parameters)
- * Update complete status for XSVF player.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo )
-{
- pXsvfInfo->ucComplete = 1;
- return( XSVF_ERROR_NONE );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXTDOMASK
- * Description: XTDOMASK <lenVal.TdoMask[XSDRSIZE]>
- * Prespecify the TDO compare mask.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo )
-{
- readVal( &(pXsvfInfo->lvTdoMask), pXsvfInfo->sShiftLengthBytes );
- XSVFDBG_PRINTF( 4, " TDO Mask = ");
- XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvTdoMask) );
- XSVFDBG_PRINTF( 4, "\n");
- return( XSVF_ERROR_NONE );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXSIR
- * Description: XSIR <(byte)shiftlen> <lenVal.TDI[shiftlen]>
- * Get the instruction and shift the instruction into the TAP.
- * If prespecified XRUNTEST!=0, goto RUNTEST and wait after
- * the shift for XRUNTEST usec.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXSIR( SXsvfInfo* pXsvfInfo )
-{
- unsigned char ucShiftIrBits;
- short sShiftIrBytes;
- int iErrorCode;
-
- /* Get the shift length and store */
- readByte( &ucShiftIrBits );
- sShiftIrBytes = xsvfGetAsNumBytes( ucShiftIrBits );
- XSVFDBG_PRINTF1( 3, " XSIR length = %d\n",
- ((unsigned int)ucShiftIrBits) );
-
- if ( sShiftIrBytes > MAX_LEN )
- {
- iErrorCode = XSVF_ERROR_DATAOVERFLOW;
- }
- else
- {
- /* Get and store instruction to shift in */
- readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( ucShiftIrBits ) );
-
- /* Shift the data */
- iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
- ucShiftIrBits, &(pXsvfInfo->lvTdi),
- /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
- /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
- pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
- }
-
- if ( iErrorCode != XSVF_ERROR_NONE )
- {
- pXsvfInfo->iErrorCode = iErrorCode;
- }
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXSIR2
- * Description: XSIR <(2-byte)shiftlen> <lenVal.TDI[shiftlen]>
- * Get the instruction and shift the instruction into the TAP.
- * If prespecified XRUNTEST!=0, goto RUNTEST and wait after
- * the shift for XRUNTEST usec.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo )
-{
- long lShiftIrBits;
- short sShiftIrBytes;
- int iErrorCode;
-
- /* Get the shift length and store */
- readVal( &(pXsvfInfo->lvTdi), 2 );
- lShiftIrBits = value( &(pXsvfInfo->lvTdi) );
- sShiftIrBytes = xsvfGetAsNumBytes( lShiftIrBits );
- XSVFDBG_PRINTF1( 3, " XSIR2 length = %d\n", (int)lShiftIrBits);
-
- if ( sShiftIrBytes > MAX_LEN )
- {
- iErrorCode = XSVF_ERROR_DATAOVERFLOW;
- }
- else
- {
- /* Get and store instruction to shift in */
- readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( lShiftIrBits ) );
-
- /* Shift the data */
- iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
- lShiftIrBits, &(pXsvfInfo->lvTdi),
- /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
- /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
- pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
- }
-
- if ( iErrorCode != XSVF_ERROR_NONE )
- {
- pXsvfInfo->iErrorCode = iErrorCode;
- }
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXSDR
- * Description: XSDR <lenVal.TDI[XSDRSIZE]>
- * Shift the given TDI data into the JTAG scan chain.
- * Compare the captured TDO with the expected TDO from the
- * previous XSDRTDO command using the previously specified
- * XTDOMASK.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXSDR( SXsvfInfo* pXsvfInfo )
-{
- int iErrorCode;
- readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
- /* use TDOExpected from last XSDRTDO instruction */
- iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
- pXsvfInfo->lShiftLengthBits, &(pXsvfInfo->lvTdi),
- &(pXsvfInfo->lvTdoCaptured),
- &(pXsvfInfo->lvTdoExpected),
- &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
- pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
- if ( iErrorCode != XSVF_ERROR_NONE )
- {
- pXsvfInfo->iErrorCode = iErrorCode;
- }
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXRUNTEST
- * Description: XRUNTEST <uint32>
- * Prespecify the XRUNTEST wait time for shift operations.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo )
-{
- readVal( &(pXsvfInfo->lvTdi), 4 );
- pXsvfInfo->lRunTestTime = value( &(pXsvfInfo->lvTdi) );
- XSVFDBG_PRINTF1( 3, " XRUNTEST = %ld\n", pXsvfInfo->lRunTestTime );
- return( XSVF_ERROR_NONE );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXREPEAT
- * Description: XREPEAT <byte>
- * Prespecify the maximum number of XC9500/XL retries.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo )
-{
- readByte( &(pXsvfInfo->ucMaxRepeat) );
- XSVFDBG_PRINTF1( 3, " XREPEAT = %d\n",
- ((unsigned int)(pXsvfInfo->ucMaxRepeat)) );
- return( XSVF_ERROR_NONE );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXSDRSIZE
- * Description: XSDRSIZE <uint32>
- * Prespecify the XRUNTEST wait time for shift operations.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo )
-{
- int iErrorCode;
- iErrorCode = XSVF_ERROR_NONE;
- readVal( &(pXsvfInfo->lvTdi), 4 );
- pXsvfInfo->lShiftLengthBits = value( &(pXsvfInfo->lvTdi) );
- pXsvfInfo->sShiftLengthBytes= xsvfGetAsNumBytes( pXsvfInfo->lShiftLengthBits );
- XSVFDBG_PRINTF1( 3, " XSDRSIZE = %ld\n", pXsvfInfo->lShiftLengthBits );
- if ( pXsvfInfo->sShiftLengthBytes > MAX_LEN )
- {
- iErrorCode = XSVF_ERROR_DATAOVERFLOW;
- pXsvfInfo->iErrorCode = iErrorCode;
- }
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXSDRTDO
- * Description: XSDRTDO <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
- * Get the TDI and expected TDO values. Then, shift.
- * Compare the expected TDO with the captured TDO using the
- * prespecified XTDOMASK.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo )
-{
- int iErrorCode;
- iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
- pXsvfInfo->lShiftLengthBits,
- pXsvfInfo->sShiftLengthBytes,
- &(pXsvfInfo->lvTdi),
- &(pXsvfInfo->lvTdoCaptured),
- &(pXsvfInfo->lvTdoExpected),
- &(pXsvfInfo->lvTdoMask),
- pXsvfInfo->ucEndDR,
- pXsvfInfo->lRunTestTime,
- pXsvfInfo->ucMaxRepeat );
- if ( iErrorCode != XSVF_ERROR_NONE )
- {
- pXsvfInfo->iErrorCode = iErrorCode;
- }
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXSETSDRMASKS
- * Description: XSETSDRMASKS <lenVal.AddressMask[XSDRSIZE]>
- * <lenVal.DataMask[XSDRSIZE]>
- * Get the prespecified address and data mask for the XSDRINC
- * command.
- * Used for xc9500/xl compressed XSVF data.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-#ifdef XSVF_SUPPORT_COMPRESSION
-int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo )
-{
- /* read the addressMask */
- readVal( &(pXsvfInfo->lvAddressMask), pXsvfInfo->sShiftLengthBytes );
- /* read the dataMask */
- readVal( &(pXsvfInfo->lvDataMask), pXsvfInfo->sShiftLengthBytes );
-
- XSVFDBG_PRINTF( 4, " Address Mask = " );
- XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvAddressMask) );
- XSVFDBG_PRINTF( 4, "\n" );
- XSVFDBG_PRINTF( 4, " Data Mask = " );
- XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvDataMask) );
- XSVFDBG_PRINTF( 4, "\n" );
-
- return( XSVF_ERROR_NONE );
-}
-#endif /* XSVF_SUPPORT_COMPRESSION */
-
-/*****************************************************************************
- * Function: xsvfDoXSDRINC
- * Description: XSDRINC <lenVal.firstTDI[XSDRSIZE]> <byte(numTimes)>
- * <lenVal.data[XSETSDRMASKS.dataMask.len]> ...
- * Get the XSDRINC parameters and execute the XSDRINC command.
- * XSDRINC starts by loading the first TDI shift value.
- * Then, for numTimes, XSDRINC gets the next piece of data,
- * replaces the bits from the starting TDI as defined by the
- * XSETSDRMASKS.dataMask, adds the address mask from
- * XSETSDRMASKS.addressMask, shifts the new TDI value,
- * and compares the TDO to the expected TDO from the previous
- * XSDRTDO command using the XTDOMASK.
- * Used for xc9500/xl compressed XSVF data.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-#ifdef XSVF_SUPPORT_COMPRESSION
-int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo )
-{
- int iErrorCode;
- int iDataMaskLen;
- unsigned char ucDataMask;
- unsigned char ucNumTimes;
- unsigned char i;
-
- readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
- iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
- pXsvfInfo->lShiftLengthBits,
- &(pXsvfInfo->lvTdi), &(pXsvfInfo->lvTdoCaptured),
- &(pXsvfInfo->lvTdoExpected),
- &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
- pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
- if ( !iErrorCode )
- {
- /* Calculate number of data mask bits */
- iDataMaskLen = 0;
- for ( i = 0; i < pXsvfInfo->lvDataMask.len; ++i )
- {
- ucDataMask = pXsvfInfo->lvDataMask.val[ i ];
- while ( ucDataMask )
- {
- iDataMaskLen += ( ucDataMask & 1 );
- ucDataMask >>= 1;
- }
- }
-
- /* Get the number of data pieces, i.e. number of times to shift */
- readByte( &ucNumTimes );
-
- /* For numTimes, get data, fix TDI, and shift */
- for ( i = 0; !iErrorCode && ( i < ucNumTimes ); ++i )
- {
- readVal( &(pXsvfInfo->lvNextData),
- xsvfGetAsNumBytes( iDataMaskLen ) );
- xsvfDoSDRMasking( &(pXsvfInfo->lvTdi),
- &(pXsvfInfo->lvNextData),
- &(pXsvfInfo->lvAddressMask),
- &(pXsvfInfo->lvDataMask) );
- iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState),
- XTAPSTATE_SHIFTDR,
- pXsvfInfo->lShiftLengthBits,
- &(pXsvfInfo->lvTdi),
- &(pXsvfInfo->lvTdoCaptured),
- &(pXsvfInfo->lvTdoExpected),
- &(pXsvfInfo->lvTdoMask),
- pXsvfInfo->ucEndDR,
- pXsvfInfo->lRunTestTime,
- pXsvfInfo->ucMaxRepeat );
- }
- }
- if ( iErrorCode != XSVF_ERROR_NONE )
- {
- pXsvfInfo->iErrorCode = iErrorCode;
- }
- return( iErrorCode );
-}
-#endif /* XSVF_SUPPORT_COMPRESSION */
-
-/*****************************************************************************
- * Function: xsvfDoXSDRBCE
- * Description: XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]>
- * If not already in SHIFTDR, goto SHIFTDR.
- * Shift the given TDI data into the JTAG scan chain.
- * Ignore TDO.
- * If cmd==XSDRE, then goto ENDDR. Otherwise, stay in ShiftDR.
- * XSDRB, XSDRC, and XSDRE are the same implementation.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo )
-{
- unsigned char ucEndDR;
- int iErrorCode;
- ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRE ) ?
- pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
- iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
- pXsvfInfo->lShiftLengthBits,
- pXsvfInfo->sShiftLengthBytes,
- &(pXsvfInfo->lvTdi),
- /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
- /*plvTdoMask*/0, ucEndDR,
- /*lRunTestTime*/0, /*ucMaxRepeat*/0 );
- if ( iErrorCode != XSVF_ERROR_NONE )
- {
- pXsvfInfo->iErrorCode = iErrorCode;
- }
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXSDRTDOBCE
- * Description: XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
- * If not already in SHIFTDR, goto SHIFTDR.
- * Shift the given TDI data into the JTAG scan chain.
- * Compare TDO, but do NOT use XTDOMASK.
- * If cmd==XSDRTDOE, then goto ENDDR. Otherwise, stay in ShiftDR.
- * XSDRTDOB, XSDRTDOC, and XSDRTDOE are the same implementation.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo )
-{
- unsigned char ucEndDR;
- int iErrorCode;
- ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRTDOE ) ?
- pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
- iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
- pXsvfInfo->lShiftLengthBits,
- pXsvfInfo->sShiftLengthBytes,
- &(pXsvfInfo->lvTdi),
- &(pXsvfInfo->lvTdoCaptured),
- &(pXsvfInfo->lvTdoExpected),
- /*plvTdoMask*/0, ucEndDR,
- /*lRunTestTime*/0, /*ucMaxRepeat*/0 );
- if ( iErrorCode != XSVF_ERROR_NONE )
- {
- pXsvfInfo->iErrorCode = iErrorCode;
- }
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXSTATE
- * Description: XSTATE <byte>
- * <byte> == XTAPSTATE;
- * Get the state parameter and transition the TAP to that state.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo )
-{
- unsigned char ucNextState;
- int iErrorCode;
- readByte( &ucNextState );
- iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucNextState );
- if ( iErrorCode != XSVF_ERROR_NONE )
- {
- pXsvfInfo->iErrorCode = iErrorCode;
- }
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXENDXR
- * Description: XENDIR/XENDDR <byte>
- * <byte>: 0 = RUNTEST; 1 = PAUSE.
- * Get the prespecified XENDIR or XENDDR.
- * Both XENDIR and XENDDR use the same implementation.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo )
-{
- int iErrorCode;
- unsigned char ucEndState;
-
- iErrorCode = XSVF_ERROR_NONE;
- readByte( &ucEndState );
- if ( ( ucEndState != XENDXR_RUNTEST ) && ( ucEndState != XENDXR_PAUSE ) )
- {
- iErrorCode = XSVF_ERROR_ILLEGALSTATE;
- }
- else
- {
-
- if ( pXsvfInfo->ucCommand == XENDIR )
- {
- if ( ucEndState == XENDXR_RUNTEST )
- {
- pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST;
- }
- else
- {
- pXsvfInfo->ucEndIR = XTAPSTATE_PAUSEIR;
- }
- XSVFDBG_PRINTF1( 3, " ENDIR State = %s\n",
- xsvf_pzTapState[ pXsvfInfo->ucEndIR ] );
- }
- else /* XENDDR */
- {
- if ( ucEndState == XENDXR_RUNTEST )
- {
- pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST;
- }
- else
- {
- pXsvfInfo->ucEndDR = XTAPSTATE_PAUSEDR;
- }
- XSVFDBG_PRINTF1( 3, " ENDDR State = %s\n",
- xsvf_pzTapState[ pXsvfInfo->ucEndDR ] );
- }
- }
-
- if ( iErrorCode != XSVF_ERROR_NONE )
- {
- pXsvfInfo->iErrorCode = iErrorCode;
- }
- return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXCOMMENT
- * Description: XCOMMENT <text string ending in \0>
- * <text string ending in \0> == text comment;
- * Arbitrary comment embedded in the XSVF.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo )
-{
- /* Use the comment for debugging */
- /* Otherwise, read through the comment to the end '\0' and ignore */
- unsigned char ucText;
-
- if ( xsvf_iDebugLevel > 0 )
- {
- putc( ' ' );
- }
-
- do
- {
- readByte( &ucText );
- if ( xsvf_iDebugLevel > 0 )
- {
- putc( ucText ? ucText : '\n' );
- }
- } while ( ucText );
-
- pXsvfInfo->iErrorCode = XSVF_ERROR_NONE;
-
- return( pXsvfInfo->iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfDoXWAIT
- * Description: XWAIT <wait_state> <end_state> <wait_time>
- * If not already in <wait_state>, then go to <wait_state>.
- * Wait in <wait_state> for <wait_time> microseconds.
- * Finally, if not already in <end_state>, then goto <end_state>.
- * Parameters: pXsvfInfo - XSVF information pointer.
- * Returns: int - 0 = success; non-zero = error.
- *****************************************************************************/
-int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo )
-{
- unsigned char ucWaitState;
- unsigned char ucEndState;
- long lWaitTime;
-
- /* Get Parameters */
- /* <wait_state> */
- readVal( &(pXsvfInfo->lvTdi), 1 );
- ucWaitState = pXsvfInfo->lvTdi.val[0];
-
- /* <end_state> */
- readVal( &(pXsvfInfo->lvTdi), 1 );
- ucEndState = pXsvfInfo->lvTdi.val[0];
-
- /* <wait_time> */
- readVal( &(pXsvfInfo->lvTdi), 4 );
- lWaitTime = value( &(pXsvfInfo->lvTdi) );
- XSVFDBG_PRINTF2( 3, " XWAIT: state = %s; time = %ld\n",
- xsvf_pzTapState[ ucWaitState ], lWaitTime );
-
- /* If not already in <wait_state>, go to <wait_state> */
- if ( pXsvfInfo->ucTapState != ucWaitState )
- {
- xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucWaitState );
- }
-
- /* Wait for <wait_time> microseconds */
- waitTime( lWaitTime );
-
- /* If not already in <end_state>, go to <end_state> */
- if ( pXsvfInfo->ucTapState != ucEndState )
- {
- xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucEndState );
- }
-
- return( XSVF_ERROR_NONE );
-}
-
-
-/*============================================================================
- * Execution Control Functions
- ============================================================================*/
-
-/*****************************************************************************
- * Function: xsvfInitialize
- * Description: Initialize the xsvf player.
- * Call this before running the player to initialize the data
- * in the SXsvfInfo struct.
- * xsvfCleanup is called to clean up the data in SXsvfInfo
- * after the XSVF is played.
- * Parameters: pXsvfInfo - ptr to the XSVF information.
- * Returns: int - 0 = success; otherwise error.
- *****************************************************************************/
-int xsvfInitialize( SXsvfInfo* pXsvfInfo )
-{
- /* Initialize values */
- pXsvfInfo->iErrorCode = xsvfInfoInit( pXsvfInfo );
-
- if ( !pXsvfInfo->iErrorCode )
- {
- /* Initialize the TAPs */
- pXsvfInfo->iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState),
- XTAPSTATE_RESET );
- }
-
- return( pXsvfInfo->iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfRun
- * Description: Run the xsvf player for a single command and return.
- * First, call xsvfInitialize.
- * Then, repeatedly call this function until an error is detected
- * or until the pXsvfInfo->ucComplete variable is non-zero.
- * Finally, call xsvfCleanup to cleanup any remnants.
- * Parameters: pXsvfInfo - ptr to the XSVF information.
- * Returns: int - 0 = success; otherwise error.
- *****************************************************************************/
-int xsvfRun( SXsvfInfo* pXsvfInfo )
-{
- /* Process the XSVF commands */
- if ( (!pXsvfInfo->iErrorCode) && (!pXsvfInfo->ucComplete) )
- {
- /* read 1 byte for the instruction */
- readByte( &(pXsvfInfo->ucCommand) );
- ++(pXsvfInfo->lCommandCount);
-
- if ( pXsvfInfo->ucCommand < XLASTCMD )
- {
- /* Execute the command. Func sets error code. */
- XSVFDBG_PRINTF1( 2, " %s\n",
- xsvf_pzCommandName[pXsvfInfo->ucCommand] );
- /* If your compiler cannot take this form,
- then convert to a switch statement */
-#if 0 /* test-only */
- xsvf_pfDoCmd[ pXsvfInfo->ucCommand ]( pXsvfInfo );
-#else
- switch (pXsvfInfo->ucCommand) {
- case 0:
- xsvfDoXCOMPLETE(pXsvfInfo); /* 0 */
- break;
- case 1:
- xsvfDoXTDOMASK(pXsvfInfo); /* 1 */
- break;
- case 2:
- xsvfDoXSIR(pXsvfInfo); /* 2 */
- break;
- case 3:
- xsvfDoXSDR(pXsvfInfo); /* 3 */
- break;
- case 4:
- xsvfDoXRUNTEST(pXsvfInfo); /* 4 */
- break;
- case 5:
- xsvfDoIllegalCmd(pXsvfInfo); /* 5 */
- break;
- case 6:
- xsvfDoIllegalCmd(pXsvfInfo); /* 6 */
- break;
- case 7:
- xsvfDoXREPEAT(pXsvfInfo); /* 7 */
- break;
- case 8:
- xsvfDoXSDRSIZE(pXsvfInfo); /* 8 */
- break;
- case 9:
- xsvfDoXSDRTDO(pXsvfInfo); /* 9 */
- break;
-#ifdef XSVF_SUPPORT_COMPRESSION
- case 10:
- xsvfDoXSETSDRMASKS(pXsvfInfo); /* 10 */
- break;
- case 11:
- xsvfDoXSDRINC(pXsvfInfo); /* 11 */
- break;
-#else
- case 10:
- xsvfDoIllegalCmd(pXsvfInfo); /* 10 */
- break;
- case 11:
- xsvfDoIllegalCmd(pXsvfInfo); /* 11 */
- break;
-#endif /* XSVF_SUPPORT_COMPRESSION */
- case 12:
- xsvfDoXSDRBCE(pXsvfInfo); /* 12 */
- break;
- case 13:
- xsvfDoXSDRBCE(pXsvfInfo); /* 13 */
- break;
- case 14:
- xsvfDoXSDRBCE(pXsvfInfo); /* 14 */
- break;
- case 15:
- xsvfDoXSDRTDOBCE(pXsvfInfo); /* 15 */
- break;
- case 16:
- xsvfDoXSDRTDOBCE(pXsvfInfo); /* 16 */
- break;
- case 17:
- xsvfDoXSDRTDOBCE(pXsvfInfo); /* 17 */
- break;
- case 18:
- xsvfDoXSTATE(pXsvfInfo); /* 18 */
- break;
- case 19:
- xsvfDoXENDXR(pXsvfInfo); /* 19 */
- break;
- case 20:
- xsvfDoXENDXR(pXsvfInfo); /* 20 */
- break;
- case 21:
- xsvfDoXSIR2(pXsvfInfo); /* 21 */
- break;
- case 22:
- xsvfDoXCOMMENT(pXsvfInfo); /* 22 */
- break;
- case 23:
- xsvfDoXWAIT(pXsvfInfo); /* 23 */
- break;
- }
-#endif
- }
- else
- {
- /* Illegal command value. Func sets error code. */
- xsvfDoIllegalCmd( pXsvfInfo );
- }
- }
-
- return( pXsvfInfo->iErrorCode );
-}
-
-/*****************************************************************************
- * Function: xsvfCleanup
- * Description: cleanup remnants of the xsvf player.
- * Parameters: pXsvfInfo - ptr to the XSVF information.
- * Returns: void.
- *****************************************************************************/
-void xsvfCleanup( SXsvfInfo* pXsvfInfo )
-{
- xsvfInfoCleanup( pXsvfInfo );
-}
-
-
-/*============================================================================
- * xsvfExecute() - The primary entry point to the XSVF player
- ============================================================================*/
-
-/*****************************************************************************
- * Function: xsvfExecute
- * Description: Process, interpret, and apply the XSVF commands.
- * See port.c:readByte for source of XSVF data.
- * Parameters: none.
- * Returns: int - Legacy result values: 1 == success; 0 == failed.
- *****************************************************************************/
-int xsvfExecute(void)
-{
- SXsvfInfo xsvfInfo;
-
- xsvfInitialize( &xsvfInfo );
-
- while ( !xsvfInfo.iErrorCode && (!xsvfInfo.ucComplete) )
- {
- xsvfRun( &xsvfInfo );
- }
-
- if ( xsvfInfo.iErrorCode )
- {
- XSVFDBG_PRINTF1( 0, "%s\n", xsvf_pzErrorName[
- ( xsvfInfo.iErrorCode < XSVF_ERROR_LAST )
- ? xsvfInfo.iErrorCode : XSVF_ERROR_UNKNOWN ] );
- XSVFDBG_PRINTF2( 0, "ERROR at or near XSVF command #%ld. See line #%ld in the XSVF ASCII file.\n",
- xsvfInfo.lCommandCount, xsvfInfo.lCommandCount );
- }
- else
- {
- XSVFDBG_PRINTF( 0, "SUCCESS - Completed XSVF execution.\n" );
- }
-
- xsvfCleanup( &xsvfInfo );
-
- return( XSVF_ERRORCODE(xsvfInfo.iErrorCode) );
-}
-
-
-/*****************************************************************************
- * Function: do_cpld
- * Description: main function.
- * Specified here for creating stand-alone debug executable.
- * Embedded users should call xsvfExecute() directly.
- * Parameters: iArgc - number of command-line arguments.
- * ppzArgv - array of ptrs to strings (command-line arguments).
- * Returns: int - Legacy return value: 1 = success; 0 = error.
- *****************************************************************************/
-int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int iErrorCode;
- unsigned long duration;
- unsigned long long startClock, endClock;
-
- if (argc == 2)
- xsvfdata = (unsigned char *)simple_strtoul(argv[1], NULL, 16);
- else {
-#ifdef CONFIG_SYS_XSVF_DEFAULT_ADDR
- xsvfdata = (unsigned char *)CONFIG_SYS_XSVF_DEFAULT_ADDR;
-#else
- printf("Usage:\ncpld %s\n", cmdtp->help);
- return -1;
-#endif
- }
-
- iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE );
- xsvf_iDebugLevel = 0;
-
- printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION);
- printf("Reading XSVF data @ %p\n", xsvfdata);
-
- /* Initialize the I/O. SetPort initializes I/O on first call */
- setPort( TMS, 1 );
-
- /* Execute the XSVF in the file */
- startClock = get_ticks();
- iErrorCode = xsvfExecute();
- endClock = get_ticks();
- duration = (unsigned long)(endClock - startClock);
- printf("\nExecution Time = %d seconds\n", (int)(duration/get_tbclk()));
-
- return( iErrorCode );
-}
-U_BOOT_CMD(
- cpld, 2, 1, do_cpld,
- "program onboard CPLD",
- "<xsvf-addr>"
-);
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*****************************************************************************
- * File: micro.h
- * Description: This header file contains the function prototype to the
- * primary interface function for the XSVF player.
- * Usage: FIRST - PORTS.C
- * Customize the ports.c function implementations to establish
- * the correct protocol for communicating with your JTAG ports
- * (setPort() and readTDOBit()) and tune the waitTime() delay
- * function. Also, establish access to the XSVF data source
- * in the readByte() function.
- * FINALLY - Call xsvfExecute().
- *****************************************************************************/
-#ifndef XSVF_MICRO_H
-#define XSVF_MICRO_H
-
-/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
-#define XSVF_LEGACY_SUCCESS 1
-#define XSVF_LEGACY_ERROR 0
-
-/* 4.04 [NEW] Error codes for xsvfExecute. */
-/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
-#define XSVF_ERROR_NONE 0
-#define XSVF_ERROR_UNKNOWN 1
-#define XSVF_ERROR_TDOMISMATCH 2
-#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */
-#define XSVF_ERROR_ILLEGALCMD 4
-#define XSVF_ERROR_ILLEGALSTATE 5
-#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/
-/* Insert new errors here */
-#define XSVF_ERROR_LAST 7
-
-/*****************************************************************************
- * Function: xsvfExecute
- * Description: Process, interpret, and apply the XSVF commands.
- * See port.c:readByte for source of XSVF data.
- * Parameters: none.
- * Returns: int - For error codes see above.
- *****************************************************************************/
-int xsvfExecute(void);
-
-#endif /* XSVF_MICRO_H */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*******************************************************/
-/* file: ports.c */
-/* abstract: This file contains the routines to */
-/* output values on the JTAG ports, to read */
-/* the TDO bit, and to read a byte of data */
-/* from the prom */
-/* */
-/*******************************************************/
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#include "ports.h"
-
-static unsigned long output = 0;
-static int filepos = 0;
-static int oldstate = 0;
-static int newstate = 0;
-static int readptr = 0;
-
-extern const unsigned char *xsvfdata;
-
-/* if in debugging mode, then just set the variables */
-void setPort(short p,short val)
-{
- if (p==TMS) {
- if (val) {
- output |= JTAG_TMS;
- } else {
- output &= ~JTAG_TMS;
- }
- }
- if (p==TDI) {
- if (val) {
- output |= JTAG_TDI;
- } else {
- output &= ~JTAG_TDI;
- }
- }
- if (p==TCK) {
- if (val) {
- output |= JTAG_TCK;
- } else {
- output &= ~JTAG_TCK;
- }
- out_be32((void *)GPIO0_OR, output);
- }
-}
-
-
-/* toggle tck LH */
-void pulseClock(void)
-{
- setPort(TCK,0); /* set the TCK port to low */
- setPort(TCK,1); /* set the TCK port to high */
-}
-
-
-/* read in a byte of data from the prom */
-void readByte(unsigned char *data)
-{
- /* pretend reading using a file */
- *data = xsvfdata[readptr++];
- newstate = filepos++ >> 10;
- if (newstate != oldstate) {
- printf("%4d kB\r\r\r\r", newstate);
- oldstate = newstate;
- }
-}
-
-/* read the TDO bit from port */
-unsigned char readTDOBit(void)
-{
- unsigned long inputs;
-
- inputs = in_be32((void *)GPIO0_IR);
- if (inputs & JTAG_TDO)
- return 1;
- else
- return 0;
-}
-
-
-/* Wait at least the specified number of microsec. */
-/* Use a timer if possible; otherwise estimate the number of instructions */
-/* necessary to be run based on the microcontroller speed. For this example */
-/* we pulse the TCK port a number of times based on the processor speed. */
-void waitTime(long microsec)
-{
- udelay(microsec); /* esd */
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*******************************************************/
-/* file: ports.h */
-/* abstract: This file contains extern declarations */
-/* for providing stimulus to the JTAG ports.*/
-/*******************************************************/
-
-#ifndef ports_dot_h
-#define ports_dot_h
-
-/* these constants are used to send the appropriate ports to setPort */
-/* they should be enumerated types, but some of the microcontroller */
-/* compilers don't like enumerated types */
-#define TCK (short) 0
-#define TMS (short) 1
-#define TDI (short) 2
-
-/*
- * Use CONFIG_SYS_FPGA_xxx defines from board include file.
- */
-#define JTAG_TMS CONFIG_SYS_FPGA_PRG /* output */
-#define JTAG_TCK CONFIG_SYS_FPGA_CLK /* output */
-#define JTAG_TDI CONFIG_SYS_FPGA_DATA /* output */
-#define JTAG_TDO CONFIG_SYS_FPGA_DONE /* input */
-
-/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */
-void setPort(short p, short val);
-
-/* read the TDO bit and store it in val */
-unsigned char readTDOBit(void);
-
-/* make clock go down->up->down*/
-void pulseClock(void);
-
-/* read the next byte of data from the xsvf file */
-void readByte(unsigned char *data);
-
-void waitTime(long microsec);
-
-#endif
+++ /dev/null
-if TARGET_CPCI2DP
-
-config SYS_BOARD
- default "cpci2dp"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "CPCI2DP"
-
-endif
+++ /dev/null
-CPCI2DP BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/cpci2dp/
-F: include/configs/CPCI2DP.h
-F: configs/CPCI2DP_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f (void)
-{
- unsigned long CPC0_CR0Reg;
-
- /*
- * Setup GPIO pins
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg |
- ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
- CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
-
- /* set output pins to high */
- out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP);
- /* setup for output (LED=off) */
- out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) unused
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
-
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- unsigned long CPC0_CR0Reg;
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /*
- * Select cts (and not dsr) on uart1
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming CPCI2DP");
- } else {
- puts(str);
- }
-
- printf(" (Ver 1.0)");
-
- putc ('\n');
-
- return 0;
-}
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
- */
-int eeprom_write_enable (unsigned dev_addr, int state) {
- if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
- return -1;
- } else {
- switch (state) {
- case 1:
- /* Enable write access, clear bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- case 0:
- /* Disable write access, set bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- default:
- /* Read current status back. */
- state = (0 == (in_be32((void *)GPIO0_OR) &
- CONFIG_SYS_EEPROM_WP));
- break;
- }
- }
- return state;
-}
-#endif
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int query = argc == 1;
- int state = 0;
-
- if (query) {
- /* Query write access state. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
- if (state < 0) {
- puts ("Query of write access state failed.\n");
- } else {
- printf ("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
- state = 0;
- }
- } else {
- if ('0' == argv[1][0]) {
- /* Disable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
- } else {
- /* Enable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0) {
- puts ("Setup of write access state failed.\n");
- }
- }
-
- return state;
-}
-
-U_BOOT_CMD(
- eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- ""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
- mtdcr(EBC0_CFGDATA, pbcr);
- /* printf("PB1CR = %x\n", pbcr); */
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -monitor_flash_len,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
+++ /dev/null
-if TARGET_CPCI4052
-
-config SYS_BOARD
- default "cpci405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "CPCI4052"
-
-endif
+++ /dev/null
-CPCI405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/cpci405/
-F: include/configs/CPCI405.h
-F: configs/CPCI405_defconfig
-F: include/configs/CPCI4052.h
-F: configs/CPCI4052_defconfig
-F: include/configs/CPCI405AB.h
-F: configs/CPCI405AB_defconfig
-F: include/configs/CPCI405DT.h
-F: configs/CPCI405DT_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpci405.o flash.o ../common/misc.o
-obj-y += ../common/cmd_loadpci.o
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <console.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-#include <net.h>
-#include <pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void __ft_board_setup(void *blob, bd_t *bd);
-
-#undef FPGA_DEBUG
-
-/* fpga configuration data - generated by bin2cc */
-const unsigned char fpgadata[] =
-{
-#if defined(CONFIG_CPCI405_VER2)
-# include "fpgadata_cpci4052.c"
-#endif
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-/* Prototypes */
-int cpci405_version(void);
-void lxt971_no_sleep(void);
-
-int board_early_init_f(void)
-{
-#ifndef CONFIG_CPCI405_VER2
- int index, len, i;
- int status;
-#endif
-
-#ifdef FPGA_DEBUG
- /* set up serial port with default baudrate */
- (void)get_clocks();
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init();
- console_init_f();
-#endif
-
- /*
- * First pull fpga-prg pin low,
- * to disable fpga logic (on version 2 board)
- */
- out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
- out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
- out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
- out_be32((void *)GPIO0_OR, 0); /* pull prg low */
-
- /*
- * Boot onboard FPGA
- */
-#ifndef CONFIG_CPCI405_VER2
- if (cpci405_version() == 1) {
- status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
- if (status != 0) {
- /* booting FPGA failed */
-#ifndef FPGA_DEBUG
- /* set up serial port with default baudrate */
- (void)get_clocks();
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init();
- console_init_f();
-#endif
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after "
- "asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after "
- "deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after "
- "programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = fpgadata[index];
- printf("FPGA: %s\n", &(fpgadata[index + 1]));
- index += len + 3;
- }
- putc('\n');
- /* delayed reboot */
- for (i = 20; i > 0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index = 0; index < 1000; index++)
- udelay(1000);
- }
- putc('\n');
- do_reset(NULL, 0, 0, NULL);
- }
- }
-#endif /* !CONFIG_CPCI405_VER2 */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
- * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
-#if defined(CONFIG_CPCI405_6U)
- if (cpci405_version() == 3) {
- mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
- } else {
- mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
- }
-#else
- mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
-#endif
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
- * INT0 highest priority */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- return 0;
-}
-
-int ctermm2(void)
-{
-#if defined(CONFIG_CPCI405_VER2)
- return 0; /* no, board is cpci405 */
-#else
- if ((in_8((void*)0xf0000400) == 0x00) &&
- (in_8((void*)0xf0000401) == 0x01))
- return 0; /* no, board is cpci405 */
- else
- return -1; /* yes, board is cterm-m2 */
-#endif
-}
-
-int cpci405_host(void)
-{
- if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
- return -1; /* yes, board is cpci405 host */
- else
- return 0; /* no, board is cpci405 adapter */
-}
-
-int cpci405_version(void)
-{
- unsigned long CPC0_CR0Reg;
- unsigned long value;
-
- /*
- * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
- out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
-
- /*
- * Restore GPIO settings
- */
- mtdcr(CPC0_CR0, CPC0_CR0Reg);
-
- switch (value) {
- case 0x00180000:
- /* CS2==1 && CS3==1 -> version 1 */
- return 1;
- case 0x00080000:
- /* CS2==0 && CS3==1 -> version 2 */
- return 2;
- case 0x00100000:
- /* CS2==1 && CS3==0 -> version 3 or 6U board */
- return 3;
- case 0x00000000:
- /* CS2==0 && CS3==0 -> version 4 */
- return 4;
- default:
- /* should not be reached! */
- return 2;
- }
-}
-
-int misc_init_r (void)
-{
- unsigned long CPC0_CR0Reg;
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
-#if defined(CONFIG_CPCI405_VER2)
- {
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
-
- /*
- * On CPCI-405 version 2 the environment is saved in eeprom!
- * FPGA can be gzip compressed (malloc) and booted this late.
- */
- if (cpci405_version() >= 2) {
- /*
- * Setup GPIO pins (CS6+CS7 as GPIO)
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
- (uchar *)fpgadata, &len) != 0) {
- printf("GUNZIP ERROR - must RESET board to recover\n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after "
- "asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after "
- "deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after "
- "programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index + 1]));
- index += len + 3;
- }
- putc('\n');
- /* delayed reboot */
- for (i = 20; i > 0; i--) {
- printf("Rebooting in %2d seconds \r", i);
- for (index = 0; index < 1000; index++)
- udelay(1000);
- }
- putc('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- /* restore gpio/cs settings */
- mtdcr(CPC0_CR0, CPC0_CR0Reg);
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index + 1]));
- index += len + 3;
- }
- putc('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_DATA pin
- */
- SET_FPGA(FPGA_PRG | FPGA_CLK);
- udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
- udelay(1000); /* wait 1ms */
-
-#if defined(CONFIG_CPCI405_6U)
-#error HIER GETH ES WEITER MIT IO ACCESSORS
- if (cpci405_version() == 3) {
- /*
- * Enable outputs in fpga on version 3 board
- */
- out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
- in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
- CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
-
- /*
- * Set outputs to 0
- */
- out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
-
- /*
- * Reset external DUART
- */
- out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
- in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
- CONFIG_SYS_FPGA_MODE_DUART_RESET);
- udelay(100);
- out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
- in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
- ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
- }
-#endif
- }
- else {
- puts("\n*** U-Boot Version does not match Board Version!\n");
- puts("*** CPCI-405 Version 1.x detected!\n");
- puts("*** Please use correct U-Boot version "
- "(CPCI405 instead of CPCI4052)!\n\n");
- }
- }
-#else /* CONFIG_CPCI405_VER2 */
- if (cpci405_version() >= 2) {
- puts("\n*** U-Boot Version does not match Board Version!\n");
- puts("*** CPCI-405 Board Version 2.x detected!\n");
- puts("*** Please use correct U-Boot version "
- "(CPCI4052 instead of CPCI405)!\n\n");
- }
-#endif /* CONFIG_CPCI405_VER2 */
-
- /*
- * Select cts (and not dsr) on uart1
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard(void)
-{
-#ifndef CONFIG_CPCI405_VER2
- int index;
- int len;
-#endif
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
- unsigned short ver;
-
- puts("Board: ");
-
- if (i == -1)
- puts("### No HW ID - assuming CPCI405");
- else
- puts(str);
-
- ver = cpci405_version();
- printf(" (Ver %d.x, ", ver);
-
- if (ctermm2()) {
- char str[4];
-
- /*
- * Read board-id and save in env-variable
- */
- sprintf(str, "%d", *(unsigned char *)0xf0000400);
- setenv("boardid", str);
- printf("CTERM-M2 - Id=%s)", str);
- } else {
- if (cpci405_host())
- puts("PCI Host Version)");
- else
- puts("PCI Adapter Version)");
- }
-
-#ifndef CONFIG_CPCI405_VER2
- puts("\nFPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = fpgadata[index];
- printf("%s ", &(fpgadata[index + 1]));
- index += len + 3;
- }
-#endif
-
- putc('\n');
- return 0;
-}
-
-void reset_phy(void)
-{
-#if defined(CONFIG_LXT971_NO_SLEEP)
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-#endif
-}
-
-#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
-void ide_set_reset(int on)
-{
- /*
- * Assert or deassert CompactFlash Reset Pin
- */
- if (on) { /* assert RESET */
- out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
- in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
- ~CONFIG_SYS_FPGA_MODE_CF_RESET);
- } else { /* release RESET */
- out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
- in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
- CONFIG_SYS_FPGA_MODE_CF_RESET);
- }
-}
-
-#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
-
-#if defined(CONFIG_PCI)
-void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char int_line = 0xff;
-
- /*
- * Write pci interrupt line register (cpci405 specific)
- */
- switch (PCI_DEV(dev) & 0x03) {
- case 0:
- int_line = 27 + 2;
- break;
- case 1:
- int_line = 27 + 3;
- break;
- case 2:
- int_line = 27 + 0;
- break;
- case 3:
- int_line = 27 + 1;
- break;
- }
-
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
-}
-
-int pci_pre_init(struct pci_controller *hose)
-{
- hose->fixup_irq = cpci405_pci_fixup_irq;
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- int rc;
-
- __ft_board_setup(blob, bd);
-
- /*
- * Disable PCI in adapter mode.
- */
- if (!cpci405_host()) {
- rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
- "disabled", sizeof("disabled"), 1);
- if (rc) {
- printf("Unable to update property status in PCI node, "
- "err=%s\n",
- fdt_strerror(rc));
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long calc_size(unsigned long size)
-{
- switch (size) {
- case 1 << 20:
- return 0;
- case 2 << 20:
- return 1;
- case 4 << 20:
- return 2;
- case 8 << 20:
- return 3;
- case 16 << 20:
- return 4;
- default:
- return 0;
- }
-}
-
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- base_b0 = FLASH_BASE0_PRELIM;
- size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- base_b1 = FLASH_BASE1_PRELIM;
- size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
-
- if (size_b1) {
- if (size_b1 < (1 << 20)) {
- /* minimum CS size on PPC405GP is 1MB !!! */
- size_b1 = 1 << 20;
- }
- base_b1 = -size_b1;
- mtdcr (EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr (EBC0_CFGDATA);
- mtdcr (EBC0_CFGADDR, PB0CR);
- pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
- mtdcr (EBC0_CFGDATA, pbcr);
-#if 0 /* test-only */
- printf("size_b1=%x base_b1=%x PB1CR = %x\n",
- size_b1, base_b1, pbcr); /* test-only */
-#endif
- }
-
- if (size_b0) {
- if (size_b0 < (1 << 20)) {
- /* minimum CS size on PPC405GP is 1MB !!! */
- size_b0 = 1 << 20;
- }
- base_b0 = base_b1 - size_b0;
- mtdcr (EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr (EBC0_CFGDATA);
- mtdcr (EBC0_CFGADDR, PB1CR);
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
- mtdcr (EBC0_CFGDATA, pbcr);
-#if 0 /* test-only */
- printf("size_b0=%x base_b0=%x PB0CR = %x\n",
- size_b0, base_b0, pbcr); /* test-only */
-#endif
- }
-
- size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
- flash_get_offsets (base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- base_b0 + size_b0 - monitor_flash_len,
- base_b0 + size_b0 - 1, &flash_info[0]);
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
- flash_get_offsets (base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- base_b1 + size_b1 - monitor_flash_len,
- base_b1 + size_b1 - 1, &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- flash_protect (FLAG_PROTECT_CLEAR,
- base_b0 + size_b0 - monitor_flash_len,
- base_b0 + size_b0 - 1, &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
- return (size_b0 + size_b1);
-}
+++ /dev/null
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-0x4b, 0x26, 0x86, 0x28, 0x78, 0xfb, 0x10, 0x9b,
-0x22, 0xc3, 0xf9, 0x20, 0x63, 0x59, 0x8c, 0x3b,
-0x1b, 0xe3, 0x14, 0x07, 0x84, 0x54, 0x67, 0xb0,
-0x95, 0x65, 0xe0, 0x83, 0xd4, 0x99, 0x69, 0x15,
-0x8d, 0xbf, 0xd2, 0xc3, 0xee, 0xd9, 0x0a, 0x1d,
-0x48, 0x4c, 0x7e, 0x5b, 0xfb, 0x0b, 0x28, 0x5d,
-0xde, 0x20, 0x02, 0x0d, 0xb5, 0xee, 0x89, 0xb8,
-0x84, 0x58, 0x87, 0x8f, 0xd1, 0xb0, 0x47, 0x26,
-0xa2, 0xb5, 0x8f, 0x62, 0x08, 0xdf, 0xec, 0x47,
-0x2b, 0xb4, 0x3e, 0x04, 0xa8, 0x88, 0x68, 0xed,
-0x3f, 0xe5, 0x5e, 0x3d, 0xfe, 0x71, 0xa0, 0x61,
-0x8b, 0x07, 0x9b, 0x0f, 0x46, 0x8c, 0x7b, 0x46,
-0x19, 0xea, 0x50, 0x29, 0x2e, 0x78, 0x39, 0xbd,
-0x21, 0x79, 0x2d, 0xbf, 0x8e, 0x2a, 0xc4, 0x06,
-0x08, 0x63, 0x92, 0x28, 0x60, 0x83, 0x6a, 0x0d,
-0xb0, 0xe6, 0xa9, 0xe3, 0xfc, 0x9d, 0xde, 0x22,
-0xd6, 0x18, 0x89, 0x7f, 0xd5, 0x5b, 0x94, 0xc3,
-0xba, 0x15, 0xb0, 0xb1, 0xab, 0x3c, 0xfe, 0xfb,
-0xde, 0x92, 0xa3, 0xc2, 0xc6, 0xae, 0x55, 0xf1,
-0xdf, 0xf4, 0x5a, 0x3e, 0xa1, 0x70, 0x2b, 0x60,
-0x09, 0xdd, 0x19, 0xff, 0x9c, 0xf7, 0xd6, 0xa3,
-0x05, 0x1b, 0xbb, 0x76, 0xc6, 0x3f, 0xef, 0xb5,
-0xfc, 0x33, 0xa6, 0xe1, 0xbc, 0x88, 0xbf, 0x1e,
-0x3d, 0x0a, 0x4b, 0xba, 0x1e, 0xc6, 0xc8, 0x5c,
-0x36, 0x6c, 0xae, 0x9d, 0x73, 0x73, 0xd5, 0xf4,
-0x3e, 0xb9, 0x94, 0x05, 0x6f, 0xd6, 0x70, 0x47,
-0x05, 0x13, 0xe7, 0x15, 0x5c, 0x43, 0x25, 0x8e,
-0x5b, 0xe1, 0x85, 0x27, 0xa1, 0xb2, 0xcb, 0xcb,
-0x22, 0x3a, 0x35, 0xbe, 0x2f, 0x86, 0x7b, 0xe3,
-0x42, 0x27, 0x14, 0xc3, 0x6f, 0x52, 0x29, 0x2b,
-0x34, 0x70, 0xc5, 0xe8, 0x33, 0xb9, 0x77, 0xc4,
-0xad, 0x81, 0xf5, 0x5d, 0x85, 0x72, 0x81, 0x7e,
-0xcf, 0x42, 0x39, 0x12, 0x45, 0x3e, 0x67, 0xcc,
-0xd3, 0x46, 0x4c, 0x33, 0x26, 0x84, 0x47, 0x74,
-0xc0, 0xb7, 0xfa, 0x30, 0x3e, 0x28, 0x47, 0x3c,
-0x32, 0x42, 0x40, 0xab, 0x10, 0x53, 0x3d, 0x08,
-0xf8, 0x25, 0x4a, 0xde, 0x3b, 0xc2, 0x30, 0x1a,
-0xb4, 0x89, 0xf8, 0x42, 0xd6, 0x60, 0x60, 0xb5,
-0x39, 0xd1, 0x3f, 0x8d, 0x3e, 0x41, 0xc3, 0x79,
-0xaa, 0x19, 0x51, 0xd1, 0x5f, 0x86, 0x69, 0x6b,
-0xbc, 0x27, 0x01, 0xc4, 0x79, 0x59, 0xf4, 0x92,
-0x02, 0x99, 0x22, 0xe0, 0xfb, 0x45, 0xb0, 0xe6,
-0x09, 0x05, 0x8c, 0x2f, 0xfd, 0x1e, 0xba, 0xa5,
-0x60, 0x11, 0x27, 0xd3, 0x9e, 0xa0, 0xe1, 0xf5,
-0x3c, 0xc5, 0x3b, 0x4e, 0xaa, 0xe1, 0x5b, 0xf0,
-0x88, 0x52, 0x98, 0x7b, 0xef, 0xf1, 0x02, 0x91,
-0xb3, 0xc3, 0x0a, 0x8a, 0x32, 0xdf, 0x8f, 0x6b,
-0xf7, 0xe5, 0xd6, 0x1e, 0x13, 0x38, 0xa8, 0x8c,
-0x89, 0x31, 0x52, 0xc6, 0xfe, 0x94, 0x4d, 0xcc,
-0xf9, 0x10, 0xf1, 0xa0, 0x7f, 0x9a, 0xf6, 0x6c,
-0x03, 0x1b, 0x14, 0x76, 0xb4, 0xc6, 0x3c, 0x6f,
-0xc0, 0x02, 0x28, 0x8a, 0x93, 0xdf, 0x86, 0x61,
-0x6b, 0xed, 0xad, 0x42, 0x5c, 0x91, 0xa4, 0xb6,
-0xf2, 0x92, 0x6e, 0x14, 0xa6, 0x5e, 0x69, 0x45,
-0x45, 0xce, 0x3f, 0x39, 0x9d, 0xbb, 0x61, 0x5c,
-0x49, 0x0a, 0xda, 0x9f, 0x45, 0x92, 0xc1, 0x7a,
-0x47, 0x9c, 0xd8, 0x86, 0x38, 0x4f, 0x11, 0xe7,
-0xe9, 0x7a, 0x1d, 0xf0, 0x9f, 0xce, 0xd9, 0x53,
-0x51, 0x62, 0x1b, 0x3d, 0x60, 0xb3, 0x71, 0x2d,
-0x23, 0xb1, 0x07, 0x3d, 0x82, 0x4d, 0xca, 0xd9,
-0x53, 0x10, 0xd3, 0x11, 0xd1, 0xb3, 0x55, 0xa8,
-0xec, 0x42, 0x9c, 0x07, 0xcf, 0x93, 0x36, 0x19,
-0xed, 0x69, 0xbc, 0x5b, 0xce, 0x6e, 0x23, 0xda,
-0xda, 0x04, 0x0d, 0xf0, 0xf7, 0x80, 0xdf, 0xc2,
-0x25, 0xe5, 0xde, 0x07, 0xf8, 0x2f, 0x2a, 0xc9,
-0xd3, 0x77, 0x2e, 0x5d, 0xfb, 0xc0, 0xbc, 0x52,
-0xe5, 0xb9, 0xb3, 0xeb, 0x96, 0x16, 0x5a, 0xf7,
-0xe4, 0xa2, 0xf2, 0xe3, 0x95, 0x3b, 0xe1, 0xf7,
-0x71, 0x2e, 0x6d, 0x8f, 0x94, 0x3c, 0x2c, 0xcc,
-0x83, 0x3c, 0x9c, 0xd7, 0xe1, 0x1d, 0x21, 0xb5,
-0xca, 0x1b, 0x1d, 0x61, 0xd8, 0xfa, 0xef, 0x80,
-0xf3, 0xb5, 0x9f, 0x32, 0xae, 0xfe, 0x53, 0xfa,
-0x18, 0xbc, 0x97, 0x1e, 0xd4, 0xe7, 0xf2, 0xda,
-0x33, 0x4b, 0x92, 0x4f, 0x5d, 0xc9, 0xf5, 0x91,
-0x24, 0xec, 0x62, 0x07, 0x0f, 0x25, 0xab, 0x91,
-0xeb, 0xc3, 0x0d, 0xcb, 0x19, 0x1b, 0xd6, 0x68,
-0xe4, 0x4d, 0x26, 0x89, 0xbc, 0x58, 0x64, 0x68,
-0x68, 0x35, 0x72, 0xd7, 0x5c, 0xd7, 0x54, 0x20,
-0xbf, 0x0f, 0xc1, 0x73, 0x4c, 0x7b, 0xb9, 0xdd,
-0x41, 0xa3, 0x91, 0x9b, 0x8b, 0xd6, 0x0b, 0x62,
-0xae, 0x61, 0xcd, 0x84, 0xf1, 0x0c, 0x59, 0x3b,
-0x3e, 0x69, 0xfd, 0x0a, 0xb1, 0xfa, 0xd8, 0x7f,
-0x8d, 0x69, 0x3f, 0xe6, 0x43, 0x7a, 0x7f, 0xae,
-0xcf, 0x9e, 0x24, 0xbb, 0x60, 0x40, 0xa9, 0x91,
-0xf4, 0x06, 0xd4, 0x48, 0xb9, 0x27, 0xde, 0xb4,
-0xbe, 0xca, 0xdc, 0xfa, 0xc4, 0x9b, 0xd7, 0x57,
-0x49, 0xac, 0x71, 0xa2, 0xc4, 0xfe, 0x3e, 0xda,
-0x18, 0x2e, 0xab, 0x5c, 0xc5, 0x86, 0xb6, 0x3e,
-0x22, 0x58, 0xe3, 0x36, 0x07, 0xf1, 0xd7, 0xbf,
-0x8e, 0xe3, 0xcc, 0x46, 0xee, 0x79, 0x84, 0x11,
-0x24, 0x59, 0x11, 0x73, 0x8d, 0x39, 0xf6, 0x94,
-0xd9, 0xf3, 0xf2, 0x1a, 0xe6, 0x25, 0x51, 0x9e,
-0x85, 0x91, 0x7a, 0xfc, 0x87, 0x37, 0x75, 0x91,
-0xf9, 0x9d, 0xcd, 0xa7, 0x5c, 0x4d, 0x4d, 0xbf,
-0xfc, 0x33, 0x97, 0xeb, 0x5f, 0x1c, 0xf6, 0x7f,
-0x71, 0x35, 0xcf, 0xce, 0xce, 0xaa, 0x73, 0x1a,
-0xff, 0x6f, 0xf6, 0x7d, 0x9a, 0xcf, 0x03, 0x73,
-0x05, 0xc8, 0xf9, 0x3c, 0xfc, 0x3b, 0xf9, 0x7c,
-0xbe, 0x57, 0xe7, 0x79, 0xe0, 0xa7, 0xfa, 0xbc,
-0x68, 0xfa, 0xbc, 0xd5, 0x98, 0xeb, 0xf3, 0x73,
-0x47, 0xfe, 0x1a, 0x9f, 0x1f, 0x1b, 0xf8, 0x7a,
-0x4d, 0xf9, 0x70, 0x6e, 0xdc, 0xaf, 0xdd, 0xd3,
-0xbf, 0xe4, 0xf3, 0xca, 0x1c, 0x9f, 0xb7, 0x96,
-0xa5, 0x39, 0xff, 0xd7, 0xa1, 0x7c, 0x58, 0xf8,
-0x97, 0xc7, 0x7d, 0xda, 0x9e, 0xfe, 0x34, 0xbb,
-0x40, 0x1e, 0x8b, 0xcb, 0x59, 0x58, 0xfe, 0xe5,
-0x9f, 0xdd, 0x74, 0x7d, 0xe6, 0xf3, 0xbf, 0xae,
-0xef, 0xd7, 0x5f, 0xec, 0x6f, 0x39, 0x12, 0xed,
-0xdf, 0x2d, 0xaf, 0xfd, 0x6b, 0xc7, 0x7c, 0x76,
-0x7d, 0x76, 0x7d, 0x76, 0x7d, 0x76, 0x7d, 0x76,
-0x7d, 0x76, 0xfd, 0xff, 0x72, 0x69, 0x71, 0x92,
-0x68, 0x71, 0x52, 0xfd, 0x8f, 0x9e, 0xcb, 0x67,
-0xd7, 0x67, 0xd7, 0x67, 0xd7, 0x67, 0xd7, 0x67,
-0xd7, 0x67, 0xd7, 0x7f, 0xc4, 0x15, 0x64, 0x65,
-0x00, 0xd8, 0xfb, 0xb2, 0xf1, 0xf7, 0xff, 0xf9,
-0x20, 0x28, 0xf3, 0x3e, 0xfd, 0xf7, 0xb5, 0xdf,
-0xb3, 0x05, 0x21, 0xcd, 0xe5, 0xc6, 0xf7, 0xa7,
-0x6e, 0x9e, 0xeb, 0xff, 0x01, 0x51, 0x16, 0x5f,
-0xd0, 0xd5, 0x60, 0x00, 0x00,
+++ /dev/null
-if TARGET_PLU405
-
-config SYS_BOARD
- default "plu405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "PLU405"
-
-endif
+++ /dev/null
-PLU405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/plu405/
-F: include/configs/PLU405.h
-F: configs/PLU405_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = plu405.o flash.o \
- ../common/misc.o \
- ../common/esd405ep_nand.o \
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
+++ /dev/null
-0x1f, 0x8b, 0x08, 0x08, 0x04, 0x44, 0x9f, 0x46,
-0x00, 0x03, 0x70, 0x6c, 0x75, 0x34, 0x30, 0x35,
-0x5f, 0x31, 0x5f, 0x31, 0x2e, 0x62, 0x69, 0x74,
-0x00, 0x94, 0x9a, 0x0f, 0x70, 0x14, 0x55, 0x9e,
-0xc7, 0x7f, 0xfd, 0xba, 0x93, 0x74, 0xa6, 0x3b,
-0xe9, 0x36, 0x7f, 0x30, 0xb7, 0x08, 0xd7, 0x19,
-0x07, 0x76, 0xc4, 0x61, 0x18, 0x42, 0x80, 0x98,
-0x0d, 0x49, 0x33, 0xa4, 0xac, 0x71, 0xc9, 0x1e,
-0xf1, 0xce, 0xbb, 0xe2, 0xf6, 0xbc, 0xdd, 0x11,
-0x71, 0x8f, 0xbb, 0xe2, 0x2c, 0xd6, 0xdd, 0xb3,
-0xb8, 0x3b, 0x4b, 0x5f, 0x66, 0xa2, 0x04, 0x92,
-0x92, 0x01, 0x39, 0x37, 0xba, 0xac, 0x35, 0x40,
-0x6e, 0x8d, 0x4a, 0x59, 0x11, 0x75, 0x8d, 0x82,
-0xbb, 0x4d, 0x0c, 0x3a, 0x60, 0xd4, 0xb9, 0x94,
-0x7b, 0x8b, 0x7f, 0x8e, 0x6d, 0xd8, 0xc0, 0x46,
-0x89, 0x3a, 0xcb, 0xa2, 0x06, 0x65, 0xcd, 0xbd,
-0xd7, 0x3d, 0xdd, 0xd3, 0x99, 0x9e, 0x04, 0x37,
-0x5a, 0xc5, 0x2f, 0xaf, 0x1f, 0x8f, 0xf7, 0xfb,
-0xcd, 0xef, 0xfd, 0x7e, 0x9f, 0xfe, 0xbe, 0x81,
-0x52, 0x29, 0x63, 0xfe, 0x07, 0xc0, 0xdc, 0x06,
-0xd2, 0x96, 0xcd, 0xff, 0x56, 0x1f, 0x5a, 0xfe,
-0xfd, 0xa5, 0xdf, 0x5f, 0x1a, 0xbc, 0xf3, 0xf6,
-0x8d, 0xb0, 0x01, 0x84, 0xba, 0x1f, 0x2d, 0x0f,
-0xdd, 0xf1, 0xe3, 0x1f, 0x2e, 0xad, 0xaf, 0x87,
-0xdb, 0xc9, 0x6f, 0xa1, 0xd0, 0xca, 0x25, 0xe4,
-0xff, 0xa5, 0x37, 0xc0, 0x46, 0x28, 0x5d, 0x5a,
-0xd7, 0xb8, 0xfc, 0x86, 0xc6, 0xa5, 0x2b, 0xe1,
-0x0e, 0x60, 0x96, 0xf5, 0x4d, 0x91, 0x9f, 0x27,
-0x1f, 0xf9, 0xdb, 0x1f, 0x84, 0x00, 0x33, 0x00,
-0x50, 0x12, 0x62, 0xa2, 0xf4, 0x4f, 0x21, 0xc4,
-0x28, 0x0c, 0xe0, 0x96, 0xc5, 0x21, 0xd0, 0xe8,
-0xef, 0x90, 0x7d, 0x5e, 0x1a, 0x02, 0xc5, 0xf9,
-0x3b, 0x13, 0x02, 0x15, 0xda, 0x41, 0xed, 0x81,
-0x0a, 0x19, 0xae, 0xf8, 0xc3, 0xa8, 0x1c, 0xb6,
-0xec, 0x3f, 0x73, 0xfe, 0xd4, 0x09, 0x3c, 0xe3,
-0xb4, 0xdc, 0x4f, 0xcb, 0x85, 0xa4, 0x65, 0xa2,
-0xd0, 0xd7, 0x59, 0x1f, 0xec, 0xf5, 0xdf, 0xfd,
-0x5a, 0xeb, 0x7f, 0x66, 0xad, 0xff, 0xe7, 0xce,
-0x87, 0x8a, 0xaf, 0x31, 0x1d, 0x80, 0xb3, 0xf7,
-0x63, 0x86, 0x87, 0x03, 0x06, 0x43, 0x14, 0x64,
-0x28, 0xa6, 0x86, 0x42, 0x46, 0x10, 0x80, 0x69,
-0x18, 0xeb, 0x0f, 0x5b, 0xf3, 0x87, 0x8a, 0xbe,
-0x82, 0x29, 0xdc, 0xa2, 0x8a, 0x1a, 0x5b, 0x8f,
-0x76, 0xe2, 0x16, 0x5d, 0x4a, 0xb1, 0x75, 0xf0,
-0x16, 0x35, 0x26, 0x59, 0xe3, 0x11, 0x35, 0x32,
-0xb0, 0xc5, 0x9a, 0x5f, 0xf3, 0x31, 0x1c, 0xc6,
-0x4b, 0xa2, 0x91, 0x2e, 0x4f, 0x33, 0xbc, 0x17,
-0x0b, 0xea, 0x42, 0x17, 0xda, 0x0f, 0x4f, 0x61,
-0x62, 0x0c, 0x22, 0xfa, 0xc8, 0x30, 0x32, 0x9c,
-0x15, 0xc5, 0x13, 0x45, 0x3d, 0xdc, 0x01, 0x10,
-0x55, 0xbf, 0xec, 0xe9, 0x84, 0x18, 0x04, 0x34,
-0x41, 0xae, 0x68, 0x85, 0x38, 0x35, 0x42, 0x68,
-0x04, 0x9e, 0x35, 0x8d, 0x43, 0x8c, 0xb5, 0xbe,
-0xc6, 0x1d, 0x84, 0xc3, 0x10, 0x8c, 0x96, 0xf6,
-0xc6, 0xbe, 0x89, 0x1e, 0x85, 0xe0, 0x51, 0xa1,
-0x17, 0xfd, 0x1e, 0x9e, 0x82, 0xa0, 0x26, 0x0c,
-0xa0, 0x09, 0xfa, 0x88, 0x18, 0xde, 0x0c, 0x17,
-0xcd, 0xce, 0x5f, 0x7d, 0xd5, 0x04, 0x9c, 0x87,
-0xe6, 0x0d, 0xa2, 0xcc, 0x2e, 0x14, 0x53, 0xbb,
-0x9a, 0xef, 0x28, 0xe9, 0x89, 0x6f, 0x80, 0xd7,
-0xa1, 0x59, 0x93, 0x06, 0xd8, 0x09, 0xf8, 0xd2,
-0x34, 0xd2, 0x9c, 0xb5, 0x7e, 0x92, 0x39, 0x02,
-0x53, 0xd0, 0xb4, 0xba, 0x3c, 0x73, 0xed, 0x08,
-0x4c, 0xf1, 0xf7, 0xa9, 0x25, 0x1a, 0x3b, 0x40,
-0x46, 0x5a, 0x34, 0x29, 0xc3, 0x5e, 0xb6, 0x8c,
-0x71, 0xb0, 0xd6, 0xd7, 0xe4, 0x83, 0x74, 0x91,
-0xa8, 0xf8, 0x73, 0x76, 0x81, 0x7a, 0x02, 0x35,
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-0x08, 0xf5, 0x1f, 0xdf, 0xed, 0x3f, 0x0a, 0xcb,
-0xf5, 0x8a, 0x0e, 0x93, 0xda, 0x03, 0xf8, 0x01,
-0xcd, 0xde, 0xa4, 0x16, 0x0a, 0xe4, 0x43, 0xed,
-0x65, 0x26, 0x24, 0x53, 0xac, 0x87, 0x6e, 0x22,
-0xaf, 0xb7, 0xa6, 0xbc, 0xc5, 0x35, 0xd8, 0x90,
-0xc7, 0xc5, 0x3e, 0x1c, 0xd5, 0x82, 0x2d, 0x79,
-0x1d, 0xcd, 0x19, 0xc7, 0x38, 0xf5, 0x2c, 0xbe,
-0x40, 0x1a, 0xf4, 0xa2, 0x0a, 0xce, 0x0b, 0x58,
-0x2d, 0x7b, 0xb0, 0x5a, 0xb0, 0xed, 0x5c, 0x25,
-0x2c, 0xec, 0x89, 0x3b, 0x19, 0x28, 0x3a, 0xf9,
-0x60, 0xfd, 0x34, 0x4d, 0x91, 0xc0, 0x2d, 0xa2,
-0xc1, 0x8d, 0xa5, 0x12, 0x1f, 0xa6, 0xc6, 0xad,
-0x9f, 0x05, 0xa9, 0x86, 0x8d, 0x66, 0xd7, 0xf3,
-0x2b, 0x32, 0xee, 0xfb, 0x68, 0x82, 0x8a, 0x54,
-0xda, 0x6f, 0x76, 0x8c, 0xe9, 0x1b, 0x03, 0xce,
-0xf5, 0xc1, 0xf7, 0xcb, 0xa0, 0x11, 0x4d, 0x78,
-0xf0, 0x4b, 0x13, 0x06, 0x8d, 0x1f, 0x45, 0x5d,
-0x2c, 0x42, 0xac, 0x31, 0x82, 0xa6, 0x19, 0x0f,
-0x8c, 0x51, 0xce, 0xf5, 0xf1, 0xa8, 0xff, 0x10,
-0x1f, 0x82, 0xc2, 0x69, 0x14, 0x70, 0x3e, 0xf5,
-0xe4, 0x82, 0xb0, 0xa0, 0xa8, 0xc6, 0xf8, 0x10,
-0xf3, 0xd9, 0x3f, 0x4d, 0x7c, 0x88, 0xcd, 0x60,
-0x3f, 0x32, 0xd9, 0x7c, 0x0b, 0xf9, 0x10, 0x52,
-0x3e, 0xcc, 0x41, 0xd1, 0xc9, 0x47, 0xec, 0xe8,
-0x3f, 0xa5, 0xb6, 0x93, 0x1b, 0xe7, 0xfa, 0xa8,
-0xca, 0x55, 0x78, 0x08, 0x35, 0xfa, 0xe2, 0x40,
-0x32, 0xf1, 0x30, 0x6b, 0x3b, 0x1e, 0x99, 0xf5,
-0xbc, 0x23, 0x39, 0xf9, 0x24, 0xb8, 0x4d, 0x53,
-0xb8, 0x4d, 0x9a, 0xf6, 0x0b, 0x37, 0x4e, 0xfb,
-0x5b, 0x70, 0x5c, 0xdc, 0xc2, 0x48, 0xbc, 0x95,
-0xfe, 0xcb, 0xe9, 0x3f, 0x31, 0x9e, 0xe0, 0x09,
-0x35, 0xf5, 0x4d, 0xf5, 0x91, 0x7e, 0xba, 0x11,
-0xa9, 0xba, 0x5f, 0x95, 0x30, 0x84, 0x48, 0x79,
-0x64, 0x7e, 0x82, 0x34, 0xe2, 0xd4, 0x33, 0xbe,
-0x53, 0x8f, 0xa9, 0xc9, 0xb8, 0x1a, 0xcb, 0xfb,
-0xd0, 0x3e, 0x3d, 0xa9, 0xaa, 0x0d, 0x5c, 0xd6,
-0x06, 0x2f, 0x46, 0xf3, 0x02, 0xda, 0xaa, 0x4e,
-0x66, 0xd3, 0xc9, 0x67, 0x51, 0x5e, 0x19, 0x86,
-0xd1, 0x52, 0x08, 0xdf, 0xcb, 0x64, 0x80, 0xa6,
-0x1e, 0xa0, 0x19, 0x1a, 0x73, 0x37, 0x33, 0x6e,
-0xff, 0x51, 0xc4, 0x87, 0x83, 0x0a, 0x3d, 0xa7,
-0xdc, 0xf9, 0xd4, 0xd0, 0x89, 0x14, 0xd7, 0xa7,
-0xd7, 0x49, 0xf6, 0x84, 0xb5, 0x25, 0xa1, 0x75,
-0xe7, 0x6b, 0x1f, 0x41, 0xb1, 0x15, 0xdc, 0xcc,
-0xb0, 0xf0, 0x81, 0x1c, 0xe3, 0x43, 0xec, 0x3f,
-0x9d, 0x8b, 0xc1, 0x8c, 0xec, 0x9e, 0xf6, 0xfd,
-0x4e, 0xec, 0x37, 0x64, 0x57, 0x04, 0xca, 0x1a,
-0x08, 0x3a, 0x32, 0x0e, 0x6c, 0xc4, 0xa9, 0x1f,
-0x2a, 0xc0, 0xfc, 0xb9, 0x83, 0xbf, 0x36, 0x81,
-0x25, 0x09, 0xb6, 0x36, 0x45, 0x6e, 0x8a, 0x7a,
-0x00, 0x69, 0xb1, 0x50, 0x95, 0xf9, 0xb0, 0x9f,
-0x19, 0x1b, 0x71, 0xeb, 0x67, 0xa5, 0x7a, 0x41,
-0xdd, 0x7b, 0xde, 0x3a, 0xaa, 0x57, 0x2a, 0x55,
-0xf5, 0xdb, 0xf3, 0x83, 0x47, 0x27, 0x57, 0xc4,
-0x05, 0x34, 0xc7, 0xd0, 0x54, 0x53, 0xe3, 0xe4,
-0x23, 0x90, 0x07, 0x90, 0x0f, 0xf1, 0xa6, 0xff,
-0xf3, 0x1c, 0xdd, 0xfd, 0x2f, 0x37, 0x0b, 0x0c,
-0x78, 0x2b, 0x0f, 0x1c, 0xc9, 0xf8, 0x70, 0xf7,
-0xd9, 0xb3, 0xc4, 0x87, 0xcf, 0xae, 0x1d, 0x31,
-0x7c, 0xf8, 0xc4, 0xf0, 0xe1, 0xef, 0x64, 0x96,
-0x9d, 0xe5, 0x70, 0x2a, 0xe3, 0xc3, 0x93, 0x37,
-0xce, 0x13, 0x1f, 0x6e, 0xbf, 0x3e, 0x65, 0xc0,
-0xec, 0x95, 0xe5, 0xc3, 0x5f, 0xb7, 0x5f, 0x6d,
-0x97, 0x78, 0xec, 0x7d, 0x65, 0xb0, 0xf0, 0xe5,
-0x3a, 0x1e, 0xf6, 0xdf, 0x14, 0x14, 0xe7, 0x1e,
-0x2f, 0x93, 0x31, 0x7c, 0x68, 0x22, 0xdf, 0xba,
-0xeb, 0x0d, 0x16, 0xfe, 0xf3, 0x37, 0xa5, 0x91,
-0x81, 0xe2, 0x0d, 0x63, 0x2c, 0x1f, 0x52, 0xa4,
-0xc4, 0xab, 0x27, 0x33, 0x3e, 0x3c, 0xb0, 0xef,
-0xdc, 0x9f, 0x77, 0xda, 0xb4, 0xfe, 0xbb, 0x73,
-0xa3, 0xcf, 0xe9, 0x85, 0x39, 0x6a, 0x7e, 0x78,
-0xf6, 0x11, 0x8e, 0x58, 0xf8, 0xb6, 0xc6, 0xbf,
-0x8b, 0xf5, 0x0f, 0x3f, 0x0a, 0x8b, 0xc5, 0x62,
-0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0xfa, 0xd4,
-0x65, 0x66, 0x07, 0xc9, 0xb3, 0x03, 0x8b, 0xc5,
-0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x7a,
-0xb7, 0xcc, 0xec, 0x50, 0xe3, 0xd9, 0x81, 0xc5,
-0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62,
-0xbd, 0x5b, 0x66, 0x76, 0xf0, 0xcc, 0xec, 0xf0,
-0xb1, 0x53, 0x61, 0xb1, 0x58, 0x2c, 0x16, 0x8b,
-0xc5, 0x62, 0xb1, 0x58, 0xff, 0xa3, 0x22, 0xfa,
-0x7d, 0x1c, 0x3c, 0xfb, 0x23, 0x02, 0x4d, 0xbf,
-0x5a, 0xa9, 0x46, 0xa0, 0xde, 0xfb, 0xf3, 0x84,
-0xf4, 0xb5, 0x13, 0x11, 0x6c, 0x88, 0xe2, 0x98,
-0x7f, 0x7d, 0xb9, 0x73, 0xdd, 0x1b, 0x3b, 0x1c,
-0x29, 0xc2, 0xf0, 0x33, 0x01, 0x00,
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-#include <sja1000.h>
-
-#undef FPGA_DEBUG
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-/*
- * generate a short spike on the CAN tx line
- * to bring the couplers in sync
- */
-void init_coupler(u32 addr)
-{
- struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
-
- /* reset */
- out_8(&ctrl->cr, CR_RR);
-
- /* dominant */
- out_8(&ctrl->btr0, 0x00); /* btr setup is required */
- out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
- out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
- OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
- out_8(&ctrl->cr, 0x00);
-
- /* delay */
- in_8(&ctrl->cr);
- in_8(&ctrl->cr);
- in_8(&ctrl->cr);
- in_8(&ctrl->cr);
-
- /* reset */
- out_8(&ctrl->cr, CR_RR);
-}
-
-int board_early_init_f(void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to
- * 512 ebc-clks -> ca. 15 us
- */
- mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- unsigned char *dst;
- unsigned char fctr;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
- (uchar *)fpgadata, &len) != 0) {
- printf("GUNZIP ERROR - must RESET board to recover\n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low "
- "after asserting PROGRAM*)\n");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high "
- "after deasserting PROGRAM*)\n");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high "
- "after programming FPGA)\n");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_DATA pin
- */
- SET_FPGA(FPGA_PRG | FPGA_CLK);
- udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
- udelay(1000); /* wait 1ms */
-
- /*
- * Reset external DUARTs
- */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
- udelay(10);
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
- udelay(1000);
-
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) &
- ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
-
- /*
- * Setup EEPROM write protection
- */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
- out_be32((void*)GPIO0_TCR,
- in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
-
- /*
- * Enable interrupts in exar duart mcr[3]
- */
- out_8((void *)DUART0_BA + 4, 0x08);
- out_8((void *)DUART1_BA + 4, 0x08);
-
- /*
- * Enable auto RS485 mode in 2nd external uart
- */
- out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
- fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
- fctr |= 0x08; /* enable RS485 mode */
- out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
- out_8((void *)DUART1_BA + 3, 0); /* write LCR */
-
- /*
- * Init magnetic couplers
- */
- if (!getenv("noinitcoupler")) {
- init_coupler(CAN0_BA);
- init_coupler(CAN1_BA);
- }
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts("Board: ");
-
- if (i == -1)
- puts("### No HW ID - assuming PLU405");
- else
- puts(str);
-
- putc('\n');
- return 0;
-}
-
-#ifdef CONFIG_IDE_RESET
-#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
-void ide_set_reset(int on)
-{
- /*
- * Assert or deassert CompactFlash Reset Pin
- */
- if (on) { /* assert RESET */
- out_be16((void *)FPGA_CTRL,
- in_be16((void *)FPGA_CTRL) &
- ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
- } else { /* release RESET */
- out_be16((void *)FPGA_CTRL,
- in_be16((void *)FPGA_CTRL) |
- CONFIG_SYS_FPGA_CTRL_CF_RESET);
- }
-}
-#endif /* CONFIG_IDE_RESET */
-
-void reset_phy(void)
-{
-#ifdef CONFIG_LXT971_NO_SLEEP
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-#endif
-}
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
- */
-int eeprom_write_enable(unsigned dev_addr, int state)
-{
- if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
- return -1;
- } else {
- switch (state) {
- case 1:
- /* Enable write access, clear bit GPIO0. */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) &
- ~CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- case 0:
- /* Disable write access, set bit GPIO0. */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) |
- CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- default:
- /* Read current status back. */
- state = ((in_be32((void*)GPIO0_OR) &
- CONFIG_SYS_EEPROM_WP) == 0);
- break;
- }
- }
- return state;
-}
-
-int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int query = argc == 1;
- int state = 0;
-
- if (query) {
- /* Query write access state. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
- if (state < 0) {
- puts("Query of write access state failed.\n");
- } else {
- printf("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR,
- state ? "en" : "dis");
- state = 0;
- }
- } else {
- if (argv[1][0] == '0') {
- /* Disable write access. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
- 0);
- } else {
- /* Enable write access. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
- 1);
- }
- if (state < 0)
- puts("Setup of write access state failed.\n");
- }
-
- return state;
-}
-
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- ""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+++ /dev/null
-if TARGET_PMC405DE
-
-config SYS_BOARD
- default "pmc405de"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "PMC405DE"
-
-endif
+++ /dev/null
-PMC405DE BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/pmc405de/
-F: include/configs/PMC405DE.h
-F: configs/PMC405DE_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pmc405de.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-obj-y += ../common/cmd_loadpci.o
+++ /dev/null
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
- {
- "133",
- "CPU: 133 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
- {
- 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x40, 0x12, 0x12, 0x42, 0x3e, 0x00, 0x00
- }
- },
- {
- "266",
- "CPU: 266 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
- {
- 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x50, 0x22, 0x2d, 0x42, 0x3e, 0x00, 0x00
- }
- },
- {
- "333",
- "CPU: 333 PLB: 111 OPB: 55 EBC: 55 PCI: 55/111",
- {
- 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x60, 0x29, 0x2d, 0x42, 0xbe, 0x00, 0x00
- }
- },
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/4xx_pci.h>
-#include <command.h>
-#include <malloc.h>
-
-/*
- * PMC405-DE cpld registers
- * - all registers are 8 bit
- * - all registers are on 32 bit addesses
- */
-struct pmc405de_cpld {
- /* cpld design version */
- u8 version;
- u8 reserved0[3];
-
- /* misc. status lines */
- u8 status;
- u8 reserved1[3];
-
- /*
- * gated control flags
- * gate bit(s) must be written with '1' to
- * access control flag
- */
- u8 control;
- u8 reserved2[3];
-};
-
-#define CPLD_VERSION_MASK 0x0f
-#define CPLD_CONTROL_POSTLED_N 0x01
-#define CPLD_CONTROL_POSTLED_GATE 0x02
-#define CPLD_CONTROL_RESETOUT_N 0x40
-#define CPLD_CONTROL_RESETOUT_N_GATE 0x80
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void __ft_board_setup(void *blob, bd_t *bd);
-extern void pll_write(u32 a, u32 b);
-
-static int wait_for_pci_ready_done;
-
-static int is_monarch(void);
-static int pci_is_66mhz(void);
-static int board_revision(void);
-static int cpld_revision(void);
-static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
-
-int board_early_init_f(void)
-{
- u32 pllmr0, pllmr1;
-
- /*
- * check M66EN and patch PLB:PCI divider for 66MHz PCI
- *
- * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
- * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
- * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
- * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
- *
- * calling upd_plb_pci_div() may end in calling pll_write() which will
- * do a chip reset and never return.
- */
- pllmr0 = mfdcr(CPC0_PLLMR0);
- pllmr1 = mfdcr(CPC0_PLLMR1);
-
- if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
- /* fCPU=333MHz, fPLB=111MHz */
- if (pci_is_66mhz())
- upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
- else
- upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
- } else {
- /* fCPU=133|266MHz, fPLB=133MHz */
- if (pci_is_66mhz())
- upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
- else
- upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
- }
-
- /*
- * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register:
- * - set ready timeout to 512 ebc-clks -> ca. 15 us
- * - EBC lines are always driven
- */
- mtebc(EBC0_CFG, 0xa8400000);
-
- return 0;
-}
-
-static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
-{
- if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
- pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
-}
-
-int misc_init_r(void)
-{
- int i;
- struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
- struct pmc405de_cpld *cpld =
- (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
-
- if (!is_monarch()) {
- /* PCI configuration done: release EREADY */
- setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
- setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
- }
-
- /* turn off POST LED */
- out_8(&cpld->control,
- CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
-
- /* turn on LEDs: RUN, A, B */
- clrbits_be32(&gpio0->or,
- CONFIG_SYS_GPIO_LEDRUN_N |
- CONFIG_SYS_GPIO_LEDA_N |
- CONFIG_SYS_GPIO_LEDB_N);
-
- for (i=0; i < 200; i++)
- udelay(1000);
-
- /* turn off LEDs: A, B */
- setbits_be32(&gpio0->or,
- CONFIG_SYS_GPIO_LEDA_N |
- CONFIG_SYS_GPIO_LEDB_N);
-
- return (0);
-}
-
-static int is_monarch(void)
-{
- struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
- return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
-}
-
-static int pci_is_66mhz(void)
-{
- struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
- return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
-}
-
-static int board_revision(void)
-{
- struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
- return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
- CONFIG_SYS_GPIO_HWREV_SHIFT);
-}
-
-static int cpld_revision(void)
-{
- struct pmc405de_cpld *cpld =
- (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
- return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
- puts("Board: esd GmbH - PMC-CPU/405-DE");
-
- gd->board_type = board_revision();
- printf(", Rev 1.%ld, ", gd->board_type);
-
- if (!is_monarch())
- puts("non-");
-
- printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
- pci_is_66mhz() ? "66" : "33", cpld_revision());
-
- return 0;
-}
-
-
-static void wait_for_pci_ready(void)
-{
- struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
- int i;
- char *s = getenv("pcidelay");
-
- /* only wait once */
- if (wait_for_pci_ready_done)
- return;
-
- /*
- * We have our own handling of the pcidelay variable.
- * Using CONFIG_PCI_BOOTDELAY enables pausing for host
- * and adapter devices. For adapter devices we do not
- * want this.
- */
- if (s) {
- int ms = simple_strtoul(s, NULL, 10);
- printf("PCI: Waiting for %d ms\n", ms);
- for (i=0; i<ms; i++)
- udelay(1000);
- }
-
- if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
- printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
- while (1) {
- if (ctrlc()) {
- puts("abort\n");
- break;
- }
- if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
- printf("done\n");
- break;
- }
- }
- }
-
- wait_for_pci_ready_done = 1;
-}
-
-/*
- * Overwrite weak is_pci_host()
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-int is_pci_host(struct pci_controller *hose)
-{
- char *s;
-
- if (!is_monarch()) {
- /*
- * Overwrite PCI identification when running in
- * non-monarch mode
- * This should be moved into pci_target_init()
- * when it is sometimes available for 405 CPUs
- */
- pci_write_config_word(PCIDEVID_405GP,
- PCI_SUBSYSTEM_ID,
- CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
- pci_write_config_word(PCIDEVID_405GP,
- PCI_CLASS_SUB_CODE,
- CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
- }
-
- s = getenv("pciscan");
- if (s == NULL) {
- if (is_monarch()) {
- wait_for_pci_ready();
- return 1;
- } else {
- return 0;
- }
- } else {
- if (!strcmp(s, "yes"))
- return 1;
- }
-
- return 0;
-}
-
-/*
- * Overwrite weak pci_pre_init()
- *
- * The default implementation enables the 405EP
- * internal PCI arbiter. We do not want that
- * on a PMC module.
- */
-int pci_pre_init(struct pci_controller *hose)
-{
- return 1;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- int rc;
-
- __ft_board_setup(blob, bd);
-
- /*
- * Disable PCI in non-monarch mode.
- */
- if (!is_monarch()) {
- rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
- "disabled", sizeof("disabled"), 1);
- if (rc) {
- printf("Unable to update property status in PCI node, "
- "err=%s\n",
- fdt_strerror(rc));
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
- */
-int eeprom_write_enable(unsigned dev_addr, int state)
-{
- struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
-
- if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
- return -1;
- } else {
- switch (state) {
- case 1:
- /* Enable write access, clear bit GPIO0. */
- clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
- state = 0;
- break;
- case 0:
- /* Disable write access, set bit GPIO0. */
- setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
- state = 0;
- break;
- default:
- /* Read current status back. */
- state = (0 == (in_be32(&gpio0->or) &
- CONFIG_SYS_GPIO_EEPROM_WP));
- break;
- }
- }
- return state;
-}
-
-int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int query = argc == 1;
- int state = 0;
-
- if (query) {
- /* Query write access state. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
- if (state < 0) {
- puts("Query of write access state failed.\n");
- } else {
- printf("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR,
- state ? "en" : "dis");
- state = 0;
- }
- } else {
- if ('0' == argv[1][0]) {
- /* Disable write access. */
- state = eeprom_write_enable(
- CONFIG_SYS_I2C_EEPROM_ADDR, 0);
- } else {
- /* Enable write access. */
- state = eeprom_write_enable(
- CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0)
- puts ("Setup of write access state failed.\n");
- }
-
- return state;
-}
-
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- ""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-#if defined(CONFIG_PRAM)
-#include <environment.h>
-
-int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 pram, nextbase, base;
- char *v;
- u32 param;
- ulong *lptr;
-
- v = getenv("pram");
- if (v)
- pram = simple_strtoul(v, NULL, 10);
- else {
- printf("Error: pram undefined. Please define pram in KiB\n");
- return 1;
- }
-
- base = gd->bd->bi_memsize;
-#if defined(CONFIG_LOGBUFFER)
- base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
-#endif
- /*
- * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
- */
- param = base - (pram << 10);
- printf("PARAM: @%08x\n", param);
- debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
-
- /* clear entire PA ram */
- memset((void*)param, 0, (pram << 10));
-
- /* reserve 4k for pointer field */
- nextbase = base - 4096;
- lptr = (ulong*)(base);
-
- /*
- * *(--lptr) = item_size;
- * *(--lptr) = base - item_base = distance from field top;
- */
-
- /* env is first (4k aligned) */
- nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
- memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
- *(--lptr) = CONFIG_ENV_SIZE; /* size */
- *(--lptr) = base - nextbase; /* offset | type=0 */
-
- /* free section */
- *(--lptr) = nextbase - param; /* size */
- *(--lptr) = (base - param) | 126; /* offset | type=126 */
-
- /* terminate pointer field */
- *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
- *(--lptr) = 0; /* offset=0 -> terminator */
- return 0;
-}
-U_BOOT_CMD(
- painit, 1, 1, do_painit,
- "prepare PciAccess system",
- ""
-);
-#endif /* CONFIG_PRAM */
-
-int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
- setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
- return 0;
-}
-U_BOOT_CMD(
- selfreset, 1, 1, do_selfreset,
- "assert self-reset# signal",
- ""
-);
-
-int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct pmc405de_cpld *cpld =
- (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
-
- if (argc > 1) {
- if (argv[1][0] == '0') {
- /* assert */
- printf("PMC-RESETOUT# asserted\n");
- out_8(&cpld->control,
- CPLD_CONTROL_RESETOUT_N_GATE);
- } else {
- /* deassert */
- printf("PMC-RESETOUT# deasserted\n");
- out_8(&cpld->control,
- CPLD_CONTROL_RESETOUT_N |
- CPLD_CONTROL_RESETOUT_N_GATE);
- }
- } else {
- printf("PMC-RESETOUT# is %s\n",
- (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
- "inactive" : "active");
- }
- return 0;
-}
-U_BOOT_CMD(
- resetout, 2, 1, do_resetout,
- "assert PMC-RESETOUT# signal",
- ""
-);
+++ /dev/null
-if TARGET_PMC440
-
-config SYS_BOARD
- default "pmc440"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "PMC440"
-
-endif
+++ /dev/null
-PMC440 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/pmc440/
-F: include/configs/PMC440.h
-F: configs/PMC440_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pmc440.o cmd_pmc440.o sdram.o fpga.o \
- ../common/cmd_loadpci.o
-extra-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/processor.h>
-#if defined(CONFIG_LOGBUFFER)
-#include <logbuff.h>
-#endif
-
-#include "pmc440.h"
-
-int is_monarch(void);
-int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt);
-int eeprom_write_enable(unsigned dev_addr, int state);
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_BSP)
-
-static int got_fifoirq;
-static int got_hcirq;
-
-int fpga_interrupt(u32 arg)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
- int rc = -1; /* not for us */
- u32 status = FPGA_IN32(&fpga->status);
-
- /* check for interrupt from fifo module */
- if (status & STATUS_FIFO_ISF) {
- /* disable this int source */
- FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
- rc = 0;
- got_fifoirq = 1; /* trigger backend */
- }
-
- if (status & STATUS_HOST_ISF) {
- FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
- rc = 0;
- got_hcirq = 1;
- }
-
- return rc;
-}
-
-int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- got_hcirq = 0;
-
- FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
- FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
-
- irq_install_handler(IRQ0_FPGA,
- (interrupt_handler_t *)fpga_interrupt,
- fpga);
-
- FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
-
- while (!got_hcirq) {
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- break;
- }
- }
- if (got_hcirq)
- printf("Got interrupt!\n");
-
- FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
- irq_free_handler(IRQ0_FPGA);
- return 0;
-}
-U_BOOT_CMD(
- waithci, 1, 1, do_waithci,
- "Wait for host control interrupt",
- ""
-);
-
-void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
-{
- u32 ctrl;
-
- while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
- printf("%5d %d %3d %08x",
- (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
- FPGA_IN32(&fpga->fifo[f].data));
- if (ctrl & FIFO_OVERFLOW) {
- printf(" OVERFLOW\n");
- FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
- } else
- printf("\n");
- }
-}
-
-int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
- int i;
- int n = 0;
- u32 ctrl, data, f;
- char str[] = "\\|/-";
- int abort = 0;
- int count = 0;
- int count2 = 0;
-
- switch (argc) {
- case 1:
- /* print all fifos status information */
- printf("fifo level status\n");
- printf("______________________________\n");
- for (i=0; i<FIFO_COUNT; i++) {
- ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
- printf(" %d %3d %s%s%s %s\n",
- i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
- ctrl & FIFO_FULL ? "FULL " : "",
- ctrl & FIFO_EMPTY ? "EMPTY " : "",
- ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
- ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
- }
- break;
-
- case 2:
- /* completely read out fifo 'n' */
- if (!strcmp(argv[1],"read")) {
- printf(" # fifo level data\n");
- printf("______________________________\n");
-
- for (i=0; i<FIFO_COUNT; i++)
- dump_fifo(fpga, i, &n);
-
- } else if (!strcmp(argv[1],"wait")) {
- got_fifoirq = 0;
-
- irq_install_handler(IRQ0_FPGA,
- (interrupt_handler_t *)fpga_interrupt,
- fpga);
-
- printf(" # fifo level data\n");
- printf("______________________________\n");
-
- /* enable all fifo interrupts */
- FPGA_OUT32(&fpga->hostctrl,
- HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
- for (i=0; i<FIFO_COUNT; i++) {
- /* enable interrupts from all fifos */
- FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
- }
-
- while (1) {
- /* wait loop */
- while (!got_fifoirq) {
- count++;
- if (!(count % 100)) {
- count2++;
- putc(0x08); /* backspace */
- putc(str[count2 % 4]);
- }
-
- /* Abort if ctrl-c was pressed */
- if ((abort = ctrlc())) {
- puts("\nAbort\n");
- break;
- }
- udelay(1000);
- }
- if (abort)
- break;
-
- /* simple fifo backend */
- if (got_fifoirq) {
- for (i=0; i<FIFO_COUNT; i++)
- dump_fifo(fpga, i, &n);
-
- got_fifoirq = 0;
- /* unmask global fifo irq */
- FPGA_OUT32(&fpga->hostctrl,
- HOSTCTRL_FIFOIE_GATE |
- HOSTCTRL_FIFOIE_FLAG);
- }
- }
-
- /* disable all fifo interrupts */
- FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
- for (i=0; i<FIFO_COUNT; i++)
- FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
-
- irq_free_handler(IRQ0_FPGA);
-
- } else {
- printf("Usage:\nfifo %s\n", cmdtp->help);
- return 1;
- }
- break;
-
- case 4:
- case 5:
- if (!strcmp(argv[1],"write")) {
- /* get fifo number or fifo address */
- f = simple_strtoul(argv[2], NULL, 16);
-
- /* data paramter */
- data = simple_strtoul(argv[3], NULL, 16);
-
- /* get optional count parameter */
- n = 1;
- if (argc >= 5)
- n = (int)simple_strtoul(argv[4], NULL, 10);
-
- if (f < FIFO_COUNT) {
- printf("writing %d x %08x to fifo %d\n",
- n, data, f);
- for (i=0; i<n; i++)
- FPGA_OUT32(&fpga->fifo[f].data, data);
- } else {
- printf("writing %d x %08x to fifo port at "
- "address %08x\n",
- n, data, f);
- for (i=0; i<n; i++)
- out_be32((void *)f, data);
- }
- } else {
- printf("Usage:\nfifo %s\n", cmdtp->help);
- return 1;
- }
- break;
-
- default:
- printf("Usage:\nfifo %s\n", cmdtp->help);
- return 1;
- }
- return 0;
-}
-U_BOOT_CMD(
- fifo, 5, 1, do_fifo,
- "Fifo module operations",
- "wait\nfifo read\n"
- "fifo write fifo(0..3) data [cnt=1]\n"
- "fifo write address(>=4) data [cnt=1]\n"
- " - without arguments: print all fifo's status\n"
- " - with 'wait' argument: interrupt driven read from all fifos\n"
- " - with 'read' argument: read current contents from all fifos\n"
- " - with 'write' argument: write 'data' 'cnt' times to "
- "'fifo' or 'address'"
-);
-
-int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong sdsdp[5];
- ulong delay;
- int count=16;
-
- if (argc < 2) {
- printf("Usage:\nsbe %s\n", cmdtp->help);
- return -1;
- }
-
- if (argc > 1) {
- if (!strcmp(argv[1], "400")) {
- /* PLB=133MHz, PLB/PCI=3 */
- printf("Bootstrapping for 400MHz\n");
- sdsdp[0]=0x8678624e;
- sdsdp[1]=0x095fa030;
- sdsdp[2]=0x40082350;
- sdsdp[3]=0x0d050000;
- } else if (!strcmp(argv[1], "533")) {
- /* PLB=133MHz, PLB/PCI=3 */
- printf("Bootstrapping for 533MHz\n");
- sdsdp[0]=0x87788252;
- sdsdp[1]=0x095fa030;
- sdsdp[2]=0x40082350;
- sdsdp[3]=0x0d050000;
- } else if (!strcmp(argv[1], "667")) {
- /* PLB=133MHz, PLB/PCI=3 */
- printf("Bootstrapping for 667MHz\n");
- sdsdp[0]=0x8778a256;
- sdsdp[1]=0x095fa030;
- sdsdp[2]=0x40082350;
- sdsdp[3]=0x0d050000;
- } else {
- printf("Usage:\nsbe %s\n", cmdtp->help);
- return -1;
- }
- }
-
- if (argc > 2) {
- sdsdp[4] = 0;
- if (argv[2][0]=='1')
- sdsdp[4]=0x19750100;
- else if (argv[2][0]=='0')
- sdsdp[4]=0x19750000;
- if (sdsdp[4])
- count += 4;
- }
-
- if (argc > 3) {
- delay = simple_strtoul(argv[3], NULL, 10);
- if (delay > 20)
- delay = 20;
- sdsdp[4] |= delay;
- }
-
- printf("Writing boot EEPROM ...\n");
- if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
- 0, (uchar*)sdsdp, count) != 0)
- printf("bootstrap_eeprom_write failed\n");
- else
- printf("done (dump via 'i2c md 52 0.1 14')\n");
-
- return 0;
-}
-U_BOOT_CMD(
- sbe, 4, 0, do_setup_bootstrap_eeprom,
- "setup bootstrap eeprom",
- "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
-);
-
-#if defined(CONFIG_PRAM)
-#include <environment.h>
-#include <search.h>
-#include <errno.h>
-
-int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 pram, nextbase, base;
- char *v;
- u32 param;
- ulong *lptr;
-
- env_t *envp;
- char *res;
- int len;
-
- v = getenv("pram");
- if (v)
- pram = simple_strtoul(v, NULL, 10);
- else {
- printf("Error: pram undefined. Please define pram in KiB\n");
- return 1;
- }
-
- base = (u32)gd->ram_size;
-#if defined(CONFIG_LOGBUFFER)
- base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
-#endif
- /*
- * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
- */
- param = base - (pram << 10);
- printf("PARAM: @%08x\n", param);
- debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base);
-
- /* clear entire PA ram */
- memset((void*)param, 0, (pram << 10));
-
- /* reserve 4k for pointer field */
- nextbase = base - 4096;
- lptr = (ulong*)(base);
-
- /*
- * *(--lptr) = item_size;
- * *(--lptr) = base - item_base = distance from field top;
- */
-
- /* env is first (4k aligned) */
- nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
- envp = (env_t *)nextbase;
- res = (char *)envp->data;
- len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
- if (len < 0) {
- error("Cannot export environment: errno = %d\n", errno);
- return 1;
- }
- envp->crc = crc32(0, envp->data, ENV_SIZE);
-
- *(--lptr) = CONFIG_ENV_SIZE; /* size */
- *(--lptr) = base - nextbase; /* offset | type=0 */
-
- /* free section */
- *(--lptr) = nextbase - param; /* size */
- *(--lptr) = (base - param) | 126; /* offset | type=126 */
-
- /* terminate pointer field */
- *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
- *(--lptr) = 0; /* offset=0 -> terminator */
- return 0;
-}
-U_BOOT_CMD(
- painit, 1, 1, do_painit,
- "prepare PciAccess system",
- ""
-);
-#endif /* CONFIG_PRAM */
-
-int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- in_be32((void*)CONFIG_SYS_RESET_BASE);
- return 0;
-}
-U_BOOT_CMD(
- selfreset, 1, 1, do_selfreset,
- "assert self-reset# signal",
- ""
-);
-
-int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- /* requiers bootet FPGA and PLD_IOEN_N active */
- if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
- printf("Error: resetout requires a bootet FPGA\n");
- return -1;
- }
-
- if (argc > 1) {
- if (argv[1][0] == '0') {
- /* assert */
- printf("PMC-RESETOUT# asserted\n");
- FPGA_OUT32(&fpga->hostctrl,
- HOSTCTRL_PMCRSTOUT_GATE);
- } else {
- /* deassert */
- printf("PMC-RESETOUT# deasserted\n");
- FPGA_OUT32(&fpga->hostctrl,
- HOSTCTRL_PMCRSTOUT_GATE |
- HOSTCTRL_PMCRSTOUT_FLAG);
- }
- } else {
- printf("PMC-RESETOUT# is %s\n",
- FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
- "inactive" : "active");
- }
-
- return 0;
-}
-U_BOOT_CMD(
- resetout, 2, 1, do_resetout,
- "assert PMC-RESETOUT# signal",
- ""
-);
-
-int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (is_monarch()) {
- printf("This command is only supported in non-monarch mode\n");
- return -1;
- }
-
- if (argc > 1) {
- if (argv[1][0] == '0') {
- /* assert */
- printf("inta# asserted\n");
- out_be32((void*)GPIO1_TCR,
- in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
- } else {
- /* deassert */
- printf("inta# deasserted\n");
- out_be32((void*)GPIO1_TCR,
- in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
- }
- } else {
- printf("inta# is %s\n",
- in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
- "active" : "inactive");
- }
- return 0;
-}
-U_BOOT_CMD(
- inta, 2, 1, do_inta,
- "Assert/Deassert or query INTA# state in non-monarch mode",
- ""
-);
-
-/* test-only */
-int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong pciaddr;
-
- if (argc > 1) {
- pciaddr = simple_strtoul(argv[1], NULL, 16);
-
- pciaddr &= 0xf0000000;
-
- /* map PCI address at 0xc0000000 in PLB space */
-
- /* PMM1 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1MA, 0x00000000);
- /* PMM1 Local Address */
- out32r(PCIL0_PMM1LA, 0xc0000000);
- /* PMM1 PCI Low Address */
- out32r(PCIL0_PMM1PCILA, pciaddr);
- /* PMM1 PCI High Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000);
- /* 256MB + No prefetching, and enable region */
- out32r(PCIL0_PMM1MA, 0xf0000001);
- } else {
- printf("Usage:\npmm %s\n", cmdtp->help);
- }
- return 0;
-}
-U_BOOT_CMD(
- pmm, 2, 1, do_pmm,
- "Setup pmm[1] registers",
- "<pciaddr> (pciaddr will be aligned to 256MB)"
-);
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int query = argc == 1;
- int state = 0;
-
- if (query) {
- /* Query write access state. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
- if (state < 0) {
- puts("Query of write access state failed.\n");
- } else {
- printf("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
- state = 0;
- }
- } else {
- if ('0' == argv[1][0]) {
- /* Disable write access. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
- } else {
- /* Enable write access. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0) {
- puts("Setup of write access state failed.\n");
- }
- }
-
- return state;
-}
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- ""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-#endif /* CONFIG_CMD_BSP */
+++ /dev/null
-#
-# (C) Copyright 2002-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <spartan2.h>
-#include <spartan3.h>
-#include <command.h>
-#include "fpga.h"
-#include "pmc440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_FPGA)
-
-#define USE_SP_CODE
-
-#ifdef USE_SP_CODE
-xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
- fpga_pre_config_fn,
- fpga_pgm_fn,
- fpga_init_fn,
- NULL, /* err */
- fpga_done_fn,
- fpga_clk_fn,
- fpga_cs_fn,
- fpga_wr_fn,
- NULL, /* rdata */
- fpga_wdata_fn,
- fpga_busy_fn,
- fpga_abort_fn,
- fpga_post_config_fn,
-};
-#else
-xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
- fpga_pre_config_fn,
- fpga_pgm_fn,
- fpga_clk_fn,
- fpga_init_fn,
- fpga_done_fn,
- fpga_wr_fn,
- fpga_post_config_fn,
-};
-#endif
-
-xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
- ngcc_fpga_pre_config_fn,
- ngcc_fpga_pgm_fn,
- ngcc_fpga_clk_fn,
- ngcc_fpga_init_fn,
- ngcc_fpga_done_fn,
- ngcc_fpga_wr_fn,
- ngcc_fpga_post_config_fn
-};
-
-xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- XILINX_XC3S1200E_DESC(
-#ifdef USE_SP_CODE
- slave_parallel,
-#else
- slave_serial,
-#endif
- (void *)&pmc440_fpga_fns,
- 0),
- XILINX_XC2S200_DESC(
- slave_serial,
- (void *)&ngcc_fpga_fns,
- 0)
-};
-
-
-/*
- * Set the active-low FPGA reset signal.
- */
-void fpga_reset(int assert)
-{
- debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
- if (assert) {
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
- debug("asserted\n");
- } else {
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
- debug("deasserted\n");
- }
-}
-
-
-/*
- * Initialize the SelectMap interface. We assume that the mode and the
- * initial state of all of the port pins have already been set!
- */
-void fpga_serialslave_init(void)
-{
- debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
- __LINE__);
- fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
-}
-
-
-/*
- * Set the FPGA's active-low SelectMap program line to the specified level
- */
-int fpga_pgm_fn(int assert, int flush, int cookie)
-{
- debug("%s:%d: FPGA PROGRAM ",
- __FUNCTION__, __LINE__);
-
- if (assert) {
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
- debug("asserted\n");
- } else {
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
- debug("deasserted\n");
- }
- return assert;
-}
-
-
-/*
- * Test the state of the active-low FPGA INIT line. Return 1 on INIT
- * asserted (low).
- */
-int fpga_init_fn(int cookie)
-{
- if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
- return 0;
- else
- return 1;
-}
-
-#ifdef USE_SP_CODE
-int fpga_abort_fn(int cookie)
-{
- return 0;
-}
-
-
-int fpga_cs_fn(int assert_cs, int flush, int cookie)
-{
- return assert_cs;
-}
-
-
-int fpga_busy_fn(int cookie)
-{
- return 1;
-}
-#endif
-
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-int fpga_done_fn(int cookie)
-{
- if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
- return 1;
- else
- return 0;
-}
-
-
-/*
- * FPGA pre-configuration function. Just make sure that
- * FPGA reset is asserted to keep the FPGA from starting up after
- * configuration.
- */
-int fpga_pre_config_fn(int cookie)
-{
- debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
- fpga_reset(true);
-
- /* release init# */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
- /* disable PLD IOs */
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
- return 0;
-}
-
-
-/*
- * FPGA post configuration function. Blip the FPGA reset line and then see if
- * the FPGA appears to be running.
- */
-int fpga_post_config_fn(int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
- int rc=0;
- char *s;
-
- debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
-
- /* enable PLD0..7 pins */
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
-
- fpga_reset(true);
- udelay (100);
- fpga_reset(false);
- udelay (100);
-
- FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
-
- /* NGCC/CANDES only: enable ledlink */
- if ((s = getenv("bd_type")) &&
- ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes"))))
- FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
-
- return rc;
-}
-
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- if (assert_clk)
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
- else
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
-
- return assert_clk;
-}
-
-
-int fpga_wr_fn(int assert_write, int flush, int cookie)
-{
- if (assert_write)
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
- else
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
-
- return assert_write;
-}
-
-#ifdef USE_SP_CODE
-int fpga_wdata_fn(uchar data, int flush, int cookie)
-{
- uchar val = data;
- ulong or = in_be32((void*)GPIO1_OR);
- int i = 7;
- do {
- /* Write data */
- if (val & 0x80)
- or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
- else
- or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
-
- out_be32((void*)GPIO1_OR, or);
-
- /* Assert the clock */
- or |= GPIO1_FPGA_CLK;
- out_be32((void*)GPIO1_OR, or);
- val <<= 1;
- i --;
- } while (i > 0);
-
- /* Write last data bit (the 8th clock comes from the sp_load() code */
- if (val & 0x80)
- or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
- else
- or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
-
- out_be32((void*)GPIO1_OR, or);
-
- return 0;
-}
-#endif
-
-#define NGCC_FPGA_PRG CLOCK_EN
-#define NGCC_FPGA_DATA RESET_OUT
-#define NGCC_FPGA_DONE CLOCK_IN
-#define NGCC_FPGA_INIT IRIGB_R_IN
-#define NGCC_FPGA_CLK CLOCK_OUT
-
-void ngcc_fpga_serialslave_init(void)
-{
- debug("%s:%d: Initialize serial slave interface\n",
- __FUNCTION__, __LINE__);
-
- /* make sure program pin is inactive */
- ngcc_fpga_pgm_fn(false, false, 0);
-}
-
-/*
- * Set the active-low FPGA reset signal.
- */
-void ngcc_fpga_reset(int assert)
-{
- debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
-
- if (assert) {
- FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
- debug("asserted\n");
- } else {
- FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
- debug("deasserted\n");
- }
-}
-
-
-/*
- * Set the FPGA's active-low SelectMap program line to the specified level
- */
-int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
-
- if (assert) {
- FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
- debug("asserted\n");
- } else {
- FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
- debug("deasserted\n");
- }
-
- return assert;
-}
-
-
-/*
- * Test the state of the active-low FPGA INIT line. Return 1 on INIT
- * asserted (low).
- */
-int ngcc_fpga_init_fn(int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
- if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
- debug("high\n");
- return 0;
- } else {
- debug("low\n");
- return 1;
- }
-}
-
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-int ngcc_fpga_done_fn(int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
- if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
- debug("DONE high\n");
- return 1;
- } else {
- debug("low\n");
- return 0;
- }
-}
-
-
-/*
- * FPGA pre-configuration function.
- */
-int ngcc_fpga_pre_config_fn(int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
- debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
-
- ngcc_fpga_reset(true);
- FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
-
- ngcc_fpga_reset(true);
- return 0;
-}
-
-
-/*
- * FPGA post configuration function. Blip the FPGA reset line and then see if
- * the FPGA appears to be running.
- */
-int ngcc_fpga_post_config_fn(int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
-
- udelay (100);
- ngcc_fpga_reset(false);
-
- FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
-
- return 0;
-}
-
-
-int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- if (assert_clk)
- FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
- else
- FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
-
- return assert_clk;
-}
-
-
-int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- if (assert_write)
- FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
- else
- FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
-
- return assert_write;
-}
-
-
-/*
- * Initialize the fpga. Return 1 on success, 0 on failure.
- */
-int pmc440_init_fpga(void)
-{
- char *s;
-
- debug("%s:%d: Initialize FPGA interface\n",
- __FUNCTION__, __LINE__);
- fpga_init();
-
- fpga_serialslave_init ();
- debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
- fpga_add (fpga_xilinx, &fpga[0]);
-
- /* NGCC only */
- if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
- ngcc_fpga_serialslave_init ();
- debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
- fpga_add (fpga_xilinx, &fpga[1]);
- }
-
- return 0;
-}
-#endif /* CONFIG_FPGA */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern int pmc440_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_init_fn(int cookie);
-extern int fpga_err_fn(int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
-extern int fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int fpga_wdata_fn (uchar data, int flush, int cookie);
-extern int fpga_read_data_fn(unsigned char *data, int cookie);
-extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
-extern int fpga_busy_fn(int cookie);
-extern int fpga_abort_fn(int cookie );
-extern int fpga_pre_config_fn(int cookie );
-extern int fpga_post_config_fn(int cookie );
-
-extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int ngcc_fpga_init_fn(int cookie);
-extern int ngcc_fpga_done_fn(int cookie);
-extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int ngcc_fpga_pre_config_fn(int cookie );
-extern int ngcc_fpga_post_config_fn(int cookie );
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- */
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-
- /* TLB entries for DDR2 SDRAM are generated dynamically */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
-#endif
-
- /* TLB-entry for PCI Memory */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
-
- /* TLB-entries for EBC */
- /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
- * tlb entry.
- * This dummy entry is only for convinience in order not to modify the
- * amount of entries. Currently OS/9 relies on this :-)
- */
- tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for NAND */
- tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for Internal Registers & OCM */
- tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
-
- /*TLB-entry PCI registers*/
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
- /* TLB-entry PCI IO space */
- tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
-
- /* TODO: what about high IO space */
- tlbtab_end
+++ /dev/null
-/*
- * (Cg) Copyright 2007-2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- * Based on board/amcc/sequoia/sequoia.c
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <console.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/ppc440.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <i2c.h>
-#ifdef CONFIG_RESET_PHY_R
-#include <miiphy.h>
-#endif
-#include <serial.h>
-#include <asm/4xx_pci.h>
-#include <usb.h>
-
-#include "fpga.h"
-#include "pmc440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-extern void __ft_board_setup(void *blob, bd_t *bd);
-
-ulong flash_get_size(ulong base, int banknum);
-static int pci_is_66mhz(void);
-int is_monarch(void);
-static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt);
-
-struct serial_device *default_serial_console(void)
-{
- uchar buf[4];
- ulong delay;
- int i;
- ulong val;
-
- /*
- * Use default console on P4 when strapping jumper
- * is installed (bootstrap option != 'H').
- */
- mfsdr(SDR0_PINSTP, val);
- if (((val & 0xf0000000) >> 29) != 7)
- return &eserial2_device;
-
- ulong scratchreg = in_be32((void *)GPIO0_ISR3L);
- if (!(scratchreg & 0x80)) {
- /* mark scratchreg valid */
- scratchreg = (scratchreg & 0xffffff00) | 0x80;
-
- i2c_init_all();
-
- i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
- 0x10, buf, 4);
- if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
- scratchreg |= buf[2];
-
- /* bringup delay for console */
- for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++)
- udelay(1000);
- } else
- scratchreg |= 0x01;
- out_be32((void *)GPIO0_ISR3L, scratchreg);
- }
-
- if (scratchreg & 0x01)
- return &eserial2_device;
- else
- return &eserial1_device;
-}
-
-int board_early_init_f(void)
-{
- u32 sdr0_cust0;
- u32 sdr0_pfc1, sdr0_pfc2;
- u32 reg;
-
- /* general EBC configuration (disable EBC timeouts) */
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, 0xf8400000);
-
- /* Setup the GPIO pins */
- out_be32((void *)GPIO0_OR, 0x40000102);
- out_be32((void *)GPIO0_TCR, 0x4c90011f);
- out_be32((void *)GPIO0_OSRL, 0x28051400);
- out_be32((void *)GPIO0_OSRH, 0x55005000);
- out_be32((void *)GPIO0_TSRL, 0x08051400);
- out_be32((void *)GPIO0_TSRH, 0x55005000);
- out_be32((void *)GPIO0_ISR1L, 0x54000000);
- out_be32((void *)GPIO0_ISR1H, 0x00000000);
- out_be32((void *)GPIO0_ISR2L, 0x44000000);
- out_be32((void *)GPIO0_ISR2H, 0x00000100);
- out_be32((void *)GPIO0_ISR3L, 0x00000000);
- out_be32((void *)GPIO0_ISR3H, 0x00000000);
-
- out_be32((void *)GPIO1_OR, 0x80002408);
- out_be32((void *)GPIO1_TCR, 0xd6003c08);
- out_be32((void *)GPIO1_OSRL, 0x0a5a0000);
- out_be32((void *)GPIO1_OSRH, 0x00000000);
- out_be32((void *)GPIO1_TSRL, 0x00000000);
- out_be32((void *)GPIO1_TSRH, 0x00000000);
- out_be32((void *)GPIO1_ISR1L, 0x00005555);
- out_be32((void *)GPIO1_ISR1H, 0x40000000);
- out_be32((void *)GPIO1_ISR2L, 0x04010000);
- out_be32((void *)GPIO1_ISR2H, 0x00000000);
- out_be32((void *)GPIO1_ISR3L, 0x01400000);
- out_be32((void *)GPIO1_ISR3H, 0x00000000);
-
- /* patch PLB:PCI divider for 66MHz PCI */
- mfcpr(CPR0_SPCID, reg);
- if (pci_is_66mhz() && (reg != 0x02000000)) {
- mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
-
- mfcpr(CPR0_ICFG, reg);
- reg |= CPR0_ICFG_RLI_MASK;
- mtcpr(CPR0_ICFG, reg);
-
- mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
- }
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffff7ef);
- mtdcr(UIC0TR, 0x00000000);
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffc7f5);
- mtdcr(UIC1TR, 0x00000000);
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0x27ffffff);
- mtdcr(UIC2TR, 0x00000000);
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- /* select Ethernet pins */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_4;
- mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_4;
-
- /* enable 2nd IIC */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
-
- mtsdr(SDR0_PFC2, sdr0_pfc2);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* setup NAND FLASH */
- mfsdr(SDR0_CUST0, sdr0_cust0);
- sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
- mtsdr(SDR0_CUST0, sdr0_cust0);
-
- return 0;
-}
-
-#if defined(CONFIG_MISC_INIT_F)
-int misc_init_f(void)
-{
- struct pci_controller hose;
- hose.first_busno = 0;
- hose.last_busno = 0;
- hose.region_count = 0;
-
- if (getenv("pciearly") && (!is_monarch())) {
- printf("PCI: early target init\n");
- pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
- pci_target_init(&hose);
- }
- return 0;
-}
-#endif
-
-/*
- * misc_init_r.
- */
-int misc_init_r(void)
-{
- uint pbcr;
- int size_val = 0;
- u32 reg;
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1;
- unsigned long sdr0_srst0, sdr0_srst1;
- char *act = getenv("usbact");
-
- /*
- * FLASH stuff...
- */
-
- /* Re-do sizing to get full correct info */
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- size_val = ffs(gd->bd->bi_flashsize) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- /* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- /*
- * USB suff...
- */
- if ((act == NULL || strcmp(act, "host") == 0) &&
- !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-
- /*
- * An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
-
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /*
- * Take USB out of reset:
- * -Initial status = all cores are in reset
- * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
- * -wait 1 ms
- * -deassert reset to PHY
- * -wait 1 ms
- * -deassert reset to HOST
- * -wait 4 ms
- * -deassert all other resets
- */
- mfsdr(SDR0_SRST1, sdr0_srst1);
- sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
- SDR0_SRST1_P4OPB0 | \
- SDR0_SRST1_OPBA2 | \
- SDR0_SRST1_PLB42OPB1 | \
- SDR0_SRST1_OPB2PLB40);
- mtsdr(SDR0_SRST1, sdr0_srst1);
- udelay(1000);
-
- mfsdr(SDR0_SRST1, sdr0_srst1);
- sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
- mtsdr(SDR0_SRST1, sdr0_srst1);
- udelay(1000);
-
- mfsdr(SDR0_SRST0, sdr0_srst0);
- sdr0_srst0 &= ~SDR0_SRST0_USB2H;
- mtsdr(SDR0_SRST0, sdr0_srst0);
- udelay(4000);
-
- /* finally all the other resets */
- mtsdr(SDR0_SRST1, 0x00000000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
- /* enable power on USB socket */
- out_be32((void *)GPIO1_OR,
- in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
- }
-
- printf("USB: Host\n");
-
- } else if ((strcmp(act, "dev") == 0) ||
- (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x672c6000);
-
- udelay (1000);
- mtsdr(SDR0_SRST0, 0x00000080);
-
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x60206000);
-
- *(unsigned int *)(0xe0000350) = 0x00000001;
-
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x60306000);
-
- /* SDR Setting */
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_PFC1, sdr0_pfc1);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
-
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
-
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
-
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /*clear resets*/
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Device\n");
- }
-
- /*
- * Clear PLB4A0_ACR[WRP]
- * This fix will make the MAL burst disabling patch for the Linux
- * EMAC driver obsolete.
- */
- reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
- mtdcr(PLB4A0_ACR, reg);
-
-#ifdef CONFIG_FPGA
- pmc440_init_fpga();
-#endif
-
- /* turn off POST LED */
- out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N);
- /* turn on RUN LED */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N);
- return 0;
-}
-
-int is_monarch(void)
-{
- if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH)
- return 0;
-
- return 1;
-}
-
-static int pci_is_66mhz(void)
-{
- if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN)
- return 1;
- return 0;
-}
-
-static int board_revision(void)
-{
- return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
-}
-
-int checkboard(void)
-{
- puts("Board: esd GmbH - PMC440");
-
- gd->board_type = board_revision();
- printf(", Rev 1.%ld, ", gd->board_type);
-
- if (!is_monarch()) {
- puts("non-");
- }
-
- printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
- return (0);
-}
-
-
-#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
-/*
- * Assign interrupts to PCI devices. Some OSs rely on this.
- */
-void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
-
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
- int_line[PCI_DEV(dev) & 0x03]);
-}
-#endif
-
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- char *ptmla_str, *ptmms_str;
-
- /*
- * Set up Direct MMIO registers
- */
- /*
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0x80000000-0xBFFFFFFF
- * ==> PCI address 0x80000000-0xBFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
- /* and enable region */
-
- if (!is_monarch()) {
- ptmla_str = getenv("ptm1la");
- ptmms_str = getenv("ptm1ms");
- if(NULL != ptmla_str && NULL != ptmms_str ) {
- out32r(PCIL0_PTM1MS,
- simple_strtoul(ptmms_str, NULL, 16));
- out32r(PCIL0_PTM1LA,
- simple_strtoul(ptmla_str, NULL, 16));
- } else {
- /* BAR1: default top 64MB of RAM */
- out32r(PCIL0_PTM1MS, 0xfc000001);
- out32r(PCIL0_PTM1LA, 0x0c000000);
- }
- } else {
- /* BAR1: default: complete 256MB RAM */
- out32r(PCIL0_PTM1MS, 0xf0000001);
- out32r(PCIL0_PTM1LA, 0x00000000);
- }
-
- ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
- ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
- if(NULL != ptmla_str && NULL != ptmms_str ) {
- out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
- out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
- } else {
- /* BAR2: default: 4MB FPGA */
- out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
- }
-
- if (is_monarch()) {
- /* BAR2: map FPGA registers behind system memory at 1GB */
- pci_hose_write_config_dword(hose, 0,
- PCI_BASE_ADDRESS_2, 0x40000008);
- }
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's vendor id */
- pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
-
- /* disabled for PMC405 backward compatibility */
- /* Configure command register as bus master */
- /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
-
-
- /* 240nS PCI clock */
- pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
-
- if (!is_monarch()) {
- /* Program the board's subsystem id/classcode */
- pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
- CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
- pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
- CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
-
- /* PCI configuration done: release ERREADY */
- out_be32((void *)GPIO1_OR,
- in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY);
- out_be32((void *)GPIO1_TCR,
- in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY);
- } else {
- /* Program the board's subsystem id/classcode */
- pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
- CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
- pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
- CONFIG_SYS_PCI_CLASSCODE_MONARCH);
- }
-
- /* enable host configuration */
- pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*
- * Override weak default pci_master_init()
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- /*
- * Only configure the master in monach mode
- */
- if (is_monarch())
- __pci_master_init(hose);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-static void wait_for_pci_ready(void)
-{
- if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) {
- printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
- while (1) {
- if (ctrlc()) {
- puts("abort\n");
- break;
- }
- if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) {
- printf("done\n");
- break;
- }
- }
- }
-}
-
-/*
- * Override weak is_pci_host()
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- char *s = getenv("pciscan");
- if (s == NULL)
- if (is_monarch()) {
- wait_for_pci_ready();
- return 1;
- } else
- return 0;
- else if (!strcmp(s, "yes"))
- return 1;
-
- return 0;
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_RESET_PHY_R
-static int pmc440_setup_vsc8601(char *devname, int phy_addr,
- unsigned short behavior, unsigned short method)
-{
- /* adjust LED behavior */
- if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) {
- printf("Phy%d: register write access failed\n", phy_addr);
- return -1;
- }
-
- miiphy_write(devname, phy_addr, 0x11, 0x0010);
- miiphy_write(devname, phy_addr, 0x11, behavior);
- miiphy_write(devname, phy_addr, 0x10, method);
- miiphy_write(devname, phy_addr, 0x1f, 0x0000);
-
- return 0;
-}
-
-static int pmc440_setup_ksz9031(char *devname, int phy_addr)
-{
- unsigned short id1, id2;
-
- if (miiphy_read(devname, phy_addr, 2, &id1) ||
- miiphy_read(devname, phy_addr, 3, &id2)) {
- printf("Phy%d: cannot read id\n", phy_addr);
- return -1;
- }
-
- if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) {
- printf("Phy%d: unexpected id\n", phy_addr);
- return -1;
- }
-
- /* MMD 2.08: adjust tx_clk pad skew */
- miiphy_write(devname, phy_addr, 0x0d, 2);
- miiphy_write(devname, phy_addr, 0x0e, 8);
- miiphy_write(devname, phy_addr, 0x0d, 0x4002);
- miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5));
-
- return 0;
-}
-
-void reset_phy(void)
-{
- char *s;
- unsigned short val_method, val_behavior;
-
- if (gd->board_type < 4) {
- /* special LED setup for NGCC/CANDES */
- s = getenv("bd_type");
- if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
- val_method = 0x0e0a;
- val_behavior = 0x0cf2;
- } else {
- /* PMC440 standard type */
- val_method = 0x0e10;
- val_behavior = 0x0cf0;
- }
-
- /* boards up to rev. 1.3 use Vitesse VSC8601 phys */
- pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR,
- val_method, val_behavior);
- pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR,
- val_method, val_behavior);
- } else {
- /* rev. 1.4 uses a Micrel KSZ9031 */
- pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR);
- pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR);
- }
-}
-#endif
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/*
- * Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
- */
-int eeprom_write_enable(unsigned dev_addr, int state)
-{
- if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
- (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
- return -1;
- } else {
- switch (state) {
- case 1:
- /* Enable write access, clear bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
- state = 0;
- break;
- case 0:
- /* Disable write access, set bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
- state = 0;
- break;
- default:
- /* Read current status back. */
- state = (0 == (in_be32((void *)GPIO0_OR)
- & GPIO0_EP_EEP));
- break;
- }
- }
- return state;
-}
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
-int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt)
-{
- unsigned end = offset + cnt;
- unsigned blk_off;
- int rcode = 0;
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
- eeprom_write_enable(dev_addr, 1);
-#endif
- /*
- * Write data until done or would cross a write page boundary.
- * We must write the address again when changing pages
- * because the address counter only increments within a page.
- */
- while (offset < end) {
- unsigned alen, len;
- unsigned maxlen;
- uchar addr[2];
-
- blk_off = offset & 0xFF; /* block offset */
-
- addr[0] = offset >> 8; /* block number */
- addr[1] = blk_off; /* block offset */
- alen = 2;
- addr[0] |= dev_addr; /* insert device address */
-
- len = end - offset;
-
-#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
-#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
-
- maxlen = BOOT_EEPROM_PAGE_SIZE -
- BOOT_EEPROM_PAGE_OFFSET(blk_off);
- if (maxlen > I2C_RXTX_LEN)
- maxlen = I2C_RXTX_LEN;
-
- if (len > maxlen)
- len = maxlen;
-
- if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
- rcode = 1;
-
- buffer += len;
- offset += len;
-
-#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
- udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-#endif
- }
-#if defined(CONFIG_SYS_EEPROM_WREN)
- eeprom_write_enable(dev_addr, 0);
-#endif
- return rcode;
-}
-
-static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt)
-{
- unsigned end = offset + cnt;
- unsigned blk_off;
- int rcode = 0;
-
- /*
- * Read data until done or would cross a page boundary.
- * We must write the address again when changing pages
- * because the next page may be in a different device.
- */
- while (offset < end) {
- unsigned alen, len;
- unsigned maxlen;
- uchar addr[2];
-
- blk_off = offset & 0xFF; /* block offset */
-
- addr[0] = offset >> 8; /* block number */
- addr[1] = blk_off; /* block offset */
- alen = 2;
-
- addr[0] |= dev_addr; /* insert device address */
-
- len = end - offset;
-
- maxlen = 0x100 - blk_off;
- if (maxlen > I2C_RXTX_LEN)
- maxlen = I2C_RXTX_LEN;
- if (len > maxlen)
- len = maxlen;
-
- if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
- rcode = 1;
- buffer += len;
- offset += len;
- }
-
- return rcode;
-}
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int board_usb_init(int index, enum usb_init_type init)
-{
- char *act = getenv("usbact");
- int i;
-
- if ((act == NULL || strcmp(act, "host") == 0) &&
- !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT))
- /* enable power on USB socket */
- out_be32((void *)GPIO1_OR,
- in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
-
- for (i=0; i<1000; i++)
- udelay(1000);
-
- return 0;
-}
-
-int usb_board_stop(void)
-{
- /* disable power on USB socket */
- out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N);
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return usb_board_stop();
-}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- int rc;
-
- __ft_board_setup(blob, bd);
-
- /*
- * Disable PCI in non-monarch mode.
- */
- if (!is_monarch()) {
- rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
- "disabled", sizeof("disabled"), 1);
- if (rc) {
- printf("Unable to update property status in PCI node, ");
- printf("err=%s\n", fdt_strerror(rc));
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PMC440_H__
-#define __PMC440_H__
-
-/*
- * GPIOs
- */
-#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */
-#define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */
-#define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */
-#define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */
-#define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */
-#define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */
-#define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */
-
-#define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */
-#define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */
-#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */
-#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */
-#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */
-
-/*
- * FPGA programming pin configuration
- */
-#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
-#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */
-#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */
-#define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */
-#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */
-#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */
-
-/*
- * FPGA interface
- */
-#define FPGA_BA CONFIG_SYS_FPGA_BASE0
-#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
-#define FPGA_IN32(p) in_be32((void*)(p))
-#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
-#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
-
-struct pmc440_fifo_s {
- u32 data;
- u32 ctrl;
-};
-
-/* fifo ctrl register */
-#define FIFO_IE (1 << 15)
-#define FIFO_OVERFLOW (1 << 10)
-#define FIFO_EMPTY (1 << 9)
-#define FIFO_FULL (1 << 8)
-#define FIFO_LEVEL_MASK 0x000000ff
-
-#define FIFO_COUNT 4
-
-struct pmc440_fpga_s {
- u32 ctrla;
- u32 status;
- u32 ctrlb;
- u32 pad1[0x40 / sizeof(u32) - 3];
- u32 irig_time; /* offset: 0x0040 */
- u32 irig_tod;
- u32 irig_cf;
- u32 pad2;
- u32 irig_rx_time; /* offset: 0x0050 */
- u32 pad3[3];
- u32 hostctrl; /* offset: 0x0060 */
- u32 pad4[0x20 / sizeof(u32) - 1];
- struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
-};
-
-typedef struct pmc440_fpga_s pmc440_fpga_t;
-
-/* ctrl register */
-#define CTRL_HOST_IE (1 << 8)
-
-/* outputs */
-#define RESET_EN (1 << 31)
-#define CLOCK_EN (1 << 30)
-#define RESET_OUT (1 << 19)
-#define CLOCK_OUT (1 << 22)
-#define RESET_OUT (1 << 19)
-#define IRIGB_R_OUT (1 << 14)
-
-/* status register */
-#define STATUS_VERSION_SHIFT 24
-#define STATUS_VERSION_MASK 0xff000000
-#define STATUS_HWREV_SHIFT 20
-#define STATUS_HWREV_MASK 0x00f00000
-
-#define STATUS_CAN_ISF (1 << 11)
-#define STATUS_CSTM_ISF (1 << 10)
-#define STATUS_FIFO_ISF (1 << 9)
-#define STATUS_HOST_ISF (1 << 8)
-
-/* inputs */
-#define RESET_IN (1 << 0)
-#define CLOCK_IN (1 << 1)
-#define IRIGB_R_IN (1 << 5)
-
-/* hostctrl register */
-#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17)
-#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16)
-#define HOSTCTRL_CSTM1IE_GATE (1 << 7)
-#define HOSTCTRL_CSTM1IW_FLAG (1 << 6)
-#define HOSTCTRL_CSTM0IE_GATE (1 << 5)
-#define HOSTCTRL_CSTM0IW_FLAG (1 << 4)
-#define HOSTCTRL_FIFOIE_GATE (1 << 3)
-#define HOSTCTRL_FIFOIE_FLAG (1 << 2)
-#define HOSTCTRL_HCINT_GATE (1 << 1)
-#define HOSTCTRL_HCINT_FLAG (1 << 0)
-
-#define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000)
-#define NGCC_CTRL_FPGARST_N (1 << 2)
-
-/*
- * FPGA to PPC interrupt
- */
-#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */
-#define IRQ1_FPGA (32+30) /* UIC1 - custom module */
-#define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */
-#define IRQ_ETH0 (64+ 4) /* UIC2 */
-#define IRQ_ETH1 ( 27) /* UIC0 */
-#define IRQ_RTC (64+ 0) /* UIC2 */
-#define IRQ_PCIA (64+ 1) /* UIC2 */
-#define IRQ_PCIB (32+18) /* UIC1 */
-#define IRQ_PCIC (32+19) /* UIC1 */
-#define IRQ_PCID (32+20) /* UIC1 */
-
-#endif /* __PMC440_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
- *
- * (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debug output */
-#undef DEBUG
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/ppc440.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-
-struct sdram_conf_s {
- ulong size;
- int rows;
- int banks;
-};
-
-struct sdram_conf_s sdram_conf[] = {
- {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
- {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
- {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
-};
-
-/*
- * dram_init -- 440EPx's DDR controller is a DENALI Core
- */
-int initdram_by_rb(int rows, int banks)
-{
- ulong speed = get_bus_freq(0);
-
- mtsdram(DDR0_02, 0x00000000);
-
- mtsdram(DDR0_00, 0x0000190A);
- mtsdram(DDR0_01, 0x01000000);
- mtsdram(DDR0_03, 0x02030602);
- mtsdram(DDR0_04, 0x0A020200);
- mtsdram(DDR0_05, 0x02020308);
- mtsdram(DDR0_06, 0x0102C812);
- mtsdram(DDR0_07, 0x000D0100);
- mtsdram(DDR0_08, 0x02430001);
- mtsdram(DDR0_09, 0x00011D5F);
- mtsdram(DDR0_10, 0x00000100);
- mtsdram(DDR0_11, 0x0027C800);
- mtsdram(DDR0_12, 0x00000003);
- mtsdram(DDR0_14, 0x00000000);
- mtsdram(DDR0_17, 0x19000000);
- mtsdram(DDR0_18, 0x19191919);
- mtsdram(DDR0_19, 0x19191919);
- mtsdram(DDR0_20, 0x0B0B0B0B);
- mtsdram(DDR0_21, 0x0B0B0B0B);
- mtsdram(DDR0_22, 0x00267F0B);
- mtsdram(DDR0_23, 0x00000000);
- mtsdram(DDR0_24, 0x01010002);
- if (speed > 133333334)
- mtsdram(DDR0_26, 0x5B26050C);
- else
- mtsdram(DDR0_26, 0x5B260408);
- mtsdram(DDR0_27, 0x0000682B);
- mtsdram(DDR0_28, 0x00000000);
- mtsdram(DDR0_31, 0x00000000);
-
- mtsdram(DDR0_42,
- DDR0_42_ADDR_PINS_DECODE(14 - rows) |
- 0x00000006);
- mtsdram(DDR0_43,
- DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
- 0x030A0200);
-
- mtsdram(DDR0_44, 0x00000003);
- mtsdram(DDR0_02, 0x00000001);
-
- denali_wait_for_dlllock();
-
-#ifdef CONFIG_DDR_DATA_EYE
- /*
- * Perform data eye search if requested.
- */
- denali_core_search_data_eye();
-#endif
- /*
- * Clear possible errors resulting from data-eye-search.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- return 0;
-}
-
-int dram_init(void)
-{
- phys_size_t size;
- int n;
-
- /* go through supported memory configurations */
- for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
- size = sdram_conf[n].size;
-
- /* program TLB entries */
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
- TLB_WORD2_I_ENABLE);
-
- /*
- * setup denali core
- */
- initdram_by_rb(sdram_conf[n].rows,
- sdram_conf[n].banks);
-
- /* check for suitable configuration */
- if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) {
- gd->ram_size = size;
- return 0;
- }
-
- /* delete TLB entries */
- remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
- }
-
- return -ENXIO;
-}
+++ /dev/null
-if TARGET_VOM405
-
-config SYS_BOARD
- default "vom405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "VOM405"
-
-endif
+++ /dev/null
-VOM405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/vom405/
-F: include/configs/VOM405.h
-F: configs/VOM405_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-CPLD = ../common/xilinx_jtag/lenval.o \
- ../common/xilinx_jtag/micro.o \
- ../common/xilinx_jtag/ports.o
-
-obj-y = vom405.o flash.o ../common/misc.o $(CPLD)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-#include <sja1000.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-/*
- * generate a short spike on the CAN tx line
- * to bring the couplers in sync
- */
-void init_coupler(u32 addr)
-{
- struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
-
- /* reset */
- out_8(&ctrl->cr, CR_RR);
-
- /* dominant */
- out_8(&ctrl->btr0, 0x00); /* btr setup is required */
- out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
- out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
- OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
- out_8(&ctrl->cr, 0x00);
-
- /* delay */
- in_8(&ctrl->cr);
- in_8(&ctrl->cr);
- in_8(&ctrl->cr);
- in_8(&ctrl->cr);
-
- /* reset */
- out_8(&ctrl->cr, CR_RR);
-}
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- /*
- * Reset CPLD via GPIO12 (CS3) pin
- */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 12));
- udelay(1000); /* wait 1ms */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | (0x80000000 >> 12));
- udelay(1000); /* wait 1ms */
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /*
- * Init magnetic coupler
- */
- if (!getenv("noinitcoupler"))
- init_coupler(CAN_BA);
-
- return (0);
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
- int flashcnt;
- int delay;
- u8 *led_reg = (u8 *)(CAN_BA + 0x1000);
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming VOM405");
- } else {
- puts(str);
- }
-
- printf(" (PLD-Version=%02d)\n", in_8(led_reg));
-
- /*
- * Flash LEDs
- */
- for (flashcnt = 0; flashcnt < 3; flashcnt++) {
- out_8(led_reg, 0x40); /* LED_B..D off */
- for (delay = 0; delay < 100; delay++)
- udelay(1000);
- out_8(led_reg, 0x47); /* LED_B..D on */
- for (delay = 0; delay < 50; delay++)
- udelay(1000);
- }
- out_8(led_reg, 0x40);
-
- return 0;
-}
-
-void reset_phy(void)
-{
-#ifdef CONFIG_LXT971_NO_SLEEP
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-#endif
-}
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/global_data.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#define REFLECTION_TESTPATTERN 0xdede
-#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
-
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-#define REFLECTION_TESTREG reflection_low
-#else
-#define REFLECTION_TESTREG reflection_high
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int get_fpga_state(unsigned dev)
-{
- return gd->arch.fpga_state[dev];
-}
-
-int board_early_init_f(void)
-{
- unsigned k;
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->arch.fpga_state[k] = 0;
-
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks
- * -> ca. 15 us
- */
- mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
- return 0;
-}
-
-int board_early_init_r(void)
-{
- unsigned k;
- unsigned ctr;
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->arch.fpga_state[k] = 0;
-
- /*
- * reset FPGA
- */
- gd405ep_init();
-
- gd405ep_set_fpga_reset(1);
-
- gd405ep_setup_hw();
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
- ctr = 0;
- while (!gd405ep_get_fpga_done(k)) {
- udelay(100000);
- if (ctr++ > 5) {
- gd->arch.fpga_state[k] |=
- FPGA_STATE_DONE_FAILED;
- break;
- }
- }
- }
-
- udelay(10);
-
- gd405ep_set_fpga_reset(0);
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
- /*
- * wait for fpga out of reset
- */
- ctr = 0;
- while (1) {
- u16 val;
-
- FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
-
- FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
- if (val == REFLECTION_TESTPATTERN_INV)
- break;
-
- udelay(100000);
- if (ctr++ > 5) {
- gd->arch.fpga_state[k] |=
- FPGA_STATE_REFLECTION_FAILED;
- break;
- }
- }
- }
-
- return 0;
-}
+++ /dev/null
-#ifndef __405EP_H_
-#define __405EP_H_
-
-/* functions to be provided by board implementation */
-void gd405ep_init(void);
-void gd405ep_set_fpga_reset(unsigned state);
-void gd405ep_setup_hw(void);
-int gd405ep_get_fpga_done(unsigned fpga);
-
-#endif /* __405EP_H_ */
+++ /dev/null
-if TARGET_DLVISION_10G
-
-config SYS_BOARD
- default "405ep"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "dlvision-10g"
-
-endif
-
-if TARGET_IO
-
-config SYS_BOARD
- default "405ep"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "io"
-
-endif
-
-if TARGET_IOCON
-
-config SYS_BOARD
- default "405ep"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "iocon"
-
-endif
-
-if TARGET_NEO
-
-config SYS_BOARD
- default "405ep"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "neo"
-
-endif
+++ /dev/null
-405EP BOARD
-M: Dirk Eibach <eibach@gdsys.de>
-S: Maintained
-F: board/gdsys/405ep/
-F: include/configs/dlvision-10g.h
-F: configs/dlvision-10g_defconfig
-F: include/configs/io.h
-F: configs/io_defconfig
-F: include/configs/iocon.h
-F: configs/iocon_defconfig
-F: include/configs/neo.h
-F: configs/neo_defconfig
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := 405ep.o
-obj-$(CONFIG_NEO) += neo.o
-obj-$(CONFIG_IO) += io.o
-obj-$(CONFIG_IOCON) += iocon.o
-obj-$(CONFIG_DLVISION_10G) += dlvision-10g.o
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#include "../common/osd.h"
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
-
-#define LATCH2_MC2_PRESENT_N 0x0080
-
-enum {
- UNITTYPE_MAIN = 1<<0,
- UNITTYPE_SERVER = 1<<1,
- UNITTYPE_DISPLAYPORT = 1<<2,
-};
-
-enum {
- HWVER_101 = 0,
- HWVER_110 = 1,
- HWVER_130 = 2,
- HWVER_140 = 3,
- HWVER_150 = 4,
- HWVER_160 = 5,
- HWVER_170 = 6,
-};
-
-enum {
- AUDIO_NONE = 0,
- AUDIO_TX = 1,
- AUDIO_RX = 2,
- AUDIO_RXTX = 3,
-};
-
-enum {
- SYSCLK_156250 = 2,
-};
-
-enum {
- RAM_NONE = 0,
- RAM_DDR2_32 = 1,
- RAM_DDR2_64 = 2,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int misc_init_r(void)
-{
- /*
- * Note: DTT has been removed. Please use UCLASS_THERMAL.
- *
- * startup fans
- *
- * dtt_init();
- */
-
- return 0;
-}
-
-static unsigned int get_hwver(void)
-{
- u16 latch3 = in_le16((void *)LATCH3_BASE);
-
- return latch3 & 0x0003;
-}
-
-static unsigned int get_mc2_present(void)
-{
- u16 latch2 = in_le16((void *)LATCH2_BASE);
-
- return !(latch2 & LATCH2_MC2_PRESENT_N);
-}
-
-static void print_fpga_info(unsigned dev)
-{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- unsigned unit_type;
- unsigned hardware_version;
- unsigned feature_rs232;
- unsigned feature_audio;
- unsigned feature_sysclock;
- unsigned feature_ramconfig;
- unsigned feature_carrier_speed;
- unsigned feature_carriers;
- unsigned feature_video_channels;
- int fpga_state = get_fpga_state(dev);
-
- printf("FPGA%d: ", dev);
-
- FPGA_GET_REG(dev, versions, &versions);
- FPGA_GET_REG(dev, fpga_version, &fpga_version);
- FPGA_GET_REG(dev, fpga_features, &fpga_features);
-
- hardware_version = versions & 0x000f;
-
- if (fpga_state
- && !((hardware_version == HWVER_101)
- && (fpga_state == FPGA_STATE_DONE_FAILED))) {
- puts("not available\n");
- if (fpga_state & FPGA_STATE_DONE_FAILED)
- puts(" Waiting for FPGA-DONE timed out.\n");
- if (fpga_state & FPGA_STATE_REFLECTION_FAILED)
- puts(" FPGA reflection test failed.\n");
- return;
- }
-
- unit_type = (versions >> 4) & 0x000f;
- hardware_version = versions & 0x000f;
- feature_rs232 = fpga_features & (1<<11);
- feature_audio = (fpga_features >> 9) & 0x0003;
- feature_sysclock = (fpga_features >> 7) & 0x0003;
- feature_ramconfig = (fpga_features >> 5) & 0x0003;
- feature_carrier_speed = fpga_features & (1<<4);
- feature_carriers = (fpga_features >> 2) & 0x0003;
- feature_video_channels = fpga_features & 0x0003;
-
- if (unit_type & UNITTYPE_MAIN)
- printf("Mainchannel ");
- else
- printf("Videochannel ");
-
- if (unit_type & UNITTYPE_SERVER)
- printf("Serverside ");
- else
- printf("Userside ");
-
- if (unit_type & UNITTYPE_DISPLAYPORT)
- printf("DisplayPort");
- else
- printf("DVI-DL");
-
- switch (hardware_version) {
- case HWVER_101:
- printf(" HW-Ver 1.01\n");
- break;
-
- case HWVER_110:
- printf(" HW-Ver 1.10-1.20\n");
- break;
-
- case HWVER_130:
- printf(" HW-Ver 1.30\n");
- break;
-
- case HWVER_140:
- printf(" HW-Ver 1.40-1.43\n");
- break;
-
- case HWVER_150:
- printf(" HW-Ver 1.50\n");
- break;
-
- case HWVER_160:
- printf(" HW-Ver 1.60-1.61\n");
- break;
-
- case HWVER_170:
- printf(" HW-Ver 1.70\n");
- break;
-
- default:
- printf(" HW-Ver %d(not supported)\n",
- hardware_version);
- break;
- }
-
- printf(" FPGA V %d.%02d, features:",
- fpga_version / 100, fpga_version % 100);
-
- printf(" %sRS232", feature_rs232 ? "" : "no ");
-
- switch (feature_audio) {
- case AUDIO_NONE:
- printf(", no audio");
- break;
-
- case AUDIO_TX:
- printf(", audio tx");
- break;
-
- case AUDIO_RX:
- printf(", audio rx");
- break;
-
- case AUDIO_RXTX:
- printf(", audio rx+tx");
- break;
-
- default:
- printf(", audio %d(not supported)", feature_audio);
- break;
- }
-
- switch (feature_sysclock) {
- case SYSCLK_156250:
- printf(", clock 156.25 MHz");
- break;
-
- default:
- printf(", clock %d(not supported)", feature_sysclock);
- break;
- }
-
- puts(",\n ");
-
- switch (feature_ramconfig) {
- case RAM_NONE:
- printf("no RAM");
- break;
-
- case RAM_DDR2_32:
- printf("RAM 32 bit DDR2");
- break;
-
- case RAM_DDR2_64:
- printf("RAM 64 bit DDR2");
- break;
-
- default:
- printf("RAM %d(not supported)", feature_ramconfig);
- break;
- }
-
- printf(", %d carrier(s) %s", feature_carriers,
- feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
-
- printf(", %d video channel(s)\n", feature_video_channels);
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- puts("Board: ");
-
- puts("DLVision 10G");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
-
- puts("\n");
-
- return 0;
-}
-
-int last_stage_init(void)
-{
- u16 versions;
-
- FPGA_GET_REG(0, versions, &versions);
-
- print_fpga_info(0);
- if (get_mc2_present())
- print_fpga_info(1);
-
- if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
- return 0;
-
- if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
- osd_probe(0);
-
- if (get_mc2_present() &&
- (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
- osd_probe(1);
-
- return 0;
-}
-
-void gd405ep_init(void)
-{
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
- if (state) {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
- } else {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- }
-}
-
-void gd405ep_setup_hw(void)
-{
- /*
- * set "startup-finished"-gpios
- */
- gpio_write_bit(21, 0);
- gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
- return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
-}
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-#include <miiphy.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
-#define PHYREG_CONTROL 0
-#define PHYREG_PAGE_ADDRESS 22
-#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
-#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
-
-enum {
- UNITTYPE_CCD_SWITCH = 1,
-};
-
-enum {
- HWVER_100 = 0,
- HWVER_110 = 1,
- HWVER_121 = 2,
- HWVER_122 = 3,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int misc_init_r(void)
-{
- /*
- * Note: DTT has been removed. Please use UCLASS_THERMAL.
- *
- * startup fans
- *
- * dtt_init();
- */
-
- return 0;
-}
-
-int configure_gbit_phy(unsigned char addr)
-{
- unsigned short value;
-
- /* select page 2 */
- if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_PAGE_ADDRESS, 0x0002))
- goto err_out;
- /* disable SGMII autonegotiation */
- if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
- goto err_out;
- /* select page 0 */
- if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_PAGE_ADDRESS, 0x0000))
- goto err_out;
- /* switch from powerdown to normal operation */
- if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
- goto err_out;
- if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
- goto err_out;
- /* reset phy so settings take effect */
- if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_CONTROL, 0x9140))
- goto err_out;
-
- return 0;
-
-err_out:
- printf("Error writing to the PHY addr=%02x\n", addr);
- return -1;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- puts("Board: CATCenter Io");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
-
- puts("\n");
-
- return 0;
-}
-
-static void print_fpga_info(void)
-{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- unsigned unit_type;
- unsigned hardware_version;
- unsigned feature_channels;
- unsigned feature_expansion;
-
- FPGA_GET_REG(0, versions, &versions);
- FPGA_GET_REG(0, fpga_version, &fpga_version);
- FPGA_GET_REG(0, fpga_features, &fpga_features);
-
- unit_type = (versions & 0xf000) >> 12;
- hardware_version = versions & 0x000f;
- feature_channels = fpga_features & 0x007f;
- feature_expansion = fpga_features & (1<<15);
-
- puts("FPGA: ");
-
- switch (unit_type) {
- case UNITTYPE_CCD_SWITCH:
- printf("CCD-Switch");
- break;
-
- default:
- printf("UnitType %d(not supported)", unit_type);
- break;
- }
-
- switch (hardware_version) {
- case HWVER_100:
- printf(" HW-Ver 1.00\n");
- break;
-
- case HWVER_110:
- printf(" HW-Ver 1.10\n");
- break;
-
- case HWVER_121:
- printf(" HW-Ver 1.21\n");
- break;
-
- case HWVER_122:
- printf(" HW-Ver 1.22\n");
- break;
-
- default:
- printf(" HW-Ver %d(not supported)\n",
- hardware_version);
- break;
- }
-
- printf(" FPGA V %d.%02d, features:",
- fpga_version / 100, fpga_version % 100);
-
- printf(" %d channel(s)", feature_channels);
-
- printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-}
-
-/*
- * setup Gbit PHYs
- */
-int last_stage_init(void)
-{
- unsigned int k;
-
- print_fpga_info();
-
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-
- for (k = 0; k < 32; ++k)
- configure_gbit_phy(k);
-
- /* take fpga serdes blocks out of reset */
- FPGA_SET_REG(0, quad_serdes_reset, 0);
-
- return 0;
-}
-
-void gd405ep_init(void)
-{
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
- if (state) {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
- } else {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- }
-}
-
-void gd405ep_setup_hw(void)
-{
- /*
- * set "startup-finished"-gpios
- */
- gpio_write_bit(21, 0);
- gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
- return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
-}
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#include "../common/osd.h"
-#include "../common/mclink.h"
-#include "../common/phy.h"
-
-#include <i2c.h>
-#include <pca953x.h>
-#include <pca9698.h>
-
-#include <miiphy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
-#define MAX_MUX_CHANNELS 2
-
-enum {
- UNITTYPE_MAIN_SERVER = 0,
- UNITTYPE_MAIN_USER = 1,
- UNITTYPE_VIDEO_SERVER = 2,
- UNITTYPE_VIDEO_USER = 3,
-};
-
-enum {
- HWVER_100 = 0,
- HWVER_104 = 1,
- HWVER_110 = 2,
- HWVER_120 = 3,
- HWVER_200 = 4,
- HWVER_210 = 5,
- HWVER_220 = 6,
- HWVER_230 = 7,
-};
-
-enum {
- FPGA_HWVER_200 = 0,
- FPGA_HWVER_210 = 1,
-};
-
-enum {
- COMPRESSION_NONE = 0,
- COMPRESSION_TYPE1_DELTA = 1,
- COMPRESSION_TYPE1_TYPE2_DELTA = 3,
-};
-
-enum {
- AUDIO_NONE = 0,
- AUDIO_TX = 1,
- AUDIO_RX = 2,
- AUDIO_RXTX = 3,
-};
-
-enum {
- SYSCLK_147456 = 0,
-};
-
-enum {
- RAM_DDR2_32 = 0,
- RAM_DDR3_32 = 1,
-};
-
-enum {
- CARRIER_SPEED_1G = 0,
- CARRIER_SPEED_2_5G = 1,
-};
-
-enum {
- MCFPGA_DONE = 1 << 0,
- MCFPGA_INIT_N = 1 << 1,
- MCFPGA_PROGRAM_N = 1 << 2,
- MCFPGA_UPDATE_ENABLE_N = 1 << 3,
- MCFPGA_RESET_N = 1 << 4,
-};
-
-enum {
- GPIO_MDC = 1 << 14,
- GPIO_MDIO = 1 << 15,
-};
-
-unsigned int mclink_fpgacount;
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
-{
- int res;
-
- switch (fpga) {
- case 0:
- out_le16(reg, data);
- break;
- default:
- res = mclink_send(fpga - 1, regoff, data);
- if (res < 0) {
- printf("mclink_send reg %02lx data %04x returned %d\n",
- regoff, data, res);
- return res;
- }
- break;
- }
-
- return 0;
-}
-
-int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
-{
- int res;
-
- switch (fpga) {
- case 0:
- *data = in_le16(reg);
- break;
- default:
- if (fpga > mclink_fpgacount)
- return -EINVAL;
- res = mclink_receive(fpga - 1, regoff, data);
- if (res < 0) {
- printf("mclink_receive reg %02lx returned %d\n",
- regoff, res);
- return res;
- }
- }
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- puts("Board: ");
-
- puts("IoCon");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
-
- puts("\n");
-
- return 0;
-}
-
-static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
-{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- unsigned unit_type;
- unsigned hardware_version;
- unsigned feature_compression;
- unsigned feature_osd;
- unsigned feature_audio;
- unsigned feature_sysclock;
- unsigned feature_ramconfig;
- unsigned feature_carrier_speed;
- unsigned feature_carriers;
- unsigned feature_video_channels;
-
- int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM;
-
- FPGA_GET_REG(fpga, versions, &versions);
- FPGA_GET_REG(fpga, fpga_version, &fpga_version);
- FPGA_GET_REG(fpga, fpga_features, &fpga_features);
-
- unit_type = (versions & 0xf000) >> 12;
- feature_compression = (fpga_features & 0xe000) >> 13;
- feature_osd = fpga_features & (1<<11);
- feature_audio = (fpga_features & 0x0600) >> 9;
- feature_sysclock = (fpga_features & 0x0180) >> 7;
- feature_ramconfig = (fpga_features & 0x0060) >> 5;
- feature_carrier_speed = fpga_features & (1<<4);
- feature_carriers = (fpga_features & 0x000c) >> 2;
- feature_video_channels = fpga_features & 0x0003;
-
- if (legacy)
- printf("legacy ");
-
- switch (unit_type) {
- case UNITTYPE_MAIN_USER:
- printf("Mainchannel");
- break;
-
- case UNITTYPE_VIDEO_USER:
- printf("Videochannel");
- break;
-
- default:
- printf("UnitType %d(not supported)", unit_type);
- break;
- }
-
- if (unit_type == UNITTYPE_MAIN_USER) {
- if (legacy)
- hardware_version =
- (in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
- else
- hardware_version =
- (!!pca9698_get_value(0x20, 24) << 0)
- | (!!pca9698_get_value(0x20, 25) << 1)
- | (!!pca9698_get_value(0x20, 26) << 2)
- | (!!pca9698_get_value(0x20, 27) << 3);
- switch (hardware_version) {
- case HWVER_100:
- printf(" HW-Ver 1.00,");
- break;
-
- case HWVER_104:
- printf(" HW-Ver 1.04,");
- break;
-
- case HWVER_110:
- printf(" HW-Ver 1.10,");
- break;
-
- case HWVER_120:
- printf(" HW-Ver 1.20-1.21,");
- break;
-
- case HWVER_200:
- printf(" HW-Ver 2.00,");
- break;
-
- case HWVER_210:
- printf(" HW-Ver 2.10,");
- break;
-
- case HWVER_220:
- printf(" HW-Ver 2.20,");
- break;
-
- case HWVER_230:
- printf(" HW-Ver 2.30,");
- break;
-
- default:
- printf(" HW-Ver %d(not supported),",
- hardware_version);
- break;
- }
- if (rgmii2_present)
- printf(" RGMII2,");
- }
-
- if (unit_type == UNITTYPE_VIDEO_USER) {
- hardware_version = versions & 0x000f;
- switch (hardware_version) {
- case FPGA_HWVER_200:
- printf(" HW-Ver 2.00,");
- break;
-
- case FPGA_HWVER_210:
- printf(" HW-Ver 2.10,");
- break;
-
- default:
- printf(" HW-Ver %d(not supported),",
- hardware_version);
- break;
- }
- }
-
- printf(" FPGA V %d.%02d\n features:",
- fpga_version / 100, fpga_version % 100);
-
-
- switch (feature_compression) {
- case COMPRESSION_NONE:
- printf(" no compression");
- break;
-
- case COMPRESSION_TYPE1_DELTA:
- printf(" type1-deltacompression");
- break;
-
- case COMPRESSION_TYPE1_TYPE2_DELTA:
- printf(" type1-deltacompression, type2-inlinecompression");
- break;
-
- default:
- printf(" compression %d(not supported)", feature_compression);
- break;
- }
-
- printf(", %sosd", feature_osd ? "" : "no ");
-
- switch (feature_audio) {
- case AUDIO_NONE:
- printf(", no audio");
- break;
-
- case AUDIO_TX:
- printf(", audio tx");
- break;
-
- case AUDIO_RX:
- printf(", audio rx");
- break;
-
- case AUDIO_RXTX:
- printf(", audio rx+tx");
- break;
-
- default:
- printf(", audio %d(not supported)", feature_audio);
- break;
- }
-
- puts(",\n ");
-
- switch (feature_sysclock) {
- case SYSCLK_147456:
- printf("clock 147.456 MHz");
- break;
-
- default:
- printf("clock %d(not supported)", feature_sysclock);
- break;
- }
-
- switch (feature_ramconfig) {
- case RAM_DDR2_32:
- printf(", RAM 32 bit DDR2");
- break;
-
- case RAM_DDR3_32:
- printf(", RAM 32 bit DDR3");
- break;
-
- default:
- printf(", RAM %d(not supported)", feature_ramconfig);
- break;
- }
-
- printf(", %d carrier(s) %s", feature_carriers,
- feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
-
- printf(", %d video channel(s)\n", feature_video_channels);
-}
-
-int last_stage_init(void)
-{
- int slaves;
- unsigned int k;
- unsigned int mux_ch;
- unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
- int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
- u16 fpga_features;
- int feature_carrier_speed;
- bool ch0_rgmii2_present = false;
-
- FPGA_GET_REG(0, fpga_features, &fpga_features);
- feature_carrier_speed = fpga_features & (1<<4);
-
- if (!legacy) {
- /* Turn on Parade DP501 */
- pca9698_direction_output(0x20, 9, 1);
-
- ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
- }
-
- /* wait for FPGA done; then reset FPGA */
- for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
- unsigned int ctr = 0;
-
- if (i2c_probe(mclink_controllers[k]))
- continue;
-
- while (!(pca953x_get_val(mclink_controllers[k])
- & MCFPGA_DONE)) {
- udelay(100000);
- if (ctr++ > 5) {
- printf("no done for mclink_controller %d\n", k);
- break;
- }
- }
-
- pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
- pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
- udelay(10);
- pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
- MCFPGA_RESET_N);
- }
-
- if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
- for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
- if ((mux_ch == 1) && !ch0_rgmii2_present)
- continue;
-
- setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
- }
- }
-
- /* give slave-PLLs and Parade DP501 some time to be up and running */
- udelay(500000);
-
- mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
- slaves = mclink_probe();
- mclink_fpgacount = 0;
-
- print_fpga_info(0, ch0_rgmii2_present);
- osd_probe(0);
-
- if (slaves <= 0)
- return 0;
-
- mclink_fpgacount = slaves;
-
- for (k = 1; k <= slaves; ++k) {
- FPGA_GET_REG(k, fpga_features, &fpga_features);
- feature_carrier_speed = fpga_features & (1<<4);
-
- print_fpga_info(k, false);
- osd_probe(k);
- if (feature_carrier_speed == CARRIER_SPEED_1G) {
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, bb_miiphy_buses[k].name,
- MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
- setup_88e1518(bb_miiphy_buses[k].name, 0);
- }
- }
-
- return 0;
-}
-
-/*
- * provide access to fpga gpios (for I2C bitbang)
- * (these may look all too simple but make iocon.h much more readable)
- */
-void fpga_gpio_set(unsigned int bus, int pin)
-{
- FPGA_SET_REG(bus, gpio.set, pin);
-}
-
-void fpga_gpio_clear(unsigned int bus, int pin)
-{
- FPGA_SET_REG(bus, gpio.clear, pin);
-}
-
-int fpga_gpio_get(unsigned int bus, int pin)
-{
- u16 val;
-
- FPGA_GET_REG(bus, gpio.read, &val);
-
- return val & pin;
-}
-
-void gd405ep_init(void)
-{
- unsigned int k;
-
- if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
- } else {
- pca9698_direction_output(0x20, 4, 1);
- }
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
- int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-
- if (legacy) {
- if (state) {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
- } else {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- }
- } else {
- pca9698_set_value(0x20, 4, state ? 0 : 1);
- }
-}
-
-void gd405ep_setup_hw(void)
-{
- /*
- * set "startup-finished"-gpios
- */
- gpio_write_bit(21, 0);
- gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
- int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-
- if (legacy)
- return in_le16((void *)LATCH2_BASE)
- & CONFIG_SYS_FPGA_DONE(fpga);
- else
- return pca9698_get_value(0x20, 20);
-}
-
-/*
- * FPGA MII bitbang implementation
- */
-
-struct fpga_mii {
- unsigned fpga;
- int mdio;
-} fpga_mii[] = {
- { 0, 1},
- { 1, 1},
- { 2, 1},
- { 3, 1},
-};
-
-static int mii_dummy_init(struct bb_miiphy_bus *bus)
-{
- return 0;
-}
-
-static int mii_mdio_active(struct bb_miiphy_bus *bus)
-{
- struct fpga_mii *fpga_mii = bus->priv;
-
- if (fpga_mii->mdio)
- FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
- else
- FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
-
- return 0;
-}
-
-static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
-{
- struct fpga_mii *fpga_mii = bus->priv;
-
- FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-
- return 0;
-}
-
-static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
- struct fpga_mii *fpga_mii = bus->priv;
-
- if (v)
- FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
- else
- FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
-
- fpga_mii->mdio = v;
-
- return 0;
-}
-
-static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
- u16 gpio;
- struct fpga_mii *fpga_mii = bus->priv;
-
- FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
-
- *v = ((gpio & GPIO_MDIO) != 0);
-
- return 0;
-}
-
-static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
- struct fpga_mii *fpga_mii = bus->priv;
-
- if (v)
- FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
- else
- FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
-
- return 0;
-}
-
-static int mii_delay(struct bb_miiphy_bus *bus)
-{
- udelay(1);
-
- return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- {
- .name = "board0",
- .init = mii_dummy_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &fpga_mii[0],
- },
- {
- .name = "board1",
- .init = mii_dummy_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &fpga_mii[1],
- },
- {
- .name = "board2",
- .init = mii_dummy_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &fpga_mii[2],
- },
- {
- .name = "board3",
- .init = mii_dummy_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &fpga_mii[3],
- },
-};
-
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
- sizeof(bb_miiphy_buses[0]);
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
-enum {
- UNITTYPE_CCX16 = 1,
- UNITTYPE_CCIP216 = 2,
-};
-
-enum {
- HWVER_300 = 3,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int misc_init_r(void)
-{
- /*
- * Note: DTT has been removed. Please use UCLASS_THERMAL.
- *
- * startup fans
- *
- * dtt_init();
- */
-
- return 0;
-}
-
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- puts("Board: CATCenter Neo");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
-
- puts("\n");
-
- return 0;
-}
-
-static void print_fpga_info(void)
-{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- int fpga_state = get_fpga_state(0);
- unsigned unit_type;
- unsigned hardware_version;
- unsigned feature_channels;
-
- puts("FPGA: ");
- if (fpga_state & FPGA_STATE_DONE_FAILED) {
- printf(" done timed out\n");
- return;
- }
-
- if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
- printf(" refelectione test failed\n");
- return;
- }
-
- FPGA_GET_REG(0, versions, &versions);
- FPGA_GET_REG(0, fpga_version, &fpga_version);
- FPGA_GET_REG(0, fpga_features, &fpga_features);
-
- unit_type = (versions & 0xf000) >> 12;
- hardware_version = versions & 0x000f;
- feature_channels = fpga_features & 0x007f;
-
- switch (unit_type) {
- case UNITTYPE_CCX16:
- printf("CCX-Switch");
- break;
-
- default:
- printf("UnitType %d(not supported)", unit_type);
- break;
- }
-
- switch (hardware_version) {
- case HWVER_300:
- printf(" HW-Ver 3.00-3.12\n");
- break;
-
- default:
- printf(" HW-Ver %d(not supported)\n",
- hardware_version);
- break;
- }
-
- printf(" FPGA V %d.%02d, features:",
- fpga_version / 100, fpga_version % 100);
-
- printf(" %d channel(s)\n", feature_channels);
-}
-
-int last_stage_init(void)
-{
- print_fpga_info();
-
- return 0;
-}
-
-void gd405ep_init(void)
-{
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
- if (state) {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
- } else {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- }
-}
-
-void gd405ep_setup_hw(void)
-{
- /*
- * set "startup-finished"-gpios
- */
- gpio_write_bit(21, 0);
- gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
- /*
- * Neo hardware has no FPGA-DONE GPIO
- */
- return 1;
-}
+++ /dev/null
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc405.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#include <gdsys_fpga.h>
-
-#include "405ex.h"
-
-#define REFLECTION_TESTPATTERN 0xdede
-#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
-
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-#define REFLECTION_TESTREG reflection_low
-#else
-#define REFLECTION_TESTREG reflection_high
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int get_fpga_state(unsigned dev)
-{
- return gd->arch.fpga_state[dev];
-}
-
-int board_early_init_f(void)
-{
- u32 val;
-
- /*--------------------------------------------------------------------+
- | Interrupt controller setup
- +--------------------------------------------------------------------+
- +---------------------------------------------------------------------+
- |Interrupt| Source | Pol. | Sensi.| Crit. |
- +---------+-----------------------------------+-------+-------+-------+
- | IRQ 00 | UART0 | High | Level | Non |
- | IRQ 01 | UART1 | High | Level | Non |
- | IRQ 02 | IIC0 | High | Level | Non |
- | IRQ 03 | TBD | High | Level | Non |
- | IRQ 04 | TBD | High | Level | Non |
- | IRQ 05 | EBM | High | Level | Non |
- | IRQ 06 | BGI | High | Level | Non |
- | IRQ 07 | IIC1 | Rising| Edge | Non |
- | IRQ 08 | SPI | High | Lvl/ed| Non |
- | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
- | IRQ 10 | MAL TX EOB | High | Level | Non |
- | IRQ 11 | MAL RX EOB | High | Level | Non |
- | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
- | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
- | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
- | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
- | IRQ 16 | PCIE0 AL | high | Level | Non |
- | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
- | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
- | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
- | IRQ 20 | PCIE0 TCR | High | Level | Non |
- | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
- | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
- | IRQ 23 | Security EIP-94 | High | Level | Non |
- | IRQ 24 | EMAC0 interrupt | High | Level | Non |
- | IRQ 25 | EMAC1 interrupt | High | Level | Non |
- | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
- | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
- | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
- | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
- | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
- | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
- |----------------------------------------------------------------------
- | IRQ 32 | MAL Serr | High | Level | Non |
- | IRQ 33 | MAL Txde | High | Level | Non |
- | IRQ 34 | MAL Rxde | High | Level | Non |
- | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
- | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
- | IRQ 37 | EBC | High |Lvl Edg| Non |
- | IRQ 38 | NDFC | High | Level | Non |
- | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
- | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
- | IRQ 41 | PCIE1 AL | high | Level | Non |
- | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
- | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
- | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
- | IRQ 45 | PCIE1 TCR | High | Level | Non |
- | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
- | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
- | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
- | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
- | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
- | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
- | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
- | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
- | IRQ 55 | Serial ROM | High | Level | Non |
- | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
- | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
- | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
- | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
- |----------------------------------------------------------------------
- | IRQ 64 | PE0 AL | High | Level | Non |
- | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
- | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
- | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
- | IRQ 68 | PE0 TCR | High | Level | Non |
- | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
- | IRQ 70 | PE0 DCR Error | High | Level | Non |
- | IRQ 71 | Reserved | N/A | N/A | Non |
- | IRQ 72 | PE1 AL | High | Level | Non |
- | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
- | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
- | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
- | IRQ 76 | PE1 TCR | High | Level | Non |
- | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
- | IRQ 78 | PE1 DCR Error | High | Level | Non |
- | IRQ 79 | Reserved | N/A | N/A | Non |
- | IRQ 80 | PE2 AL | High | Level | Non |
- | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
- | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
- | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
- | IRQ 84 | PE2 TCR | High | Level | Non |
- | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
- | IRQ 86 | PE2 DCR Error | High | Level | Non |
- | IRQ 87 | Reserved | N/A | N/A | Non |
- | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
- | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
- | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
- | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
- | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
- | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
- | IRQ 94 | Reserved | N/A | N/A | Non |
- | IRQ 95 | Reserved | N/A | N/A | Non |
- |---------------------------------------------------------------------
- +---------+-----------------------------------+-------+-------+------*/
- /*--------------------------------------------------------------------+
- | Initialise UIC registers. Clear all interrupts. Disable all
- | interrupts.
- | Set critical interrupt values. Set interrupt polarities. Set
- | interrupt trigger levels. Make bit 0 High priority. Clear all
- | interrupts again.
- +-------------------------------------------------------------------*/
-
- mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
- mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
- mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
- mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
- mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
- mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
- mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
- mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
- mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
- mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */
- mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
- mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */
- /* Except cascade UIC0 and UIC1 */
- mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
- mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
- mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */
- mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
-
- /*
- * Note: Some cores are still in reset when the chip starts, so
- * take them out of reset
- */
- mtsdr(SDR0_SRST, 0);
-
- /*
- * Configure PFC (Pin Function Control) registers
- */
- val = SDR0_PFC1_GPT_FREQ;
- mtsdr(SDR0_PFC1, val);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- unsigned k;
- unsigned ctr;
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->arch.fpga_state[k] = 0;
-
- /*
- * reset FPGA
- */
- gd405ex_init();
-
- gd405ex_set_fpga_reset(1);
-
- gd405ex_setup_hw();
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
- ctr = 0;
- while (!gd405ex_get_fpga_done(k)) {
- udelay(100000);
- if (ctr++ > 5) {
- gd->arch.fpga_state[k] |=
- FPGA_STATE_DONE_FAILED;
- break;
- }
- }
- }
-
- udelay(10);
-
- gd405ex_set_fpga_reset(0);
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
- /*
- * wait for fpga out of reset
- */
- ctr = 0;
- while (1) {
- u16 val;
-
- FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
-
- FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
- if (val == REFLECTION_TESTPATTERN_INV)
- break;
-
- udelay(100000);
- if (ctr++ > 5) {
- gd->arch.fpga_state[k] |=
- FPGA_STATE_REFLECTION_FAILED;
- break;
- }
- }
- }
-
- return 0;
-}
+++ /dev/null
-#ifndef __405EX_H_
-#define __405EX_H_
-
-/* functions to be provided by board implementation */
-void gd405ex_init(void);
-void gd405ex_set_fpga_reset(unsigned state);
-void gd405ex_setup_hw(void);
-int gd405ex_get_fpga_done(unsigned fpga);
-
-#endif /* __405EX_H_ */
+++ /dev/null
-if TARGET_IO64
-
-config SYS_BOARD
- default "405ex"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "io64"
-
-endif
+++ /dev/null
-405EX BOARD
-M: Dirk Eibach <eibach@gdsys.de>
-S: Maintained
-F: board/gdsys/405ex/
-F: include/configs/io64.h
-F: configs/io64_defconfig
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := 405ex.o
-obj-$(CONFIG_IO64) += io64.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
-
-struct ppc4xx_config ppc4xx_config_val[] = {
- {
- "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
- {
- 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
- {
- 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66",
- {
- 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
- {
- 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
- {
- 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
- 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
- {
- "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
- 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
- {
- 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
- 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
- }
- },
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * based on kilauea.c
- * by Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc405.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/ppc4xx-gpio.h>
-#include <flash.h>
-
-#include <pca9698.h>
-
-#include "405ex.h"
-#include <gdsys_fpga.h>
-
-#include <miiphy.h>
-#include <i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PHYREG_CONTROL 0
-#define PHYREG_PAGE_ADDRESS 22
-#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
-#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
-#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17
-#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
-
-enum {
- UNITTYPE_CCD_SWITCH = 1,
-};
-
-enum {
- HWVER_100 = 0,
- HWVER_110 = 1,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-static inline void blank_string(int size)
-{
- int i;
-
- for (i = 0; i < size; i++)
- putc('\b');
- for (i = 0; i < size; i++)
- putc(' ');
- for (i = 0; i < size; i++)
- putc('\b');
-}
-
-/*
- * Board early initialization function
- */
-int misc_init_r(void)
-{
- /*
- * Note: DTT has been removed. Please use UCLASS_THERMAL.
- *
- * startup fans
- *
- * dtt_init();
- */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* Monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-#endif
-
- return 0;
-}
-
-static void print_fpga_info(unsigned dev)
-{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- int fpga_state = get_fpga_state(dev);
-
- unsigned unit_type;
- unsigned hardware_version;
- unsigned feature_channels;
- unsigned feature_expansion;
-
- FPGA_GET_REG(dev, versions, &versions);
- FPGA_GET_REG(dev, fpga_version, &fpga_version);
- FPGA_GET_REG(dev, fpga_features, &fpga_features);
-
- printf("FPGA%d: ", dev);
- if (fpga_state & FPGA_STATE_PLATFORM)
- printf("(legacy) ");
-
- if (fpga_state & FPGA_STATE_DONE_FAILED) {
- printf(" done timed out\n");
- return;
- }
-
- if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
- printf(" refelectione test failed\n");
- return;
- }
-
- unit_type = (versions & 0xf000) >> 12;
- hardware_version = versions & 0x000f;
- feature_channels = fpga_features & 0x007f;
- feature_expansion = fpga_features & (1<<15);
-
- switch (unit_type) {
- case UNITTYPE_CCD_SWITCH:
- printf("CCD-Switch");
- break;
-
- default:
- printf("UnitType %d(not supported)", unit_type);
- break;
- }
-
- switch (hardware_version) {
- case HWVER_100:
- printf(" HW-Ver 1.00\n");
- break;
-
- case HWVER_110:
- printf(" HW-Ver 1.10\n");
- break;
-
- default:
- printf(" HW-Ver %d(not supported)\n",
- hardware_version);
- break;
- }
-
- printf(" FPGA V %d.%02d, features:",
- fpga_version / 100, fpga_version % 100);
-
- printf(" %d channel(s)", feature_channels);
-
- printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-}
-
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- printf("Board: CATCenter Io64\n");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
-
- return 0;
-}
-
-int configure_gbit_phy(char *bus, unsigned char addr)
-{
- unsigned short value;
-
- /* select page 0 */
- if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
- goto err_out;
- /* switch to powerdown */
- if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
- &value))
- goto err_out;
- if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
- value | 0x0004))
- goto err_out;
- /* select page 2 */
- if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
- goto err_out;
- /* disable SGMII autonegotiation */
- if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
- goto err_out;
- /* select page 0 */
- if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
- goto err_out;
- /* switch from powerdown to normal operation */
- if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
- &value))
- goto err_out;
- if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
- value & ~0x0004))
- goto err_out;
- /* reset phy so settings take effect */
- if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
- goto err_out;
-
- return 0;
-
-err_out:
- printf("Error writing to the PHY addr=%02x\n", addr);
- return -1;
-}
-
-int verify_gbit_phy(char *bus, unsigned char addr)
-{
- unsigned short value;
-
- /* select page 2 */
- if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
- goto err_out;
- /* verify SGMII link status */
- if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
- goto err_out;
- if (!(value & (1 << 10)))
- return -2;
-
- return 0;
-
-err_out:
- printf("Error writing to the PHY addr=%02x\n", addr);
- return -1;
-}
-
-int last_stage_init(void)
-{
- unsigned int k;
- unsigned int fpga;
- int failed = 0;
- char str_phys[] = "Setup PHYs -";
- char str_serdes[] = "Start SERDES blocks";
- char str_channels[] = "Start FPGA channels";
- char str_locks[] = "Verify SERDES locks";
- char str_hicb[] = "Verify HICB status";
- char str_status[] = "Verify PHY status -";
- char slash[] = "\\|/-\\|/-";
-
- print_fpga_info(0);
- print_fpga_info(1);
-
- /* setup Gbit PHYs */
- puts("TRANS: ");
- puts(str_phys);
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-
- for (k = 0; k < 32; ++k) {
- configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
- putc('\b');
- putc(slash[k % 8]);
- }
-
- mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-
- for (k = 0; k < 32; ++k) {
- configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
- putc('\b');
- putc(slash[k % 8]);
- }
- blank_string(strlen(str_phys));
-
- /* take fpga serdes blocks out of reset */
- puts(str_serdes);
- udelay(500000);
- FPGA_SET_REG(0, quad_serdes_reset, 0);
- FPGA_SET_REG(1, quad_serdes_reset, 0);
- blank_string(strlen(str_serdes));
-
- /* take channels out of reset */
- puts(str_channels);
- udelay(500000);
- for (fpga = 0; fpga < 2; ++fpga) {
- for (k = 0; k < 32; ++k)
- FPGA_SET_REG(fpga, ch[k].config_int, 0);
- }
- blank_string(strlen(str_channels));
-
- /* verify channels serdes lock */
- puts(str_locks);
- udelay(500000);
- for (fpga = 0; fpga < 2; ++fpga) {
- for (k = 0; k < 32; ++k) {
- u16 status;
- FPGA_GET_REG(fpga, ch[k].status_int, &status);
- if (!(status & (1 << 4))) {
- failed = 1;
- printf("fpga %d channel %d: no serdes lock\n",
- fpga, k);
- }
- /* reset events */
- FPGA_SET_REG(fpga, ch[k].status_int, 0);
- }
- }
- blank_string(strlen(str_locks));
-
- /* verify hicb_status */
- puts(str_hicb);
- for (fpga = 0; fpga < 2; ++fpga) {
- for (k = 0; k < 32; ++k) {
- u16 status;
- FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
- if (status)
- printf("fpga %d hicb %d: hicb status %04x\n",
- fpga, k, status);
- /* reset events */
- FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
- }
- }
- blank_string(strlen(str_hicb));
-
- /* verify phy status */
- puts(str_status);
- for (k = 0; k < 32; ++k) {
- if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
- printf("verify baseboard phy %d failed\n", k);
- failed = 1;
- }
- putc('\b');
- putc(slash[k % 8]);
- }
- for (k = 0; k < 32; ++k) {
- if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
- printf("verify extensionboard phy %d failed\n", k);
- failed = 1;
- }
- putc('\b');
- putc(slash[k % 8]);
- }
- blank_string(strlen(str_status));
-
- printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
-
- return 0;
-}
-
-void gd405ex_init(void)
-{
- unsigned int k;
-
- if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
- } else {
- pca9698_direction_output(0x22, 39, 1);
- }
-}
-
-void gd405ex_set_fpga_reset(unsigned state)
-{
- int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-
- if (legacy) {
- if (state) {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
- } else {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- }
- } else {
- pca9698_set_value(0x22, 39, state ? 0 : 1);
- }
-}
-
-void gd405ex_setup_hw(void)
-{
- gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
- gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
-}
-
-int gd405ex_get_fpga_done(unsigned fpga)
-{
- int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-
- if (legacy)
- return in_le16((void *)LATCH3_BASE)
- & CONFIG_SYS_FPGA_DONE(fpga);
- else
- return pca9698_get_value(0x22, fpga ? 9 : 8);
-}
+++ /dev/null
-if TARGET_DLVISION
-
-config SYS_BOARD
- default "dlvision"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "dlvision"
-
-endif
+++ /dev/null
-DLVISION BOARD
-M: Dirk Eibach <eibach@gdsys.de>
-S: Maintained
-F: board/gdsys/dlvision/
-F: include/configs/dlvision.h
-F: configs/dlvision_defconfig
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = dlvision.o
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-enum {
- HWTYPE_DLVISION_CPU = 0,
- HWTYPE_DLVISION_CON = 1,
-};
-
-#define HWREV_100 6
-
-int board_early_init_f(void)
-{
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks
- * -> ca. 15 us
- */
- mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- /*
- * setup io-latches
- */
- out_le16((void *)CONFIG_SYS_LATCH_BASE, 0x00f0);
- out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0x0002);
- out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200), 0x0000);
- return 0;
-}
-
-int misc_init_r(void)
-{
- /*
- * set "startup-finished"-gpios
- */
- gpio_write_bit(21, 0);
- gpio_write_bit(22, 1);
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
- u8 channel2_msr = in_8((void *)CONFIG_UART_BASE + 0x26);
- u8 channel3_msr = in_8((void *)CONFIG_UART_BASE + 0x36);
- u8 channel7_msr = in_8((void *)CONFIG_UART_BASE + 0x76);
- u8 unit_type;
- u8 local_con;
- u8 audio;
- u8 hardware_version;
-
- printf("Board: ");
-
- unit_type = (channel2_msr & 0x80) ? 0x01 : 0x00;
- local_con = (channel2_msr & 0x20) ? 0x01 : 0x00;
- audio = (channel3_msr & 0x20) ? 0x01 : 0x00;
- hardware_version =
- ((channel7_msr & 0x20) ? 0x01 : 0x00)
- | ((channel7_msr & 0x80) ? 0x02 : 0x00)
- | ((channel7_msr & 0x40) ? 0x04 : 0x00);
-
- switch (unit_type) {
- case HWTYPE_DLVISION_CON:
- printf("DL-Vision-CON");
- break;
-
- case HWTYPE_DLVISION_CPU:
- printf("DL-Vision-CPU");
- break;
-
- default:
- printf("UnitType %d, unsupported", unit_type);
- break;
- }
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- puts("\n ");
-
- switch (hardware_version) {
- case HWREV_100:
- printf("HW-Ver 1.00");
- break;
-
- default:
- printf("HW-Ver %d, unsupported",
- hardware_version);
- break;
- }
-
- if (local_con)
- printf(", local console");
-
- if (audio)
- printf(", audio support");
-
- puts("\n");
-
- return 0;
-}
+++ /dev/null
-if TARGET_GDPPC440ETX
-
-config SYS_BOARD
- default "gdppc440etx"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "gdppc440etx"
-
-endif
+++ /dev/null
-GDPPC440ETX BOARD
-M: Dirk Eibach <eibach@gdsys.de>
-S: Maintained
-F: board/gdsys/gdppc440etx/
-F: include/configs/gdppc440etx.h
-F: configs/gdppc440etx_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = gdppc440etx.o
-extra-y += init.o
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# G&D 440EP/GR ETX-Module
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on board/amcc/yosemite/yosemite.c
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/4xx_pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* info for FLASH chips */
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-int board_early_init_f(void)
-{
- register uint reg;
-
- /*
- * Setup the external bus controller/chip selects
- */
- mfebc(EBC0_CFG, reg);
- mtebc(EBC0_CFG, reg | 0x04000000); /* Set ATC */
-
- /*
- * Setup the GPIO pins
- */
-
- /* setup Address lines for flash size 64Meg. */
- out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
-
- /* setup emac */
- out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
- out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
- out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
-
- /* UART0 and UART1*/
- out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000);
- out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000);
- out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
- out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
-
- /* disable boot-eeprom WP */
- out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
- out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
- out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
-
- /* external interrupts IRQ0...3 */
- out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
- out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
- out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
-
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
- mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- /*
- * Setup other serial configuration
- */
- mfsdr(SDR0_PCI0, reg);
- mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
- mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
- mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- uint pbcr;
- int size_val;
- uint sz;
-
- /* Re-do sizing to get full correct info */
- mfebc(PB0CR, pbcr);
-
- if (gd->bd->bi_flashsize > 0x08000000)
- panic("Max. flash banksize is 128 MB!\n");
-
- for (sz = gd->bd->bi_flashsize, size_val = 7;
- ((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
- sz <<= 1;
-
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtebc(PB0CR, pbcr);
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-/*
- * Override weak pci_pre_init()
- */
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- /* First call common code */
- __pci_pre_init(hose);
-
- /* enable 66 MHz ext. Clock */
- out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
- out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
+++ /dev/null
-/*
-* (C) Copyright 2008
-* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
-*
-* based on board/amcc/yosemite/init.S
-* original Copyright not specified there
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
- * the speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
- 0, AC_RWX | SA_G/*|SA_I*/)
-
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
- 0, AC_RWX | SA_G )
-
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
- 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
- 0, AC_RW | SA_IG )
-
- /* PCI */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
- 0, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
- 0, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
- 0, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
- 0, AC_RW | SA_IG )
-
- tlbtab_end
+++ /dev/null
-if TARGET_INTIP
-
-config SYS_BOARD
- default "intip"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "intip"
-
-endif
+++ /dev/null
-INTIP BOARD
-M: Dirk Eibach <eibach@gdsys.de>
-S: Maintained
-F: board/gdsys/intip/
-F: include/configs/intip.h
-F: configs/devconcenter_defconfig
-F: configs/intip_defconfig
+++ /dev/null
-#
-# (C) Copyright 2008
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := intip.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
- {
- "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
- 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
- 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
- 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88",
- {
- 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88",
- {
- 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
- 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
- }
- },
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-#
-# (C) Copyright 2008-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# G&D CompactCenter
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on board/amcc/canyonlands/init.S
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
- * use the speed up boot process. It is patched after relocation to
- * enable SA_I
- */
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
- 4, AC_RWX | SA_G) /* TLB 0 */
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
- 0, AC_RWX | SA_G)
-#endif
-
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
- AC_RW | SA_IG)
-
- /* TLB-entry for NVRAM */
- tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
- AC_RW | SA_IG)
-
- /* TLB-entry for UART */
- tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
- AC_RW | SA_IG)
-
- /* TLB-entry for IO */
- tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
- AC_RW | SA_IG)
-
- /* TLB-entry for OCM */
- tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
- AC_RWX | SA_I)
-
- /* TLB-entry for Local Configuration registers => peripherals */
- tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
- 4, AC_RWX | SA_IG)
-
- /* AHB: Internal USB Peripherals (USB, SATA) */
- tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
- AC_RWX | SA_IG)
-
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on board/amcc/canyonlands/canyonlands.c
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc440.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/4xx_pcie.h>
-#include <asm/ppc4xx-gpio.h>
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CONFIG_SYS_BCSR3_PCIE 0x10
-
-int board_early_init_f(void)
-{
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC3SR, 0xffffffff); /* clear all */
- mtdcr(UIC3ER, 0x00000000); /* disable all */
- mtdcr(UIC3CR, 0x00000000); /* all non-critical */
- mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC3SR, 0xffffffff); /* clear all */
-
- /*
- * Configure PFC (Pin Function Control) registers
- * enable GPIO 49-63
- * UART0: 4 pins
- */
- mtsdr(SDR0_PFC0, 0x00007fff);
- mtsdr(SDR0_PFC1, 0x00040000);
-
- /* Enable PCI host functionality in SDR0_PCI0 */
- mtsdr(SDR0_PCI0, 0xe0000000);
-
- mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
-
- /* Setup PLB4-AHB bridge based on the system address map */
- mtdcr(AHB_TOP, 0x8000004B);
- mtdcr(AHB_BOT, 0x8000004B);
-
- /*
- * Configure USB-STP pins as alternate and not GPIO
- * It seems to be neccessary to configure the STP pins as GPIO
- * input at powerup (perhaps while USB reset is asserted). So
- * we configure those pins to their "real" function now.
- */
- gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
- gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-
- /* Trigger board component reset */
- out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
- out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
- udelay(50);
- out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
- out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
- udelay(50);
- out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
- out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
-
- return 0;
-}
-
-int get_cpu_num(void)
-{
- int cpu = NA_OR_UNKNOWN_CPU;
-
- return cpu;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
-#ifdef CONFIG_DEVCONCENTER
- printf("Board: DevCon-Center");
-#else
- printf("Board: Intip");
-#endif
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- /*
- * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
- * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
- * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
- * To solve this problem, the FLASH has to get remapped to another
- * EBC address which accepts bigger regions:
- *
- * 0xfn00.0000 -> 4.cn00.0000
- */
-
- u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
- EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
-
- /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
- mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L
- | bxcr_bw
- | EBC_BXCR_BU_RW
- | EBC_BXCR_BW_16BIT);
-
- /* Remove TLB entry of boot EBC mapping */
- remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
-
- /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
- program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
-
- /*
- * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
- * 0xfc00.0000 is possible
- */
-
- /*
- * Clear potential errors resulting from auto-calibration.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- u32 sdr0_srst1 = 0;
- u32 eth_cfg;
-
- /*
- * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
- * This is board specific, so let's do it here.
- */
- mfsdr(SDR0_ETH_CFG, eth_cfg);
- /* disable SGMII mode */
- eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
- SDR0_ETH_CFG_SGMII1_ENABLE |
- SDR0_ETH_CFG_SGMII0_ENABLE);
- /* Set the for 2 RGMII mode */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
- eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
- eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
- mtsdr(SDR0_ETH_CFG, eth_cfg);
-
- /*
- * The AHB Bridge core is held in reset after power-on or reset
- * so enable it now
- */
- mfsdr(SDR0_SRST1, sdr0_srst1);
- sdr0_srst1 &= ~SDR0_SRST1_AHB;
- mtsdr(SDR0_SRST1, sdr0_srst1);
-
- return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-extern void __ft_board_setup(void *blob, bd_t *bd);
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- __ft_board_setup(blob, bd);
-
- fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
- "disabled", sizeof("disabled"), 1);
-
- fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
- "disabled", sizeof("disabled"), 1);
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
#include <asm/global_data.h>
#include "mpc8308.h"
+++ /dev/null
-if TARGET_LWMON5
-
-config SYS_BOARD
- default "lwmon5"
-
-config SYS_VENDOR
- default "liebherr"
-
-config SYS_CONFIG_NAME
- default "lwmon5"
-
-endif
+++ /dev/null
-LWMON5 BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/liebherr/lwmon5/
-F: include/configs/lwmon5.h
-F: configs/lwmon5_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = lwmon5.o kbd.o sdram.o
-extra-y += init.o
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# lwmon5 (440EPx)
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-#endif
-
- /* TLB-entry for PCI Memory */
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
-
- /* TLB-entry for the FPGA Chip select 2 */
- tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
-
- /* TLB-entry for the FPGA Chip select 3 */
- tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
-
- /* TLB-entry for the LIME Controller */
- tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
-
- /* TLB-entry for Internal Registers & OCM */
- tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I)
-
- /*TLB-entry PCI registers*/
- tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG)
-
- /* TLB-entry for peripherals */
- tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2001, 2002
- * DENX Software Engineering
- * Wolfgang Denk, wd@denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <i2c.h>
-#include <command.h>
-#include <console.h>
-#include <post.h>
-#include <serial.h>
-#include <malloc.h>
-
-#include <linux/types.h>
-#include <linux/string.h> /* for strdup */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void kbd_init (void);
-static int compare_magic (uchar *kbd_data, uchar *str);
-
-/*--------------------- Local macros and constants --------------------*/
-#define _NOT_USED_ 0xFFFFFFFF
-
-/*------------------------- dspic io expander -----------------------*/
-#define DSPIC_PON_STATUS_REG 0x80A
-#define DSPIC_PON_INV_STATUS_REG 0x80C
-#define DSPIC_PON_KEY_REG 0x810
-/*------------------------- Keyboard controller -----------------------*/
-/* command codes */
-#define KEYBD_CMD_READ_KEYS 0x01
-#define KEYBD_CMD_READ_VERSION 0x02
-#define KEYBD_CMD_READ_STATUS 0x03
-#define KEYBD_CMD_RESET_ERRORS 0x10
-
-/* status codes */
-#define KEYBD_STATUS_MASK 0x3F
-#define KEYBD_STATUS_H_RESET 0x20
-#define KEYBD_STATUS_BROWNOUT 0x10
-#define KEYBD_STATUS_WD_RESET 0x08
-#define KEYBD_STATUS_OVERLOAD 0x04
-#define KEYBD_STATUS_ILLEGAL_WR 0x02
-#define KEYBD_STATUS_ILLEGAL_RD 0x01
-
-/* Number of bytes returned from Keyboard Controller */
-#define KEYBD_VERSIONLEN 2 /* version information */
-
-/*
- * This is different from the "old" lwmon dsPIC kbd controller
- * implementation. Now the controller still answers with 9 bytes,
- * but the last 3 bytes are always "0x06 0x07 0x08". So we just
- * set the length to compare to 6 instead of 9.
- */
-#define KEYBD_DATALEN 6 /* normal key scan data */
-
-/* maximum number of "magic" key codes that can be assigned */
-
-static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
-static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
-
-static uchar *key_match (uchar *);
-
-#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */
-
-/***********************************************************************
-F* Function: int board_postclk_init (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: int
-P* - 0 is always returned.
- *
-Z* Intention: This function is the board_postclk_init() method implementation
-Z* for the lwmon board.
- *
- ***********************************************************************/
-int board_postclk_init (void)
-{
- kbd_init();
-
- return (0);
-}
-
-static void kbd_init (void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- uchar tmp_data[KEYBD_DATALEN];
- uchar val, errcd;
- int i;
-
- i2c_set_bus_num(0);
-
- gd->arch.kbd_status = 0;
-
- /* Forced by PIC. Delays <= 175us loose */
- udelay(1000);
-
- /* Read initial keyboard error code */
- val = KEYBD_CMD_READ_STATUS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, &errcd, 1);
- /* clear unused bits */
- errcd &= KEYBD_STATUS_MASK;
- /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
- errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
- if (errcd) {
- gd->arch.kbd_status |= errcd << 8;
- }
- /* Reset error code and verify */
- val = KEYBD_CMD_RESET_ERRORS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- udelay(1000); /* delay NEEDED by keyboard PIC !!! */
-
- val = KEYBD_CMD_READ_STATUS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, &val, 1);
-
- val &= KEYBD_STATUS_MASK; /* clear unused bits */
- if (val) { /* permanent error, report it */
- gd->arch.kbd_status |= val;
- return;
- }
-
- /*
- * Read current keyboard state.
- *
- * After the error reset it may take some time before the
- * keyboard PIC picks up a valid keyboard scan - the total
- * scan time is approx. 1.6 ms (information by Martin Rajek,
- * 28 Sep 2002). We read a couple of times for the keyboard
- * to stabilize, using a big enough delay.
- * 10 times should be enough. If the data is still changing,
- * we use what we get :-(
- */
-
- memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */
- for (i=0; i<10; ++i) {
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
- /* consistent state, done */
- break;
- }
- /* remeber last state, delay, and retry */
- memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
- udelay (5000);
- }
-}
-
-
-/* Read a register from the dsPIC. */
-int _dspic_read(ushort reg, ushort *data)
-{
- uchar buf[sizeof(*data)];
- int rval;
-
- if (i2c_read(dspic_addr, reg, 2, buf, 2))
- return -1;
-
- rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
- *data = (buf[0] << 8) | buf[1];
-
- return rval;
-}
-
-
-/***********************************************************************
-F* Function: int misc_init_r (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: int
-P* - 0 is always returned, even in the case of a keyboard
-P* error.
- *
-Z* Intention: This function is the misc_init_r() method implementation
-Z* for the lwmon board.
-Z* The keyboard controller is initialized and the result
-Z* of a read copied to the environment variable "keybd".
-Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for
-Z* this key, and if found display to the LCD will be enabled.
-Z* The keys in "keybd" are checked against the magic
-Z* keycommands defined in the environment.
-Z* See also key_match().
- *
-D* Design: wd@denx.de
-C* Coding: wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int misc_init_r_kbd (void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- uchar kbd_init_status = gd->arch.kbd_status >> 8;
- uchar kbd_status = gd->arch.kbd_status;
- uchar val;
- ushort data, inv_data;
- char *str;
- int i;
-
- if (kbd_init_status) {
- printf ("KEYBD: Error %02X\n", kbd_init_status);
- }
- if (kbd_status) { /* permanent error, report it */
- printf ("*** Keyboard error code %02X ***\n", kbd_status);
- sprintf (keybd_env, "%02X", kbd_status);
- setenv ("keybd", keybd_env);
- return 0;
- }
-
- /*
- * Now we know that we have a working keyboard, so disable
- * all output to the LCD except when a key press is detected.
- */
-
- if ((console_assign (stdout, "serial") < 0) ||
- (console_assign (stderr, "serial") < 0)) {
- printf ("Can't assign serial port as output device\n");
- }
-
- /* Read Version */
- val = KEYBD_CMD_READ_VERSION;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
- printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
-
- /* Read current keyboard state */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- /* read out start key from bse01 received via can */
- _dspic_read(DSPIC_PON_STATUS_REG, &data);
- /* check highbyte from status register */
- if (data > 0xFF) {
- _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
-
- /* check inverse data */
- if ((data+inv_data) == 0xFFFF) {
- /* don't overwrite local key */
- if (kbd_data[1] == 0) {
- /* read key value */
- _dspic_read(DSPIC_PON_KEY_REG, &data);
- str = (char *)&data;
- /* swap bytes */
- kbd_data[1] = str[1];
- kbd_data[2] = str[0];
- printf("CAN received startkey: 0x%X\n", data);
- }
- }
- }
-
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- }
-
- setenv ("keybd", keybd_env);
-
- str = strdup ((char *)key_match (kbd_data)); /* decode keys */
-#ifdef KEYBD_SET_DEBUGMODE
- if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
- if ((console_assign (stdout, "lcd") < 0) ||
- (console_assign (stderr, "lcd") < 0)) {
- printf ("Can't assign LCD display as output device\n");
- }
- }
-#endif /* KEYBD_SET_DEBUGMODE */
-#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
- setenv ("preboot", str); /* set or delete definition */
-#endif /* CONFIG_PREBOOT */
- if (str != NULL) {
- free (str);
- }
- return (0);
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
- uchar compare[KEYBD_DATALEN-1];
- char *nxt;
- int i;
-
- /* Don't include modifier byte */
- memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
-
- for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
- uchar c;
- int k;
-
- c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
- if (str == (uchar *)nxt) { /* invalid character */
- break;
- }
-
- /*
- * Check if this key matches the input.
- * Set matches to zero, so they match only once
- * and we can find duplicates or extra keys
- */
- for (k = 0; k < sizeof(compare); ++k) {
- if (compare[k] == '\0') /* only non-zero entries */
- continue;
- if (c == compare[k]) { /* found matching key */
- compare[k] = '\0';
- break;
- }
- }
- if (k == sizeof(compare)) {
- return -1; /* unmatched key */
- }
- }
-
- /*
- * A full match leaves no keys in the `compare' array,
- */
- for (i = 0; i < sizeof(compare); ++i) {
- if (compare[i])
- {
- return -1;
- }
- }
-
- return 0;
-}
-
-/***********************************************************************
-F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z*
- *
-P* Parameters: uchar *kbd_data
-P* - The keys to match against our magic definitions
-P*
-P* Returnvalue: uchar *
-P* - != NULL: Pointer to the corresponding command(s)
-P* NULL: No magic is about to happen
- *
-Z* Intention: Check if pressed key(s) match magic sequence,
-Z* and return the command string associated with that key(s).
-Z*
-Z* If no key press was decoded, NULL is returned.
-Z*
-Z* Note: the first character of the argument will be
-Z* overwritten with the "magic charcter code" of the
-Z* decoded key(s), or '\0'.
-Z*
-Z* Note: the string points to static environment data
-Z* and must be saved before you call any function that
-Z* modifies the environment.
- *
-D* Design: wd@denx.de
-C* Coding: wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-static uchar *key_match (uchar *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- uchar *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can pe appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
- debug ("### Check magic \"%s\"\n", magic);
- if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
- cmd = getenv (cmd_name);
- debug ("### Set PREBOOT to $(%s): \"%s\"\n",
- cmd_name, cmd ? cmd : "<<NULL>>");
- *kbd_data = *suffix;
- return ((uchar *)cmd);
- }
- }
- debug ("### Delete PREBOOT\n");
- *kbd_data = '\0';
- return (NULL);
-}
-#endif /* CONFIG_PREBOOT */
-
-/***********************************************************************
-F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag,
-F* int argc, char * const argv[]) P*A*Z*
- *
-P* Parameters: cmd_tbl_t *cmdtp
-P* - Pointer to our command table entry
-P* int flag
-P* - If the CMD_FLAG_REPEAT bit is set, then this call is
-P* a repetition
-P* int argc
-P* - Argument count
-P* char * const argv[]
-P* - Array of the actual arguments
-P*
-P* Returnvalue: int
-P* - 0 is always returned.
- *
-Z* Intention: Implement the "kbd" command.
-Z* The keyboard status is read. The result is printed on
-Z* the console and written into the "keybd" environment
-Z* variable.
- *
-D* Design: wd@denx.de
-C* Coding: wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- uchar val;
- int i;
-
-#if 0 /* Done in kbd_init */
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- /* Read keys */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- puts ("Keys:");
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- printf (" %02x", kbd_data[i]);
- }
- putc ('\n');
- setenv ("keybd", keybd_env);
- return 0;
-}
-
-U_BOOT_CMD(
- kbd, 1, 1, do_kbd,
- "read keyboard status",
- ""
-);
-
-/*----------------------------- Utilities -----------------------------*/
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- uchar val;
-
- /* Read keys */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc440.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <post.h>
-#include <flash.h>
-#include <video.h>
-#include <mtd/cfi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
-
-ulong flash_get_size(ulong base, int banknum);
-int misc_init_r_kbd(void);
-
-int board_early_init_f(void)
-{
- u32 sdr0_pfc1, sdr0_pfc2;
- u32 reg;
-
- /* PLB Write pipelining disabled. Denali Core workaround */
- mtdcr(PLB4A0_ACR, 0xDE000000);
- mtdcr(PLB4A1_ACR, 0xDE000000);
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
- mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
- mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
- mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
- mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- /* Trace Pins are disabled. SDR0_PFC0 Register */
- mtsdr(SDR0_PFC0, 0x0);
-
- /* select Ethernet pins */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- /* SMII via ZMII */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_6;
- mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_6;
-
- /* enable SPI (SCP) */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
-
- mtsdr(SDR0_PFC2, sdr0_pfc2);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- mtsdr(SDR0_PFC4, 0x80000000);
-
- /* PCI arbiter disabled */
- /* PCI Host Configuration disbaled */
- mfsdr(SDR0_PCI0, reg);
- reg = 0;
- mtsdr(SDR0_PCI0, 0x00000000 | reg);
-
- gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
- /* enable the LSB transmitter */
- gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
- /* enable the CAN transmitter */
- gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
-
- reg = 0; /* reuse as counter */
- out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
- in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
- & ~CONFIG_SYS_DSPIC_TEST_MASK);
- while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
- udelay(1000);
- }
- if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
- /* set "boot error" flag */
- out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
- in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
- CONFIG_SYS_DSPIC_TEST_MASK);
- }
-#endif
-
- /*
- * Reset PHY's:
- * The PHY's need a 2nd reset pulse, since the MDIO address is latched
- * upon reset, and with the first reset upon powerup, the addresses are
- * not latched reliable, since the IRQ line is multiplexed with an
- * MDIO address. A 2nd reset at this time will make sure, that the
- * correct address is latched.
- */
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
- udelay(1000);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
- udelay(1000);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
-
- return 0;
-}
-
-/*
- * Override weak default with board specific version
- */
-phys_addr_t cfi_flash_bank_addr(int bank)
-{
- return lwmon5_cfi_flash_bank_addr[bank];
-}
-
-/*
- * Override the weak default mapping function with a board specific one
- */
-u32 flash_get_bank_size(int cs, int idx)
-{
- return flash_info[idx].size;
-}
-
-int board_early_init_r(void)
-{
- u32 val0, val1;
-
- /*
- * lwmon5 is manufactured in 2 different board versions:
- * The lwmon5a board has 64MiB NOR flash instead of the
- * 128MiB of the original lwmon5. Unfortunately the CFI driver
- * will report 2 banks of 64MiB even for the smaller flash
- * chip, since the bank is mirrored. To fix this, we bring
- * one bank into CFI query mode and read its response. This
- * enables us to detect the real number of flash devices/
- * banks which will be used later on by the common CFI driver.
- */
-
- /* Put bank 0 into CFI command mode and read */
- out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
- val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
- val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
-
- /* Reset flash again out of query mode */
- out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
-
- /* When not identical, we have 2 different flash devices/banks */
- if (val0 != val1)
- return 0;
-
- /*
- * Now we're sure that we're running on a LWMON5a board with
- * only 64MiB NOR flash in one bank:
- *
- * Set flash base address and bank count for CFI driver probing.
- */
- cfi_flash_num_flash_banks = 1;
- lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- u32 pbcr;
- int size_val = 0;
- u32 reg;
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1, sdr0_srst;
-
- /*
- * FLASH stuff...
- */
-
- /* Re-do sizing to get full correct info */
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- mfebc(PB0CR, pbcr);
- size_val = ffs(gd->bd->bi_flashsize) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtebc(PB0CR, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
- /* Monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
- &flash_info[cfi_flash_num_flash_banks - 1]);
-
- /* Env protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[cfi_flash_num_flash_banks - 1]);
-
- /*
- * USB suff...
- */
-
- /* Reset USB */
- /* Reset of USB2PHY0 must be active at least 10 us */
- mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
- udelay(2000);
-
- mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
- SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
- SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
- udelay(2000);
-
- /* Errata CHIP_6 */
-
- /* 1. Set internal PHY configuration */
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB0, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
-
- /*
- * An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB0, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /* 2. De-assert internal PHY reset */
- mfsdr(SDR0_SRST1, sdr0_srst);
- sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
- mtsdr(SDR0_SRST1, sdr0_srst);
-
- /* 3. Wait for more than 1 ms */
- udelay(2000);
-
- /* 4. De-assert USB 2.0 Host main reset */
- mfsdr(SDR0_SRST0, sdr0_srst);
- sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
- mtsdr(SDR0_SRST0, sdr0_srst);
- udelay(1000);
-
- /* 5. De-assert reset of OPB2 cores */
- mfsdr(SDR0_SRST1, sdr0_srst);
- sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
- sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
- sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
- mtsdr(SDR0_SRST1, sdr0_srst);
- udelay(1000);
-
- /* 6. Set EHCI Configure FLAG */
-
- /* 7. Reassert internal PHY reset: */
- mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
- udelay(1000);
-
- /*
- * Clear resets
- */
- mtsdr(SDR0_SRST1, 0x00000000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Host(int phy) Device(ext phy)\n");
-
- /*
- * Clear PLB4A0_ACR[WRP]
- * This fix will make the MAL burst disabling patch for the Linux
- * EMAC driver obsolete.
- */
- reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
- mtdcr(PLB4A0_ACR, reg);
-
- /*
- * Init matrix keyboard
- */
- misc_init_r_kbd();
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: %s", __stringify(CONFIG_HOSTNAME));
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-void hw_watchdog_reset(void)
-{
- int val;
-#if defined(CONFIG_WD_MAX_RATE)
- unsigned long long ct = get_ticks();
-
- /*
- * Don't allow watch-dog triggering more frequently than
- * the predefined value CONFIG_WD_MAX_RATE [ticks].
- */
- if (ct >= gd->arch.wdt_last) {
- if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
- return;
- } else {
- /* Time base counter had been reset */
- if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
- CONFIG_WD_MAX_RATE)
- return;
- }
- gd->arch.wdt_last = get_ticks();
-#endif
-
- /*
- * Toggle watchdog output
- */
- val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
- gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
-}
-
-int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- if ((strcmp(argv[1], "on") == 0))
- gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
- else if ((strcmp(argv[1], "off") == 0))
- gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
- else
- return cmd_usage(cmdtp);
-
- return 0;
-}
-
-U_BOOT_CMD(
- eepromwp, 2, 0, do_eeprom_wp,
- "eeprom write protect off/on",
- "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
-);
-
-#if defined(CONFIG_VIDEO)
-#include <video_fb.h>
-#include <mb862xx.h>
-
-extern GraphicDevice mb862xx;
-
-static const gdc_regs init_regs [] = {
- { 0x0100, 0x00000f00 },
- { 0x0020, 0x801401df },
- { 0x0024, 0x00000000 },
- { 0x0028, 0x00000000 },
- { 0x002c, 0x00000000 },
- { 0x0110, 0x00000000 },
- { 0x0114, 0x00000000 },
- { 0x0118, 0x01df0280 },
- { 0x0004, 0x031f0000 },
- { 0x0008, 0x027f027f },
- { 0x000c, 0x015f028f },
- { 0x0010, 0x020c0000 },
- { 0x0014, 0x01df01ea },
- { 0x0018, 0x00000000 },
- { 0x001c, 0x01e00280 },
- { 0x0100, 0x80010f00 },
- { 0x0, 0x0 }
-};
-
-const gdc_regs *board_get_regs(void)
-{
- return init_regs;
-}
-
-/* Returns Lime base address */
-unsigned int board_video_init(void)
-{
- /*
- * Reset Lime controller
- */
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
- udelay(500);
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
- mb862xx.winSizeX = 640;
- mb862xx.winSizeY = 480;
- mb862xx.gdfBytesPP = 2;
- mb862xx.gdfIndex = GDF_15BIT_555RGB;
-
- return CONFIG_SYS_LIME_BASE_0;
-}
-
-#define DEFAULT_BRIGHTNESS 0x64
-
-static void board_backlight_brightness(int brightness)
-{
- if (brightness > 0) {
- /* pwm duty, lamp on */
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
- } else {
- /* lamp off */
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
- }
-}
-
-void board_backlight_switch(int flag)
-{
- char * param;
- int rc;
-
- if (flag) {
- param = getenv("brightness");
- rc = param ? simple_strtol(param, NULL, 10) : -1;
- if (rc < 0)
- rc = DEFAULT_BRIGHTNESS;
- } else {
- rc = 0;
- }
- board_backlight_brightness(rc);
-}
-
-#if defined(CONFIG_CONSOLE_EXTRA_INFO)
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str(int line_number, char *info)
-{
- if (line_number == 1)
- strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
- else
- info [0] = '\0';
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-#endif /* CONFIG_VIDEO */
-
-void board_reset(void)
-{
- gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * lwmon5 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if booting into OS is selected (default)
- * 1 if booting into U-Boot is selected
- */
-int spl_start_uboot(void)
-{
- char s[8];
-
- env_init();
- getenv_f("boot_os", s, sizeof(s));
- if ((s != NULL) && (strcmp(s, "yes") == 0))
- return 0;
-
- return 1;
-}
-
-/*
- * This function is called from the SPL U-Boot version for
- * early init stuff, that needs to be done for OS (e.g. Linux)
- * booting. Doing it later in the real U-Boot would not work
- * in case that the SPL U-Boot boots Linux directly.
- */
-void spl_board_init(void)
-{
- const gdc_regs *regs = board_get_regs();
-
- /*
- * Setup PFC registers, mainly for ethernet support
- * later on in Linux
- */
- board_early_init_f();
-
- /* enable the LSB transmitter */
- gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
-
- /*
- * Clear resets
- */
- mtsdr(SDR0_SRST1, 0x00000000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- /*
- * Reset Lime controller
- */
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
- udelay(500);
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
- out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
- udelay(300);
- out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
-
- while (regs->index) {
- out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
- regs->index, regs->value);
- regs++;
- }
-
- board_backlight_brightness(DEFAULT_BRIGHTNESS);
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/ppc440.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
- * region. Right now the cache should still be disabled in U-Boot because of the
- * EMAC driver, that need it's buffer descriptor to be located in non cached
- * memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#ifdef CONFIG_4xx_DCACHE
-#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
-#else
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Prototypes
- *-----------------------------------------------------------------------------*/
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-extern void dcbz_area(u32 start_address, u32 num_bytes);
-
-static u32 is_ecc_enabled(void)
-{
- u32 val;
-
- mfsdram(DDR0_22, val);
- val &= DDR0_22_CTRL_RAW_MASK;
- if (val)
- return 1;
- else
- return 0;
-}
-
-void board_add_ram_info(int use_default)
-{
- PPC4xx_SYS_INFO board_cfg;
- u32 val;
-
- if (is_ecc_enabled())
- puts(" (ECC");
- else
- puts(" (ECC not");
-
- get_sys_info(&board_cfg);
- printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
-
- mfsdram(DDR0_03, val);
- val = DDR0_03_CASLAT_DECODE(val);
- printf(", CL%d)", val);
-}
-
-#ifdef CONFIG_DDR_ECC
-static void wait_ddr_idle(void)
-{
- /*
- * Controller idle status cannot be determined for Denali
- * DDR2 code. Just return here.
- */
-}
-
-static void program_ecc(u32 start_address,
- u32 num_bytes,
- u32 tlb_word2_i_value)
-{
- u32 val;
- u32 current_addr = start_address;
- u32 size;
- int bytes_remaining;
-
- sync();
- wait_ddr_idle();
-
- /*
- * Because of 440EPx errata CHIP 11, we don't touch the last 256
- * bytes of SDRAM.
- */
- bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
-
- /*
- * We have to write the ECC bytes by zeroing and flushing in smaller
- * steps, since the whole 256MByte takes too long for the external
- * watchdog.
- */
- while (bytes_remaining > 0) {
- size = min((64 << 20), bytes_remaining);
-
- /* Write zero's to SDRAM */
- dcbz_area(current_addr, size);
-
- /* Write modified dcache lines back to memory */
- clean_dcache_range(current_addr, current_addr + size);
-
- current_addr += 64 << 20;
- bytes_remaining -= 64 << 20;
- WATCHDOG_RESET();
- }
-
- sync();
- wait_ddr_idle();
-
- /* Clear error status */
- mfsdram(DDR0_00, val);
- mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
-
- /* Set 'int_mask' parameter to functionnal value */
- mfsdram(DDR0_01, val);
- mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
-
- sync();
- wait_ddr_idle();
-}
-#endif
-
-/*************************************************************************
- *
- * dram_init -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-int dram_init(void)
-{
- /* CL=4 */
- mtsdram(DDR0_02, 0x00000000);
-
- mtsdram(DDR0_00, 0x0000190A);
- mtsdram(DDR0_01, 0x01000000);
- mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
-
- mtsdram(DDR0_04, 0x0B030300);
- mtsdram(DDR0_05, 0x02020308);
- mtsdram(DDR0_06, 0x0003C812);
- mtsdram(DDR0_07, 0x00090100);
- mtsdram(DDR0_08, 0x03c80001);
- mtsdram(DDR0_09, 0x00011D5F);
- mtsdram(DDR0_10, 0x00000100);
- mtsdram(DDR0_11, 0x000CC800);
- mtsdram(DDR0_12, 0x00000003);
- mtsdram(DDR0_14, 0x00000000);
- mtsdram(DDR0_17, 0x1e000000);
- mtsdram(DDR0_18, 0x1e1e1e1e);
- mtsdram(DDR0_19, 0x1e1e1e1e);
- mtsdram(DDR0_20, 0x0B0B0B0B);
- mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
- mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
-#else
- mtsdram(DDR0_22, 0x00267F0B);
-#endif
-
- mtsdram(DDR0_23, 0x01000000);
- mtsdram(DDR0_24, 0x01010001);
-
- mtsdram(DDR0_26, 0x2D93028A);
- mtsdram(DDR0_27, 0x0784682B);
-
- mtsdram(DDR0_28, 0x00000080);
- mtsdram(DDR0_31, 0x00000000);
- mtsdram(DDR0_42, 0x01000008);
-
- mtsdram(DDR0_43, 0x050A0200);
- mtsdram(DDR0_44, 0x00000005);
- mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
-
- denali_wait_for_dlllock();
-
-#if defined(CONFIG_DDR_DATA_EYE)
- /* -----------------------------------------------------------+
- * Perform data eye search if requested.
- * ----------------------------------------------------------*/
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
- TLB_WORD2_I_ENABLE);
- denali_core_search_data_eye();
- remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif
-
- /*
- * Program tlb entries for this size (dynamic)
- */
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
- MY_TLB_WORD2_I_ENABLE);
-
-#if defined(CONFIG_DDR_ECC)
-#if defined(CONFIG_4xx_DCACHE)
- /*
- * If ECC is enabled, initialize the parity bits.
- */
- program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#else /* CONFIG_4xx_DCACHE */
- /*
- * Setup 2nd TLB with same physical address but different virtual address
- * with cache enabled. This is done for fast ECC generation.
- */
- program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
- /*
- * If ECC is enabled, initialize the parity bits.
- */
- program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
- /*
- * Now after initialization (auto-calibration and ECC generation)
- * remove the TLB entries with caches enabled and program again with
- * desired cache functionality
- */
- remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif /* CONFIG_4xx_DCACHE */
-#endif /* CONFIG_DDR_ECC */
-
- /*
- * Clear possible errors resulting from data-eye-search.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
-
- return 0;
-}
+++ /dev/null
-if TARGET_ICON
-
-config SYS_BOARD
- default "icon"
-
-config SYS_VENDOR
- default "mosaixtech"
-
-config SYS_CONFIG_NAME
- default "icon"
-
-endif
+++ /dev/null
-ICON BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/mosaixtech/icon/
-F: include/configs/icon.h
-F: configs/icon_defconfig
+++ /dev/null
-#
-# (C) Copyright 2009-2010
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := icon.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2009-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
- {
- "400-133", "CPU: 400 PLB: 133 OPB: 66 EBC: 66",
- { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
- },
- {
- "500-166", "CPU: 500 PLB: 166 OPB: 83 EBC: 83",
- { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
- },
- {
- "533-133", "CPU: 533 PLB: 133 OPB: 66 EBC: 66",
- { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
- },
- {
- "667-133", "CPU: 667 PLB: 133 OPB: 66 EBC: 66",
- { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
- },
- {
- "667-166", "CPU: 667 PLB: 166 OPB: 83 EBC: 83",
- { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
- },
- {
- "800-160", "CPU: 800 PLB: 160 OPB: 53 EBC: 17",
- { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
- },
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-#
-# (C) Copyright 2009-2010
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2009-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <i2c.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-#include <video.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/4xx_pcie.h>
-#include <linux/errno.h>
-#include <asm/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- unsigned long mfr;
-
- /*
- * Interrupt controller setup for the ICON 440SPe board.
- *
- *--------------------------------------------------------------------
- * IRQ | Source | Pol. | Sensi.| Crit.
- *--------+-----------------------------------+-------+-------+-------
- * IRQ 00 | UART0 | High | Level | Non
- * IRQ 01 | UART1 | High | Level | Non
- * IRQ 02 | IIC0 | High | Level | Non
- * IRQ 03 | IIC1 | High | Level | Non
- * IRQ 04 | PCI0X0 MSG IN | High | Level | Non
- * IRQ 05 | PCI0X0 CMD Write | High | Level | Non
- * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non
- * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non
- * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non
- * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non
- * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non
- * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit
- * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non
- * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non
- * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non
- * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non
- * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non
- * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit
- * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non
- * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non
- * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non
- * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non
- * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non
- * IRQ 23 | I2O Inbound Doorbell | High | Level | Non
- * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non
- * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non
- * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non
- * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non
- * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non
- * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non
- * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non
- * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit.
- *--------------------------------------------------------------------
- * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non
- * IRQ 33 | MAL Serr | High | Level | Non
- * IRQ 34 | MAL Txde | High | Level | Non
- * IRQ 35 | MAL Rxde | High | Level | Non
- * IRQ 36 | DMC CE or DMC UE | High | Level | Non
- * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non
- * IRQ 38 | MAL TX EOB | High | Level | Non
- * IRQ 39 | MAL RX EOB | High | Level | Non
- * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non
- * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non
- * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non
- * IRQ 43 | L2 Cache | Risin | Edge | Non
- * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non
- * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non
- * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non
- * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non
- * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non
- * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non
- * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non
- * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non
- * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non
- * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non
- * IRQ 54 | DMA Error | High | Level | Non
- * IRQ 55 | DMA I2O Error | High | Level | Non
- * IRQ 56 | Serial ROM | High | Level | Non
- * IRQ 57 | PCIX0 Error | High | Edge | Non
- * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non
- * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non
- * IRQ 60 | EMAC0 Interrupt | High | Level | Non
- * IRQ 61 | EMAC0 Wake-up | High | Level | Non
- * IRQ 62 | Reserved | High | Level | Non
- * IRQ 63 | XOR | High | Level | Non
- *--------------------------------------------------------------------
- * IRQ 64 | PE0 AL | High | Level | Non
- * IRQ 65 | PE0 VPD Access | Risin | Edge | Non
- * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non
- * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non
- * IRQ 68 | PE0 TCR | High | Level | Non
- * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non
- * IRQ 70 | PE0 DCR Error | High | Level | Non
- * IRQ 71 | Reserved | N/A | N/A | Non
- * IRQ 72 | PE1 AL | High | Level | Non
- * IRQ 73 | PE1 VPD Access | Risin | Edge | Non
- * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non
- * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non
- * IRQ 76 | PE1 TCR | High | Level | Non
- * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non
- * IRQ 78 | PE1 DCR Error | High | Level | Non
- * IRQ 79 | Reserved | N/A | N/A | Non
- * IRQ 80 | PE2 AL | High | Level | Non
- * IRQ 81 | PE2 VPD Access | Risin | Edge | Non
- * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non
- * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non
- * IRQ 84 | PE2 TCR | High | Level | Non
- * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non
- * IRQ 86 | PE2 DCR Error | High | Level | Non
- * IRQ 87 | Reserved | N/A | N/A | Non
- * IRQ 88 | External IRQ(5) | Progr | Progr | Non
- * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non
- * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non
- * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non
- * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non
- * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non
- * IRQ 94 | Reserved | N/A | N/A | Non
- * IRQ 95 | Reserved | N/A | N/A | Non
- *--------------------------------------------------------------------
- * IRQ 96 | PE0 INTA | High | Level | Non
- * IRQ 97 | PE0 INTB | High | Level | Non
- * IRQ 98 | PE0 INTC | High | Level | Non
- * IRQ 99 | PE0 INTD | High | Level | Non
- * IRQ 100| PE1 INTA | High | Level | Non
- * IRQ 101| PE1 INTB | High | Level | Non
- * IRQ 102| PE1 INTC | High | Level | Non
- * IRQ 103| PE1 INTD | High | Level | Non
- * IRQ 104| PE2 INTA | High | Level | Non
- * IRQ 105| PE2 INTB | High | Level | Non
- * IRQ 106| PE2 INTC | High | Level | Non
- * IRQ 107| PE2 INTD | Risin | Edge | Non
- * IRQ 108| PCI Express MSI Level 4 | Risin | Edge | Non
- * IRQ 109| PCI Express MSI Level 5 | Risin | Edge | Non
- * IRQ 110| PCI Express MSI Level 6 | Risin | Edge | Non
- * IRQ 111| PCI Express MSI Level 7 | Risin | Edge | Non
- * IRQ 116| PCI Express MSI Level 12 | Risin | Edge | Non
- * IRQ 112| PCI Express MSI Level 8 | Risin | Edge | Non
- * IRQ 113| PCI Express MSI Level 9 | Risin | Edge | Non
- * IRQ 114| PCI Express MSI Level 10 | Risin | Edge | Non
- * IRQ 115| PCI Express MSI Level 11 | Risin | Edge | Non
- * IRQ 117| PCI Express MSI Level 13 | Risin | Edge | Non
- * IRQ 118| PCI Express MSI Level 14 | Risin | Edge | Non
- * IRQ 119| PCI Express MSI Level 15 | Risin | Edge | Non
- * IRQ 120| PCI Express MSI Level 16 | Risin | Edge | Non
- * IRQ 121| PCI Express MSI Level 17 | Risin | Edge | Non
- * IRQ 122| PCI Express MSI Level 18 | Risin | Edge | Non
- * IRQ 123| PCI Express MSI Level 19 | Risin | Edge | Non
- * IRQ 124| PCI Express MSI Level 20 | Risin | Edge | Non
- * IRQ 125| PCI Express MSI Level 21 | Risin | Edge | Non
- * IRQ 126| PCI Express MSI Level 22 | Risin | Edge | Non
- * IRQ 127| PCI Express MSI Level 23 | Risin | Edge | Non
- */
-
- /*
- * Put UICs in PowerPC 440SPe mode.
- * Initialise UIC registers. Clear all interrupts. Disable all
- * interrupts. Set critical interrupt values. Set interrupt polarities.
- * Set interrupt trigger levels. Make bit 0 High priority. Clear all
- * interrupts again.
- */
- mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
- mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
- mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical IRQs */
- mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
- mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
- mtdcr(UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
- mtdcr(UIC3SR, 0x00000000); /* clear all interrupts*/
- mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts*/
-
- mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
- mtdcr(UIC2ER, 0x00000000); /* disable all interrupts*/
- mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical IRQs */
- mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
- mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
- mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
- mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
- mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts*/
- mtdcr(UIC1ER, 0x00000000); /* disable all interrupts*/
- mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical IRQs */
- mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr(UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
- mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
- mtdcr(UIC1SR, 0x00000000); /* clear all interrupts*/
- mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts*/
-
- mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
- mtdcr(UIC0ER, 0x00000000); /* disable all int. excepted cascade */
- mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical IRQs */
- mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
- mtdcr(UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
- mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
- mtdcr(UIC0SR, 0x00000000); /* clear all interrupts*/
- mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts*/
-
- mfsdr(SDR0_MFR, mfr);
- mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
- mtsdr(SDR0_MFR, mfr);
-
- mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
-
- out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR);
- out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
- out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- /*
- * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the
- * boot EBC mapping only supports a maximum of 16MBytes
- * (4.ff00.0000 - 4.ffff.ffff).
- * To solve this problem, the FLASH has to get remapped to another
- * EBC address which accepts bigger regions:
- *
- * 0xfc00.0000 -> 4.ec00.0000
- */
-
- /* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */
- mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-
- /* Remove TLB entry of boot EBC mapping */
- remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
-
- /* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */
- program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
-
- /*
- * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
- * 0xfc00.0000 is possible
- */
-
- /*
- * Clear potential errors resulting from auto-calibration.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: ICON");
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- *
- * Tested successfully with the following SODIMM:
- * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
- *
- * Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state,
- * directly after power-up. Only after running for more than 10 minutes
- * real stable auto-calibration windows could be found.
- */
-u32 ddr_wrdtr(u32 default_val)
-{
- return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV;
-}
-
-u32 ddr_clktr(u32 default_val)
-{
- return SDRAM_CLKTR_CLKP_180_DEG_ADV;
-}
-
-/*
- * Override the weak default implementation and return the
- * last PCIe slot number (max number - 1).
- */
-int board_pcie_last(void)
-{
- /* Only 2 PCIe ports used on ICON, so the last one is 1 */
- return 1;
-}
-
-/*
- * Video
- */
-#ifdef CONFIG_VIDEO_SM501
-#include <sm501.h>
-
-#define DISPLAY_WIDTH 640
-#define DISPLAY_HEIGHT 480
-
-static const SMI_REGS sm502_init_regs[] = {
- {0x00004, 0x0},
- {0x00040, 0x00021847},
- {0x00044, 0x091a0a01}, /* 24 MHz pixclk */
- {0x00054, 0x0},
- {0x00048, 0x00021847},
- {0x0004C, 0x091a0a01},
- {0x00054, 0x1},
- {0x80004, 0xc428bb17},
- {0x8000C, 0x00000000},
- {0x80010, 0x0a000a00},
- {0x80014, 0x02800000},
- {0x80018, 0x01e00000},
- {0x8001C, 0x00000000},
- {0x80020, 0x01e00280},
- {0x80024, 0x02fa027f},
- {0x80028, 0x004a0280},
- {0x8002C, 0x020c01df},
- {0x80030, 0x000201e7},
- {0x80200, 0x00010000},
- {0x00008, 0x20000000}, /* gpio29 is pwm0, LED_PWM */
- {0x0000C, 0x3f000000}, /* gpio56 - gpio61 as flat panel data pins */
- {0x10020, 0x25725728}, /* 20 kHz pwm0, 50 % duty cycle, disabled */
- {0x80000, 0x0f010106}, /* vsync & hsync pos, disp on */
- {0, 0}
-};
-
-/*
- * Return a pointer to the register initialization table.
- */
-const SMI_REGS *board_get_regs(void)
-{
- return sm502_init_regs;
-}
-
-int board_get_width(void)
-{
- return DISPLAY_WIDTH;
-}
-
-int board_get_height(void)
-{
- return DISPLAY_HEIGHT;
-}
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str(int line_number, char *info)
-{
- if (line_number == 1)
- strcpy(info, " Board: ICON");
- else
- info[0] = '\0';
-}
-#endif
-
-#endif /* CONFIG_VIDEO_SM501 */
+++ /dev/null
-/*
- * (C) Copyright 2009-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- */
-
- .section .bootpg,"ax"
-
- .globl tlbtab
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
- * use the speed up boot process. It is patched after relocation to
- * enable SA_I.
- */
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
- 4, AC_RWX | SA_G) /* TLB 0 */
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4,
- AC_RWX | SA_I)
-
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4,
- AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K,
- CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H,
- AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD,
- AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD,
- AC_RW | SA_IG)
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <video_fb.h>
-#include "common_util.h"
-#include <asm/processor.h>
-#include <asm/byteorder.h>
-#include <i2c.h>
-#include <pci.h>
-#include <malloc.h>
-#include <bzlib.h>
-#include <video.h>
-
-#ifdef CONFIG_PIP405
-#include "../pip405/pip405.h"
-#include <asm/4xx_pci.h>
-#endif
-#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
-#include "../mip405/mip405.h"
-#include <asm/4xx_pci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int mem_test(ulong start, ulong ramsize, int quiet);
-
-#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
-#define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN /* ugly, but it works for now */
-
-#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
- || defined(CONFIG_TARGET_MIP405T)
-/*-----------------------------------------------------------------------
- * On PIP/MIP405 we have 3 (4) possible boot mode
- *
- * - Boot from Flash (Flash CS = CS0, MPS CS = CS1)
- * - Boot from MPS (Flash CS = CS1, MPS CS = CS0)
- * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1)
- * - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0)
- * The flash init is the first board specific routine which is called
- * after code relocation (running from SDRAM)
- * The first thing we do is to map the Flash CS to the Flash area and
- * the MPS CS to the MPS area. Since the flash size is unknown at this
- * point, we use the max flash size and the lowest flash address as base.
- *
- * After flash detection we adjust the size of the CS area accordingly.
- * update_flash_size() will fix in wrong values in the flash_info structure,
- * misc_init_r() will fix the values in the board info structure
- */
-int get_boot_mode(void)
-{
- unsigned long pbcr;
- int res = 0;
- pbcr = mfdcr(CPC0_PSR);
- if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
- /* boot via MPS or MPS mapping */
- res = BOOT_MPS;
- if (pbcr & PSR_ROM_LOC)
- /* boot via PCI.. */
- res |= BOOT_PCI;
- return res;
-}
-
-/* Map the flash high (in boot area)
- This code can only be executed from SDRAM (after relocation).
-*/
-void setup_cs_reloc(void)
-{
- int mode;
- /*
- * since we are relocated, we can set-up the CS finaly
- * but first of all, switch off PCI mapping (in case it
- * was a PCI boot)
- */
- out32r(PMM0MA, 0L);
- /* get boot mode */
- mode = get_boot_mode();
- /*
- * we map the flash high in every case
- * first find out to which CS the flash is attached to
- */
- if (mode & BOOT_MPS) {
- /* map flash high on CS1 and MPS on CS0 */
- mtdcr(EBC0_CFGADDR, PB0AP);
- mtdcr(EBC0_CFGDATA, MPS_AP);
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, MPS_CR);
- /*
- * we use the default values (max values) for the flash
- * because its real size is not yet known
- */
- mtdcr(EBC0_CFGADDR, PB1AP);
- mtdcr(EBC0_CFGDATA, FLASH_AP);
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, FLASH_CR_B);
- } else {
- /* map flash high on CS0 and MPS on CS1 */
- mtdcr(EBC0_CFGADDR, PB1AP);
- mtdcr(EBC0_CFGDATA, MPS_AP);
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, MPS_CR);
- /*
- * we use the default values (max values) for the flash
- * because its real size is not yet known
- */
- mtdcr(EBC0_CFGADDR, PB0AP);
- mtdcr(EBC0_CFGDATA, FLASH_AP);
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, FLASH_CR_B);
- }
-}
-#endif /* #if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) */
-
-#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
-/* adjust flash start and protection info */
-int update_flash_size(int flash_size)
-{
- int i = 0, mode;
- flash_info_t *info = &flash_info[0];
- unsigned long flashcr;
- unsigned long flash_base = (0 - flash_size) & 0xFFF00000;
-
- if (flash_size > 128*1024*1024) {
- printf("\n ### ERROR, wrong flash size: %X, reset board ###\n",
- flash_size);
- hang();
- }
-
- if ((flash_size >> 20) != 0)
- i = __ilog2(flash_size >> 20);
-
- /* set up flash CS according to the size */
- mode = get_boot_mode();
- if (mode & BOOT_MPS) {
- /* flash is on CS1 */
- mtdcr(EBC0_CFGADDR, PB1CR);
- flashcr = mfdcr(EBC0_CFGDATA);
- /* we map the flash high in every case */
- flashcr &= 0x0001FFFF; /* mask out address bits */
- flashcr |= flash_base; /* start addr */
- flashcr |= (i << 17); /* size addr */
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, flashcr);
- } else {
- /* flash is on CS0 */
- mtdcr(EBC0_CFGADDR, PB0CR);
- flashcr = mfdcr(EBC0_CFGDATA);
- /* we map the flash high in every case */
- flashcr &= 0x0001FFFF; /* mask out address bits */
- flashcr |= flash_base; /* start addr */
- flashcr |= (i << 17); /* size addr */
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, flashcr);
- }
-
- for (i = 0; i < info->sector_count; i++)
- /* adjust sector start address */
- info->start[i] = flash_base +
- (info->start[i] - CONFIG_SYS_FLASH_BASE);
-
- /* unprotect all sectors */
- flash_protect(FLAG_PROTECT_CLEAR,
- info->start[0],
- 0xFFFFFFFF,
- info);
- flash_protect_default();
- /* protect reset vector too*/
- flash_protect(FLAG_PROTECT_SET,
- info->start[info->sector_count-1],
- 0xFFFFFFFF,
- info);
-
- return 0;
-}
-#endif
-
-static int
-mpl_prg(uchar *src, ulong size)
-{
- ulong start;
- flash_info_t *info = &flash_info[0];
- int i, rc;
-#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) || \
- defined(CONFIG_TARGET_MIP405T)
- char *copystr = (char *)src;
- ulong *magic = (ulong *)src;
-
- if (uimage_to_cpu (magic[0]) != IH_MAGIC) {
- puts("Bad Magic number\n");
- return -1;
- }
- /* some more checks before we delete the Flash... */
- /* Checking the ISO_STRING prevents to program a
- * wrong Firmware Image into the flash.
- */
- i = 4; /* skip Magic number */
- while (1) {
- if (strncmp(©str[i], "MEV-", 4) == 0)
- break;
- if (i++ >= 0x100) {
- puts("Firmware Image for unknown Target\n");
- return -1;
- }
- }
- /* we have the ISO STRING, check */
- if (strncmp(©str[i], CONFIG_ISO_STRING, sizeof(CONFIG_ISO_STRING)-1) != 0) {
- printf("Wrong Firmware Image: %s\n", ©str[i]);
- return -1;
- }
- start = 0 - size;
-
- /* unprotect sectors used by u-boot */
- flash_protect(FLAG_PROTECT_CLEAR,
- start,
- 0xFFFFFFFF,
- info);
-
- /* search start sector */
- for (i = info->sector_count-1; i > 0; i--)
- if (start >= info->start[i])
- break;
-
- /* now erase flash */
- printf("Erasing at %lx (sector %d) (start %lx)\n",
- start,i,info->start[i]);
- if ((rc = flash_erase (info, i, info->sector_count-1)) != 0) {
- puts("ERROR ");
- flash_perror(rc);
- return (1);
- }
-#endif
- printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
- (ulong)src, size);
- if ((rc = flash_write ((char *)src, start, size)) != 0) {
- puts("ERROR ");
- flash_perror(rc);
- return (1);
- }
- puts("OK programming done\n");
- return 0;
-}
-
-
-static int
-mpl_prg_image(uchar *ld_addr)
-{
- unsigned long len;
- uchar *data;
- image_header_t *hdr = (image_header_t *)ld_addr;
- int rc;
-
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- if (!image_check_magic (hdr)) {
- puts("Bad Magic Number\n");
- return 1;
- }
- image_print_contents (hdr);
- if (!image_check_os (hdr, IH_OS_U_BOOT)) {
- puts("No U-Boot Image\n");
- return 1;
- }
- if (!image_check_type (hdr, IH_TYPE_FIRMWARE)) {
- puts("No Firmware Image\n");
- return 1;
- }
- if (!image_check_hcrc (hdr)) {
- puts("Bad Header Checksum\n");
- return 1;
- }
- puts("Verifying Checksum ... ");
- if (!image_check_dcrc (hdr)) {
- puts("Bad Data CRC\n");
- return 1;
- }
- puts("OK\n");
-
- data = (uchar *)image_get_data (hdr);
- len = image_get_data_size (hdr);
-
- if (image_get_comp (hdr) != IH_COMP_NONE) {
- uchar *buf;
- /* reserve space for uncompressed image */
- if ((buf = malloc(IMAGE_SIZE)) == NULL) {
- puts("Insufficient space for decompression\n");
- return 1;
- }
-
- switch (image_get_comp (hdr)) {
- case IH_COMP_GZIP:
- puts("Uncompressing (GZIP) ... ");
- rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len);
- if (rc != 0) {
- puts("GUNZIP ERROR\n");
- free(buf);
- return 1;
- }
- puts("OK\n");
- break;
-#ifdef CONFIG_BZIP2
- case IH_COMP_BZIP2:
- puts("Uncompressing (BZIP2) ... ");
- {
- uint retlen = IMAGE_SIZE;
- rc = BZ2_bzBuffToBuffDecompress ((char *)(buf), &retlen,
- (char *)data, len, 0, 0);
- len = retlen;
- }
- if (rc != BZ_OK) {
- printf ("BUNZIP2 ERROR: %d\n", rc);
- free(buf);
- return 1;
- }
- puts("OK\n");
- break;
-#endif
- default:
- printf ("Unimplemented compression type %d\n",
- image_get_comp (hdr));
- free(buf);
- return 1;
- }
-
- rc = mpl_prg(buf, len);
- free(buf);
- } else {
- rc = mpl_prg(data, len);
- }
-
- return(rc);
-}
-
-void get_backup_values(backup_t *buf)
-{
- i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t));
-}
-
-void set_backup_values(int overwrite)
-{
- backup_t back;
- int i;
-
- get_backup_values(&back);
- if(!overwrite) {
- if(strncmp(back.signature,"MPL\0",4)==0) {
- puts("Not possible to write Backup\n");
- return;
- }
- }
- memcpy(back.signature,"MPL\0",4);
- i = getenv_f("serial#",back.serial_name,16);
- if(i < 0) {
- puts("Not possible to write Backup\n");
- return;
- }
- back.serial_name[16]=0;
- i = getenv_f("ethaddr",back.eth_addr,20);
- if(i < 0) {
- puts("Not possible to write Backup\n");
- return;
- }
- back.eth_addr[20]=0;
- i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
-}
-
-void clear_env_values(void)
-{
- backup_t back;
- unsigned char env_crc[4];
-
- memset(&back,0xff,sizeof(backup_t));
- memset(env_crc,0x00,4);
- i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
- i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,CONFIG_ENV_OFFSET,2,(void *)env_crc,4);
-}
-
-/*
- * check crc of "older" environment
- */
-int check_env_old_size(ulong oldsize)
-{
- ulong crc, len, new;
- unsigned off;
- uchar buf[64];
-
- /* read old CRC */
- eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR,
- CONFIG_ENV_OFFSET,
- (uchar *)&crc, sizeof(ulong));
-
- new = 0;
- len = oldsize;
- off = sizeof(long);
- len = oldsize-off;
- while (len > 0) {
- int n = (len > sizeof(buf)) ? sizeof(buf) : len;
-
- eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, buf, n);
- new = crc32 (new, buf, n);
- len -= n;
- off += n;
- }
-
- return (crc == new);
-}
-
-static ulong oldsizes[] = {
- 0x200,
- 0x800,
- 0
-};
-
-void copy_old_env(ulong size)
-{
- uchar name_buf[64];
- uchar value_buf[0x800];
- uchar c;
- ulong len;
- unsigned off;
- uchar *name, *value;
-
- name = &name_buf[0];
- value = &value_buf[0];
- len=size;
- off = sizeof(long);
- while (len > off) {
- eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
- if(c != '=') {
- *name++=c;
- off++;
- }
- else {
- *name++='\0';
- off++;
- do {
- eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
- *value++=c;
- off++;
- if(c == '\0')
- break;
- } while(len > off);
- name = &name_buf[0];
- value = &value_buf[0];
- if(strncmp((char *)name,"baudrate",8)!=0) {
- setenv((char *)name,(char *)value);
- }
-
- }
- }
-}
-
-
-void check_env(void)
-{
- char *s;
- int i=0;
- char buf[32];
- backup_t back;
-
- s=getenv("serial#");
- if(!s) {
- while(oldsizes[i]) {
- if(check_env_old_size(oldsizes[i]))
- break;
- i++;
- }
- if(!oldsizes[i]) {
- /* no old environment has been found */
- get_backup_values (&back);
- if (strncmp (back.signature, "MPL\0", 4) == 0) {
- sprintf (buf, "%s", back.serial_name);
- setenv ("serial#", buf);
- sprintf (buf, "%s", back.eth_addr);
- setenv ("ethaddr", buf);
- printf ("INFO: serial# and ethaddr recovered, use saveenv\n");
- return;
- }
- }
- else {
- copy_old_env(oldsizes[i]);
- puts("INFO: old environment ajusted, use saveenv\n");
- }
- }
- else {
- /* check if back up is set */
- get_backup_values(&back);
- if(strncmp(back.signature,"MPL\0",4)!=0) {
- set_backup_values(0);
- }
- }
-}
-
-int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong ld_addr;
- int result;
- ulong size = IMAGE_SIZE;
- ulong src = MULTI_PURPOSE_SOCKET_ADDR;
- backup_t back;
-
- if (strcmp(argv[1], "flash") == 0)
- {
-#if defined(CONFIG_CMD_FDC)
- if (strcmp(argv[2], "floppy") == 0) {
- char *local_args[3];
- extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]);
- puts("\nupdating bootloader image from floppy\n");
- local_args[0] = argv[0];
- if(argc==4) {
- local_args[1] = argv[3];
- local_args[2] = NULL;
- ld_addr=simple_strtoul(argv[3], NULL, 16);
- result=do_fdcboot(cmdtp, 0, 2, local_args);
- }
- else {
- local_args[1] = NULL;
- ld_addr=CONFIG_SYS_LOAD_ADDR;
- result=do_fdcboot(cmdtp, 0, 1, local_args);
- }
- result=mpl_prg_image((uchar *)ld_addr);
- return result;
- }
-#endif
- if (strcmp(argv[2], "mem") == 0) {
- if(argc==4) {
- ld_addr=simple_strtoul(argv[3], NULL, 16);
- }
- else {
- ld_addr=load_addr;
- }
- printf ("\nupdating bootloader image from memory at %lX\n",ld_addr);
- result=mpl_prg_image((uchar *)ld_addr);
- return result;
- }
- if (strcmp(argv[2], "mps") == 0) {
- puts("\nupdating bootloader image from MPS\n");
- result=mpl_prg((uchar *)src,size);
- return result;
- }
- }
- if (strcmp(argv[1], "clearenvvalues") == 0)
- {
- if (strcmp(argv[2], "yes") == 0)
- {
- clear_env_values();
- return 0;
- }
- }
- if (strcmp(argv[1], "getback") == 0) {
- get_backup_values(&back);
- back.signature[3]=0;
- back.serial_name[16]=0;
- back.eth_addr[20]=0;
- printf("GetBackUp: signature: %s\n",back.signature);
- printf(" serial#: %s\n",back.serial_name);
- printf(" ethaddr: %s\n",back.eth_addr);
- return 0;
- }
- if (strcmp(argv[1], "setback") == 0) {
- set_backup_values(1);
- return 0;
- }
- return cmd_usage(cmdtp);
-}
-
-#ifdef CONFIG_VIDEO
-/******************************************************
- * Routines to display the Board information
- * to the screen (since the VGA will be initialized as last,
- * we must resend the infos)
- */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-extern GraphicDevice ctfb;
-extern int get_boot_mode(void);
-
-void video_get_info_str (int line_number, char *info)
-{
- /* init video info strings for graphic console */
- PPC4xx_SYS_INFO sys_info;
- char rev;
- int i,boot;
- unsigned long pvr;
- char buf[64];
- char buf1[32], buf2[32], buf3[32], buf4[32];
- char cpustr[16];
- char *s, *e, bc;
- switch (line_number)
- {
- case 2:
- /* CPU and board infos */
- pvr=get_pvr();
- get_sys_info (&sys_info);
- switch (pvr) {
- case PVR_405GP_RB: rev='B'; break;
- case PVR_405GP_RC: rev='C'; break;
- case PVR_405GP_RD: rev='D'; break;
- case PVR_405GP_RE: rev='E'; break;
- case PVR_405GPR_RB: rev='B'; break;
- default: rev='?'; break;
- }
- if(pvr==PVR_405GPR_RB)
- sprintf(cpustr,"PPC405GPr %c",rev);
- else
- sprintf(cpustr,"PPC405GP %c",rev);
- /* Board info */
- i=0;
- s=getenv ("serial#");
-#ifdef CONFIG_PIP405
- if (!s || strncmp (s, "PIP405", 6)) {
- strcpy(buf,"### No HW ID - assuming PIP405");
- }
-#endif
-#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
- if (!s || strncmp (s, "MIP405", 6)) {
- strcpy(buf,"### No HW ID - assuming MIP405");
- }
-#endif
- else {
- for (e = s; *e; ++e) {
- if (*e == ' ')
- break;
- }
- for (; s < e; ++s) {
- if (*s == '_') {
- ++s;
- break;
- }
- buf[i++] = *s;
- }
- strcpy(&buf[i]," SN ");
- i+=4;
- for (; s < e; ++s) {
- buf[i++] = *s;
- }
- buf[i++]=0;
- }
- sprintf (info," %s %s %s MHz (%s/%s/%s MHz)",
- buf, cpustr,
- strmhz (buf1, gd->cpu_clk),
- strmhz (buf2, sys_info.freqPLB),
- strmhz (buf3, sys_info.freqPLB / sys_info.pllOpbDiv),
- strmhz (buf4, sys_info.freqPLB / sys_info.pllExtBusDiv));
- return;
- case 3:
- /* Memory Info */
- boot = get_boot_mode();
- bc = in8 (CONFIG_PORT_ADDR);
- sprintf(info, " %luMB RAM, %luMB Flash Cfg 0x%02X %s %s",
- gd->bd->bi_memsize / 0x100000,
- gd->bd->bi_flashsize / 0x100000,
- bc,
- (boot & BOOT_MPS) ? "MPS boot" : "Flash boot",
- ctfb.modeIdent);
- return;
- case 1:
- strcpy(buf, CONFIG_IDENT_STRING);
- sprintf (info, " %s", &buf[1]);
- return;
- }
- /* no more info lines */
- *info = 0;
- return;
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-
-#endif /* CONFIG_VIDEO */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _COMMON_UTIL_H_
-#define _COMMON_UTIL_H_
-
-typedef struct {
- char signature[4];
- char serial_name[17]; /* "MIP405_1000xxxxx" */
- char eth_addr[21]; /* "00:60:C2:0a:00:00" */
-} backup_t;
-
-extern flash_info_t flash_info[]; /* info for FLASH chips */
-
-void get_backup_values(backup_t *buf);
-
-#define BOOT_MPS 0x01
-#define BOOT_PCI 0x02
-int get_boot_mode(void);
-void setup_cs_reloc(void);
-
-void check_env(void);
-
-#endif /* _COMMON_UTIL_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * TODO: clean-up
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <stdio_dev.h>
-#include "isa.h"
-#include "piix4_pci.h"
-#include "kbd.h"
-#include "video.h"
-
-
-#undef ISA_DEBUG
-
-#ifdef ISA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-#if defined(CONFIG_PIP405)
-
-extern int drv_isa_kbd_init (void);
-
-/* fdc (logical device 0) */
-const SIO_LOGDEV_TABLE sio_fdc[] = {
- {0x60, 3}, /* set IO to FDPort (3F0) */
- {0x61, 0xF0}, /* set IO to FDPort (3F0) */
- {0x70, 06}, /* set IRQ 6 for FDPort */
- {0x74, 02}, /* set DMA 2 for FDPort */
- {0xF0, 0x05}, /* set to PS2 type */
- {0xF1, 0x00}, /* default value */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-/* paralell port (logical device 3) */
-const SIO_LOGDEV_TABLE sio_pport[] = {
- {0x60, 3}, /* set IO to PPort (378) */
- {0x61, 0x78}, /* set IO to PPort (378) */
- {0x70, 07}, /* set IRQ 7 for PPort */
- {0xF1, 00}, /* set PPort to normal */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-/* paralell port (logical device 3) Floppy assigned to lpt */
-const SIO_LOGDEV_TABLE sio_pport_fdc[] = {
- {0x60, 3}, /* set IO to PPort (378) */
- {0x61, 0x78}, /* set IO to PPort (378) */
- {0x70, 07}, /* set IRQ 7 for PPort */
- {0xF1, 02}, /* set PPort to Floppy */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-/* uart 1 (logical device 4) */
-const SIO_LOGDEV_TABLE sio_com1[] = {
- {0x60, 3}, /* set IO to COM1 (3F8) */
- {0x61, 0xF8}, /* set IO to COM1 (3F8) */
- {0x70, 04}, /* set IRQ 4 for COM1 */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-/* uart 2 (logical device 5) */
-const SIO_LOGDEV_TABLE sio_com2[] = {
- {0x60, 2}, /* set IO to COM2 (2F8) */
- {0x61, 0xF8}, /* set IO to COM2 (2F8) */
- {0x70, 03}, /* set IRQ 3 for COM2 */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-
-/* keyboard controller (logical device 7) */
-const SIO_LOGDEV_TABLE sio_keyboard[] = {
- {0x70, 1}, /* set IRQ 1 for keyboard */
- {0x72, 12}, /* set IRQ 12 for mouse */
- {0xF0, 0}, /* disable Port92 (this is a PowerPC!!) */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-
-
-/*******************************************************************************
-* Config SuperIO FDC37C672
-********************************************************************************/
-unsigned char open_cfg_super_IO(int address)
-{
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */
- if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */
- return true;
- else
- return false;
-}
-
-void close_cfg_super_IO(int address)
-{
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */
-}
-
-
-unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr)
-{
- /* assuming config reg is open */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
- return in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1);
-}
-
-void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data)
-{
- /* assuming config reg is open */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */
-}
-
-void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev)
-{
- while (ldt->index != 0xFF) {
- write_cfg_super_IO(SIO_CFG_PORT, ldev, ldt->index, ldt->val);
- ldt++;
- } /* endwhile */
-}
-
-void isa_sio_loadtable(void)
-{
- char *s = getenv("floppy");
- /* setup Floppy device 0*/
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0);
- /* setup parallel port device 3 */
- if(s && !strncmp(s, "lpt", 3)) {
- printf("SIO: Floppy assigned to LPT\n");
- /* floppy is assigned to the LPT */
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport_fdc,3);
- }
- else {
- /*printf("Floppy assigned to internal port\n");*/
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport,3);
- }
- /* setup Com1 port device 4 */
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_com1,4);
- /* setup Com2 port device 5 */
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_com2,5);
- /* setup keyboards device 7 */
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_keyboard,7);
-}
-
-
-void isa_sio_setup(void)
-{
- if (open_cfg_super_IO(SIO_CFG_PORT) == true)
- {
- isa_sio_loadtable();
- close_cfg_super_IO(0x3F0);
- }
-}
-#endif
-
-/******************************************************************************
- * IRQ Controller
- * we use the Vector mode
- */
-
-struct isa_irq_action {
- interrupt_handler_t *handler;
- void *arg;
- int count;
-};
-
-static struct isa_irq_action isa_irqs[16];
-
-
-/*
- * This contains the irq mask for both 8259A irq controllers,
- */
-static unsigned int cached_irq_mask = 0xfff9;
-
-#define cached_imr1 (unsigned char)cached_irq_mask
-#define cached_imr2 (unsigned char)(cached_irq_mask>>8)
-#define IMR_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1
-#define IMR_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1
-#define ICW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1
-#define ICW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1
-#define ICW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2
-#define ICW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2
-#define ICW3_1 ICW2_1
-#define ICW3_2 ICW2_2
-#define ICW4_1 ICW2_1
-#define ICW4_2 ICW2_2
-#define ISR_1 ICW1_1
-#define ISR_2 ICW1_2
-
-
-void disable_8259A_irq(unsigned int irq)
-{
- unsigned int mask = 1 << irq;
-
- cached_irq_mask |= mask;
- if (irq & 8)
- out8(IMR_2,cached_imr2);
- else
- out8(IMR_1,cached_imr1);
-}
-
-void enable_8259A_irq(unsigned int irq)
-{
- unsigned int mask = ~(1 << irq);
-
- cached_irq_mask &= mask;
- if (irq & 8)
- out8(IMR_2,cached_imr2);
- else
- out8(IMR_1,cached_imr1);
-}
-/*
-int i8259A_irq_pending(unsigned int irq)
-{
- unsigned int mask = 1<<irq;
- int ret;
-
- if (irq < 8)
- ret = inb(0x20) & mask;
- else
- ret = inb(0xA0) & (mask >> 8);
- spin_unlock_irqrestore(&i8259A_lock, flags);
-
- return ret;
-}
-*/
-
-/*
- * This function assumes to be called rarely. Switching between
- * 8259A registers is slow.
- */
-int i8259A_irq_real(unsigned int irq)
-{
- int value;
- int irqmask = 1<<irq;
-
- if (irq < 8) {
- out8(ISR_1,0x0B); /* ISR register */
- value = in8(ISR_1) & irqmask;
- out8(ISR_1,0x0A); /* back to the IRR register */
- return value;
- }
- out8(ISR_2,0x0B); /* ISR register */
- value = in8(ISR_2) & (irqmask >> 8);
- out8(ISR_2,0x0A); /* back to the IRR register */
- return value;
-}
-
-/*
- * Careful! The 8259A is a fragile beast, it pretty
- * much _has_ to be done exactly like this (mask it
- * first, _then_ send the EOI, and the order of EOI
- * to the two 8259s is important!
- */
-void mask_and_ack_8259A(unsigned int irq)
-{
- unsigned int irqmask = 1 << irq;
- unsigned int temp_irqmask = cached_irq_mask;
- /*
- * Lightweight spurious IRQ detection. We do not want
- * to overdo spurious IRQ handling - it's usually a sign
- * of hardware problems, so we only do the checks we can
- * do without slowing down good hardware unnecesserily.
- *
- * Note that IRQ7 and IRQ15 (the two spurious IRQs
- * usually resulting from the 8259A-1|2 PICs) occur
- * even if the IRQ is masked in the 8259A. Thus we
- * can check spurious 8259A IRQs without doing the
- * quite slow i8259A_irq_real() call for every IRQ.
- * This does not cover 100% of spurious interrupts,
- * but should be enough to warn the user that there
- * is something bad going on ...
- */
- if (temp_irqmask & irqmask)
- goto spurious_8259A_irq;
- temp_irqmask |= irqmask;
-
-handle_real_irq:
- if (irq & 8) {
- in8(IMR_2); /* DUMMY - (do we need this?) */
- out8(IMR_2,(unsigned char)(temp_irqmask>>8));
- out8(ISR_2,0x60+(irq&7));/* 'Specific EOI' to slave */
- out8(ISR_1,0x62); /* 'Specific EOI' to master-IRQ2 */
- out8(IMR_2,cached_imr2); /* turn it on again */
- } else {
- in8(IMR_1); /* DUMMY - (do we need this?) */
- out8(IMR_1,(unsigned char)temp_irqmask);
- out8(ISR_1,0x60+irq); /* 'Specific EOI' to master */
- out8(IMR_1,cached_imr1); /* turn it on again */
- }
-
- return;
-
-spurious_8259A_irq:
- /*
- * this is the slow path - should happen rarely.
- */
- if (i8259A_irq_real(irq))
- /*
- * oops, the IRQ _is_ in service according to the
- * 8259A - not spurious, go handle it.
- */
- goto handle_real_irq;
-
- {
- static int spurious_irq_mask;
- /*
- * At this point we can be sure the IRQ is spurious,
- * lets ACK and report it. [once per IRQ]
- */
- if (!(spurious_irq_mask & irqmask)) {
- PRINTF("spurious 8259A interrupt: IRQ%d.\n", irq);
- spurious_irq_mask |= irqmask;
- }
- /* irq_err_count++; */
- /*
- * Theoretically we do not have to handle this IRQ,
- * but in Linux this does not cause problems and is
- * simpler for us.
- */
- goto handle_real_irq;
- }
-}
-
-void init_8259A(void)
-{
- out8(IMR_1,0xff); /* mask all of 8259A-1 */
- out8(IMR_2,0xff); /* mask all of 8259A-2 */
-
- out8(ICW1_1,0x11); /* ICW1: select 8259A-1 init */
- out8(ICW2_1,0x20 + 0); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
- out8(ICW3_1,0x04); /* 8259A-1 (the master) has a slave on IR2 */
- out8(ICW4_1,0x01); /* master expects normal EOI */
- out8(ICW1_2,0x11); /* ICW2: select 8259A-2 init */
- out8(ICW2_2,0x20 + 8); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
- out8(ICW3_2,0x02); /* 8259A-2 is a slave on master's IR2 */
- out8(ICW4_2,0x01); /* (slave's support for AEOI in flat mode
- is to be investigated) */
- udelay(10000); /* wait for 8259A to initialize */
- out8(IMR_1,cached_imr1); /* restore master IRQ mask */
- udelay(10000); /* wait for 8259A to initialize */
- out8(IMR_2,cached_imr2); /* restore slave IRQ mask */
-}
-
-
-#define PCI_INT_ACK_ADDR 0xEED00000
-
-int handle_isa_int(void)
-{
- unsigned long irqack;
- unsigned char irq;
- /* first we acknokledge the int via the PCI bus */
- irqack=in32(PCI_INT_ACK_ADDR);
- /* now we get the ISRs */
- in8(ISR_2);
- in8(ISR_1);
- irq=(unsigned char)irqack;
- irq-=32;
-/* if((irq==7)&&((isr1&0x80)==0)) {
- PRINTF("IRQ7 detected but not in ISR\n");
- }
- else {
-*/ /* we should handle cascaded interrupts here also */
- {
-/* printf("ISA Irq %d\n",irq); */
- isa_irqs[irq].count++;
- if(irq!=2) { /* just swallow the cascade irq 2 */
- if (isa_irqs[irq].handler != NULL)
- (*isa_irqs[irq].handler)(isa_irqs[irq].arg); /* call isr */
- else {
- PRINTF ("bogus interrupt vector 0x%x\n", irq);
- }
- }
- }
- /* issue EOI instruction to clear the IRQ */
- mask_and_ack_8259A(irq);
- return 0;
-}
-
-
-/******************************************************************
- * Install and free an ISA interrupt handler.
- */
-
-void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
-{
- if (isa_irqs[vec].handler != NULL) {
- printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
- vec, (uint)handler, (uint)isa_irqs[vec].handler);
- }
- isa_irqs[vec].handler = handler;
- isa_irqs[vec].arg = arg;
- enable_8259A_irq(vec);
- PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask);
-
-}
-
-void isa_irq_free_handler(int vec)
-{
- disable_8259A_irq(vec);
- isa_irqs[vec].handler = NULL;
- isa_irqs[vec].arg = NULL;
- PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
-
-}
-
-/****************************************************************************/
-void isa_init_irq_contr(void)
-{
- int i;
- /* disable all Interrupts */
- /* first write icws controller 1 */
- for(i=0;i<16;i++)
- {
- isa_irqs[i].handler=NULL;
- isa_irqs[i].arg=NULL;
- isa_irqs[i].count=0;
- }
- init_8259A();
- out8(IMR_2,0xFF);
-}
-/*************************************************************************/
-
-void isa_show_irq(void)
-{
- int vec;
-
- printf ("\nISA Interrupt-Information:\n");
- printf ("Nr Routine Arg Count\n");
-
- for (vec=0; vec<16; vec++) {
- if (isa_irqs[vec].handler != NULL) {
- printf ("%02d %08lx %08lx %d\n",
- vec,
- (ulong)isa_irqs[vec].handler,
- (ulong)isa_irqs[vec].arg,
- isa_irqs[vec].count);
- }
- }
-}
-
-int isa_irq_get_count(int vec)
-{
- return(isa_irqs[vec].count);
-}
-
-/******************************************************************
- * Init the ISA bus and devices.
- */
-
-#if defined(CONFIG_PIP405)
-
-int isa_init(void)
-{
- isa_sio_setup();
- isa_init_irq_contr();
- drv_isa_kbd_init();
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ISA_H_
-#define _ISA_H_
-/* Super IO */
-#define SIO_CFG_PORT 0x3F0 /* Config Port Address */
-
-#if defined(CONFIG_PIP405)
-/* table fore SIO initialization */
-typedef struct {
- const uchar index;
- const uchar val;
-} SIO_LOGDEV_TABLE;
-
-typedef struct {
- const uchar ldev;
- const SIO_LOGDEV_TABLE *ldev_table;
-} SIO_TABLE;
-
-
-unsigned char open_cfg_super_IO(int address);
-unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr);
-void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data);
-void close_cfg_super_IO(int address);
-void isa_sio_setup(void);
-#endif
-
-void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg);
-void isa_irq_free_handler(int vec);
-int handle_isa_int(void);
-void isa_init_irq_contr(void);
-void isa_show_irq(void);
-int isa_irq_get_count(int vec);
-
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Source partly derived from:
- * linux/drivers/char/pc_keyb.c
- */
-#include <common.h>
-#include <console.h>
-#include <asm/processor.h>
-#include <stdio_dev.h>
-#include "isa.h"
-#include "kbd.h"
-
-
-unsigned char kbd_read_status(void);
-unsigned char kbd_read_input(void);
-void kbd_send_data(unsigned char data);
-void disable_8259A_irq(unsigned int irq);
-void enable_8259A_irq(unsigned int irq);
-
-/* used only by send_data - set by keyboard_interrupt */
-
-
-#undef KBG_DEBUG
-
-#ifdef KBG_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-#define KBD_STAT_KOBF 0x01
-#define KBD_STAT_IBF 0x02
-#define KBD_STAT_SYS 0x04
-#define KBD_STAT_CD 0x08
-#define KBD_STAT_LOCK 0x10
-#define KBD_STAT_MOBF 0x20
-#define KBD_STAT_TI_OUT 0x40
-#define KBD_STAT_PARERR 0x80
-
-#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */
-#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */
-#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */
-/*
- * Keyboard Controller Commands
- */
-
-#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
-#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
-#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
-#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
-#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
-#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
-#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
-#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
-#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
-#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
-#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
- initiated by the auxiliary device */
-#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
-
-/*
- * Keyboard Commands
- */
-
-#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
-#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
-#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
-#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
-#define KBD_CMD_RESET 0xFF /* Reset */
-
-/*
- * Keyboard Replies
- */
-
-#define KBD_REPLY_POR 0xAA /* Power on reset */
-#define KBD_REPLY_ACK 0xFA /* Command ACK */
-#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
-
-/*
- * Status Register Bits
- */
-
-#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
-#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
-#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
-#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
-#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
-#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
-#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
-#define KBD_STAT_PERR 0x80 /* Parity error */
-
-#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
-
-/*
- * Controller Mode Register Bits
- */
-
-#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
-#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
-#define KBD_MODE_SYS 0x04 /* The system flag (?) */
-#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
-#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
-#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
-#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
-#define KBD_MODE_RFU 0x80
-
-
-#define KDB_DATA_PORT 0x60
-#define KDB_COMMAND_PORT 0x64
-
-#define LED_SCR 0x01 /* scroll lock led */
-#define LED_CAP 0x04 /* caps lock led */
-#define LED_NUM 0x02 /* num lock led */
-
-#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
-
-
-static volatile char kbd_buffer[KBD_BUFFER_LEN];
-static volatile int in_pointer = 0;
-static volatile int out_pointer = 0;
-
-
-static unsigned char num_lock = 0;
-static unsigned char caps_lock = 0;
-static unsigned char scroll_lock = 0;
-static unsigned char shift = 0;
-static unsigned char ctrl = 0;
-static unsigned char alt = 0;
-static unsigned char e0 = 0;
-static unsigned char leds = 0;
-
-#define DEVNAME "kbd"
-
-/* Simple translation table for the keys */
-
-static unsigned char kbd_plain_xlate[] = {
- 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */
- 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */
- 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
- '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
- '\r',0xff,0xff
- };
-
-static unsigned char kbd_shift_xlate[] = {
- 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */
- 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */
- 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */
- 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
- '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
- '\r',0xff,0xff
- };
-
-static unsigned char kbd_ctrl_xlate[] = {
- 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */
- 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */
- 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */
- 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
- '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
- '\r',0xff,0xff
- };
-
-/******************************************************************
- * Init
- ******************************************************************/
-int isa_kbd_init(void)
-{
- char* result;
- result=kbd_initialize();
- if(result==NULL) {
- PRINTF("AT Keyboard initialized\n");
- irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL);
- isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
- return (1);
- } else {
- printf("%s\n",result);
- return (-1);
- }
-}
-
-#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-extern int overwrite_console (void);
-#else
-int overwrite_console (void)
-{
- return (0);
-}
-#endif
-
-int drv_isa_kbd_init (void)
-{
- int error;
- struct stdio_dev kbddev ;
- char *stdinname = getenv ("stdin");
-
- if(isa_kbd_init()==-1)
- return -1;
- memset (&kbddev, 0, sizeof(kbddev));
- strcpy(kbddev.name, DEVNAME);
- kbddev.flags = DEV_FLAGS_INPUT;
- kbddev.getc = kbd_getc ;
- kbddev.tstc = kbd_testc ;
-
- error = stdio_register (&kbddev);
- if(error==0) {
- /* check if this is the standard input device */
- if(strcmp(stdinname,DEVNAME)==0) {
- /* reassign the console */
- if(overwrite_console()) {
- return 1;
- }
- error=console_assign(stdin,DEVNAME);
- if(error==0)
- return 1;
- else
- return error;
- }
- return 1;
- }
- return error;
-}
-
-/******************************************************************
- * Queue handling
- ******************************************************************/
-/* puts character in the queue and sets up the in and out pointer */
-void kbd_put_queue(char data)
-{
- if((in_pointer+1)==KBD_BUFFER_LEN) {
- if(out_pointer==0) {
- return; /* buffer full */
- } else{
- in_pointer=0;
- }
- } else {
- if((in_pointer+1)==out_pointer)
- return; /* buffer full */
- in_pointer++;
- }
- kbd_buffer[in_pointer]=data;
- return;
-}
-
-/* test if a character is in the queue */
-int kbd_testc(struct stdio_dev *dev)
-{
- if(in_pointer==out_pointer)
- return(0); /* no data */
- else
- return(1);
-}
-/* gets the character from the queue */
-int kbd_getc(struct stdio_dev *dev)
-{
- char c;
- while(in_pointer==out_pointer);
- if((out_pointer+1)==KBD_BUFFER_LEN)
- out_pointer=0;
- else
- out_pointer++;
- c=kbd_buffer[out_pointer];
- return (int)c;
-
-}
-
-
-/* set LEDs */
-
-void kbd_set_leds(void)
-{
- if(caps_lock==0)
- leds&=~LED_CAP; /* switch caps_lock off */
- else
- leds|=LED_CAP; /* switch on LED */
- if(num_lock==0)
- leds&=~LED_NUM; /* switch LED off */
- else
- leds|=LED_NUM; /* switch on LED */
- if(scroll_lock==0)
- leds&=~LED_SCR; /* switch LED off */
- else
- leds|=LED_SCR; /* switch on LED */
- kbd_send_data(KBD_CMD_SET_LEDS);
- kbd_send_data(leds);
-}
-
-
-void handle_keyboard_event (unsigned char scancode)
-{
- unsigned char keycode;
-
- /* Convert scancode to keycode */
- PRINTF ("scancode %x\n", scancode);
- if (scancode == 0xe0) {
- e0 = 1; /* special charakters */
- return;
- }
- if (e0 == 1) {
- e0 = 0; /* delete flag */
- if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */
- ((scancode & 0x7F) == 0x1D) || /* the right alt key */
- ((scancode & 0x7F) == 0x35) || /* the right '/' key */
- ((scancode & 0x7F) == 0x1C)))
- /* the right enter key */
- /* we swallow unknown e0 codes */
- return;
- }
- /* special cntrl keys */
- switch (scancode) {
- case 0x2A:
- case 0x36: /* shift pressed */
- shift = 1;
- return; /* do nothing else */
- case 0xAA:
- case 0xB6: /* shift released */
- shift = 0;
- return; /* do nothing else */
- case 0x38: /* alt pressed */
- alt = 1;
- return; /* do nothing else */
- case 0xB8: /* alt released */
- alt = 0;
- return; /* do nothing else */
- case 0x1d: /* ctrl pressed */
- ctrl = 1;
- return; /* do nothing else */
- case 0x9d: /* ctrl released */
- ctrl = 0;
- return; /* do nothing else */
- case 0x46: /* scrollock pressed */
- scroll_lock = ~scroll_lock;
- kbd_set_leds ();
- return; /* do nothing else */
- case 0x3A: /* capslock pressed */
- caps_lock = ~caps_lock;
- kbd_set_leds ();
- return;
- case 0x45: /* numlock pressed */
- num_lock = ~num_lock;
- kbd_set_leds ();
- return;
- case 0xC6: /* scroll lock released */
- case 0xC5: /* num lock released */
- case 0xBA: /* caps lock released */
- return; /* just swallow */
- }
- if ((scancode & 0x80) == 0x80) /* key released */
- return;
- /* now, decide which table we need */
- if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) { /* scancode not in list */
- PRINTF ("unkown scancode %X\n", scancode);
- return; /* swallow it */
- }
- /* setup plain code first */
- keycode = kbd_plain_xlate[scancode];
- if (caps_lock == 1) { /* caps_lock is pressed, overwrite plain code */
- if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
- PRINTF ("unkown caps-locked scancode %X\n", scancode);
- return; /* swallow it */
- }
- keycode = kbd_shift_xlate[scancode];
- if (keycode < 'A') { /* we only want the alphas capital */
- keycode = kbd_plain_xlate[scancode];
- }
- }
- if (shift == 1) { /* shift overwrites caps_lock */
- if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
- PRINTF ("unkown shifted scancode %X\n", scancode);
- return; /* swallow it */
- }
- keycode = kbd_shift_xlate[scancode];
- }
- if (ctrl == 1) { /* ctrl overwrites caps_lock and shift */
- if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) { /* scancode not in list */
- PRINTF ("unkown ctrl scancode %X\n", scancode);
- return; /* swallow it */
- }
- keycode = kbd_ctrl_xlate[scancode];
- }
- /* check if valid keycode */
- if (keycode == 0xff) {
- PRINTF ("unkown scancode %X\n", scancode);
- return; /* swallow unknown codes */
- }
-
- kbd_put_queue (keycode);
- PRINTF ("%x\n", keycode);
-}
-
-/*
- * This reads the keyboard status port, and does the
- * appropriate action.
- *
- */
-unsigned char handle_kbd_event(void)
-{
- unsigned char status = kbd_read_status();
- unsigned int work = 10000;
-
- while ((--work > 0) && (status & KBD_STAT_OBF)) {
- unsigned char scancode;
-
- scancode = kbd_read_input();
-
- /* Error bytes must be ignored to make the
- Synaptics touchpads compaq use work */
- /* Ignore error bytes */
- if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
- {
- if (status & KBD_STAT_MOUSE_OBF)
- ; /* not supported: handle_mouse_event(scancode); */
- else
- handle_keyboard_event(scancode);
- }
- status = kbd_read_status();
- }
- if (!work)
- PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
- return status;
-}
-
-
-/******************************************************************************
- * Lowlevel Part of keyboard section
- */
-unsigned char kbd_read_status(void)
-{
- return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
-}
-
-unsigned char kbd_read_input(void)
-{
- return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
-}
-
-void kbd_write_command(unsigned char cmd)
-{
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
-}
-
-void kbd_write_output(unsigned char data)
-{
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
-}
-
-int kbd_read_data(void)
-{
- int val;
- unsigned char status;
-
- val = -1;
- status = kbd_read_status();
- if (status & KBD_STAT_OBF) {
- val = kbd_read_input();
- if (status & (KBD_STAT_GTO | KBD_STAT_PERR))
- val = -2;
- }
- return val;
-}
-
-int kbd_wait_for_input(void)
-{
- unsigned long timeout;
- int val;
-
- timeout = KBD_TIMEOUT;
- val=kbd_read_data();
- while(val < 0)
- {
- if(timeout--==0)
- return -1;
- udelay(1000);
- val=kbd_read_data();
- }
- return val;
-}
-
-
-int kb_wait(void)
-{
- unsigned long timeout = KBC_TIMEOUT * 10;
-
- do {
- unsigned char status = handle_kbd_event();
- if (!(status & KBD_STAT_IBF))
- return 0; /* ok */
- udelay(1000);
- timeout--;
- } while (timeout);
- return 1;
-}
-
-void kbd_write_command_w(int data)
-{
- if(kb_wait())
- PRINTF("timeout in kbd_write_command_w\n");
- kbd_write_command(data);
-}
-
-void kbd_write_output_w(int data)
-{
- if(kb_wait())
- PRINTF("timeout in kbd_write_output_w\n");
- kbd_write_output(data);
-}
-
-void kbd_send_data(unsigned char data)
-{
- unsigned char status;
- disable_8259A_irq(1); /* disable interrupt */
- kbd_write_output_w(data);
- status = kbd_wait_for_input();
- if (status == KBD_REPLY_ACK)
- enable_8259A_irq(1); /* enable interrupt */
-}
-
-
-char * kbd_initialize(void)
-{
- int status;
-
- in_pointer = 0; /* delete in Buffer */
- out_pointer = 0;
- /*
- * Test the keyboard interface.
- * This seems to be the only way to get it going.
- * If the test is successful a x55 is placed in the input buffer.
- */
- kbd_write_command_w(KBD_CCMD_SELF_TEST);
- if (kbd_wait_for_input() != 0x55)
- return "Kbd: failed self test";
- /*
- * Perform a keyboard interface test. This causes the controller
- * to test the keyboard clock and data lines. The results of the
- * test are placed in the input buffer.
- */
- kbd_write_command_w(KBD_CCMD_KBD_TEST);
- if (kbd_wait_for_input() != 0x00)
- return "Kbd: interface failed self test";
- /*
- * Enable the keyboard by allowing the keyboard clock to run.
- */
- kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
- status = kbd_wait_for_input();
- /*
- * Reset keyboard. If the read times out
- * then the assumption is that no keyboard is
- * plugged into the machine.
- * This defaults the keyboard to scan-code set 2.
- *
- * Set up to try again if the keyboard asks for RESEND.
- */
- do {
- kbd_write_output_w(KBD_CMD_RESET);
- status = kbd_wait_for_input();
- if (status == KBD_REPLY_ACK)
- break;
- if (status != KBD_REPLY_RESEND) {
- PRINTF("status: %X\n",status);
- return "Kbd: reset failed, no ACK";
- }
- } while (1);
- if (kbd_wait_for_input() != KBD_REPLY_POR)
- return "Kbd: reset failed, no POR";
-
- /*
- * Set keyboard controller mode. During this, the keyboard should be
- * in the disabled state.
- *
- * Set up to try again if the keyboard asks for RESEND.
- */
- do {
- kbd_write_output_w(KBD_CMD_DISABLE);
- status = kbd_wait_for_input();
- if (status == KBD_REPLY_ACK)
- break;
- if (status != KBD_REPLY_RESEND)
- return "Kbd: disable keyboard: no ACK";
- } while (1);
-
- kbd_write_command_w(KBD_CCMD_WRITE_MODE);
- kbd_write_output_w(KBD_MODE_KBD_INT
- | KBD_MODE_SYS
- | KBD_MODE_DISABLE_MOUSE
- | KBD_MODE_KCC);
-
- /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
- kbd_write_command_w(KBD_CCMD_READ_MODE);
- if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
- /*
- * If the controller does not support conversion,
- * Set the keyboard to scan-code set 1.
- */
- kbd_write_output_w(0xF0);
- kbd_wait_for_input();
- kbd_write_output_w(0x01);
- kbd_wait_for_input();
- }
- kbd_write_output_w(KBD_CMD_ENABLE);
- if (kbd_wait_for_input() != KBD_REPLY_ACK)
- return "Kbd: enable keyboard: no ACK";
-
- /*
- * Finally, set the typematic rate to maximum.
- */
- kbd_write_output_w(KBD_CMD_SET_RATE);
- if (kbd_wait_for_input() != KBD_REPLY_ACK)
- return "Kbd: Set rate: no ACK";
- kbd_write_output_w(0x00);
- if (kbd_wait_for_input() != KBD_REPLY_ACK)
- return "Kbd: Set rate: no ACK";
- return NULL;
-}
-
-void kbd_interrupt(void)
-{
- handle_kbd_event();
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _KBD_H_
-#define _KBD_H_
-
-struct stdio_dev;
-
-int kbd_testc(struct stdio_dev *sdev);
-int kbd_getc(struct stdio_dev *sdev);
-extern void kbd_interrupt(void);
-extern char *kbd_initialize(void);
-
-unsigned char kbd_is_init(void);
-#define KBD_INTERRUPT 1
-#endif
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*
- * Adapted for PIP405 03.07.01
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * TODO: Clean-up
- */
-
-#include <common.h>
-#include <pci.h>
-#include "isa.h"
-
-#ifdef CONFIG_405GP
-#ifdef CONFIG_PCI
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#include "piix4_pci.h"
-#include "pci_parts.h"
-
-void pci_405gp_init(struct pci_controller *hose);
-
-void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *entry)
-{
- struct pci_pip405_config_entry *table;
- int i;
-
- table = (struct pci_pip405_config_entry *)entry->priv[0];
-
- for (i = 0; table[i].width; i++) {
-#ifdef DEBUG
- printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
- table[i].index, table[i].val, table[i].width);
-#endif
-
- switch (table[i].width) {
- case 1:
- pci_hose_write_config_byte(hose, dev,
- table[i].index, table[i].val);
- break;
- case 2:
- pci_hose_write_config_word(hose, dev,
- table[i].index, table[i].val);
- break;
- case 4:
- pci_hose_write_config_dword(hose, dev,
- table[i].index, table[i].val);
- break;
- }
- }
-}
-
-
-static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char int_line = 0xff;
- unsigned char pin;
- /*
- * Write pci interrupt line register
- */
- if (PCI_DEV(dev) == 0) /* Device0 = PPC405 -> skip */
- return;
- pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
- if ((pin == 0) || (pin > 4))
- return;
-
- int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
-#ifdef DEBUG
- printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
- PCI_DEV(dev), dev, int_line, int_line);
-#endif
-}
-
-
-static struct pci_controller hose = {
-config_table: pci_pip405_config_table,
-fixup_irq : pci_pip405_fixup_irq,
-};
-
-
-void pci_init_board(void)
-{
- /*we want the ptrs to RAM not flash (ie don't use init list)*/
- hose.fixup_irq = pci_pip405_fixup_irq;
- hose.config_table = pci_pip405_config_table;
-#ifdef DEBUG
- printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",
- pci_pip405_fixup_irq, pci_pip405_config_table, hose);
-#endif
- pci_405gp_init(&hose);
-}
-
-#endif /* CONFIG_PCI */
-#endif /* CONFIG_405GP */
+++ /dev/null
- /*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _PCI_PARTS_H_
-#define _PCI_PARTS_H_
-
-
-/* Board specific file containing:
- * - PCI Memory Mapping
- * - PCI IO Mapping
- * - PCI Interrupt Mapping
- */
-
-/* PIP405 PCI INT Routing:
- * IRQ0 VECTOR
- * PIXX4 IDSEL = AD16 INTA# 28 (Function 2 USB is INTD# = 31)
- * VGA IDSEL = AD17 INTB# 29
- * SCSI IDSEL = AD18 INTC# 30
- * PC104 IDSEL0 = AD20 INTA# 28
- * PC104 IDSEL1 = AD21 INTB# 29
- * PC104 IDSEL2 = AD22 INTC# 30
- * PC104 IDSEL3 = AD23 INTD# 31
- *
- * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00
- * ^ ^ ^ ^ ^
- * 31 23 15 10 7
- * E = Enabled
- * B = Bussnumber
- * D = Devicenumber (Device0 = AD10)
- * F = Functionnumber
- * R = Registernumber
- *
- * Device = (busdevfunc>>11) + 10
- * Vector = devicenumber % 4 + 28
- *
- */
-#define PCI_HIGHEST_ON_BOARD_ID 19
-/*#define PCI_DEV_NUMBER(x) (((x>>11) & 0x1f) + 10) */
-#define PCI_IRQ_VECTOR(x) ((PCI_DEV(x) + 10) % 4) + 28
-
-
-/* PCI Device List for PIP405 */
-
-/* Mapping:
- * +-------------+------------+------------+--------------------------------+
- * | PCI MemAddr | PCI IOAddr | Local Addr | Device / Function |
- * +-------------+------------+------------+--------------------------------+
- * | 0x00000000 | | 0xA0000000 | ISA Memory (hard wired) |
- * | 0x00FFFFFF | | 0xA0FFFFFF | |
- * +-------------+------------+------------+--------------------------------+
- * | | 0x00000000 | 0xE8000000 | ISA IO (hard wired) |
- * | | 0x0000FFFF | 0xE800FFFF | |
- * +-------------+------------+------------+--------------------------------+
- * | 0x80000000 | | 0x80000000 | VGA Controller Memory |
- * | 0x80FFFFFF | | 0x80FFFFFF | |
- * +-------------+------------+------------+--------------------------------+
- * | 0x81000000 | | 0x81000000 | SCSI Controller Memory |
- * | 0x81FFFFFF | | 0x81FFFFFF | |
- * +-------------+------------+------------+--------------------------------+
- */
-
-struct pci_pip405_config_entry {
- int index; /* address */
- unsigned long val; /* value */
- int width; /* data size */
-};
-
-extern void pci_pip405_write_regs(struct pci_controller *,
- pci_dev_t,
- struct pci_config_table *);
-
-/* PIIX4 ISA Bridge Function 0 */
-static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
- {PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */
- {PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */
- {PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */
- {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */
- {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */
-#if defined(CONFIG_PIP405)
- {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */
- {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */
-#endif
- {PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */
- { } /* end of device table */
-};
-
-/* PIIX4 IDE Controller Function 1 */
-static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
- {PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */
- {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
-#if !defined(CONFIG_TARGET_MIP405T)
- {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
-#else
- {PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */
-#endif
- { } /* end of device table */
-};
-
-/* PIIX4 USB Controller Function 2 */
-static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
-#if !defined(CONFIG_TARGET_MIP405T)
- {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */
- {PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */
- {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */
- {0xC0, 0x2000, 2}, /* Legacy support */
- {PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */
-#endif
- { } /* end of device table */
-};
-
-/* PIIX4 Power Management Function 3 */
-static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
- {PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */
- {PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */
- {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */
- {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
- { } /* end of device table */
-};
-/* PPC405 Dummy only used to prevent autosetup on this host bridge */
-static struct pci_pip405_config_entry ppc405_dummy[] = {
- { } /* end of device table */
-};
-
-void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *entry);
-
-
-static struct pci_config_table pci_pip405_config_table[]={
- {PCI_VENDOR_ID_IBM, /* 405 dummy */
- PCI_DEVICE_ID_IBM_405GP,
- PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, 0,
- pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
-
- {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */
- PCI_DEVICE_ID_INTEL_82371AB_0,
- PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, 0,
- pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}},
-
- {PCI_VENDOR_ID_INTEL, /* PIIX4 IDE Controller Function 1 */
- PCI_DEVICE_ID_INTEL_82371AB,
- PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, 1,
- pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}},
-
- {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 2 */
- PCI_DEVICE_ID_INTEL_82371AB_2,
- PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, 2,
- pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}},
-
- {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 3 */
- PCI_DEVICE_ID_INTEL_82371AB_3,
- PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, 3,
- pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}},
-
- {PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_CLASS_DISPLAY_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- pci_405gp_setup_vga},
-
- {PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_CLASS_NOT_DEFINED_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- pci_405gp_setup_vga},
-
- { }
-};
-#endif /* _PCI_PARTS_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#ifndef _PIIX4_PCI_H
-#define _PIIX4_PCI_H
-
-/***************************************************************************
-* Defines PIIX4 Config Registers
-****************************************************************************/
-
-/* Function 0 ISA Bridge */
-#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */
-#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */
-#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/
-#define PCI_CFG_PIIX4_SERIRQ 0x64
-#define PCI_CFG_PIIX4_TOM 0x69
-#define PCI_CFG_PIIX4_MSTAT 0x6A
-#define PCI_CFG_PIIX4_MBDMA 0x76
-#define PCI_CFG_PIIX4_APICBS 0x80
-#define PCI_CFG_PIIX4_DLC 0x82
-#define PCI_CFG_PIIX4_PDMACFG 0x90
-#define PCI_CFG_PIIX4_DDMABS 0x92
-#define PCI_CFG_PIIX4_GENCFG 0xB0
-#define PCI_CFG_PIIX4_RTCCFG 0xCB
-
-/* IO Addresses */
-#define PIIX4_ISA_DMA1_CH0BA 0x00
-#define PIIX4_ISA_DMA1_CH0CA 0x01
-#define PIIX4_ISA_DMA1_CH1BA 0x02
-#define PIIX4_ISA_DMA1_CH1CA 0x03
-#define PIIX4_ISA_DMA1_CH2BA 0x04
-#define PIIX4_ISA_DMA1_CH2CA 0x05
-#define PIIX4_ISA_DMA1_CH3BA 0x06
-#define PIIX4_ISA_DMA1_CH3CA 0x07
-#define PIIX4_ISA_DMA1_CMDST 0x08
-#define PIIX4_ISA_DMA1_REQ 0x09
-#define PIIX4_ISA_DMA1_WSBM 0x0A
-#define PIIX4_ISA_DMA1_CH_MOD 0x0B
-#define PIIX4_ISA_DMA1_CLR_PT 0x0C
-#define PIIX4_ISA_DMA1_M_CLR 0x0D
-#define PIIX4_ISA_DMA1_CLR_M 0x0E
-#define PIIX4_ISA_DMA1_RWAMB 0x0F
-
-#define PIIX4_ISA_DMA2_CH0BA 0xC0
-#define PIIX4_ISA_DMA2_CH0CA 0xC1
-#define PIIX4_ISA_DMA2_CH1BA 0xC2
-#define PIIX4_ISA_DMA2_CH1CA 0xC3
-#define PIIX4_ISA_DMA2_CH2BA 0xC4
-#define PIIX4_ISA_DMA2_CH2CA 0xC5
-#define PIIX4_ISA_DMA2_CH3BA 0xC6
-#define PIIX4_ISA_DMA2_CH3CA 0xC7
-#define PIIX4_ISA_DMA2_CMDST 0xD0
-#define PIIX4_ISA_DMA2_REQ 0xD2
-#define PIIX4_ISA_DMA2_WSBM 0xD4
-#define PIIX4_ISA_DMA2_CH_MOD 0xD6
-#define PIIX4_ISA_DMA2_CLR_PT 0xD8
-#define PIIX4_ISA_DMA2_M_CLR 0xDA
-#define PIIX4_ISA_DMA2_CLR_M 0xDC
-#define PIIX4_ISA_DMA2_RWAMB 0xDE
-
-#define PIIX4_ISA_INT1_ICW1 0x20
-#define PIIX4_ISA_INT1_OCW2 0x20
-#define PIIX4_ISA_INT1_OCW3 0x20
-#define PIIX4_ISA_INT1_ICW2 0x21
-#define PIIX4_ISA_INT1_ICW3 0x21
-#define PIIX4_ISA_INT1_ICW4 0x21
-#define PIIX4_ISA_INT1_OCW1 0x21
-
-#define PIIX4_ISA_INT1_ELCR 0x4D0
-
-#define PIIX4_ISA_INT2_ICW1 0xA0
-#define PIIX4_ISA_INT2_OCW2 0xA0
-#define PIIX4_ISA_INT2_OCW3 0xA0
-#define PIIX4_ISA_INT2_ICW2 0xA1
-#define PIIX4_ISA_INT2_ICW3 0xA1
-#define PIIX4_ISA_INT2_ICW4 0xA1
-#define PIIX4_ISA_INT2_OCW1 0xA1
-#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */
-
-#define PIIX4_ISA_INT2_ELCR 0x4D1
-
-#define PIIX4_ISA_TMR0_CNT_ST 0x40
-#define PIIX4_ISA_TMR1_CNT_ST 0x41
-#define PIIX4_ISA_TMR2_CNT_ST 0x42
-#define PIIX4_ISA_TMR_TCW 0x43
-
-#define PIIX4_ISA_RST_XBUS 0x60
-
-#define PIIX4_ISA_NMI_CNT_ST 0x61
-#define PIIX4_ISA_NMI_ENABLE 0x70
-
-#define PIIX4_ISA_RTC_INDEX 0x70
-#define PIIX4_ISA_RTC_DATA 0x71
-#define PIIX4_ISA_RTCEXT_IND 0x70
-#define PIIX4_ISA_RTCEXT_DATA 0x71
-
-#define PIIX4_ISA_DMA1_CH2LPG 0x81
-#define PIIX4_ISA_DMA1_CH3LPG 0x82
-#define PIIX4_ISA_DMA1_CH1LPG 0x83
-#define PIIX4_ISA_DMA1_CH0LPG 0x87
-#define PIIX4_ISA_DMA2_CH2LPG 0x89
-#define PIIX4_ISA_DMA2_CH3LPG 0x8A
-#define PIIX4_ISA_DMA2_CH1LPG 0x8B
-#define PIIX4_ISA_DMA2_LPGRFR 0x8F
-
-#define PIIX4_ISA_PORT_92 0x92
-
-#define PIIX4_ISA_APM_CONTRL 0xB2
-#define PIIX4_ISA_APM_STATUS 0xB3
-
-#define PIIX4_ISA_COCPU_ERROR 0xF0
-
-/* Function 1 IDE Controller */
-#define PCI_CFG_PIIX4_BMIBA 0x20
-#define PCI_CFG_PIIX4_IDETIM 0x40
-#define PCI_CFG_PIIX4_SIDETIM 0x44
-#define PCI_CFG_PIIX4_UDMACTL 0x48
-#define PCI_CFG_PIIX4_UDMATIM 0x4A
-
-/* Function 2 USB Controller */
-#define PCI_CFG_PIIX4_SBRNUM 0x60
-#define PCI_CFG_PIIX4_LEGSUP 0xC0
-
-/* Function 3 Power Management */
-#define PCI_CFG_PIIX4_PMBA 0x40
-#define PCI_CFG_PIIX4_CNTA 0x44
-#define PCI_CFG_PIIX4_CNTB 0x48
-#define PCI_CFG_PIIX4_GPICTL 0x4C
-#define PCI_CFG_PIIX4_DEVRESD 0x50
-#define PCI_CFG_PIIX4_DEVACTA 0x54
-#define PCI_CFG_PIIX4_DEVACTB 0x58
-#define PCI_CFG_PIIX4_DEVRESA 0x5C
-#define PCI_CFG_PIIX4_DEVRESB 0x60
-#define PCI_CFG_PIIX4_DEVRESC 0x64
-#define PCI_CFG_PIIX4_DEVRESE 0x68
-#define PCI_CFG_PIIX4_DEVRESF 0x6C
-#define PCI_CFG_PIIX4_DEVRESG 0x70
-#define PCI_CFG_PIIX4_DEVRESH 0x74
-#define PCI_CFG_PIIX4_DEVRESI 0x78
-#define PCI_CFG_PIIX4_PMMISC 0x80
-#define PCI_CFG_PIIX4_SMBBA 0x90
-
-
-#endif
+++ /dev/null
-/*
- * Part of this code has been derived from linux:
- * Universal Host Controller Interface driver for USB (take II).
- *
- * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar)
- * Deti Fliegl, deti@fliegl.de (executive slave) (lead voice)
- * Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader)
- * Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter)
- * (c) 2000 Yggdrasil Computing, Inc. (port of new PCI interface support
- * from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
- * (C) 2000 David Brownell, david-b@pacbell.net (usb-ohci.c)
- *
- * HW-initalization based on material of
- *
- * (C) Copyright 1999 Linus Torvalds
- * (C) Copyright 1999 Johannes Erdfelt
- * (C) Copyright 1999 Randy Dunlap
- * (C) Copyright 1999 Gregory P. Smith
- *
- *
- * Adapted for U-Boot:
- * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/**********************************************************************
- * How it works:
- * -------------
- * The framelist / Transfer descriptor / Queue Heads are similar like
- * in the linux usb_uhci.c.
- *
- * During initialization, the following skeleton is allocated in init_skel:
- *
- * framespecific | common chain
- *
- * framelist[]
- * [ 0 ]-----> TD ---------\
- * [ 1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL
- * ... TD ---------/
- * [1023]-----> TD --------/
- *
- * ^^ ^^ ^^ ^^ ^^
- * 7 TDs for 1 TD for Start of Start of End Chain
- * INT (2-128ms) 1ms-INT CTRL Chain BULK Chain
- *
- *
- * Since this is a bootloader, the isochronous transfer descriptor have been removed.
- *
- * Interrupt Transfers.
- * --------------------
- * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
- * will be inserted after the appropriate (depending the interval setting) skeleton TD.
- * If an interrupt has been detected the dev->irqhandler is called. The status and number
- * of transferred bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
- * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
- * the interrupt TD will be reactivated.
- *
- * Control Transfers
- * -----------------
- * Control Transfers are issued by filling the tmp_td with the appropriate data and connect
- * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued,
- * the programm has to wait for completion. This does not allows asynchronous data transfer.
- *
- * Bulk Transfers
- * --------------
- * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect
- * them to the qh_bulk queue header. Before other control/bulk transfers can be issued,
- * the programm has to wait for completion. This does not allows asynchronous data transfer.
- *
- *
- */
-
-#include <common.h>
-#include <pci.h>
-
-#ifdef CONFIG_USB_UHCI
-
-#include <usb.h>
-#include "usb_uhci.h"
-
-#define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */
-#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */
-
-
-#undef USB_UHCI_DEBUG
-
-#ifdef USB_UHCI_DEBUG
-#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define USB_UHCI_PRINTF(fmt,args...)
-#endif
-
-
-static int irqvec = -1; /* irq vector, if -1 uhci is stopped / reseted */
-unsigned int usb_base_addr; /* base address */
-
-static uhci_td_t td_int[8]; /* Interrupt Transfer descriptors */
-static uhci_qh_t qh_cntrl; /* control Queue Head */
-static uhci_qh_t qh_bulk; /* bulk Queue Head */
-static uhci_qh_t qh_end; /* end Queue Head */
-static uhci_td_t td_last; /* last TD (linked with end chain) */
-
-/* temporary tds */
-static uhci_td_t tmp_td[USB_MAX_TEMP_TD]; /* temporary bulk/control td's */
-static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD]; /* temporary interrupt td's */
-
-static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */
-
-static struct virt_root_hub rh; /* struct for root hub */
-
-/**********************************************************************
- * some forward decleration
- */
-int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len,struct devrequest *setup);
-
-/* fill a td with the approproiate data. Link, status, info and buffer
- * are used by the USB controller itselfes, dev is used to identify the
- * "connected" device
- */
-void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status,
- unsigned long info, unsigned long buffer, unsigned long dev)
-{
- td->link=swap_32(link);
- td->status=swap_32(status);
- td->info=swap_32(info);
- td->buffer=swap_32(buffer);
- td->dev_ptr=dev;
-}
-
-/* fill a qh with the approproiate data. Head and element are used by the USB controller
- * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh.
- * Please note, that after completion of the td chain, the entry element is removed /
- * marked invalid by the USB controller.
- */
-void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element)
-{
- qh->head=swap_32(head);
- qh->element=swap_32(element);
- qh->dev_ptr=0L;
-}
-
-/* get the status of a td->status
- */
-unsigned long usb_uhci_td_stat(unsigned long status)
-{
- unsigned long result=0;
- result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0;
- result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0;
- result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0;
- result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0;
- result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0;
- result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0;
- result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0;
- return result;
-}
-
-/* get the status and the transferred len of a td chain.
- * called from the completion handler
- */
-int usb_get_td_status(uhci_td_t *td,struct usb_device *dev)
-{
- unsigned long temp,info;
- unsigned long stat;
- uhci_td_t *mytd=td;
-
- if(dev->devnum==rh.devnum)
- return 0;
- dev->act_len=0;
- stat=0;
- do {
- temp=swap_32((unsigned long)mytd->status);
- stat=usb_uhci_td_stat(temp);
- info=swap_32((unsigned long)mytd->info);
- if(((info & 0xff)!= USB_PID_SETUP) &&
- (((info >> 21) & 0x7ff)!= 0x7ff) &&
- (temp & 0x7FF)!=0x7ff)
- { /* if not setup and not null data pack */
- dev->act_len+=(temp & 0x7FF) + 1; /* the transferred len is act_len + 1 */
- }
- if(stat) { /* status no ok */
- dev->status=stat;
- return -1;
- }
- temp=swap_32((unsigned long)mytd->link);
- mytd=(uhci_td_t *)(temp & 0xfffffff0);
- }while((temp & 0x1)==0); /* process all TDs */
- dev->status=stat;
- return 0; /* Ok */
-}
-
-
-/*-------------------------------------------------------------------
- * LOW LEVEL STUFF
- * assembles QHs und TDs for control, bulk and iso
- *-------------------------------------------------------------------*/
-
-/* Submits a control message. That is a Setup, Data and Status transfer.
- * Routine does not wait for completion.
- */
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len,struct devrequest *setup)
-{
- unsigned long destination, status;
- int maxsze = usb_maxpacket(dev, pipe);
- unsigned long dataptr;
- int len;
- int pktsze;
- int i=0;
-
- if (!maxsze) {
- USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe);
- return -1;
- }
- if(((pipe>>8)&0x7f)==rh.devnum) {
- /* this is the root hub -> redirect it */
- return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup);
- }
- USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze);
- /* The "pipe" thing contains the destination in bits 8--18 */
- destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */
- /* 3 errors */
- status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
- /* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */
- /* Build the TD for the control request, try forever, 8 bytes of data */
- usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev);
-#if 0
- {
- char *sp=(char *)setup;
- printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe,
- sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]);
- }
-#endif
- dataptr = (unsigned long)buffer;
- len=transfer_len;
-
- /* If direction is "send", change the frame from SETUP (0x2D)
- to OUT (0xE1). Else change it from SETUP to IN (0x69). */
- destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN);
- while (len > 0) {
- /* data stage */
- pktsze = len;
- i++;
- if (pktsze > maxsze)
- pktsze = maxsze;
- destination ^= 1 << TD_TOKEN_TOGGLE; /* toggle DATA0/1 */
- usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */
- tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
-
- dataptr += pktsze;
- len -= pktsze;
- }
-
- /* Build the final TD for control status */
- /* It's only IN if the pipe is out AND we aren't expecting data */
-
- destination &= ~UHCI_PID;
- if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0))
- destination |= USB_PID_IN;
- else
- destination |= USB_PID_OUT;
- destination |= 1 << TD_TOKEN_TOGGLE; /* End in Data1 */
- i++;
- status &=~TD_CTRL_SPD;
- /* no limit on errors on final packet , 0 bytes of data */
- usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev);
- tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); /* queue status td */
- /* usb_show_td(i+1);*/
- USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i);
- /* first mark the control QH element terminated */
- qh_cntrl.element=0xffffffffL;
- /* set qh active */
- qh_cntrl.dev_ptr=(unsigned long)dev;
- /* fill in tmp_td_chain */
- qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]);
- return 0;
-}
-
-/*-------------------------------------------------------------------
- * Prepare TDs for bulk transfers.
- */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len)
-{
- unsigned long destination, status,info;
- unsigned long dataptr;
- int maxsze = usb_maxpacket(dev, pipe);
- int len;
- int i=0;
-
- if(transfer_len < 0) {
- printf("Negative transfer length in submit_bulk\n");
- return -1;
- }
- if (!maxsze)
- return -1;
- /* The "pipe" thing contains the destination in bits 8--18. */
- destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe);
- /* 3 errors */
- status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
- /* ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */
- /* Build the TDs for the bulk request */
- len = transfer_len;
- dataptr = (unsigned long)buffer;
- do {
- int pktsze = len;
- if (pktsze > maxsze)
- pktsze = maxsze;
- /* pktsze bytes of data */
- info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) |
- (usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE);
-
- if((len-pktsze)==0)
- status |= TD_CTRL_IOC; /* last one generates INT */
-
- usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */
- if(i>0)
- tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
- i++;
- dataptr += pktsze;
- len -= pktsze;
- usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
- } while (len > 0);
- /* first mark the bulk QH element terminated */
- qh_bulk.element=0xffffffffL;
- /* set qh active */
- qh_bulk.dev_ptr=(unsigned long)dev;
- /* fill in tmp_td_chain */
- qh_bulk.element=swap_32((unsigned long)&tmp_td[0]);
- return 0;
-}
-
-
-/* search a free interrupt td
- */
-uhci_td_t *uhci_alloc_int_td(void)
-{
- int i;
- for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
- if(tmp_int_td[i].dev_ptr==0) /* no device assigned -> free TD */
- return &tmp_int_td[i];
- }
- return NULL;
-}
-
-#if 0
-void uhci_show_temp_int_td(void)
-{
- int i;
- for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
- if((tmp_int_td[i].dev_ptr&0x01)!=0x1L) /* no device assigned -> free TD */
- printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr);
- }
- printf("all others temp_tds are free\n");
-}
-#endif
-/*-------------------------------------------------------------------
- * submits USB interrupt (ie. polling ;-)
- */
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval)
-{
- int nint, n;
- unsigned long status, destination;
- unsigned long info,tmp;
- uhci_td_t *mytd;
- if (interval < 0 || interval >= 256)
- return -1;
-
- if (interval == 0)
- nint = 0;
- else {
- for (nint = 0, n = 1; nint <= 8; nint++, n += n) /* round interval down to 2^n */
- {
- if(interval < n) {
- interval = n / 2;
- break;
- }
- }
- nint--;
- }
-
- USB_UHCI_PRINTF("Rounded interval to %i, chain %i\n", interval, nint);
- mytd=uhci_alloc_int_td();
- if(mytd==NULL) {
- printf("No free INT TDs found\n");
- return -1;
- }
- status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27);
-/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27);
-*/
-
- destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21);
-
- info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE);
- tmp = swap_32(td_int[nint].link);
- usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev);
- /* Link it */
- tmp = swap_32((unsigned long)mytd);
- td_int[nint].link=tmp;
-
- usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
-
- return 0;
-}
-
-/**********************************************************************
- * Low Level functions
- */
-
-
-void reset_hc(void)
-{
-
- /* Global reset for 100ms */
- out16r( usb_base_addr + USBPORTSC1,0x0204);
- out16r( usb_base_addr + USBPORTSC2,0x0204);
- out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS);
- /* Turn off all interrupts */
- out16r(usb_base_addr + USBINTR,0);
- mdelay(50);
- out16r( usb_base_addr + USBCMD,0);
- mdelay(10);
-}
-
-void start_hc(void)
-{
- int timeout = 1000;
-
- while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) {
- if (!--timeout) {
- printf("USBCMD_HCRESET timed out!\n");
- break;
- }
- }
- /* Turn on all interrupts */
- out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP);
- /* Start at frame 0 */
- out16r(usb_base_addr + USBFRNUM,0);
- /* set Framebuffer base address */
- out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist);
- /* Run and mark it configured with a 64-byte max packet */
- out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
-}
-
-/* Initialize the skeleton
- */
-void usb_init_skel(void)
-{
- unsigned long temp;
- int n;
-
- for(n=0;n<USB_MAX_TEMP_INT_TD;n++)
- tmp_int_td[n].dev_ptr=0L; /* no devices connected */
- /* last td */
- usb_fill_td(&td_last,UHCI_PTR_TERM,TD_CTRL_IOC ,0,0,0L);
- /* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */
- /* End Queue Header */
- usb_fill_qh(&qh_end,UHCI_PTR_TERM,(unsigned long)&td_last);
- /* Bulk Queue Header */
- temp=(unsigned long)&qh_end;
- usb_fill_qh(&qh_bulk,temp | UHCI_PTR_QH,UHCI_PTR_TERM);
- /* Control Queue Header */
- temp=(unsigned long)&qh_bulk;
- usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH,UHCI_PTR_TERM);
- /* 1ms Interrupt td */
- temp=(unsigned long)&qh_cntrl;
- usb_fill_td(&td_int[0],temp | UHCI_PTR_QH,0,0,0,0L);
- temp=(unsigned long)&td_int[0];
- for(n=1; n<8; n++)
- usb_fill_td(&td_int[n],temp,0,0,0,0L);
- for (n = 0; n < 1024; n++) {
- /* link all framelist pointers to one of the interrupts */
- int m, o;
- if ((n&127)==127)
- framelist[n]= swap_32((unsigned long)&td_int[0]);
- else
- for (o = 1, m = 2; m <= 128; o++, m += m)
- if ((n & (m - 1)) == ((m - 1) / 2))
- framelist[n]= swap_32((unsigned long)&td_int[o]);
- }
-}
-
-/* check the common skeleton for completed transfers, and update the status
- * of the "connected" device. Called from the IRQ routine.
- */
-void usb_check_skel(void)
-{
- struct usb_device *dev;
- /* start with the control qh */
- if(qh_cntrl.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
- {
- dev=(struct usb_device *)qh_cntrl.dev_ptr;
- usb_get_td_status(&tmp_td[0],dev); /* update status */
- if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
- qh_cntrl.dev_ptr=0;
- }
- }
- /* now process the bulk */
- if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
- {
- dev=(struct usb_device *)qh_bulk.dev_ptr;
- usb_get_td_status(&tmp_td[0],dev); /* update status */
- if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
- qh_bulk.dev_ptr=0;
- }
- }
-}
-
-/* check the interrupt chain, ubdate the status of the appropriate device,
- * call the appropriate irqhandler and reactivate the TD if the irqhandler
- * returns with 1
- */
-void usb_check_int_chain(void)
-{
- int i,res;
- unsigned long link,status;
- struct usb_device *dev;
- uhci_td_t *td,*prevtd;
-
- for(i=0;i<8;i++) {
- prevtd = &td_int[i]; /* the first previous td is the skeleton td */
- link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
- td=(uhci_td_t *)link; /* assign it */
- /* all interrupt TDs are finally linked to the td_int[0].
- * so we process all until we find the td_int[0].
- * if int0 chain points to a QH, we're also done
- */
- while(((i>0) && (link != (unsigned long)&td_int[0])) ||
- ((i==0) && !(swap_32(td->link) & UHCI_PTR_QH)))
- {
- /* check if a device is assigned with this td */
- status=swap_32(td->status);
- if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) {
- /* td is not active and a device is assigned -> call irqhandler */
- dev=(struct usb_device *)td->dev_ptr;
- dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transferred length */
- dev->irq_status=usb_uhci_td_stat(status); /* get status */
- res=dev->irq_handle(dev); /* call irqhandler */
- if(res==1) {
- /* reactivate */
- status|=TD_CTRL_ACTIVE;
- td->status=swap_32(status);
- prevtd=td; /* previous td = this td */
- }
- else {
- prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */
- /* remove device pointer */
- td->dev_ptr=0L;
- }
- } /* if we call the irq handler */
- link=swap_32(td->link) & 0xfffffff0; /* next in chain */
- td=(uhci_td_t *)link; /* assign it */
- } /* process all td in this int chain */
- } /* next interrupt chain */
-}
-
-
-/* usb interrupt service routine.
- */
-void handle_usb_interrupt(void)
-{
- unsigned short status;
-
- /*
- * Read the interrupt status, and write it back to clear the
- * interrupt cause
- */
-
- status = in16r(usb_base_addr + USBSTS);
-
- if (!status) /* shared interrupt, not mine */
- return;
- if (status != 1) {
- /* remove host controller halted state */
- if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) {
- out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD));
- }
- }
- usb_check_int_chain(); /* call interrupt handlers for int tds */
- usb_check_skel(); /* call completion handler for common transfer routines */
- out16r(usb_base_addr+USBSTS,status);
-}
-
-
-/* init uhci
- */
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
- unsigned char temp;
- int busdevfunc;
-
- busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */
- if(busdevfunc==-1) {
- printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID);
- return -1;
- }
- pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp);
- irqvec = temp;
- irq_free_handler(irqvec);
- USB_UHCI_PRINTF("Interrupt Line = %d, is %d\n",irqvec);
- pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp);
- USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp);
- pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
- USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
- usb_base_addr&=0xFFFFFFF0;
- usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS;
- rh.devnum = 0;
- usb_init_skel();
- reset_hc();
- start_hc();
- irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL);
- return 0;
-}
-
-/* stop uhci
- */
-int usb_lowlevel_stop(int index)
-{
- if(irqvec==-1)
- return 1;
- irq_free_handler(irqvec);
- reset_hc();
- irqvec = -1;
- return 0;
-}
-
-/*******************************************************************************************
- * Virtual Root Hub
- * Since the uhci does not have a real HUB, we simulate one ;-)
- */
-#undef USB_RH_DEBUG
-
-#ifdef USB_RH_DEBUG
-#define USB_RH_PRINTF(fmt,args...) printf (fmt ,##args)
-static void usb_display_wValue(unsigned short wValue,unsigned short wIndex);
-static void usb_display_Req(unsigned short req);
-#else
-#define USB_RH_PRINTF(fmt,args...)
-static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {}
-static void usb_display_Req(unsigned short req) {}
-#endif
-
-#define WANT_USB_ROOT_HUB_HUB_DES
-#include <usbroothubdes.h>
-#undef WANT_USB_ROOT_HUB_HUB_DES
-
-/*
- * Root Hub Control Pipe (interrupt Pipes are not supported)
- */
-
-
-int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd)
-{
- void *data = buffer;
- int leni = transfer_len;
- int len = 0;
- int status = 0;
- int stat = 0;
- int i;
-
- unsigned short cstatus;
-
- unsigned short bmRType_bReq;
- unsigned short wValue;
- unsigned short wIndex;
- unsigned short wLength;
-
- if (usb_pipeint(pipe)) {
- printf("Root-Hub submit IRQ: NOT implemented\n");
-#if 0
- uhci->rh.urb = urb;
- uhci->rh.send = 1;
- uhci->rh.interval = urb->interval;
- rh_init_int_timer (urb);
-#endif
- return 0;
- }
- bmRType_bReq = cmd->requesttype | cmd->request << 8;
- wValue = swap_16(cmd->value);
- wIndex = swap_16(cmd->index);
- wLength = swap_16(cmd->length);
- usb_display_Req(bmRType_bReq);
- for (i = 0; i < 8; i++)
- rh.c_p_r[i] = 0;
- USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n",
- dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength);
-
- switch (bmRType_bReq) {
- /* Request Destination:
- without flags: Device,
- RH_INTERFACE: interface,
- RH_ENDPOINT: endpoint,
- RH_CLASS means HUB here,
- RH_OTHER | RH_CLASS almost ever means HUB_PORT here
- */
-
- case RH_GET_STATUS:
- *(unsigned short *) data = swap_16(1);
- len=2;
- break;
- case RH_GET_STATUS | RH_INTERFACE:
- *(unsigned short *) data = swap_16(0);
- len=2;
- break;
- case RH_GET_STATUS | RH_ENDPOINT:
- *(unsigned short *) data = swap_16(0);
- len=2;
- break;
- case RH_GET_STATUS | RH_CLASS:
- *(unsigned long *) data = swap_32(0);
- len=4;
- break; /* hub power ** */
- case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-
- status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1));
- cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) |
- ((status & USBPORTSC_PEC) >> (3 - 1)) |
- (rh.c_p_r[wIndex - 1] << (0 + 4));
- status = (status & USBPORTSC_CCS) |
- ((status & USBPORTSC_PE) >> (2 - 1)) |
- ((status & USBPORTSC_SUSP) >> (12 - 2)) |
- ((status & USBPORTSC_PR) >> (9 - 4)) |
- (1 << 8) | /* power on ** */
- ((status & USBPORTSC_LSDA) << (-8 + 9));
-
- *(unsigned short *) data = swap_16(status);
- *(unsigned short *) (data + 2) = swap_16(cstatus);
- len=4;
- break;
- case RH_CLEAR_FEATURE | RH_ENDPOINT:
- switch (wValue) {
- case (RH_ENDPOINT_STALL):
- len=0;
- break;
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_CLASS:
- switch (wValue) {
- case (RH_C_HUB_OVER_CURRENT):
- len=0; /* hub power over current ** */
- break;
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
- usb_display_wValue(wValue,wIndex);
- switch (wValue) {
- case (RH_PORT_ENABLE):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) & ~USBPORTSC_PE;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_PORT_SUSPEND):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) & ~USBPORTSC_SUSP;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_PORT_POWER):
- len=0; /* port power ** */
- break;
- case (RH_C_PORT_CONNECTION):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) | USBPORTSC_CSC;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_C_PORT_ENABLE):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) | USBPORTSC_PEC;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_C_PORT_SUSPEND):
-/*** WR_RH_PORTSTAT(RH_PS_PSSC); */
- len=0;
- break;
- case (RH_C_PORT_OVER_CURRENT):
- len=0;
- break;
- case (RH_C_PORT_RESET):
- rh.c_p_r[wIndex - 1] = 0;
- len=0;
- break;
- }
- break;
- case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
- usb_display_wValue(wValue,wIndex);
- switch (wValue) {
- case (RH_PORT_SUSPEND):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) | USBPORTSC_SUSP;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_PORT_RESET):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) | USBPORTSC_PR;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- mdelay(10);
- status = (status & 0xfff5) & ~USBPORTSC_PR;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- udelay(10);
- status = (status & 0xfff5) | USBPORTSC_PE;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- mdelay(10);
- status = (status & 0xfff5) | 0xa;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_PORT_POWER):
- len=0; /* port power ** */
- break;
- case (RH_PORT_ENABLE):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) | USBPORTSC_PE;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- }
- break;
-
- case RH_SET_ADDRESS:
- rh.devnum = wValue;
- len=0;
- break;
- case RH_GET_DESCRIPTOR:
- switch ((wValue & 0xff00) >> 8) {
- case (0x01): /* device descriptor */
- i=sizeof(root_hub_config_des);
- status=i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy (data, root_hub_dev_des, len);
- break;
- case (0x02): /* configuration descriptor */
- i=sizeof(root_hub_config_des);
- status=i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy (data, root_hub_config_des, len);
- break;
- case (0x03): /*string descriptors */
- if(wValue==0x0300) {
- i=sizeof(root_hub_str_index0);
- status = i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy (data, root_hub_str_index0, len);
- break;
- }
- if(wValue==0x0301) {
- i=sizeof(root_hub_str_index1);
- status = i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy (data, root_hub_str_index1, len);
- break;
- }
- stat = USB_ST_STALLED;
- }
- break;
-
- case RH_GET_DESCRIPTOR | RH_CLASS:
- root_hub_hub_des[2] = 2;
- i=sizeof(root_hub_hub_des);
- status= i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy (data, root_hub_hub_des, len);
- break;
- case RH_GET_CONFIGURATION:
- *(unsigned char *) data = 0x01;
- len = 1;
- break;
- case RH_SET_CONFIGURATION:
- len=0;
- break;
- default:
- stat = USB_ST_STALLED;
- }
- USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat,
- in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2));
- dev->act_len=len;
- dev->status=stat;
- return stat;
-
-}
-
-/********************************************************************************
- * Some Debug Routines
- */
-
-#ifdef USB_RH_DEBUG
-
-static void usb_display_Req(unsigned short req)
-{
- USB_RH_PRINTF("- Root-Hub Request: ");
- switch (req) {
- case RH_GET_STATUS:
- USB_RH_PRINTF("Get Status ");
- break;
- case RH_GET_STATUS | RH_INTERFACE:
- USB_RH_PRINTF("Get Status Interface ");
- break;
- case RH_GET_STATUS | RH_ENDPOINT:
- USB_RH_PRINTF("Get Status Endpoint ");
- break;
- case RH_GET_STATUS | RH_CLASS:
- USB_RH_PRINTF("Get Status Class");
- break; /* hub power ** */
- case RH_GET_STATUS | RH_OTHER | RH_CLASS:
- USB_RH_PRINTF("Get Status Class Others");
- break;
- case RH_CLEAR_FEATURE | RH_ENDPOINT:
- USB_RH_PRINTF("Clear Feature Endpoint ");
- break;
- case RH_CLEAR_FEATURE | RH_CLASS:
- USB_RH_PRINTF("Clear Feature Class ");
- break;
- case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
- USB_RH_PRINTF("Clear Feature Other Class ");
- break;
- case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
- USB_RH_PRINTF("Set Feature Other Class ");
- break;
- case RH_SET_ADDRESS:
- USB_RH_PRINTF("Set Address ");
- break;
- case RH_GET_DESCRIPTOR:
- USB_RH_PRINTF("Get Descriptor ");
- break;
- case RH_GET_DESCRIPTOR | RH_CLASS:
- USB_RH_PRINTF("Get Descriptor Class ");
- break;
- case RH_GET_CONFIGURATION:
- USB_RH_PRINTF("Get Configuration ");
- break;
- case RH_SET_CONFIGURATION:
- USB_RH_PRINTF("Get Configuration ");
- break;
- default:
- USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req);
- }
- USB_RH_PRINTF("\n");
-
-}
-
-static void usb_display_wValue(unsigned short wValue,unsigned short wIndex)
-{
- switch (wValue) {
- case (RH_PORT_ENABLE):
- USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex);
- break;
- case (RH_PORT_SUSPEND):
- USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex);
- break;
- case (RH_PORT_POWER):
- USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex);
- break;
- case (RH_C_PORT_CONNECTION):
- USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex);
- break;
- case (RH_C_PORT_ENABLE):
- USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex);
- break;
- case (RH_C_PORT_SUSPEND):
- USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex);
- break;
- case (RH_C_PORT_OVER_CURRENT):
- USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex);
- break;
- case (RH_C_PORT_RESET):
- USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex);
- break;
- default:
- USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex);
- break;
- }
-}
-
-#endif
-
-
-#ifdef USB_UHCI_DEBUG
-
-static int usb_display_td(uhci_td_t *td)
-{
- unsigned long tmp;
- int valid;
-
- printf("TD at %p:\n",td);
-
- tmp=swap_32(td->link);
- printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0,
- ((tmp & 0x4)==0x4) ? "Depth" : "Breath",
- ((tmp & 0x2)==0x2) ? "QH" : "TD",
- ((tmp & 0x1)==0x1) ? "invalid" : "valid");
- valid=((tmp & 0x1)==0x0);
- tmp=swap_32(td->status);
- printf(" %s %ld Errors %s %s %s \n %s %s %s %s %s %s\n Len 0x%lX\n",
- (((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable",
- ((tmp>>28)&0x3),
- (((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed",
- (((tmp>>25)&0x1)==0x1) ? "ISO " : "",
- (((tmp>>24)&0x1)==0x1) ? "IOC " : "",
- (((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ",
- (((tmp>>22)&0x1)==0x1) ? "Stalled" : "",
- (((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "",
- (((tmp>>20)&0x1)==0x1) ? "Babble" : "",
- (((tmp>>19)&0x1)==0x1) ? "NAK" : "",
- (((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "",
- (tmp&0x7ff));
- tmp=swap_32(td->info);
- printf(" MaxLen 0x%lX\n",((tmp>>21)&0x7FF));
- printf(" %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "",
- ((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF);
- tmp=swap_32(td->buffer);
- printf(" Buffer 0x%08lX\n",tmp);
- printf(" DEV %08lX\n",td->dev_ptr);
- return valid;
-}
-
-
-void usb_show_td(int max)
-{
- int i;
- if(max>0) {
- for(i=0;i<max;i++) {
- usb_display_td(&tmp_td[i]);
- }
- }
- else {
- i=0;
- do {
- printf("tmp_td[%d]\n",i);
- }while(usb_display_td(&tmp_td[i++]));
- }
-}
-
-
-#endif
-#endif /* CONFIG_USB_UHCI */
-
-/* EOF */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Note: Part of this code has been derived from linux
- */
-#ifndef _USB_UHCI_H_
-#define _USB_UHCI_H_
-
-
-/* Command register */
-#define USBCMD 0
-#define USBCMD_RS 0x0001 /* Run/Stop */
-#define USBCMD_HCRESET 0x0002 /* Host reset */
-#define USBCMD_GRESET 0x0004 /* Global reset */
-#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
-#define USBCMD_FGR 0x0010 /* Force Global Resume */
-#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
-#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
-#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
-
-/* Status register */
-#define USBSTS 2
-#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
-#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
-#define USBSTS_RD 0x0004 /* Resume Detect */
-#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
-#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
-#define USBSTS_HCH 0x0020 /* HC Halted */
-
-/* Interrupt enable register */
-#define USBINTR 4
-#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
-#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
-#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
-#define USBINTR_SP 0x0008 /* Short packet interrupt enable */
-
-#define USBFRNUM 6
-#define USBFLBASEADD 8
-#define USBSOF 12
-
-/* USB port status and control registers */
-#define USBPORTSC1 16
-#define USBPORTSC2 18
-#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
-#define USBPORTSC_CSC 0x0002 /* Connect Status Change */
-#define USBPORTSC_PE 0x0004 /* Port Enable */
-#define USBPORTSC_PEC 0x0008 /* Port Enable Change */
-#define USBPORTSC_LS 0x0030 /* Line Status */
-#define USBPORTSC_RD 0x0040 /* Resume Detect */
-#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
-#define USBPORTSC_PR 0x0200 /* Port Reset */
-#define USBPORTSC_SUSP 0x1000 /* Suspend */
-
-/* Legacy support register */
-#define USBLEGSUP 0xc0
-#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
-
-#define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */
-#define UHCI_PID 0xff /* PID MASK */
-
-#define UHCI_PTR_BITS 0x000F
-#define UHCI_PTR_TERM 0x0001
-#define UHCI_PTR_QH 0x0002
-#define UHCI_PTR_DEPTH 0x0004
-
-/* for TD <status>: */
-#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
-#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
-#define TD_CTRL_LS (1 << 26) /* Low Speed Device */
-#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
-#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
-#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
-#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
-#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
-#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
-#define TD_CTRL_NAK (1 << 19) /* NAK Received */
-#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
-#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
-#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */
-
-#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
- TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
-
-#define TD_TOKEN_TOGGLE 19
-
-/* ------------------------------------------------------------------------------------
- Virtual Root HUB
- ------------------------------------------------------------------------------------ */
-/* destination of request */
-#define RH_INTERFACE 0x01
-#define RH_ENDPOINT 0x02
-#define RH_OTHER 0x03
-
-#define RH_CLASS 0x20
-#define RH_VENDOR 0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS 0x0080
-#define RH_CLEAR_FEATURE 0x0100
-#define RH_SET_FEATURE 0x0300
-#define RH_SET_ADDRESS 0x0500
-#define RH_GET_DESCRIPTOR 0x0680
-#define RH_SET_DESCRIPTOR 0x0700
-#define RH_GET_CONFIGURATION 0x0880
-#define RH_SET_CONFIGURATION 0x0900
-#define RH_GET_STATE 0x0280
-#define RH_GET_INTERFACE 0x0A80
-#define RH_SET_INTERFACE 0x0B00
-#define RH_SYNC_FRAME 0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP 0x2000
-
-/* Hub port features */
-#define RH_PORT_CONNECTION 0x00
-#define RH_PORT_ENABLE 0x01
-#define RH_PORT_SUSPEND 0x02
-#define RH_PORT_OVER_CURRENT 0x03
-#define RH_PORT_RESET 0x04
-#define RH_PORT_POWER 0x08
-#define RH_PORT_LOW_SPEED 0x09
-#define RH_C_PORT_CONNECTION 0x10
-#define RH_C_PORT_ENABLE 0x11
-#define RH_C_PORT_SUSPEND 0x12
-#define RH_C_PORT_OVER_CURRENT 0x13
-#define RH_C_PORT_RESET 0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER 0x00
-#define RH_C_HUB_OVER_CURRENT 0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL 0x01
-
-/* Our Vendor Specific feature */
-#define RH_REMOVE_EP 0x00
-
-
-#define RH_ACK 0x01
-#define RH_REQ_ERR -1
-#define RH_NACK 0x00
-
-
-/* Transfer descriptor structure */
-typedef struct {
- unsigned long link; /* next td/qh (LE)*/
- unsigned long status; /* status of the td */
- unsigned long info; /* Max Lenght / Endpoint / device address and PID */
- unsigned long buffer; /* pointer to data buffer (LE) */
- unsigned long dev_ptr; /* pointer to the assigned device (BE) */
- unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */
-} uhci_td_t, *puhci_td_t;
-
-/* Queue Header structure */
-typedef struct {
- unsigned long head; /* Next QH (LE)*/
- unsigned long element; /* Queue element pointer (LE) */
- unsigned long res[5]; /* reserved */
- unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */
-} uhci_qh_t, *puhci_qh_t;
-
-struct virt_root_hub {
- int devnum; /* Address of Root Hub endpoint */
- int numports; /* number of ports */
- int c_p_r[8]; /* C_PORT_RESET */
-};
-
-
-#endif /* _USB_UHCI_H_ */
+++ /dev/null
-if TARGET_MIP405 || TARGET_MIP405T
-
-config SYS_BOARD
- default "mip405"
-
-config SYS_VENDOR
- default "mpl"
-
-config SYS_CONFIG_NAME
- default "MIP405"
-
-config ISO_STRING
- string
- default "MEV-10082-001" if TARGET_MIP405T
- default "MEV-10072-001" if TARGET_MIP405
-
-endif
+++ /dev/null
-MIP405 BOARD
-M: Denis Peter <d.peter@mpl.ch>
-S: Maintained
-F: board/mpl/mip405/
-F: include/configs/MIP405.h
-F: configs/MIP405_defconfig
-F: configs/MIP405T_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = mip405.o cmd_mip405.o \
- ../common/pci.o \
- ../common/usb_uhci.o \
- ../common/common_util.o
-obj-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * hacked for MIP405
- */
-
-#include <common.h>
-#include <command.h>
-#include "mip405.h"
-#include "../common/common_util.h"
-
-
-extern void print_mip405_info(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-
-/* ------------------------------------------------------------------------- */
-
-int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-
- ulong led_on;
-
- if (strcmp(argv[1], "info") == 0)
- {
- print_mip405_info();
- return 0;
- }
- if (strcmp(argv[1], "led") == 0)
- {
- led_on = (ulong)simple_strtoul(argv[2], NULL, 10);
- user_led0(led_on);
- return 0;
- }
- return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-U_BOOT_CMD(
- mip405, 8, 1, do_mip405,
- "MIP405 specific Cmds",
- "flash mem [SrcAddr] - updates U-Boot with image in memory\n"
- "mip405 flash mps - updates U-Boot with image from MPS\n"
- "mip405 info - displays board information\n"
- "mip405 led <on> - switches LED on (on=1) or off (on=0)"
-);
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*-----------------------------------------------------------------------------
- * Function: ext_bus_cntlr_init
- * Description: Initializes the External Bus Controller for the external
- * peripherals. IMPORTANT: For pass1 this code must run from
- * cache since you can not reliably change a peripheral banks
- * timing register (pbxap) while running code from that bank.
- * For ex., since we are running from ROM on bank 0, we can NOT
- * execute the code that modifies bank 0 timings from ROM, so
- * we run it from cache.
- * Bank 0 - Flash or Multi Purpose Socket
- * Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
- * Bank 2 - UART 1 (set in C-Code)
- * Bank 3 - UART 2 (set in C-Code)
- * Bank 4 - not used
- * Bank 5 - not used
- * Bank 6 - not used
- * Bank 7 - PLD Register
- *-----------------------------------------------------------------------------*/
-
-#include <configs/MIP405.h>
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-#include "mip405.h"
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 /* save link register */
- mfdcr r3,CPC0_PSR /* get strapping reg */
- andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
- bnelr /* jump back if PCI boot */
-
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 14; used to prefetch */
- mtctr r4 /* 14 cache lines to fit this function */
- /* in cache (gives us 8x14=112 instrctns) */
-..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 14 cache lines */
-
- /*-------------------------------------------------------------------
- * Delay to ensure all accesses to ROM are complete before changing
- * bank 0 timings.
- *------------------------------------------------------------------- */
- addis r3,0,0x0
- ori r3,r3,0xA000
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /*-----------------------------------------------------------------------
- * decide boot up mode
- *----------------------------------------------------------------------- */
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- mfdcr r4,EBC0_CFGDATA
-
- andi. r0, r4, 0x2000 /* mask out irrelevant bits */
- beq 0f /* jump if 8 bit bus width */
-
- /* setup 16 bit things
- *-----------------------------------------------------------------------
- * Memory Bank 0 (16 Bit Flash) initialization
- *---------------------------------------------------------------------- */
-
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,(FLASH_AP_B)@h
- ori r4,r4,(FLASH_AP_B)@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- /* BS=0x010(4MB),BU=0x3(R/W), */
- addis r4,0,(FLASH_CR_B)@h
- ori r4,r4,(FLASH_CR_B)@l
- mtdcr EBC0_CFGDATA,r4
- b 1f
-
-0:
-
- /* 8Bit boot mode: */
- /*-----------------------------------------------------------------------
- * Memory Bank 0 Multi Purpose Socket initialization
- *----------------------------------------------------------------------- */
- /* 0x7F8FFE80 slowest boot */
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,(MPS_AP_B)@h
- ori r4,r4,(MPS_AP_B)@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- /* BS=0x010(4MB),BU=0x3(R/W), */
- addis r4,0,(MPS_CR_B)@h
- ori r4,r4,(MPS_CR_B)@l
-
- mtdcr EBC0_CFGDATA,r4
-
-
-1:
- /*-----------------------------------------------------------------------
- * Memory Bank 2-3-4-5-6 (not used) initialization
- *-----------------------------------------------------------------------*/
- addi r4,0,PB1CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB2CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB3CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB4CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB5CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB6CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB7CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
- nop /* pass2 DCR errata #8 */
- blr
-
-#if defined(CONFIG_BOOT_PCI)
- .section .bootpg,"ax"
- .globl _start_pci
-/*******************************************
- */
-
-_start_pci:
- /* first handle errata #68 / PCI_18 */
- iccci r0, r0 /* invalidate I-cache */
- lis r31, 0
- mticcr r31 /* ICCR = 0 (all uncachable) */
- isync
-
- mfccr0 r28 /* set CCR0[24] = 1 */
- ori r28, r28, 0x0080
- mtccr0 r28
-
- /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
- lis r28, 0xEF40
- addi r28, r28, 0x0004
- stw r31, 0x0C(r28) /* clear PMM0PCIHA */
- lis r29, 0xFFF8 /* open 512 kByte */
- addi r29, r29, 0x0001/* and enable this region */
- stwbrx r29, r0, r28 /* write PMM0MA */
-
- lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
- addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
-
- lis r31, 0x8000 /* set en bit bus 0 */
- ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
- stwbrx r31, r0, r28 /* write it */
-
- lwbrx r31, r0, r29 /* load XBCS register */
- oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
- stwbrx r31, r0, r29 /* write back XBCS register */
-
- nop
- nop
- b _start /* normal start */
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * TODO: clean-up
- */
-
-/*
- * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
- *
- * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
- * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
- * parameters from the datasheet are:
- * Tclk = 7.5ns (CL = 2)
- * Trp = 15ns
- * Trc = 60ns
- * Trcd = 15ns
- * Trfc = 66ns
- *
- * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
- * period is 10ns and the parameters needed for the Timing Register are:
- * CASL = CL = 2 clock cycles
- * PTA = Trp = 15ns / 10ns = 2 clock cycles
- * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
- * LDF = 2 clock cycles (but can be extended to meet board-level timing)
- * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
- * RCD = Trcd = 15ns / 10ns= 2 clock cycles
- *
- * The actual bit settings in the register would be:
- *
- * CASL = 0b01
- * PTA = 0b01
- * CTP = 0b10
- * LDF = 0b01
- * RFTA = 0b011
- * RCD = 0b01
- *
- * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
- * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
- * defined as Trc rather than Trfc.
- * When using DIMM modules, most but not all of the required timing parameters can be read
- * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
- * are not available from the EEPROM
- */
-
-#include <common.h>
-#include "mip405.h"
-#include <asm/processor.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-i2c.h>
-#include <miiphy.h>
-#include "../common/common_util.h"
-#include <stdio_dev.h>
-#include <i2c.h>
-#include <rtc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef SDRAM_DEBUG
-#define ENABLE_ECC /* for ecc boards */
-
-/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
-#ifndef __ldiv_t_defined
-typedef struct {
- long int quot; /* Quotient */
- long int rem; /* Remainder */
-} ldiv_t;
-extern ldiv_t ldiv (long int __numer, long int __denom);
-# define __ldiv_t_defined 1
-#endif
-
-
-#define PLD_PART_REG PER_PLD_ADDR + 0
-#define PLD_VERS_REG PER_PLD_ADDR + 1
-#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
-#define PLD_IRQ_REG PER_PLD_ADDR + 3
-#define PLD_COM_MODE_REG PER_PLD_ADDR + 4
-#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
-
-#define MEGA_BYTE (1024*1024)
-
-typedef struct {
- unsigned char boardtype; /* Board revision and Population Options */
- unsigned char cal; /* cas Latency (will be programmend as cal-1) */
- unsigned char trp; /* datain27 in clocks */
- unsigned char trcd; /* datain29 in clocks */
- unsigned char tras; /* datain30 in clocks */
- unsigned char tctp; /* tras - trcd in clocks */
- unsigned char am; /* Address Mod (will be programmed as am-1) */
- unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
- unsigned char ecc; /* if true, ecc is enabled */
-} sdram_t;
-#if defined(CONFIG_TARGET_MIP405T)
-const sdram_t sdram_table[] = {
- { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 2, /* Address Mode = 2 (12x9x4) */
- 3, /* size value (32MByte) */
- 0}, /* ECC disabled */
- { 0xff, /* terminator */
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff }
-};
-#else
-const sdram_t sdram_table[] = {
- { 0x0f, /* Rev A, 128MByte -1 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 3, /* Address Mode = 3 */
- 5, /* size value */
- 1}, /* ECC enabled */
- { 0x07, /* Rev A, 64MByte -2 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 2, /* Address Mode = 2 */
- 4, /* size value */
- 1}, /* ECC enabled */
- { 0x03, /* Rev A, 128MByte -4 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 3, /* Address Mode = 3 */
- 5, /* size value */
- 1}, /* ECC enabled */
- { 0x1f, /* Rev B, 128MByte -3 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 3, /* Address Mode = 3 */
- 5, /* size value */
- 1}, /* ECC enabled */
- { 0x2f, /* Rev C, 128MByte -3 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 3, /* Address Mode = 3 */
- 5, /* size value */
- 1}, /* ECC enabled */
- { 0xff, /* terminator */
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff }
-};
-#endif /*CONFIG_TARGET_MIP405T */
-void SDRAM_err (const char *s)
-{
-#ifndef SDRAM_DEBUG
- (void) get_clocks ();
- gd->baudrate = 9600;
- serial_init ();
-#endif
- serial_puts ("\n");
- serial_puts (s);
- serial_puts ("\n enable SDRAM_DEBUG for more info\n");
- for (;;);
-}
-
-
-unsigned char get_board_revcfg (void)
-{
- out8 (PER_BOARD_ADDR, 0);
- return (in8 (PER_BOARD_ADDR));
-}
-
-
-#ifdef SDRAM_DEBUG
-
-void write_hex (unsigned char i)
-{
- char cc;
-
- cc = i >> 4;
- cc &= 0xf;
- if (cc > 9)
- serial_putc (cc + 55);
- else
- serial_putc (cc + 48);
- cc = i & 0xf;
- if (cc > 9)
- serial_putc (cc + 55);
- else
- serial_putc (cc + 48);
-}
-
-void write_4hex (unsigned long val)
-{
- write_hex ((unsigned char) (val >> 24));
- write_hex ((unsigned char) (val >> 16));
- write_hex ((unsigned char) (val >> 8));
- write_hex ((unsigned char) val);
-}
-
-#endif
-
-
-int init_sdram (void)
-{
- unsigned long tmp, baseaddr;
- unsigned short i;
- unsigned char trp_clocks,
- trcd_clocks,
- tras_clocks,
- trc_clocks;
- unsigned char cal_val;
- unsigned char bc;
- unsigned long sdram_tim, sdram_bank;
-
- /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
- (void) get_clocks ();
- gd->baudrate = 9600;
- serial_init ();
- /* set up the pld */
- mtdcr (EBC0_CFGADDR, PB7AP);
- mtdcr (EBC0_CFGDATA, PLD_AP);
- mtdcr (EBC0_CFGADDR, PB7CR);
- mtdcr (EBC0_CFGDATA, PLD_CR);
- /* THIS IS OBSOLETE */
- /* set up the board rev reg*/
- mtdcr (EBC0_CFGADDR, PB5AP);
- mtdcr (EBC0_CFGDATA, BOARD_AP);
- mtdcr (EBC0_CFGADDR, PB5CR);
- mtdcr (EBC0_CFGDATA, BOARD_CR);
-#ifdef SDRAM_DEBUG
- /* get all informations from PLD */
- serial_puts ("\nPLD Part 0x");
- bc = in8 (PLD_PART_REG);
- write_hex (bc);
- serial_puts ("\nPLD Vers 0x");
- bc = in8 (PLD_VERS_REG);
- write_hex (bc);
- serial_puts ("\nBoard Rev 0x");
- bc = in8 (PLD_BOARD_CFG_REG);
- write_hex (bc);
- serial_puts ("\n");
-#endif
- /* check board */
- bc = in8 (PLD_PART_REG);
-#if defined(CONFIG_TARGET_MIP405T)
- if((bc & 0x80)==0)
- SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
-#else
- if((bc & 0x80)==0x80)
- SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
-#endif
- /* set-up the chipselect machine */
- mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */
- tmp = mfdcr (EBC0_CFGDATA);
- if ((tmp & 0x00002000) == 0) {
- /* MPS Boot, set up the flash */
- mtdcr (EBC0_CFGADDR, PB1AP);
- mtdcr (EBC0_CFGDATA, FLASH_AP);
- mtdcr (EBC0_CFGADDR, PB1CR);
- mtdcr (EBC0_CFGDATA, FLASH_CR);
- } else {
- /* Flash boot, set up the MPS */
- mtdcr (EBC0_CFGADDR, PB1AP);
- mtdcr (EBC0_CFGDATA, MPS_AP);
- mtdcr (EBC0_CFGADDR, PB1CR);
- mtdcr (EBC0_CFGDATA, MPS_CR);
- }
- /* set up UART0 (CS2) and UART1 (CS3) */
- mtdcr (EBC0_CFGADDR, PB2AP);
- mtdcr (EBC0_CFGDATA, UART0_AP);
- mtdcr (EBC0_CFGADDR, PB2CR);
- mtdcr (EBC0_CFGDATA, UART0_CR);
- mtdcr (EBC0_CFGADDR, PB3AP);
- mtdcr (EBC0_CFGDATA, UART1_AP);
- mtdcr (EBC0_CFGADDR, PB3CR);
- mtdcr (EBC0_CFGDATA, UART1_CR);
- bc = in8 (PLD_BOARD_CFG_REG);
-#ifdef SDRAM_DEBUG
- serial_puts ("\nstart SDRAM Setup\n");
- serial_puts ("\nBoard Rev: ");
- write_hex (bc);
- serial_puts ("\n");
-#endif
- i = 0;
- baseaddr = CONFIG_SYS_SDRAM_BASE;
- while (sdram_table[i].sz != 0xff) {
- if (sdram_table[i].boardtype == bc)
- break;
- i++;
- }
- if (sdram_table[i].boardtype != bc)
- SDRAM_err ("No SDRAM table found for this board!!!\n");
-#ifdef SDRAM_DEBUG
- serial_puts (" found table ");
- write_hex (i);
- serial_puts (" \n");
-#endif
- /* since the ECC initialisation needs some time,
- * we show that we're alive
- */
- if (sdram_table[i].ecc)
- serial_puts ("\nInitializing SDRAM, Please stand by");
- cal_val = sdram_table[i].cal - 1; /* Cas Latency */
- trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
- trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
- tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
- /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
- /* trc_clocks is sum of trp_clocks + tras_clocks */
- trc_clocks = trp_clocks + tras_clocks;
- /* get SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
- /* insert CASL value */
- sdram_tim |= ((unsigned long) (cal_val)) << 23;
- /* insert PTA value */
- sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
- /* insert CTP value */
- sdram_tim |=
- ((unsigned long) (trc_clocks - trp_clocks -
- trcd_clocks)) << 16;
- /* insert LDF (always 01) */
- sdram_tim |= ((unsigned long) 0x01) << 14;
- /* insert RFTA value */
- sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
- /* insert RCD value */
- sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
-
- tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
- /* insert SZ value; */
- tmp |= ((unsigned long) sdram_table[i].sz << 17);
- /* get SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
- sdram_bank |= (baseaddr | tmp | 0x01);
-
-#ifdef SDRAM_DEBUG
- serial_puts ("sdtr: ");
- write_4hex (sdram_tim);
- serial_puts ("\n");
-#endif
-
- /* write SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- mtdcr (SDRAM0_CFGDATA, sdram_tim);
-
-#ifdef SDRAM_DEBUG
- serial_puts ("mb0cf: ");
- write_4hex (sdram_bank);
- serial_puts ("\n");
-#endif
-
- /* write SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- mtdcr (SDRAM0_CFGDATA, sdram_bank);
-
- if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
- /* get SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
- tmp |= 0x07F00000;
- } else {
- /* get SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
- tmp |= 0x05F00000;
- }
- /* write SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- mtdcr (SDRAM0_CFGDATA, tmp);
- /* enable ECC if used */
-#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
- if (sdram_table[i].ecc) {
- /* disable checking for all banks */
- unsigned long *p;
-#ifdef SDRAM_DEBUG
- serial_puts ("disable ECC.. ");
-#endif
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- tmp = mfdcr (SDRAM0_CFGDATA);
- tmp &= 0xff0fffff; /* disable all banks */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- /* set up SDRAM Controller with ECC enabled */
-#ifdef SDRAM_DEBUG
- serial_puts ("setup SDRAM Controller.. ");
-#endif
- mtdcr (SDRAM0_CFGDATA, tmp);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, tmp);
- udelay (600);
-#ifdef SDRAM_DEBUG
- serial_puts ("fill the memory..\n");
-#endif
- serial_puts (".");
- /* now, fill all the memory */
- tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
- p = (unsigned long) 0;
- while ((unsigned long) p < tmp) {
- *p++ = 0L;
- if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
- serial_puts (".");
- }
- /* enable bank 0 */
- serial_puts (".");
-#ifdef SDRAM_DEBUG
- serial_puts ("enable ECC\n");
-#endif
- udelay (400);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- tmp = mfdcr (SDRAM0_CFGDATA);
- tmp |= 0x00800000; /* enable bank 0 */
- mtdcr (SDRAM0_CFGDATA, tmp);
- udelay (400);
- } else
-#endif
- {
- /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, tmp);
- udelay (400);
- }
- serial_puts ("\n");
- return (0);
-}
-
-int board_early_init_f (void)
-{
- init_sdram ();
-
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the PIP405 board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
- | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
- | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
- | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
- | Note for MIP405 board:
- | An interrupt taken for the SouthBridge (IRQ 25) indicates that
- | the Interrupt Controller in the South Bridge has caused the
- | interrupt. The IC must be read to determine which device
- | caused the interrupt.
- |
- +-------------------------------------------------------------------------*/
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
- mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- return 0;
-}
-
-int board_early_init_r(void)
-{
- int mode;
-
- /*
- * since we are relocated, we can finally enable i-cache
- * and set up the flash CS correctly
- */
- icache_enable();
- setup_cs_reloc();
- /* get and display boot mode */
- mode = get_boot_mode();
- if (mode & BOOT_PCI)
- printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
- "MPS" : "Flash");
- else
- printf("%s Boot\n", (mode & BOOT_MPS) ?
- "MPS" : "Flash");
-
- return 0;
-}
-
-/*
- * Get some PLD Registers
- */
-
-unsigned short get_pld_parvers (void)
-{
- unsigned short result;
- unsigned char rc;
-
- rc = in8 (PLD_PART_REG);
- result = (unsigned short) rc << 8;
- rc = in8 (PLD_VERS_REG);
- result |= rc;
- return result;
-}
-
-
-void user_led0 (unsigned char on)
-{
- if (on)
- out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
- else
- out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
-}
-
-
-void ide_set_reset (int idereset)
-{
- /* if reset = 1 IDE reset will be asserted */
- if (idereset)
- out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
- else {
- udelay (10000);
- out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
- }
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
-{
-#if !defined(CONFIG_TARGET_MIP405T)
- unsigned char bc,rc,tmp;
- int i;
-
- bc = in8 (PLD_BOARD_CFG_REG);
- tmp = ~bc;
- tmp &= 0xf;
- rc = 0;
- for (i = 0; i < 4; i++) {
- rc <<= 1;
- rc += (tmp & 0x1);
- tmp >>= 1;
- }
- rc++;
- if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
- || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
- && (rc==0x1)) /* Population Option 1 is a -3 */
- rc=3;
- *pcbrev=(bc >> 4) & 0xf;
- *var=rc;
-#else
- unsigned char bc;
- bc = in8 (PLD_BOARD_CFG_REG);
- *pcbrev=(bc >> 4) & 0xf;
- *var=16-(bc & 0xf);
-#endif
-}
-
-/*
- * Check Board Identity:
- */
-/* serial String: "MIP405_1000" OR "MIP405T_1000" */
-#if !defined(CONFIG_TARGET_MIP405T)
-#define BOARD_NAME "MIP405"
-#else
-#define BOARD_NAME "MIP405T"
-#endif
-
-int checkboard (void)
-{
- char s[50];
- unsigned char bc, var;
- int i;
- backup_t *b = (backup_t *) s;
-
- puts ("Board: ");
- get_pcbrev_var(&bc,&var);
- i = getenv_f("serial#", (char *)s, 32);
- if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
- get_backup_values (b);
- if (strncmp (b->signature, "MPL\0", 4) != 0) {
- puts ("### No HW ID - assuming " BOARD_NAME);
- printf ("-%d Rev %c", var, 'A' + bc);
- } else {
- b->serial_name[sizeof(BOARD_NAME)-1] = 0;
- printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
- 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
- }
- } else {
- s[sizeof(BOARD_NAME)-1] = 0;
- printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
- &s[sizeof(BOARD_NAME)]);
- }
- bc = in8 (PLD_EXT_CONF_REG);
- printf (" Boot Config: 0x%x\n", bc);
- return (0);
-}
-
-
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-/*
- dram_init() reads EEPROM via I2c. EEPROM contains all of
- the necessary info for SDRAM controller configuration
-*/
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-static int test_dram (unsigned long ramsize);
-
-int dram_init(void)
-{
-
- unsigned long bank_reg[4], tmp, bank_size;
- int i;
- unsigned long TotalSize;
-
- /* since the DRAM controller is allready set up, calculate the size with the
- bank registers */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
- TotalSize = 0;
- for (i = 0; i < 4; i++) {
- if ((bank_reg[i] & 0x1) == 0x1) {
- tmp = (bank_reg[i] >> 17) & 0x7;
- bank_size = 4 << tmp;
- TotalSize += bank_size;
- }
- }
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- tmp = mfdcr (SDRAM0_CFGDATA);
-
- if (!tmp)
- printf ("No ");
- printf ("ECC ");
-
- test_dram (TotalSize * MEGA_BYTE);
- gd->ram_size = TotalSize * MEGA_BYTE;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-static int test_dram (unsigned long ramsize)
-{
-#ifdef SDRAM_DEBUG
- mem_test (0L, ramsize, 1);
-#endif
- /* not yet implemented */
- return (1);
-}
-
-/* used to check if the time in RTC is valid */
-static unsigned long start;
-static struct rtc_time tm;
-
-int misc_init_r (void)
-{
- /* adjust flash start and size as well as the offset */
- gd->bd->bi_flashstart=0-flash_info[0].size;
- gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
- gd->bd->bi_flashoffset=0;
-
- /* check, if RTC is running */
- rtc_get (&tm);
- start=get_timer(0);
- /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
- if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
- mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
-
- return (0);
-}
-
-
-void print_mip405_rev (void)
-{
- unsigned char part, vers, pcbrev, var;
-
- get_pcbrev_var(&pcbrev,&var);
- part = in8 (PLD_PART_REG);
- vers = in8 (PLD_VERS_REG);
- printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
- var, pcbrev + 'A', part & 0x7F, vers);
-}
-
-
-extern int mk_date (char *, struct rtc_time *);
-
-int last_stage_init (void)
-{
- unsigned long stop;
- struct rtc_time newtm;
- char *s;
-
- /* write correct LED configuration */
- if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
- printf ("Error writing to the PHY\n");
- }
- /* since LED/CFG2 is not connected on the -2,
- * write to correct capability information */
- if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
- printf ("Error writing to the PHY\n");
- }
- print_mip405_rev ();
- stdio_print_current_devices ();
- check_env ();
- /* check if RTC time is valid */
- stop=get_timer(start);
- while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
- udelay(1000);
- stop=get_timer(start);
- }
- rtc_get (&newtm);
- if(tm.tm_sec==newtm.tm_sec) {
- s=getenv("defaultdate");
- if(!s)
- mk_date ("010112001970", &newtm);
- else
- if(mk_date (s, &newtm)!=0) {
- printf("RTC: Bad date format in defaultdate\n");
- return 0;
- }
- rtc_reset ();
- rtc_set(&newtm);
- }
- return 0;
-}
-
-/***************************************************************************
- * some helping routines
- */
-
-int overwrite_console (void)
-{
- /* return true if console should be overwritten */
- return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0);
-}
-
-
-/************************************************************************
-* Print MIP405 Info
-************************************************************************/
-void print_mip405_info (void)
-{
- unsigned char part, vers, cfg, irq_reg, com_mode, ext;
-
- part = in8 (PLD_PART_REG);
- vers = in8 (PLD_VERS_REG);
- cfg = in8 (PLD_BOARD_CFG_REG);
- irq_reg = in8 (PLD_IRQ_REG);
- com_mode = in8 (PLD_COM_MODE_REG);
- ext = in8 (PLD_EXT_CONF_REG);
-
- printf ("PLD Part %d version %d\n", part & 0x7F, vers);
- printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
- printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
- (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
- printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
- printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
-#if !defined(CONFIG_TARGET_MIP405T)
- printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
- (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
- (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
- (ext >> 6) & 0x1, (ext >> 7) & 0x1);
- printf ("SER1 uses handshakes %s\n",
- (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
-#else
- printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
- (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
- (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
- (ext >> 6) & 0x1,(ext >> 7) & 0x1);
-#endif
- printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
- printf ("IRQs:\n");
- printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
-#if !defined(CONFIG_TARGET_MIP405T)
- printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
- printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
-#endif
- printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
- printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
- printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- /****************************************************************************
- * Global routines used for MIP405
- *****************************************************************************/
-#ifndef __ASSEMBLY__
-/*int switch_cs(unsigned char boot);*/
-
-extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
-
-void user_led0(unsigned char on);
-
-
-#endif
-/* timings */
-/* PLD (CS7) */
-#define PLD_BME 0 /* Burst disable */
-#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define PLD_OEN 1 /* Cycles from CS low to OE low */
-#define PLD_WBN 1 /* Cycles from CS low to WE low */
-#define PLD_WBF 1 /* Cycles from WE high to CS high */
-#define PLD_TH 2 /* Number of hold cycles after transfer */
-#define PLD_RE 0 /* Ready disabled */
-#define PLD_SOR 1 /* Sample on Ready disabled */
-#define PLD_BEM 0 /* Byte Write only active on Write cycles */
-#define PLD_PEN 0 /* Parity disable */
-#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
- (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define PLD_BS 0 /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define PLD_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define PLD_BW 0 /* 16Bit */
-#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
-
-
-/* timings */
-
-#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
-/* Dummy CS to get the board revision */
-#define BOARD_BME 0 /* Burst disable */
-#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define BOARD_OEN 1 /* Cycles from CS low to OE low */
-#define BOARD_WBN 1 /* Cycles from CS low to WE low */
-#define BOARD_WBF 1 /* Cycles from WE high to CS high */
-#define BOARD_TH 2 /* Number of hold cycles after transfer */
-#define BOARD_RE 0 /* Ready disabled */
-#define BOARD_SOR 1 /* Sample on Ready disabled */
-#define BOARD_BEM 0 /* Byte Write only active on Write cycles */
-#define BOARD_PEN 0 /* Parity disable */
-#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
- (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define BOARD_BS 0 /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define BOARD_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define BOARD_BW 0 /* 16Bit */
-#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
-
-
-/* UART0 CS2 */
-#define UART0_BME 0 /* Burst disable */
-#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
-#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define UART0_OEN 1 /* Cycles from CS low to OE low */
-#define UART0_WBN 1 /* Cycles from CS low to WE low */
-#define UART0_WBF 1 /* Cycles from WE high to CS high */
-#define UART0_TH 2 /* Number of hold cycles after transfer */
-#define UART0_RE 0 /* Ready disabled */
-#define UART0_SOR 1 /* Sample on Ready disabled */
-#define UART0_BEM 0 /* Byte Write only active on Write cycles */
-#define UART0_PEN 0 /* Parity disable */
-#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
- (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define UART0_BS 0 /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define UART0_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define UART0_BW 0 /* 8Bit */
-#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
-/* UART1 CS3 */
-#define UART1_AP UART0_AP /* same timing as UART0 */
-#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
-
-/* Flash CS0 or CS 1 */
-/* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B 1 /* Burst enable */
-#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
-#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME 0 /* Burst disable */
-#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define FLASH_OEN 1 /* Cycles from CS low to OE low */
-#define FLASH_WBN 1 /* Cycles from CS low to WE low */
-#define FLASH_WBF 1 /* Cycles from WE high to CS high */
-#define FLASH_TH 2 /* Number of hold cycles after transfer */
-#define FLASH_RE 0 /* Ready disabled */
-#define FLASH_SOR 1 /* Sample on Ready disabled */
-#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
-#define FLASH_PEN 0 /* Parity disable */
-/* Access Parameter Register for non Boot */
-#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
- (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-/* Access Parameter Register for Boot */
-#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
- (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define FLASH_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define FLASH_BW 1 /* 16Bit */
-/* CR register for Boot */
-#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-/* CR register for non Boot */
-#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-
-/* MPS CS1 or CS0 */
-/* Boot CS: */
-#define MPS_BME_B 1 /* Burst enable */
-#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
-#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME 0 /* Burst disable */
-#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define MPS_OEN 1 /* Cycles from CS low to OE low */
-#define MPS_WBN 1 /* Cycles from CS low to WE low */
-#define MPS_WBF 1 /* Cycles from WE high to CS high */
-#define MPS_TH 2 /* Number of hold cycles after transfer */
-#define MPS_RE 0 /* Ready disabled */
-#define MPS_SOR 1 /* Sample on Ready disabled */
-#define MPS_BEM 0 /* Byte Write only active on Write cycles */
-#define MPS_PEN 0 /* Parity disable */
-/* Access Parameter Register for non Boot */
-#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
- (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-/* Access Parameter Register for Boot */
-#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
- (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define MPS_BS 2 /* 4 MByte */
-#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define MPS_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define MPS_BW 0 /* 8Bit */
-/* CR register for Boot */
-#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
-/* CR register for non Boot */
-#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+++ /dev/null
-if TARGET_PIP405
-
-config SYS_BOARD
- default "pip405"
-
-config SYS_VENDOR
- default "mpl"
-
-config SYS_CONFIG_NAME
- default "PIP405"
-
-config ISO_STRING
- string
- default "MEV-10066-001"
-endif
+++ /dev/null
-PIP405 BOARD
-M: Denis Peter <d.peter@mpl.ch>
-S: Maintained
-F: board/mpl/pip405/
-F: include/configs/PIP405.h
-F: configs/PIP405_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pip405.o cmd_pip405.o \
- ../common/pci.o \
- ../common/isa.o \
- ../common/kbd.o \
- ../common/usb_uhci.o \
- ../common/common_util.o
-obj-y += init.o
+++ /dev/null
-U-Boot Changes due to PIP405 Port:
-===================================
-
-Changed files:
-==============
-- MAKEALL added PIP405
-- makefile added PIP405
-- common/Makefile added Floppy disk and SCSI support
-- common/board.c added PIP405, SCSI support, get_PCI_freq()
-- common/bootm.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
-- common/cmd_i2c.c added "defined(CONFIG_PIP405)"
-- common/cmd_ide.c changed div. functions to work with block device
- description
- added ATAPI support
-- common/command.c added SCSI and Floppy support
-- common/console.c replaced // with /* comments
- added console settings from environment
-- common/devices.c added ISA keyboard init
-- common/main.c corrected the read of bootdelay
-- arch/powerpc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405
-- arch/powerpc/cpu/ppc4xx/i2c.c added 16bit read write I2C support
- added page write
-- arch/powerpc/cpu/ppc4xx/speed.c added get_PCI_freq
-- arch/powerpc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING
-- disk/Makefile added part_iso for CD support
-- disk/part.c changed to work with block device description
- added ISO CD support
- added dev_print (was ide_print in cmd_ide.c)
-- disk/part_dos.c changed to work with block device description
-- disk/part_mac.c changed to work with block device description
-- include/ata.h added ATAPI commands
-- include/cmd_bsp.h added PIP405 commands definitions
-- include/cmd_condefs.h added Floppy and SCSI support
-- include/cmd_disk.h changed to work with block device description
-- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_SCSI
-- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_SCSI
-- include/flash.h added INTEL_ID_28F320C3T 0x88C488C4
-- include/i2c.h added "defined(CONFIG_PIP405)"
-- include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
-- include/u-boot.h moved partitions functions definitions to part.h
- added "defined(CONFIG_PIP405)"
- added get_PCI_freq() definition
-- rtc/Makefile added MC146818 RTC support
-- tools/mkimage.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
-
-Added files:
-============
-- board/pip405 directory for PIP405
-- board/pip405/cmd_pip405.c board specific commands
-- board/pip405/config.mk config make
-- board/pip405/flash.c flash support
-- board/pip405/init.s start-up
-- board/pip405/kbd.c keyboard support
-- board/pip405/kbd.h keyboard support
-- board/pip405/Makefile Makefile
-- board/pip405/pci_piix4.h southbridge definitions
-- board/pip405/pci_pip405.c PCI support for PIP405
-- board/pip405/pci_pip405.h PCI support for PIP405
-- board/pip405/pip405.c PIP405 board init
-- board/pip405/pip405.h PIP405 board init
-- board/pip405/pip405_isa.c ISA support
-- board/pip405/pip405_isa.h ISA support
-- board/pip405/u-boot.lds Linker description
-- board/pip405/u-boot.lds.debugLinker description debug
-- board/pip405/sym53c8xx.c SYM53C810A support
-- board/pip405/sym53c8xx_defs.h SYM53C810A definitions
-- board/pip405/vga_table.h definitions of tables for VGA
-- board/pip405/video.c CT69000 support
-- board/pip405/video.h CT69000 support
-- common/cmd_fdc.c Floppy disk support
-- common/cmd_scsi.c SCSI support
-- disk/part_iso.c ISO CD ROM support
-- disk/part_iso.h ISO CD ROM support
-- include/cmd_fdc.h command forFloppy disk support
-- include/cmd_scsi.h command for SCSI support
-- include/part.h partitions functions definitions
- (was part of u-boot.h)
-- include/scsi.h SCSI support
-- rtc/mc146818.c MC146818 RTC support
-
-
-New Config Switches:
-====================
-For detailed description, refer to the corresponding paragraph in the
-section "Changes".
-
-New Commands:
--------------
-CONFIG_SCSI SCSI Support
-CONFIG_CMF_FDC Floppy disk support
-
-IDE additions:
---------------
-CONFIG_IDE_RESET_ROUTINE defines that instead of a reset Pin,
- the routine ide_set_reset(int idereset) is used.
-ATAPI support (experimental)
-----------------------------
-CONFIG_ATAPI enables ATAPI Support
-
-SCSI support (experimental) only SYM53C8xx supported
-----------------------------------------------------
-CONFIG_SCSI_SYM53C8XX type of SCSI controller
-CONFIG_SYS_SCSI_MAX_LUN 8 number of supported LUNs
-CONFIG_SYS_SCSI_MAX_SCSI_ID 7 maximum SCSI ID (0..6)
-CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN
- maximum of Target devices (multiple LUN support
- for boot)
-
-ISO (CD-Boot) partition support (Experimental)
-----------------------------------------------
-CONFIG_ISO_PARTITION CD-boot support
-
-RTC
-----
-CONFIG_RTC_MC146818 MC146818 RTC support
-
-Video:
-------
-CONFIG_VIDEO_CT69000 Enable Chips & Technologies 69000 Video chip
- CONFIG_VIDEO must be defined also
-
-External peripheral base address:
----------------------------------
-CONFIG_SYS_ISA_IO_BASE_ADDRESS address of all ISA-bus related parts
- _must_ be defined for ISA-bus parts
-
-Identify:
----------
-CONFIG_IDENT_STRING added to the U_BOOT_VERSION String
-
-Environment / Console:
-----------------------
-
-CONFIG_SYS_CONSOLE_IS_IN_ENV if defined, stdin, stdout and stderr used from
- the values stored in the evironment.
-
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE if defined, console_overwrite() decides if the
- values stored in the environment or the standard
- serial in/out put should be assigned to the console.
-
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE if defined, the start-up console switching
- are stored in the environment.
-
-PIP405 specific:
-----------------
-CONFIG_PORT_ADDR address used to read boot configuration
-MULTI_PURPOSE_SOCKET_ADDR address of the multi purpose socked
-SDRAM_EEPROM_WRITE_ADDRESS addresses of the serial presence detect
-SDRAM_EEPROM_READ_ADDRESS EEPROM on the SDRAM module.
-
-
-Changes:
-========
-
-Added Devices:
-==============
-
-Floppy support:
----------------
-Support of a standard floppy disk controller at address CONFIG_SYS_ISA_IO_BASE_ADDRESS
-+ 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk
-with a image header (see: mkimage). No interrupts and no DMA are used for this.
-Added files:
-- common/cmd_fdc.c
-- include/cmd_fdc.h
-
-SCSI support:
--------------
-Support for Symbios SYM53C810A chip. Implemented as follows:
-- without disconnect
-- only asynchrounous
-- multiple LUN support (caution, needs a lot of RAM. define CONFIG_SYS_SCSI_MAX_LUN 1 to
- save RAM)
-- multiple SCSI ID support
-- no write support
-- analyses the MAC, DOS and ISO pratition similar to the IDE support
-- allows booting from SCSI devices similar to the IDE support.
-The device numbers are not assigned like they are within the IDE support. The first
-device found will get the number 0, the next 1 etc. If all SCSI IDs (0..6) and all
-LUNs (8) are enabled, 56 boot devices are possible. This uses a lot of RAM since the
-device descriptors are not yet dynamically allocated. 56 boot devices are overkill
-anyway. Please refer to the section "Todo" chapter "block device support enhancement".
-The SYM53C810A uses 1 Interrupt and must be able of mastering the PCI bus.
-Added files:
-- common/cmd_scsi.c
-- common/board.c
-- include/cmd_scsi.h
-- include/scsi.h
-- board/pip405/sym53c8xx.c
-- board/pip405/sym53c8xx_defs.h
-
-ATAPI support (IDE changes):
-----------------------------
-Added ATAPI support (with CONFIG_ATAPI) in the file cmd_ide.c.
-To support a hardreset, when the IDE reset pin is not connected to the
-CONFIG_SYS_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When
-this switch is enabled the routine void ide_set_reset(int idereset) must be
-within the board specific files.
-Only read from ATAPI devices are supported.
-Found out that the function trim_trail cuts off the last character if the whole
-string is filled. Added function cpy_ident instead, which trims also leading
-spaces and copies the string in the buffer.
-Changed files:
-- common/cmd_ide.c
-- include/ata.h
-
-ISO partition support:
-----------------------
-Added CD boot support for El-Torito bootable ISO CDs. The bootfile image must contain
-the U-Boot image header. Since CDs do not have "partitions", the boot partition is 0.
-The bootcatalog feature has not been tested so far. CD Boot is supported for ATAPI
-("diskboot") and SCSI ("scsiboot") devices.
-Added files:
-- disk/iso_part.c
-- disk/iso_part.h
-
-Block device changes:
----------------------
-To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter
-blk_desc will be used when accessing the functions in these files. The block
-device descriptor (blk_desc) contains a pointer to the read routine of the
-device, which will be used to read blocks from the device.
-Renamed function ide_print to dev_print and moved it to the file disk/part.c to use
-it for IDE ATAPI and SCSI devices.
-Please refer to the section "Todo" chapter "block device support enhancement".
-Added files:
-- include/part.h
-changed files:
-- disk/dos_part.c
-- disk/dos_part.h
-- disk/mac_part.c
-- disk/mac_part.h
-- disk/part.c
-- common/cmd_ide.c
-- include/u-boot.h
-
-
-MC146818 RTC support:
----------------------
-Added support for MC146818 RTC with defining CONFIG_RTC_MC146818. The ISA bus IO
-base address must be defined with CONFIG_SYS_ISA_IO_BASE_ADDRESS.
-Added files:
-- rtc/mc146818.c
-
-Standard ISA bus Keyboard support:
-----------------------------------
-Added support for the standard PC kyeboard controller. For the PIP405 the superIO
-controller must be set up previously. The keyboard uses the standard ISA IRQ, so
-the ISA PIC must also be set up.
-Added files:
-- board/pip405/kbd.c
-- board/pip405/kbd.h
-- board/pip405/pip405_isa.c
-- board/pip405/pip405_isa.h
-
-Chips and Technologie 69000 VGA controller support:
----------------------------------------------------
-Added support for the CT69000 VGA controller.
-Added files:
-- board/pip405/video.c
-- board/pip405/video.h
-- board/pip405/vga_table.h
-
-
-Changed Items:
-==============
-
-Identify:
----------
-Added the config variable CONFIG_IDENT_STRING which will be added to the
-"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate
-and custom versions.
-Changed files:
-- arch/powerpc/cpu/ppc4xx/start.s
-
-Firmware Image:
----------------
-Added IH_OS_U_BOOT and IH_TYPE_FIRMWARE to the image definitions to allows the
-U-Boot update with prior CRC check.
-Changed files:
-- include/image.h
-- tools/mkimage.c
-- common/cmd_bootm.c
-
-Correct PCI Frequency for PPC405:
----------------------------------
-Added function (in arch/powerpc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
-The PCI Frequency will now be set correct in the board description in common/board.c.
-(was set to the busfreq before).
-Changed files:
-- arch/powerpc/cpu/ppc4xx/speed.c
-- common/board.c
-
-I2C Stuff:
-----------
-Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c.
-Added 16bit read/write support for I2C (PPC405), and page write to
-I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE.
-Changed files:
-- arch/powerpc/cpu/ppc4xx/i2c.c
-- common/cmd_i2c.c
-
-Environment / Console:
-----------------------
-Although in README.console described, the U-Boot has not assinged the values
-found in the environment to the console. Corrected this behavior, but only if
-CONFIG_SYS_CONSOLE_IS_IN_ENV is defined.
-If CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the
-values stored in the environment or the standard serial in/output should be
-assigned to the console. This is useful if the environment values are not correct.
-If CONFIG_SYS_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at
-start-up time will be written to the environment. This means that if the
-environment values are overwritten by the overwrite_console() routine, they will be
-stored in the environment.
-Changed files:
-- common/console.c
-
-Correct bootdelay intepretation:
---------------------------------
-Changed bootdelay read from the environment from simple_strtoul (unsigned) to
-simple_strtol (signed), to be able to get a bootdelay of -1.
-Changed files:
-- common/main.c
-
-Todo:
-=====
-
-Block device support enhancement:
----------------------------------
-Consider to unify the block device handling. Instead of using diskboot for IDE,
-scsiboot for SCSI and fdcboot for floppy disks, it would make sense to use only
-one command ("devboot" ???) with a parameter of the desired device ("hda1", "sda1",
-"fd0" ???) to boot from. The other ide commands can be handled in the same way
-("dev hda read.." instead of "ide read.." or "dev sda read.." instead of
-"scsi read..."). Todo this, a common way of assign a block device to its name
-(first found ide device = hda, second found hdb etc., or hda is device 0 on bus 0,
-hdb is device 1 on bus 0 etc.) as well as the names (hdx for ide, sdx for scsi, fx for
-floppy ???) must be defined.
-Maybe there are better ideas to do this.
-
-Console assingment:
--------------------
-Consider to initialize and assign the console stdin, stdout and stderr as soon as
-possible to see the boot messages also on an other console than serial.
-
-
-Todo for PIP405:
-================
-
-LCD support for VGA:
---------------------
-Add LCD support for the CT69000
-
-Default environment:
---------------------
-Consider to write a default environment to the OTP part of the EEPROM and use it
-if the normal environment is not valid. Useful for serial# and ethaddr values.
-
-Watchdog:
----------
-Implement Watchdog.
-
-Files clean-up:
----------------
-Following files needs to be cleaned up:
-- cmd_pip405.c
-- flash.c
-- pci_pip405.c
-- pip405.c
-- pip405_isa.c
-Consider to split up the files in their functions.
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * hacked for PIP405
- */
-
-#include <common.h>
-#include <command.h>
-#include "pip405.h"
-#include "../common/common_util.h"
-
-
-extern void print_pip405_info(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-
-/* ------------------------------------------------------------------------- */
-
-int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-
- ulong led_on,led_nr;
-
- if (strcmp(argv[1], "info") == 0)
- {
- print_pip405_info();
- return 0;
- }
- if (strcmp(argv[1], "led") == 0)
- {
- led_nr = (ulong)simple_strtoul(argv[2], NULL, 10);
- led_on = (ulong)simple_strtoul(argv[3], NULL, 10);
- if(!led_nr)
- user_led0(led_on);
- else
- user_led1(led_on);
- return 0;
- }
-
- return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-U_BOOT_CMD(
- pip405, 6, 1, do_pip405,
- "PIP405 specific Cmds",
- "flash mem [SrcAddr] - updates U-Boot with image in memory\n"
- "pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n"
- "pip405 flash mps - updates U-Boot with image from MPS"
-);
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*-----------------------------------------------------------------------------
- * Function: ext_bus_cntlr_init
- * Description: Initializes the External Bus Controller for the external
- * peripherals. IMPORTANT: For pass1 this code must run from
- * cache since you can not reliably change a peripheral banks
- * timing register (pbxap) while running code from that bank.
- * For ex., since we are running from ROM on bank 0, we can NOT
- * execute the code that modifies bank 0 timings from ROM, so
- * we run it from cache.
- * Bank 0 - Flash or Multi Purpose Socket
- * Bank 1 - Multi Purpose Socket or Flash
- * Bank 2 - not used
- * Bank 3 - not used
- * Bank 4 - not used
- * Bank 5 - not used
- * Bank 6 - used to switch on the 12V for the Multipurpose socket
- * Bank 7 - Config Register
- *-----------------------------------------------------------------------------*/
-
-#include <configs/PIP405.h>
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-#include "pip405.h"
-
- .globl ext_bus_cntlr_init
- ext_bus_cntlr_init:
- mflr r4 /* save link register */
- mfdcr r3,CPC0_PSR /* get strapping reg */
- andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
- bnelr /* jump back if PCI boot */
-
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 14; used to prefetch */
- mtctr r4 /* 14 cache lines to fit this function */
- /* in cache (gives us 8x14=112 instrctns) */
-..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 14 cache lines */
-
- /*-------------------------------------------------------------------
- * Delay to ensure all accesses to ROM are complete before changing
- * bank 0 timings.
- *------------------------------------------------------------------- */
- addis r3,0,0x0
- ori r3,r3,0xA000
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /*-----------------------------------------------------------------------
- * decide boot up mode
- *----------------------------------------------------------------------- */
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- mfdcr r4,EBC0_CFGDATA
-
- andi. r0, r4, 0x2000 /* mask out irrelevant bits */
- beq 0f /* jump if 8 bit bus width */
-
- /* setup 16 bit things
- *-----------------------------------------------------------------------
- * Memory Bank 0 (16 Bit Flash) initialization
- *---------------------------------------------------------------------- */
-
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,(FLASH_AP_B)@h
- ori r4,r4,(FLASH_AP_B)@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- /* BS=0x010(4MB),BU=0x3(R/W), */
- addis r4,0,(FLASH_CR_B)@h
- ori r4,r4,(FLASH_CR_B)@l
- mtdcr EBC0_CFGDATA,r4
- b 1f
-
-0:
- /* 8Bit boot mode: */
- /*-----------------------------------------------------------------------
- * Memory Bank 0 Multi Purpose Socket initialization
- *----------------------------------------------------------------------- */
- /* 0x7F8FFE80 slowest boot */
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,(MPS_AP_B)@h
- ori r4,r4,(MPS_AP_B)@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- /* BS=0x010(4MB),BU=0x3(R/W), */
- addis r4,0,(MPS_CR_B)@h
- ori r4,r4,(MPS_CR_B)@l
- mtdcr EBC0_CFGDATA,r4
-
-
-1:
- /*-----------------------------------------------------------------------
- * Memory Bank 2-3-4-5-6 (not used) initialization
- *-----------------------------------------------------------------------*/
- addi r4,0,PB1CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB2CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB3CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB4CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB5CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB6CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB7CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
- nop /* pass2 DCR errata #8 */
- blr
-
-#if defined(CONFIG_BOOT_PCI)
- .section .bootpg,"ax"
- .globl _start_pci
-/*******************************************
- */
-
-_start_pci:
- /* first handle errata #68 / PCI_18 */
- iccci r0, r0 /* invalidate I-cache */
- lis r31, 0
- mticcr r31 /* ICCR = 0 (all uncachable) */
- isync
-
- mfccr0 r28 /* set CCR0[24] = 1 */
- ori r28, r28, 0x0080
- mtccr0 r28
-
- /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
- lis r28, 0xEF40
- addi r28, r28, 0x0004
- stw r31, 0x0C(r28) /* clear PMM0PCIHA */
- lis r29, 0xFFF8 /* open 512 kByte */
- addi r29, r29, 0x0001/* and enable this region */
- stwbrx r29, r0, r28 /* write PMM0MA */
-
- lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
- addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
-
- lis r31, 0x8000 /* set en bit bus 0 */
- ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
- stwbrx r31, r0, r28 /* write it */
-
- lwbrx r31, r0, r29 /* load XBCS register */
- oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
- stwbrx r31, r0, r29 /* write back XBCS register */
-
- nop
- nop
- b _start /* normal start */
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * TODO: clean-up
- */
-
-#include <common.h>
-#include "pip405.h"
-#include <asm/processor.h>
-#include <i2c.h>
-#include <stdio_dev.h>
-#include "../common/isa.h"
-#include "../common/common_util.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef SDRAM_DEBUG
-
-/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
-#ifndef __ldiv_t_defined
-typedef struct {
- long int quot; /* Quotient */
- long int rem; /* Remainder */
-} ldiv_t;
-extern ldiv_t ldiv (long int __numer, long int __denom);
-
-# define __ldiv_t_defined 1
-#endif
-
-
-typedef enum {
- SDRAM_NO_ERR,
- SDRAM_SPD_COMM_ERR,
- SDRAM_SPD_CHKSUM_ERR,
- SDRAM_UNSUPPORTED_ERR,
- SDRAM_UNKNOWN_ERR
-} SDRAM_ERR;
-
-typedef struct {
- const unsigned char mode;
- const unsigned char row;
- const unsigned char col;
- const unsigned char bank;
-} SDRAM_SETUP;
-
-static const SDRAM_SETUP sdram_setup_table[] = {
- {1, 11, 9, 2},
- {1, 11, 10, 2},
- {2, 12, 9, 4},
- {2, 12, 10, 4},
- {3, 13, 9, 4},
- {3, 13, 10, 4},
- {3, 13, 11, 4},
- {4, 12, 8, 2},
- {4, 12, 8, 4},
- {5, 11, 8, 2},
- {5, 11, 8, 4},
- {6, 13, 8, 2},
- {6, 13, 8, 4},
- {7, 13, 9, 2},
- {7, 13, 10, 2},
- {0, 0, 0, 0}
-};
-
-static const unsigned char cal_indextable[] = {
- 9, 23, 25
-};
-
-
-/*
- * translate ns.ns/10 coding of SPD timing values
- * into 10 ps unit values
- */
-
-unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
-{
- unsigned short ns, ns10;
-
- /* isolate upper nibble */
- ns = (spd_byte >> 4) & 0x0F;
- /* isolate lower nibble */
- ns10 = (spd_byte & 0x0F);
-
- return (ns * 100 + ns10 * 10);
-}
-
-/*
- * translate ns.ns/4 coding of SPD timing values
- * into 10 ps unit values
- */
-
-unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
-{
- unsigned short ns, ns4;
-
- /* isolate upper 6 bits */
- ns = (spd_byte >> 2) & 0x3F;
- /* isloate lower 2 bits */
- ns4 = (spd_byte & 0x03);
-
- return (ns * 100 + ns4 * 25);
-}
-
-/*
- * translate ns coding of SPD timing values
- * into 10 ps unit values
- */
-
-unsigned short NSto10PS (unsigned char spd_byte)
-{
- return (spd_byte * 100);
-}
-
-void SDRAM_err (const char *s)
-{
-#ifndef SDRAM_DEBUG
- (void) get_clocks ();
- gd->baudrate = 9600;
- serial_init ();
-#endif
- serial_puts ("\n");
- serial_puts (s);
- serial_puts ("\n enable SDRAM_DEBUG for more info\n");
- for (;;);
-}
-
-
-#ifdef SDRAM_DEBUG
-
-void write_hex (unsigned char i)
-{
- char cc;
-
- cc = i >> 4;
- cc &= 0xf;
- if (cc > 9)
- serial_putc (cc + 55);
- else
- serial_putc (cc + 48);
- cc = i & 0xf;
- if (cc > 9)
- serial_putc (cc + 55);
- else
- serial_putc (cc + 48);
-}
-
-void write_4hex (unsigned long val)
-{
- write_hex ((unsigned char) (val >> 24));
- write_hex ((unsigned char) (val >> 16));
- write_hex ((unsigned char) (val >> 8));
- write_hex ((unsigned char) val);
-}
-
-#endif
-
-int board_early_init_f (void)
-{
- unsigned char datain[128];
- unsigned long sdram_size = 0;
- SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
- unsigned long memclk;
- unsigned long tmemclk = 0;
- unsigned long tmp, bank, baseaddr, bank_size;
- unsigned short i;
- unsigned char rows, cols, banks, sdram_banks, density;
- unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
- trc_clocks;
- unsigned char cal_index, cal_val, spd_version, spd_chksum;
- unsigned char buf[8];
-#ifdef SDRAM_DEBUG
- unsigned char tctp_clocks;
-#endif
-
- /* set up the config port */
- mtdcr (EBC0_CFGADDR, PB7AP);
- mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
- mtdcr (EBC0_CFGADDR, PB7CR);
- mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR);
-
- memclk = get_bus_freq (tmemclk);
- tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
-
-#ifdef SDRAM_DEBUG
- (void) get_clocks ();
- gd->baudrate = 9600;
- serial_init ();
- serial_puts ("\nstart SDRAM Setup\n");
-#endif
-
- /* Read Serial Presence Detect Information */
- i2c_set_bus_num(0);
- for (i = 0; i < 128; i++)
- datain[i] = 127;
- i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
-#ifdef SDRAM_DEBUG
- serial_puts ("\ni2c_read returns ");
- write_hex (i);
- serial_puts ("\n");
-#endif
-
-#ifdef SDRAM_DEBUG
- for (i = 0; i < 128; i++) {
- write_hex (datain[i]);
- serial_puts (" ");
- if (((i + 1) % 16) == 0)
- serial_puts ("\n");
- }
- serial_puts ("\n");
-#endif
- spd_chksum = 0;
- for (i = 0; i < 63; i++) {
- spd_chksum += datain[i];
- } /* endfor */
- if (datain[63] != spd_chksum) {
-#ifdef SDRAM_DEBUG
- serial_puts ("SPD chksum: 0x");
- write_hex (datain[63]);
- serial_puts (" != calc. chksum: 0x");
- write_hex (spd_chksum);
- serial_puts ("\n");
-#endif
- SDRAM_err ("SPD checksum Error");
- }
- /* SPD seems to be ok, use it */
-
- /* get SPD version */
- spd_version = datain[62];
-
- /* do some sanity checks on the kind of RAM */
- if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */
- (datain[2] != 0x04) || /* if not SDRAM */
- (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
- (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */
- (datain[126] == 0x66)) /* or a 66MHz modules */
- SDRAM_err ("unsupported SDRAM");
-#ifdef SDRAM_DEBUG
- serial_puts ("SDRAM sanity ok\n");
-#endif
-
- /* get number of rows/cols/banks out of byte 3+4+5 */
- rows = datain[3];
- cols = datain[4];
- banks = datain[5];
-
- /* get number of SDRAM banks out of byte 17 and
- supported CAS latencies out of byte 18 */
- sdram_banks = datain[17];
- supported_cal = datain[18] & ~0x81;
-
- while (t->mode != 0) {
- if ((t->row == rows) && (t->col == cols)
- && (t->bank == sdram_banks))
- break;
- t++;
- } /* endwhile */
-
-#ifdef SDRAM_DEBUG
- serial_puts ("rows: ");
- write_hex (rows);
- serial_puts (" cols: ");
- write_hex (cols);
- serial_puts (" banks: ");
- write_hex (banks);
- serial_puts (" mode: ");
- write_hex (t->mode);
- serial_puts ("\n");
-#endif
- if (t->mode == 0)
- SDRAM_err ("unsupported SDRAM");
- /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
-#ifdef SDRAM_DEBUG
- serial_puts ("tRP: ");
- write_hex (datain[27]);
- serial_puts ("\ntRCD: ");
- write_hex (datain[29]);
- serial_puts ("\ntRAS: ");
- write_hex (datain[30]);
- serial_puts ("\n");
-#endif
-
- trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
- trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
- tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
- density = datain[31];
-
- /* trc_clocks is sum of trp_clocks + tras_clocks */
- trc_clocks = trp_clocks + tras_clocks;
-
-#ifdef SDRAM_DEBUG
- /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
- tctp_clocks =
- ((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
- (tmemclk - 1)) / tmemclk;
-
- serial_puts ("c_RP: ");
- write_hex (trp_clocks);
- serial_puts ("\nc_RCD: ");
- write_hex (trcd_clocks);
- serial_puts ("\nc_RAS: ");
- write_hex (tras_clocks);
- serial_puts ("\nc_RC: (RP+RAS): ");
- write_hex (trc_clocks);
- serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
- write_hex (tctp_clocks);
- serial_puts ("\nt_CTP: RAS - RCD: ");
- write_hex ((unsigned
- char) ((NSto10PS (datain[30]) -
- NSto10PS (datain[29])) >> 8));
- write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
- serial_puts ("\ntmemclk: ");
- write_hex ((unsigned char) (tmemclk >> 8));
- write_hex ((unsigned char) (tmemclk));
- serial_puts ("\n");
-#endif
-
-
- cal_val = 255;
- for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
- /* is this CAS latency supported ? */
- if ((supported_cal >> i) & 0x01) {
- buf[0] = datain[cal_indextable[cal_index]];
- if (cal_index < 2) {
- if (NS10to10PS (buf[0], spd_version) <= tmemclk)
- cal_val = i;
- } else {
- /* SPD bytes 25+26 have another format */
- if (NS4to10PS (buf[0], spd_version) <= tmemclk)
- cal_val = i;
- } /* endif */
- cal_index++;
- } /* endif */
- } /* endfor */
-#ifdef SDRAM_DEBUG
- serial_puts ("CAL: ");
- write_hex (cal_val + 1);
- serial_puts ("\n");
-#endif
-
- if (cal_val == 255)
- SDRAM_err ("unsupported SDRAM");
-
- /* get SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
- /* insert CASL value */
-/* tmp |= ((unsigned long)cal_val) << 23; */
- tmp |= ((unsigned long) cal_val) << 23;
- /* insert PTA value */
- tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
- /* insert CTP value */
-/* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
- tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
- /* insert LDF (always 01) */
- tmp |= ((unsigned long) 0x01) << 14;
- /* insert RFTA value */
- tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
- /* insert RCD value */
- tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
-
-#ifdef SDRAM_DEBUG
- serial_puts ("sdtr: ");
- write_4hex (tmp);
- serial_puts ("\n");
-#endif
-
- /* write SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- mtdcr (SDRAM0_CFGDATA, tmp);
- baseaddr = CONFIG_SYS_SDRAM_BASE;
- bank_size = (((unsigned long) density) << 22) / 2;
- /* insert AM value */
- tmp = ((unsigned long) t->mode - 1) << 13;
- /* insert SZ value; */
- switch (bank_size) {
- case 0x00400000:
- tmp |= ((unsigned long) 0x00) << 17;
- break;
- case 0x00800000:
- tmp |= ((unsigned long) 0x01) << 17;
- break;
- case 0x01000000:
- tmp |= ((unsigned long) 0x02) << 17;
- break;
- case 0x02000000:
- tmp |= ((unsigned long) 0x03) << 17;
- break;
- case 0x04000000:
- tmp |= ((unsigned long) 0x04) << 17;
- break;
- case 0x08000000:
- tmp |= ((unsigned long) 0x05) << 17;
- break;
- case 0x10000000:
- tmp |= ((unsigned long) 0x06) << 17;
- break;
- default:
- SDRAM_err ("unsupported SDRAM");
- } /* endswitch */
- /* get SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
- bank |= (baseaddr | tmp | 0x01);
-#ifdef SDRAM_DEBUG
- serial_puts ("bank0: baseaddr: ");
- write_4hex (baseaddr);
- serial_puts (" banksize: ");
- write_4hex (bank_size);
- serial_puts (" mb0cf: ");
- write_4hex (bank);
- serial_puts ("\n");
-#endif
- baseaddr += bank_size;
- sdram_size += bank_size;
-
- /* write SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- mtdcr (SDRAM0_CFGDATA, bank);
-
- /* get SDRAM bank 1 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
- sdram_size = 0;
-
-#ifdef SDRAM_DEBUG
- serial_puts ("bank1: baseaddr: ");
- write_4hex (baseaddr);
- serial_puts (" banksize: ");
- write_4hex (bank_size);
-#endif
- if (banks == 2) {
- bank |= (baseaddr | tmp | 0x01);
- baseaddr += bank_size;
- sdram_size += bank_size;
- } /* endif */
-#ifdef SDRAM_DEBUG
- serial_puts (" mb1cf: ");
- write_4hex (bank);
- serial_puts ("\n");
-#endif
- /* write SDRAM bank 1 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- mtdcr (SDRAM0_CFGDATA, bank);
-
- /* get SDRAM bank 2 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
-
- bank |= (baseaddr | tmp | 0x01);
-
-#ifdef SDRAM_DEBUG
- serial_puts ("bank2: baseaddr: ");
- write_4hex (baseaddr);
- serial_puts (" banksize: ");
- write_4hex (bank_size);
- serial_puts (" mb2cf: ");
- write_4hex (bank);
- serial_puts ("\n");
-#endif
-
- baseaddr += bank_size;
- sdram_size += bank_size;
-
- /* write SDRAM bank 2 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- mtdcr (SDRAM0_CFGDATA, bank);
-
- /* get SDRAM bank 3 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
-
-#ifdef SDRAM_DEBUG
- serial_puts ("bank3: baseaddr: ");
- write_4hex (baseaddr);
- serial_puts (" banksize: ");
- write_4hex (bank_size);
-#endif
-
- if (banks == 2) {
- bank |= (baseaddr | tmp | 0x01);
- baseaddr += bank_size;
- sdram_size += bank_size;
- }
- /* endif */
-#ifdef SDRAM_DEBUG
- serial_puts (" mb3cf: ");
- write_4hex (bank);
- serial_puts ("\n");
-#endif
-
- /* write SDRAM bank 3 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- mtdcr (SDRAM0_CFGDATA, bank);
-
-
- /* get SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
-
- if (tmemclk < NSto10PS (16))
- tmp |= 0x05F00000;
- else
- tmp |= 0x03F80000;
-
- /* write SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- mtdcr (SDRAM0_CFGDATA, tmp);
-
- /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, tmp);
-
-
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the PIP405 board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
- | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
- | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
- | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
- | Note for PIP405 board:
- | An interrupt taken for the SouthBridge (IRQ 25) indicates that
- | the Interrupt Controller in the South Bridge has caused the
- | interrupt. The IC must be read to determine which device
- | caused the interrupt.
- |
- +-------------------------------------------------------------------------*/
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
- mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- int mode;
-
- /*
- * since we are relocated, we can finally enable i-cache
- * and set up the flash CS correctly
- */
- icache_enable();
- setup_cs_reloc();
- /* get and display boot mode */
- mode = get_boot_mode();
- if (mode & BOOT_PCI)
- printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
- "MPS" : "Flash");
- else
- printf("%s Boot\n", (mode & BOOT_MPS) ?
- "MPS" : "Flash");
-
- return 0;
-}
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char s[50];
- unsigned char bc;
- int i;
- backup_t *b = (backup_t *) s;
-
- puts ("Board: ");
-
- i = getenv_f("serial#", (char *)s, 32);
- if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
- get_backup_values (b);
- if (strncmp (b->signature, "MPL\0", 4) != 0) {
- puts ("### No HW ID - assuming PIP405");
- } else {
- b->serial_name[6] = 0;
- printf ("%s SN: %s", b->serial_name,
- &b->serial_name[7]);
- }
- } else {
- s[6] = 0;
- printf ("%s SN: %s", s, &s[7]);
- }
- bc = in8 (CONFIG_PORT_ADDR);
- printf (" Boot Config: 0x%x\n", bc);
- return (0);
-}
-
-
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-/*
- dram_init() reads EEPROM via I2c. EEPROM contains all of
- the necessary info for SDRAM controller configuration
-*/
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-static int test_dram (unsigned long ramsize);
-
-int dram_init(void)
-{
- unsigned long bank_reg[4], tmp, bank_size;
- int i, ds;
- unsigned long TotalSize;
-
- ds = 0;
- /* since the DRAM controller is allready set up,
- * calculate the size with the bank registers
- */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
- TotalSize = 0;
- for (i = 0; i < 4; i++) {
- if ((bank_reg[i] & 0x1) == 0x1) {
- tmp = (bank_reg[i] >> 17) & 0x7;
- bank_size = 4 << tmp;
- TotalSize += bank_size;
- } else
- ds = 1;
- }
- if (ds == 1)
- printf ("single-sided DIMM ");
- else
- printf ("double-sided DIMM ");
- test_dram (TotalSize * 1024 * 1024);
- /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
- (void) get_clocks();
- if (gd->cpu_clk > 220000000)
- TotalSize /= 2;
- gd->ram_size = TotalSize * 1024 * 1024;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-static int test_dram (unsigned long ramsize)
-{
- /* not yet implemented */
- return (1);
-}
-
-int misc_init_r (void)
-{
- /* adjust flash start and size as well as the offset */
- gd->bd->bi_flashstart=0-flash_info[0].size;
- gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
- gd->bd->bi_flashoffset=0;
-
- /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
- if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
- mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
-
- return (0);
-}
-
-/***************************************************************************
- * some helping routines
- */
-
-int overwrite_console (void)
-{
- /* return true if console should be overwritten */
- return in8(CONFIG_PORT_ADDR) & 0x1;
-}
-
-
-extern int isa_init (void);
-
-
-void print_pip405_rev (void)
-{
- unsigned char part, vers, cfg;
-
- part = in8 (PLD_PART_REG);
- vers = in8 (PLD_VERS_REG);
- cfg = in8 (PLD_BOARD_CFG_REG);
- printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
- 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
- vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
-}
-
-extern void check_env(void);
-
-
-int last_stage_init (void)
-{
- print_pip405_rev ();
- isa_init ();
- stdio_print_current_devices ();
- check_env();
- return 0;
-}
-
-/************************************************************************
-* Print PIP405 Info
-************************************************************************/
-void print_pip405_info (void)
-{
- unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
- compwr, nicvga, scsirst;
-
- part = in8 (PLD_PART_REG);
- vers = in8 (PLD_VERS_REG);
- cfg = in8 (PLD_BOARD_CFG_REG);
- ledu = in8 (PLD_LED_USER_REG);
- sysman = in8 (PLD_SYS_MAN_REG);
- flashcom = in8 (PLD_FLASH_COM_REG);
- can = in8 (PLD_CAN_REG);
- serpwr = in8 (PLD_SER_PWR_REG);
- compwr = in8 (PLD_COM_PWR_REG);
- nicvga = in8 (PLD_NIC_VGA_REG);
- scsirst = in8 (PLD_SCSI_RST_REG);
- printf ("PLD Part %d version %d\n",
- part & 0xf, vers & 0xf);
- printf ("PLD Part %d version %d\n",
- (part >> 4) & 0xf, (vers >> 4) & 0xf);
- printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
- printf ("Population Options %d %d %d %d\n",
- (cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
- (cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
- printf ("User LED0 %s User LED1 %s\n",
- ((ledu & 0x1) == 0x1) ? "on" : "off",
- ((ledu & 0x2) == 0x2) ? "on" : "off");
- printf ("Additionally Options %d %d\n",
- (ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
- printf ("User Config Switch %d %d %d %d\n",
- (ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
- (ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
- switch (sysman & 0x3) {
- case 0:
- printf ("PCI Clocks are running\n");
- break;
- case 1:
- printf ("PCI Clocks are stopped in POS State\n");
- break;
- case 2:
- printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
- break;
- case 3:
- printf ("PCI Clocks are stopped\n");
- break;
- }
- switch ((sysman >> 2) & 0x3) {
- case 0:
- printf ("Main Clocks are running\n");
- break;
- case 1:
- printf ("Main Clocks are stopped in POS State\n");
- break;
- case 2:
- case 3:
- printf ("PCI Clocks are stopped\n");
- break;
- }
- printf ("INIT asserts %sINT2# (SMI)\n",
- ((sysman & 0x10) == 0x10) ? "" : "not ");
- printf ("INIT asserts %sINT1# (NMI)\n",
- ((sysman & 0x20) == 0x20) ? "" : "not ");
- printf ("INIT occurred %d\n", (sysman >> 6) & 0x1);
- printf ("SER1 is routed to %s\n",
- ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
- printf ("COM2 is routed to %s\n",
- ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
- printf ("RS485 is configured as %s duplex\n",
- ((flashcom & 0x4) == 0x4) ? "full" : "half");
- printf ("RS485 is connected to %s\n",
- ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
- printf ("SER1 uses handshakes %s\n",
- ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
- printf ("Bootflash is %swriteprotected\n",
- ((flashcom & 0x20) == 0x20) ? "not " : "");
- printf ("Bootflash VPP is %s\n",
- ((flashcom & 0x40) == 0x40) ? "on" : "off");
- printf ("Bootsector is %swriteprotected\n",
- ((flashcom & 0x80) == 0x80) ? "not " : "");
- switch ((can) & 0x3) {
- case 0:
- printf ("CAN Controller is on address 0x1000..0x10FF\n");
- break;
- case 1:
- printf ("CAN Controller is on address 0x8000..0x80FF\n");
- break;
- case 2:
- printf ("CAN Controller is on address 0xE000..0xE0FF\n");
- break;
- case 3:
- printf ("CAN Controller is disabled\n");
- break;
- }
- switch ((can >> 2) & 0x3) {
- case 0:
- printf ("CAN Controller Reset is ISA Reset\n");
- break;
- case 1:
- printf ("CAN Controller Reset is ISA Reset and POS State\n");
- break;
- case 2:
- case 3:
- printf ("CAN Controller is in reset\n");
- break;
- }
- if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
- printf ("CAN Interrupt is disabled\n");
- else
- printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
- switch (serpwr & 0x3) {
- case 0:
- printf ("SER0 Drivers are enabled\n");
- break;
- case 1:
- printf ("SER0 Drivers are disabled in the POS state\n");
- break;
- case 2:
- case 3:
- printf ("SER0 Drivers are disabled\n");
- break;
- }
- switch ((serpwr >> 2) & 0x3) {
- case 0:
- printf ("SER1 Drivers are enabled\n");
- break;
- case 1:
- printf ("SER1 Drivers are disabled in the POS state\n");
- break;
- case 2:
- case 3:
- printf ("SER1 Drivers are disabled\n");
- break;
- }
- switch (compwr & 0x3) {
- case 0:
- printf ("COM1 Drivers are enabled\n");
- break;
- case 1:
- printf ("COM1 Drivers are disabled in the POS state\n");
- break;
- case 2:
- case 3:
- printf ("COM1 Drivers are disabled\n");
- break;
- }
- switch ((compwr >> 2) & 0x3) {
- case 0:
- printf ("COM2 Drivers are enabled\n");
- break;
- case 1:
- printf ("COM2 Drivers are disabled in the POS state\n");
- break;
- case 2:
- case 3:
- printf ("COM2 Drivers are disabled\n");
- break;
- }
- switch ((nicvga) & 0x3) {
- case 0:
- printf ("PHY is running\n");
- break;
- case 1:
- printf ("PHY is in Power save mode in POS state\n");
- break;
- case 2:
- case 3:
- printf ("PHY is in Power save mode\n");
- break;
- }
- switch ((nicvga >> 2) & 0x3) {
- case 0:
- printf ("VGA is running\n");
- break;
- case 1:
- printf ("VGA is in Power save mode in POS state\n");
- break;
- case 2:
- case 3:
- printf ("VGA is in Power save mode\n");
- break;
- }
- printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
- printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
- printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
- (nicvga >> 7) & 0x1);
- switch ((scsirst) & 0x3) {
- case 0:
- printf ("SCSI Controller is running\n");
- break;
- case 1:
- printf ("SCSI Controller is in Power save mode in POS state\n");
- break;
- case 2:
- case 3:
- printf ("SCSI Controller is in Power save mode\n");
- break;
- }
- printf ("SCSI termination is %s\n",
- ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
- printf ("SCSI Controller is %sreseted\n",
- ((scsirst & 0x10) == 0x10) ? "" : "not ");
- printf ("IDE disks are %sreseted\n",
- ((scsirst & 0x20) == 0x20) ? "" : "not ");
- printf ("ISA Bus is %sreseted\n",
- ((scsirst & 0x40) == 0x40) ? "" : "not ");
- printf ("Super IO is %sreseted\n",
- ((scsirst & 0x80) == 0x80) ? "" : "not ");
-}
-
-void user_led0 (unsigned char on)
-{
- if (on == true)
- out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
- else
- out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
-}
-
-void user_led1 (unsigned char on)
-{
- if (on == true)
- out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
- else
- out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
-}
-
-void ide_set_reset (int idereset)
-{
- /* if reset = 1 IDE reset will be asserted */
- unsigned char resreg;
-
- resreg = in8 (PLD_SCSI_RST_REG);
- if (idereset == 1)
- resreg |= 0x20;
- else {
- udelay(10000);
- resreg &= 0xdf;
- }
- out8 (PLD_SCSI_RST_REG, resreg);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- /****************************************************************************
- * Global routines used for PIP405
- *****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
-
-void print_pip405_info(void);
-
-void user_led0(unsigned char on);
-void user_led1(unsigned char on);
-
-
-#define PLD_BASE_ADDRESS CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800
-#define PLD_PART_REG PLD_BASE_ADDRESS + 0
-#define PLD_VERS_REG PLD_BASE_ADDRESS + 1
-#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2
-#define PLD_LED_USER_REG PLD_BASE_ADDRESS + 3
-#define PLD_SYS_MAN_REG PLD_BASE_ADDRESS + 4
-#define PLD_FLASH_COM_REG PLD_BASE_ADDRESS + 5
-#define PLD_CAN_REG PLD_BASE_ADDRESS + 6
-#define PLD_SER_PWR_REG PLD_BASE_ADDRESS + 7
-#define PLD_COM_PWR_REG PLD_BASE_ADDRESS + 8
-#define PLD_NIC_VGA_REG PLD_BASE_ADDRESS + 9
-#define PLD_SCSI_RST_REG PLD_BASE_ADDRESS + 0xA
-
-#define PIIX4_VENDOR_ID 0x8086
-#define PIIX4_IDE_DEV_ID 0x7111
-
-#endif
-
-/* timings */
-
-/* CS Config register (CS7) */
-#define CONFIG_PORT_BME 0 /* Burst disable */
-#define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */
-#define CONFIG_PORT_WBN 1 /* Cycles from CS low to WE low */
-#define CONFIG_PORT_WBF 1 /* Cycles from WE high to CS high */
-#define CONFIG_PORT_TH 2 /* Number of hold cycles after transfer */
-#define CONFIG_PORT_RE 0 /* Ready disabled */
-#define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */
-#define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */
-#define CONFIG_PORT_PEN 0 /* Parity disable */
-#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
- (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define CONFIG_PORT_BS 0 /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define CONFIG_PORT_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define CONFIG_PORT_BW 0 /* 16Bit */
-#define CONFIG_PORT_CR ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
-
-/* Flash CS0 or CS 1 */
-/* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B 1 /* Burst enable */
-#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
-#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME 0 /* Burst disable */
-#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define FLASH_OEN 1 /* Cycles from CS low to OE low */
-#define FLASH_WBN 1 /* Cycles from CS low to WE low */
-#define FLASH_WBF 1 /* Cycles from WE high to CS high */
-#define FLASH_TH 2 /* Number of hold cycles after transfer */
-#define FLASH_RE 0 /* Ready disabled */
-#define FLASH_SOR 1 /* Sample on Ready disabled */
-#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
-#define FLASH_PEN 0 /* Parity disable */
-/* Access Parameter Register for non Boot */
-#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
- (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-/* Access Parameter Register for Boot */
-#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
- (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define FLASH_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define FLASH_BW 1 /* 16Bit */
-/* CR register for Boot */
-#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-/* CR register for non Boot */
-#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-
-/* MPS CS1 or CS0 */
-/* Boot CS: */
-#define MPS_BME_B 1 /* Burst enable */
-#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
-#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME 0 /* Burst disable */
-#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define MPS_OEN 1 /* Cycles from CS low to OE low */
-#define MPS_WBN 1 /* Cycles from CS low to WE low */
-#define MPS_WBF 1 /* Cycles from WE high to CS high */
-#define MPS_TH 2 /* Number of hold cycles after transfer */
-#define MPS_RE 0 /* Ready disabled */
-#define MPS_SOR 1 /* Sample on Ready disabled */
-#define MPS_BEM 0 /* Byte Write only active on Write cycles */
-#define MPS_PEN 0 /* Parity disable */
-/* Access Parameter Register for non Boot */
-#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
- (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-/* Access Parameter Register for Boot */
-#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
- (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define MPS_BS 2 /* 4 MByte */
-#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define MPS_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define MPS_BW 0 /* 8Bit */
-/* CR register for Boot */
-#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
-/* CR register for non Boot */
-#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-if TARGET_T3CORP
-
-config SYS_BOARD
- default "t3corp"
-
-config SYS_CONFIG_NAME
- default "t3corp"
-
-endif
+++ /dev/null
-T3CORP BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/t3corp/
-F: include/configs/t3corp.h
-F: configs/t3corp_defconfig
+++ /dev/null
-#
-# (C) Copyright 2010
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := t3corp.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
- {
- "600-67", "CPU: 600 PLB: 200 OPB: 67 EBC: 67",
- {
- 0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "667", "CPU: 667 PLB: 166 OPB: 83 EBC: 83",
- {
- 0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
- 0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "1000", "CPU:1000 PLB: 200 OPB: 100 EBC: 100",
- {
- 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
- {
- "1066", "CPU:1066 PLB: 266 OPB: 88 EBC: 88",
- {
- 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
- }
- },
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-#
-# (C) Copyright 2010
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- */
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
- * use the speed up boot process. It is patched after relocation to
- * enable SA_I
- */
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M,
- CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the DDR(2) detection
- * routine.
- */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0,
- AC_RWX | SA_G)
-#endif
-
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd,
- AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd,
- AC_RW | SA_IG)
-
- /* PCIe UTL register */
- tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
-
- /* TLB-entry for FPGA(s) */
- tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
- CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
- AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
- AC_RW | SA_IG)
-
- /* TLB-entry for OCM */
- tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
- AC_RWX | SA_I)
-
- /* TLB-entry for Local Configuration registers => peripherals */
- tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M,
- CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
-
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc440.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <mtd/cfi_flash.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/4xx_pcie.h>
-#include <asm/ppc4xx-gpio.h>
-
-int board_early_init_f(void)
-{
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC3SR, 0xffffffff); /* clear all */
- mtdcr(UIC3ER, 0x00000000); /* disable all */
- mtdcr(UIC3CR, 0x00000000); /* all non-critical */
- mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC3SR, 0xffffffff); /* clear all */
-
- /*
- * Configure PFC (Pin Function Control) registers
- * enable GPIO 49-63
- * UART0: 4 pins
- */
- mtsdr(SDR0_PFC0, 0x00007fff);
- mtsdr(SDR0_PFC1, 0x00040000);
-
- /* Enable PCI host functionality in SDR0_PCI0 */
- mtsdr(SDR0_PCI0, 0xe0000000);
-
- mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
-
- /* Setup PLB4-AHB bridge based on the system address map */
- mtdcr(AHB_TOP, 0x8000004B);
- mtdcr(AHB_BOT, 0x8000004B);
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: T3CORP");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- /*
- * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
- * boot EBC mapping only supports a maximum of 16MBytes
- * (4.ff00.0000 - 4.ffff.ffff).
- * To solve this problem, the flash has to get remapped to another
- * EBC address which accepts bigger regions:
- *
- * 0xfn00.0000 -> 4.cn00.0000
- */
-
- /* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */
- mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB |
- EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
-
- /* Remove TLB entry of boot EBC mapping */
- remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
-
- /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
- program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
-
- /*
- * Now accessing of the whole 64Mbytes of NOR flash at virtual address
- * 0xfc00.0000 is possible
- */
-
- /*
- * Clear potential errors resulting from auto-calibration.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- u32 sdr0_srst1 = 0;
- u32 eth_cfg;
-
- /*
- * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
- * This is board specific, so let's do it here.
- */
- mfsdr(SDR0_ETH_CFG, eth_cfg);
- /* disable SGMII mode */
- eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
- SDR0_ETH_CFG_SGMII1_ENABLE |
- SDR0_ETH_CFG_SGMII0_ENABLE);
- /* Set the for 2 RGMII mode */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
- eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
- eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
- mtsdr(SDR0_ETH_CFG, eth_cfg);
-
- /*
- * The AHB Bridge core is held in reset after power-on or reset
- * so enable it now
- */
- mfsdr(SDR0_SRST1, sdr0_srst1);
- sdr0_srst1 &= ~SDR0_SRST1_AHB;
- mtsdr(SDR0_SRST1, sdr0_srst1);
-
- return 0;
-}
-
-int board_pcie_last(void)
-{
- /*
- * Only PCIe0 for now, PCIe1 hangs on this board
- */
- return 0;
-}
-
-/*
- * Board specific WRDTR and CLKTR values used by the auto-
- * calibration code (4xx_ibm_ddr2_autocalib.c).
- */
-static struct sdram_timing board_scan_options[] = {
- {1, 2},
- {-1, -1}
-};
-
-struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
-{
- return board_scan_options;
-}
-
-/*
- * Accessor functions replacing the "weak" functions in
- * drivers/mtd/cfi_flash.c
- *
- * The NOR flash devices "behind" the FPGA's (Xilinx DS617)
- * can only be read correctly in 16bit mode. We need to emulate
- * 8bit and 32bit reads here in the board specific code.
- */
-u8 flash_read8(void *addr)
-{
- u16 val = __raw_readw((void *)((u32)addr & ~1));
-
- if ((u32)addr & 1)
- return val;
-
- return val >> 8;
-}
-
-u32 flash_read32(void *addr)
-{
- return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
-}
-
-void flash_cmd_reset(flash_info_t *info)
-{
- /*
- * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
- * needs the Spansion type reset commands. The other flash chip
- * is located behind a FPGA (Xilinx DS617) and needs the Intel type
- * reset command.
- */
- if (info->start[0] == CONFIG_SYS_FLASH_BASE)
- flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
- else
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-}
+++ /dev/null
-if TARGET_XPEDITE1000
-
-config SYS_BOARD
- default "xpedite1000"
-
-config SYS_VENDOR
- default "xes"
-
-config SYS_CONFIG_NAME
- default "xpedite1000"
-
-endif
+++ /dev/null
-XPEDITE1000 BOARD
-M: Peter Tyser <ptyser@xes-inc.com>
-S: Maintained
-F: board/xes/xpedite1000/
-F: include/configs/xpedite1000.h
-F: configs/xpedite1000_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = xpedite1000.o
-extra-y += init.o
+++ /dev/null
- XES XPedite1000 Board
-
- Last Update: December 29, 2003
-=======================================================================
-
-This file contains some handy info regarding U-Boot and the XES
-XPedite1000 PPC440GX PrPMC board. See the README.ppc440 for additional
-information.
-
-
-SWITCH SETTINGS & JUMPERS
-==========================
-
-Jumpers selected for AMD29LV040B flash part as the boot flash.
-
-
-I2C Strap EEPROM & Environment Settings
-=======================================
-
-The XPedite1000 uses a single I2C eeprom for the 440 strappings and for
-the environment variables. The first page (256 bytes) contains the
-strappings and the 2 EMAC HW Ethernet addresses. Be careful not to
-change the 1st page of the EEPROM! Unpopulated jumper J560 can get you
-out of trouble as it disables the strapping read from EEPROM.
-
-I2C probe
-=====================
-
-The i2c utilities work and have been tested on Rev B. of the 440GX. See
-README.ebony for more information about i2c probing with the 440.
-
-
-GETTING OUT OF I2C TROUBLE
-===========================
-
-(Direct quote from README.ebony)
-If you're like me ... you may have screwed up your bootstrap serial
-eeprom ... or worse, your SPD eeprom when experimenting with the
-i2c commands. If so, here are some ideas on how to get out of
-trouble:
-
-Serial bootstrap eeprom corruption:
------------------------------------
-Power down the board and set the following straps:
-
-J560 - closed
-
-This will select the default sys0 and sys1 settings (the serial
-eeproms are not used). Then power up the board and fix the serial
-eeprom using the 'i2c mm' command. Here are the values I currently
-use:
-
-=> i2c md 50 0 10
-
-0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00 .}B.............
-
-Once you have the eeproms set correctly change the
-J560 straps as you desire.
-
-
-PPC440GX Ethernet EMACs
-=======================
-
-The XES XPedite1000 uses emac 2 & 3 and ignores emac 0 & 1. PHYs are connected
-only to emac 2 & 3. The HW Ethernet addresses are read from the i2c eeprom and
-placed in the bd info structure for enet2addr and enet3addr. The ethernet driver
-senses that enetaddr and enet1addr are 0's and does not use them.
-
-As of this writing gigabit ethernet and the TCPIP acceleration hardware is not
-supported.
-
-
-Flash Support
-=============
-
-As of this writing, there is support for the 1/2mb boot flash only. User flash
-is not yet supported.
-
-
-Regards,
---Travis
-<travis.sawyer@sandburst.com>
+++ /dev/null
-#
-# (C) Copyright 2002-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# XES XPedite1000 PPC440GX
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
-* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- */
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
- tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
- tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/xes/xpedite1000/init.o (.text)
- arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
- arch/powerpc/cpu/ppc4xx/traps.o (.text)
- arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
- arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
- arch/powerpc/cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
-
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <asm/processor.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- unsigned long sdrreg;
-
- /*
- * Enable GPIO for pins 18 - 24
- * 18 = SEEPROM_WP
- * 19 = #M_RST
- * 20 = #MONARCH
- * 21 = #LED_ALARM
- * 22 = #LED_ACT
- * 23 = #LED_STATUS1
- * 24 = #LED_STATUS2
- */
- mfsdr(SDR0_PFC0, sdrreg);
- mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00);
- out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
- LED0_OFF();
- LED1_OFF();
- LED2_OFF();
- LED3_OFF();
-
- /* Setup the external bus controller/chip selects */
- mtebc(PB0AP, 0x04055200); /* 16MB Strata FLASH */
- mtebc(PB0CR, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
- mtebc(PB1AP, 0x04055200); /* 512KB Socketed AMD FLASH */
- mtebc(PB1CR, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
- mtebc(PB6AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
- mtebc(PB6CR, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */
- mtebc(PB7AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
- mtebc(PB7CR, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- *
- * Because of the interrupt handling rework to handle 440GX interrupts
- * with the common code, we needed to change names of the UIC registers.
- * Here the new relationship:
- *
- * U-Boot name 440GX name
- * -----------------------
- * UIC0 UICB0
- * UIC1 UIC0
- * UIC2 UIC1
- * UIC3 UIC2
- */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */
- mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */
- mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC3SR, 0xffffffff); /* clear all */
- mtdcr(UIC3ER, 0x00000000); /* disable all */
- mtdcr(UIC3CR, 0x00000000); /* all non-critical */
- mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */
- mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC3SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC0SR, 0xfc000000); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000000); /* all non-critical */
- mtdcr(UIC0PR, 0xfc000000); /* */
- mtdcr(UIC0TR, 0x00000000); /* */
- mtdcr(UIC0VR, 0x00000001); /* */
-
- LED0_ON();
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i;
-
- printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME);
- printf(" ");
- i = getenv_f("board_rev", buf, sizeof(buf));
- if (i > 0)
- printf("Rev %s, ", buf);
- i = getenv_f("serial#", buf, sizeof(buf));
- if (i > 0)
- printf("Serial# %s, ", buf);
- i = getenv_f("board_cfg", buf, sizeof(buf));
- if (i > 0)
- printf("Cfg %s", buf);
- printf("\n");
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = spd_sdram();
-
- return 0;
-}
-
-/*
- * Override weak pci_pre_init()
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- */
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose)
-{
- unsigned long strap;
-
- /* See if we're supposed to setup the pci */
- mfsdr(SDR0_SDSTP1, strap);
- if ((strap & 0x00010000) == 0)
- return 0;
-
-#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
- /* Setup System Device Register PCIL0_XCR */
- mfsdr(SDR0_XCR, strap);
- strap &= 0x0f000000;
- mtsdr(SDR0_XCR, strap);
-#endif
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-#if defined(CONFIG_PCI)
-/*
- * Override weak is_pci_host()
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-int is_pci_host(struct pci_controller *hose)
-{
- return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return ctrlc();
-}
-#endif
+++ /dev/null
-if TARGET_XILINX_PPC405_GENERIC
-
-config SYS_BOARD
- default "ppc405-generic"
-
-config SYS_VENDOR
- default "xilinx"
-
-config SYS_CONFIG_NAME
- default "xilinx-ppc405-generic"
-
-endif
+++ /dev/null
-PPC405-GENERIC BOARD
-M: Ricardo Ribalda <ricardo.ribalda@gmail.com>
-S: Maintained
-F: board/xilinx/ppc405-generic/
-F: include/configs/xilinx-ppc405-generic.h
-F: configs/xilinx-ppc405-generic_defconfig
-F: configs/xilinx-ppc405-generic_flash_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
-# Work supported by Qtechnology http://www.qtec.com
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += xilinx_ppc405_generic.o
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-ulong get_PCI_freq(void)
-{
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Xilinx PPC405 Generic Board\n");
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
- CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
-
- return 0;
-}
-
-void get_sys_info(sys_info_t *sys_info)
-{
- sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
- sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
- sys_info->freqPCI = 0;
-
- return;
-}
-
-int get_serial_clock(void){
- return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- * based on xparameters-ml507.h by Xilinx
- *
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#ifndef XPARAMETER_H
-#define XPARAMETER_H
-
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
-#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
-#define XPAR_INTC_0_BASEADDR 0x81800000
-#define XPAR_SPI_0_BASEADDR 0x83400000
-#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
-#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
-#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
-
-#endif
+++ /dev/null
-if TARGET_XILINX_PPC440_GENERIC
-
-config SYS_BOARD
- default "ppc440-generic"
-
-config SYS_VENDOR
- default "xilinx"
-
-config SYS_CONFIG_NAME
- default "xilinx-ppc440-generic"
-
-endif
+++ /dev/null
-PPC440-GENERIC BOARD
-M: Ricardo Ribalda <ricardo.ribalda@gmail.com>
-S: Maintained
-F: board/xilinx/ppc440-generic/
-F: include/configs/xilinx-ppc440-generic.h
-F: configs/xilinx-ppc440-generic_defconfig
-F: configs/xilinx-ppc440-generic_flash_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
-# Work supported by Qtechnology http://www.qtec.com
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += xilinx_ppc440_generic.o
-extra-y += init.o
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-.section .bootpg,"ax"
-.globl tlbtab
-
-tlbtab:
-tlbtab_start
-tlbentry(0x00000000, SZ_256M, 0x00000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x10000000, SZ_256M, 0x10000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x20000000, SZ_256M, 0x20000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x30000000, SZ_256M, 0x30000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x40000000, SZ_256M, 0x40000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x50000000, SZ_256M, 0x50000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x60000000, SZ_256M, 0x60000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x70000000, SZ_256M, 0x70000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x80000000, SZ_256M, 0x80000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x90000000, SZ_256M, 0x90000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xa0000000, SZ_256M, 0xa0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xb0000000, SZ_256M, 0xb0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xc0000000, SZ_256M, 0xc0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xd0000000, SZ_256M, 0xd0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xe0000000, SZ_256M, 0xe0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xf0000000, SZ_256M, 0xf0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#include <config.h>
-#include <common.h>
-#include <netdev.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- puts("Xilinx PPC440 Generic Board\n");
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
- CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
-
- return 0;
-}
-
-void get_sys_info(sys_info_t *sys_info)
-{
- sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
- sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
- sys_info->freqPCI = 0;
-
- return;
-}
-
-int get_serial_clock(void){
- return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int ret = 0;
-
- puts("Init xilinx temac\n");
-#ifdef XPAR_LLTEMAC_0_BASEADDR
- ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR,
- XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
- XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR);
-
-#endif
-
-#ifdef XPAR_LLTEMAC_1_BASEADDR
- ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR,
- XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
- XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR);
-#endif
-
- return ret;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- * based on xparameters-ml507.h by Xilinx
- *
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#ifndef XPARAMETER_H
-#define XPARAMETER_H
-
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
-#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
-#define XPAR_INTC_0_BASEADDR 0x87000000
-#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000
-#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
-#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80
-#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98
-#define XPAR_LLTEMAC_0_BASEADDR 0x83000000
-#define XPAR_LLTEMAC_1_BASEADDR 0x83000040
-
-#endif
help
Access the system timer.
-config CMD_SETGETDCR
- bool "getdcr, setdcr, getidcr, setidcr"
- depends on 4xx
- default y
- help
- getdcr - Get an AMCC PPC 4xx DCR's value
- setdcr - Set an AMCC PPC 4xx DCR's value
- getidcr - Get a register value via indirect DCR addressing
- setidcr - Set a register value via indirect DCR addressing
-
config CMD_SOUND
bool "sound"
depends on SOUND
obj-$(CONFIG_CMD_DATE) += date.o
obj-$(CONFIG_CMD_DEMO) += demo.o
obj-$(CONFIG_CMD_SOUND) += sound.o
-ifdef CONFIG_4xx
-obj-$(CONFIG_CMD_SETGETDCR) += dcr.o
-endif
ifdef CONFIG_POST
obj-$(CONFIG_CMD_DIAG) += diag.o
endif
print_num("immr_base", bd->bi_immr_base);
#endif
print_num("bootflags", bd->bi_bootflags);
-#if defined(CONFIG_405EP) || \
- defined(CONFIG_405GP) || \
- defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_XILINX_405)
- print_mhz("procfreq", bd->bi_procfreq);
- print_mhz("plb_busfreq", bd->bi_plb_busfreq);
-#if defined(CONFIG_405EP) || defined(CONFIG_405GP) || \
- defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405)
- print_mhz("pci_busfreq", bd->bi_pci_busfreq);
-#endif
-#else /* ! CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
#if defined(CONFIG_CPM2)
print_mhz("vco", bd->bi_vco);
print_mhz("sccfreq", bd->bi_sccfreq);
print_mhz("cpmfreq", bd->bi_cpmfreq);
#endif
print_mhz("busfreq", bd->bi_busfreq);
-#endif /* CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
#ifdef CONFIG_ENABLE_36BIT_PHYS
#ifdef CONFIG_PHYS_64BIT
void bedbug_init (void)
{
/* -------------------------------------------------- */
-
-#if defined(CONFIG_4xx)
- void bedbug405_init (void);
-
- bedbug405_init ();
-#endif
-
return;
} /* bedbug_init */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * AMCC 4XX DCR Functions
- */
-
-#include <common.h>
-#include <cli.h>
-#include <config.h>
-#include <command.h>
-#include <console.h>
-
-unsigned long get_dcr (unsigned short);
-unsigned long set_dcr (unsigned short, unsigned long);
-
-/* =======================================================================
- * Interpreter command to retrieve an AMCC PPC 4xx Device Control Register
- * =======================================================================
- */
-int do_getdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
-{
- unsigned short dcrn; /* Device Control Register Num */
- unsigned long value; /* DCR's value */
-
- unsigned long get_dcr (unsigned short);
-
- /* Validate arguments */
- if (argc < 2)
- return CMD_RET_USAGE;
-
- /* Get a DCR */
- dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
- value = get_dcr (dcrn);
-
- printf ("%04x: %08lx\n", dcrn, value);
-
- return 0;
-}
-
-
-/* ======================================================================
- * Interpreter command to set an AMCC PPC 4xx Device Control Register
- * ======================================================================
-*/
-int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned short dcrn; /* Device Control Register Num */
- unsigned long value;
-
- /* DCR's value */
- int nbytes;
-
- /* Validate arguments */
- if (argc < 2)
- return CMD_RET_USAGE;
-
- /* Set a DCR */
- dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
- do {
- value = get_dcr (dcrn);
- printf ("%04x: %08lx", dcrn, value);
- nbytes = cli_readline(" ? ");
- if (nbytes == 0) {
- /*
- * <CR> pressed as only input, don't modify current
- * location and exit command.
- */
- nbytes = 1;
- return 0;
- } else {
- unsigned long i;
- char *endp;
-
- i = simple_strtoul (console_buffer, &endp, 16);
- nbytes = endp - console_buffer;
- if (nbytes)
- set_dcr (dcrn, i);
- }
- } while (nbytes);
-
- return 0;
-}
-
-/* =======================================================================
- * Interpreter command to retrieve an register value through AMCC PPC 4xx
- * Device Control Register inderect addressing.
- * =======================================================================
- */
-int do_getidcr (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned short adr_dcrn; /* Device Control Register Num for Address */
- unsigned short dat_dcrn; /* Device Control Register Num for Data */
- unsigned short offset; /* Register's offset */
- unsigned long value; /* Register's value */
- char *ptr = NULL;
- char buf[80];
-
- /* Validate arguments */
- if (argc < 3)
- return CMD_RET_USAGE;
-
- /* Find out whether ther is '.' (dot) symbol in the first parameter. */
- strncpy (buf, argv[1], sizeof(buf)-1);
- buf[sizeof(buf)-1] = 0; /* will guarantee zero-end string */
- ptr = strchr (buf, '.');
-
- if (ptr != NULL) {
- /* First parameter has format adr_dcrn.dat_dcrn */
- *ptr++ = 0; /* erase '.', create zero-end string */
- adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16);
- dat_dcrn = (unsigned short) simple_strtoul (ptr, NULL, 16);
- } else {
- /*
- * First parameter has format adr_dcrn; dat_dcrn will be
- * calculated as adr_dcrn+1.
- */
- adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16);
- dat_dcrn = adr_dcrn+1;
- }
-
- /* Register's offset */
- offset = (unsigned short) simple_strtoul (argv[2], NULL, 16);
-
- /* Disable interrupts */
- disable_interrupts ();
- /* Set offset */
- set_dcr (adr_dcrn, offset);
- /* get data */
- value = get_dcr (dat_dcrn);
- /* Enable interrupts */
- enable_interrupts ();
-
- printf ("%04x.%04x-%04x Read %08lx\n", adr_dcrn, dat_dcrn, offset, value);
-
- return 0;
-}
-
-/* =======================================================================
- * Interpreter command to update an register value through AMCC PPC 4xx
- * Device Control Register inderect addressing.
- * =======================================================================
- */
-int do_setidcr (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned short adr_dcrn; /* Device Control Register Num for Address */
- unsigned short dat_dcrn; /* Device Control Register Num for Data */
- unsigned short offset; /* Register's offset */
- unsigned long value; /* Register's value */
- char *ptr = NULL;
- char buf[80];
-
- /* Validate arguments */
- if (argc < 4)
- return CMD_RET_USAGE;
-
- /* Find out whether ther is '.' (dot) symbol in the first parameter. */
- strncpy (buf, argv[1], sizeof(buf)-1);
- buf[sizeof(buf)-1] = 0; /* will guarantee zero-end string */
- ptr = strchr (buf, '.');
-
- if (ptr != NULL) {
- /* First parameter has format adr_dcrn.dat_dcrn */
- *ptr++ = 0; /* erase '.', create zero-end string */
- adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16);
- dat_dcrn = (unsigned short) simple_strtoul (ptr, NULL, 16);
- } else {
- /*
- * First parameter has format adr_dcrn; dat_dcrn will be
- * calculated as adr_dcrn+1.
- */
- adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16);
- dat_dcrn = adr_dcrn+1;
- }
-
- /* Register's offset */
- offset = (unsigned short) simple_strtoul (argv[2], NULL, 16);
- /* New value */
- value = (unsigned long) simple_strtoul (argv[3], NULL, 16);
-
- /* Disable interrupts */
- disable_interrupts ();
- /* Set offset */
- set_dcr (adr_dcrn, offset);
- /* set data */
- set_dcr (dat_dcrn, value);
- /* Enable interrupts */
- enable_interrupts ();
-
- printf ("%04x.%04x-%04x Write %08lx\n", adr_dcrn, dat_dcrn, offset, value);
-
- return 0;
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
- getdcr, 2, 1, do_getdcr,
- "Get an AMCC PPC 4xx DCR's value",
- "dcrn - return a DCR's value."
-);
-U_BOOT_CMD(
- setdcr, 2, 1, do_setdcr,
- "Set an AMCC PPC 4xx DCR's value",
- "dcrn - set a DCR's value."
-);
-
-U_BOOT_CMD(
- getidcr, 3, 1, do_getidcr,
- "Get a register value via indirect DCR addressing",
- "adr_dcrn[.dat_dcrn] offset - write offset to adr_dcrn, read value from dat_dcrn."
-);
-
-U_BOOT_CMD(
- setidcr, 4, 1, do_setidcr,
- "Set a register value via indirect DCR addressing",
- "adr_dcrn[.dat_dcrn] offset value - write offset to adr_dcrn, write value to dat_dcrn."
-);
#include <common.h>
#include <command.h>
-#if defined (CONFIG_4xx)
-extern void ppc4xx_reginfo(void);
-#elif defined (CONFIG_MPC86xx)
+#if defined(CONFIG_MPC86xx)
extern void mpc86xx_reginfo(void);
#elif defined(CONFIG_MPC85xx)
extern void mpc85xx_reginfo(void);
static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
-#if defined (CONFIG_4xx)
- ppc4xx_reginfo();
-#elif defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC86xx)
mpc86xx_reginfo();
#elif defined(CONFIG_MPC85xx)
setup_board_part2,
#endif
display_new_sp,
-#ifdef CONFIG_SYS_EXTBDINFO
- setup_board_extra,
-#endif
#ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt,
#endif
}
#endif
-#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-/*
- * Provide a weak default function to return the flash bank size.
- * There might be multiple non-identical flash chips connected to one
- * chip-select, so we need to pass an index as well.
- */
-u32 __flash_get_bank_size(int cs, int idx)
-{
- extern flash_info_t flash_info[];
-
- /*
- * As default, a simple 1:1 mapping is provided. Boards with
- * a different mapping need to supply a board specific mapping
- * routine.
- */
- return flash_info[cs].size;
-}
-u32 flash_get_bank_size(int cs, int idx)
- __attribute__((weak, alias("__flash_get_bank_size")));
-
-/*
- * This function can be used to update the size in the "reg" property
- * of all NOR FLASH device nodes. This is necessary for boards with
- * non-fixed NOR FLASH sizes.
- */
-int fdt_fixup_nor_flash_size(void *blob)
-{
- char compat[][16] = { "cfi-flash", "jedec-flash" };
- int off;
- int len;
- struct fdt_property *prop;
- u32 *reg, *reg2;
- int i;
-
- for (i = 0; i < 2; i++) {
- off = fdt_node_offset_by_compatible(blob, -1, compat[i]);
- while (off != -FDT_ERR_NOTFOUND) {
- int idx;
-
- /*
- * Found one compatible node, so fixup the size
- * int its reg properties
- */
- prop = fdt_get_property_w(blob, off, "reg", &len);
- if (prop) {
- int tuple_size = 3 * sizeof(reg);
-
- /*
- * There might be multiple reg-tuples,
- * so loop through them all
- */
- reg = reg2 = (u32 *)&prop->data[0];
- for (idx = 0; idx < (len / tuple_size); idx++) {
- /*
- * Update size in reg property
- */
- reg[2] = flash_get_bank_size(reg[0],
- idx);
-
- /*
- * Point to next reg tuple
- */
- reg += 3;
- }
-
- fdt_setprop(blob, off, "reg", reg2, len);
- }
-
- /* Move to next compatible node */
- off = fdt_node_offset_by_compatible(blob, off,
- compat[i]);
- }
- }
-
- return 0;
-}
-#endif
-
int fdt_increase_size(void *fdt, int add_len)
{
int newlen;
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-void lynxkdi_boot(image_header_t *hdr)
-{
- void (*lynxkdi)(void) = (void(*)(void))image_get_ep(hdr);
- lynxos_bootparms_t *parms = (lynxos_bootparms_t *)0x0020;
- bd_t *kbd;
- u32 *psz = (u32 *)(image_get_load(hdr) + 0x0204);
-
- memset(parms, 0, sizeof(*parms));
- kbd = gd->bd;
- parms->clock_ref = kbd->bi_busfreq;
- parms->dramsz = kbd->bi_memsize;
- eth_getenv_enetaddr("ethaddr", parms->ethaddr);
- mtspr(SPRN_SPRG2, 0x0020);
-
- /* Do a simple check for Bluecat so we can pass the
- * kernel command line parameters.
- */
- /* FIXME: NOT SURE HERE ! */
- if (le32_to_cpu(*psz) == image_get_data_size(hdr)) {
- char *args;
- char *cmdline = (char *)(image_get_load(hdr) + 0x020c);
- int len;
-
- printf("Booting Bluecat KDI ...\n");
- udelay(200*1000); /* Allow serial port to flush */
- if ((args = getenv("bootargs")) == NULL)
- args = "";
- /* Prepend the cmdline */
- len = strlen(args);
- if (len && (len + strlen(cmdline) + 2 < (0x0400 - 0x020c))) {
- memmove(cmdline + strlen(args) + 1, cmdline,
- strlen(cmdline));
- strcpy(cmdline, args);
- cmdline[len] = ' ';
- }
- }
- else {
- printf("Booting LynxOS KDI ...\n");
- }
-
- lynxkdi();
-}
-#else
#error "Lynx KDI support not implemented for configured CPU"
-#endif
#include <asm/unaligned.h>
#include <errno.h>
#include <usb.h>
-#ifdef CONFIG_4xx
-#include <asm/4xx_pci.h>
-#endif
#define USB_BUFSIZ 512
DECLARE_GLOBAL_DATA_PTR;
#include <usb.h>
-#ifdef CONFIG_4xx
-#include <asm/4xx_pci.h>
-#endif
#define USB_BUFSIZ 512
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CPCI2DP=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_BSP=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CPCI4052=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10082-001 released"
-CONFIG_VIDEO=y
-CONFIG_4xx=y
-CONFIG_TARGET_MIP405T=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_VIDEO_CT69000=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10072-001 released"
-CONFIG_VIDEO=y
-CONFIG_4xx=y
-CONFIG_TARGET_MIP405=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_VIDEO_CT69000=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING="\n(c) 2002 by MPL AG Switzerland, MEV-10066-001 released"
-CONFIG_VIDEO=y
-CONFIG_4xx=y
-CONFIG_TARGET_PIP405=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_FDC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_VIDEO_CT69000=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PLU405=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_UBI=y
-CONFIG_MAC_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PMC405DE=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_DATE=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PMC440=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_API=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_FAT=y
-# CONFIG_CMD_IRQ is not set
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_VOM405=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BSP=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_ACADIA=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CANYONLANDS=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_ARCHES=y
-CONFIG_DEFAULT_DEVICE_TREE="arches"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_BAMBOO=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI_PNP is not set
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_BUBINGA=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CANYONLANDS=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_CANYONLANDS=y
-CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING=" devconcenter 0.06"
-CONFIG_4xx=y
-CONFIG_TARGET_INTIP=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING=" dlvision-10g 0.06"
-CONFIG_4xx=y
-CONFIG_TARGET_DLVISION_10G=y
-CONFIG_FIT=y
-# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_CMD_ELF is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_IRQ is not set
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING=" dlvision 0.02"
-CONFIG_4xx=y
-CONFIG_TARGET_DLVISION=y
-CONFIG_FIT=y
-# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_ELF is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_LOOPW=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_IRQ is not set
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_GDPPC440ETX=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI_PNP is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CANYONLANDS=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_GLACIER=y
-CONFIG_DEFAULT_DEVICE_TREE="glacier"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CANYONLANDS=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_GLACIER=y
-CONFIG_DEFAULT_DEVICE_TREE="glacier"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_KILAUEA=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_4xx=y
-CONFIG_TARGET_ICON=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING=" intip 0.06"
-CONFIG_4xx=y
-CONFIG_TARGET_INTIP=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="INTIB"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING=" io64 0.02"
-CONFIG_4xx=y
-CONFIG_TARGET_IO64=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING=" io 0.06"
-CONFIG_4xx=y
-CONFIG_TARGET_IO=y
-CONFIG_FIT=y
-# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_CMD_ELF is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_LOOPW=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_IRQ is not set
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING=" iocon 0.06"
-CONFIG_4xx=y
-CONFIG_TARGET_IOCON=y
-CONFIG_FIT=y
-# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_CMD_ELF is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_FPGAD=y
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_CMD_IRQ is not set
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_KATMAI=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_CMD_ECCTEST=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_KILAUEA=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_LUAN=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING=" - v2.0"
-CONFIG_VIDEO=y
-CONFIG_4xx=y
-CONFIG_TARGET_LWMON5=y
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_MAKALU=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_IDENT_STRING=" neo 0.02"
-CONFIG_4xx=y
-CONFIG_TARGET_NEO=y
-CONFIG_FIT=y
-# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_ELF is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_LOOPW=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_IRQ is not set
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_SEQUOIA=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_SEQUOIA=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_REDWOOD=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_SEQUOIA=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_SEQUOIA=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_WALNUT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_T3CORP=y
-CONFIG_CMD_CHIP_CONFIG=y
-CONFIG_CMD_ECCTEST=y
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_WALNUT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_XILINX_PPC405_GENERIC=y
-CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc405-generic"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="xlx-ppc405:/# "
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_OF_EMBED=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_XILINX_UARTLITE=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_XILINX_PPC440_GENERIC=y
-CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="board:/# "
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_OF_EMBED=y
-CONFIG_NETCONSOLE=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_XILINX_UARTLITE=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_XPEDITE1000=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=3
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_JFFS2=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_YOSEMITE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI_PNP is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_YOSEMITE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI_PNP is not set
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_YUCCA=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_LOOPW=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
- PowerPC 440
-
- Last Update: September 11, 2002
-=======================================================================
-
-
-OVERVIEW
-============
-
-Support for the ppc440 is contained in the cpu/ppc44x directory
-and enabled via the CONFIG_440 flag. It is largely based on the
-405gp code. A sample board support implementation is contained
-in the board/ebony directory.
-
-All testing was performed using the AMCC Ebony board using both
-Rev B and Rev C silicon. However, since the Rev B. silicon has
-extensive errata, support for Rev B. is minimal (it boots, and
-features such as i2c, pci, tftpboot, etc. seem to work ok).
-The expectation is that all new board designs will be using
-Rev C or later parts -- if not, you may be in for a rough ride ;-)
-
-The ppc440 port does a fair job of keeping "board-specific" code
-out of the "cpu-specific" source. The goal of course was to
-provide mechanisms for each board to customize without having
-to clutter the cpu-specific source with a lot of ifdefs. Most
-of these mechanisms are described in the following sections.
-
-
-MEMORY MANAGEMENT
-=================
-
-The ppc440 doesn't run in "real mode". The MMU must be active
-at all times. Additionally, the 440 implements a 36-bit physical
-memory space that gets mapped into the PowerPC 32-bit virtual
-address space. So things like memory-mapped peripherals, etc must
-all be mapped in. Once this is done, the 32-bit virtual address
-space is then viewed as though it were physical memory.
-
-However, this means that memory, peripherals, etc can be configured
-to appear (mostly) anywhere in the virtual address space. Each board
-must define its own mappings using the tlbtab (see board/ebony/init.S).
-The actual TLB setup is performed by the cpu-specific code.
-
-Although each board is free to define its own mappings, there are
-several definitions to be aware of. These definitions may be used in
-the cpu-specific code (vs. board-specific code), so you should
-at least review these before deciding to make any changes ... it
-will probably save you some headaches ;-)
-
-CONFIG_SYS_SDRAM_BASE - The virtual address where SDRAM is mapped (always 0)
-
-CONFIG_SYS_FLASH_BASE - The virtual address where FLASH is mapped.
-
-CONFIG_SYS_PCI_MEMBASE - The virtual address where PCI-bus memory is mapped.
- This mapping provides access to PCI-bus memory.
-
-CONFIG_SYS_PERIPHERAL_BASE - The virtual address where the 440 memory-mapped
- peripherals are mapped. (e.g. -- UART registers, IIC registers, etc).
-
-CONFIG_SYS_ISRAM_BASE - The virtual address where the 440 internal SRAM is
- mapped. The internal SRAM is equivalent to 405gp OCM and is used
- for the initial stack.
-
-CONFIG_SYS_PCI_BASE - The virtual address where the 440 PCI-x bridge config
- registers are mapped.
-
-CONFIG_SYS_PCI_TARGBASE - The PCI address that is mapped to the virtual address
- defined by CONFIG_SYS_PCI_MEMBASE.
-
-
-UART / SERIAL
-=================
-
-The UART port works fine when an external serial clock is provided
-(like the one on the Ebony board) and when using internal clocking.
-This is controlled with the CONFIG_SYS_EXT_SERIAL_CLOCK flag. When using
-internal clocking, the "ideal baud rate" settings in the 440GP
-user manual are automatically calculated.
-
-
-I2C
-=================
-
-The i2c utilities have been tested on both Rev B. and Rev C. and
-look good. The 'i2c probe' command implementation has been updated to
-allow for 'skipped' addresses. Some i2c slaves are write only and
-cause problems when a probe (read) is performed (for example the
-CDCV850 clock controller at address 0x69 on the ebony board).
-
-To prevent probing certain addresses you can define the
-CONFIG_SYS_I2C_NOPROBES macro in your board-specific header file. When
-defined, all specified addresses are skipped during a probe.
-The addresses that are skipped will be displayed in the output
-of the 'i2c probe' command.
-
-For example, to prevent probing address 0x69, define the macro as
-follows:
-
-#define CONFIG_SYS_I2C_NOPROBES {0x69}
-
-Similarly, to prevent probing addresses 0x69 and 0x70, define the
-macro a:
-
-#define CONFIG_SYS_I2C_NOPROBES {0x69, 0x70}
-
-
-DDR SDRAM CONTROLLER
-====================
-
-SDRAM controller intialization using Serial Presence Detect (SPD) is
-now supported (thanks Jun). It is enabled by defining CONFIG_SPD_EEPROM.
-The i2c eeprom addresses are controlled by the SPD_EEPROM_ADDRESS macro.
-
-NOTE: The SPD_EEPROM_ADDRESS macro is defined differently than for other
-processors. Traditionally, it defined a single address. For the 440 it
-defines an array of addresses to support multiple banks. Address order
-is significant: the addresses are used in order to program the BankN
-registers. For example, two banks with i2c addresses of 0x53 (bank 0)
-and 0x52 (bank 1) would be defined as follows:
-
-#define SPD_EEPROM_ADDRESS {0x53,0x52}
-
-
-PCI-X BRIDGE
-====================
-
-PCI is an area that requires lots of flexibility since every board has
-its own set of constraints and configuration. This section describes the
-440 implementation.
-
-CPC0_STRP1[PISE] -- if the PISE strap bit is not asserted, PCI init
-is aborted and an indication is printed. This is NOT considered an
-error -- only an indication that PCI shouldn't be initialized. This
-gives you a chance to edit the i2c bootstrap eeproms using the i2c
-utilities once you get to the U-Boot command prompt. NOTE: the default
-440 bootstrap options (not using i2c eeprom) negates this bit.
-
-The cpu-specific code sets up a default pci_controller structure
-that maps in a single PCI I/O space and PCI memory space. The I/O
-space begins at PCI I/O address 0 and the PCI memory space is
-256 MB starting at PCI address CONFIG_SYS_PCI_TARGBASE. After the
-pci_controller structure is initialized, the cpu-specific code will
-call the routine pci_pre_init(). This routine is implemented by
-board-specific code & is where the board can over-ride/extend the
-default pci_controller structure settings and exspecially provide
-a routine to map the PCI interrupts and do other pre-initialization
-tasks. If pci_pre_init() returns a value of zero, PCI initialization
-is aborted; otherwise the controller structure is registered and
-initialization continues.
-
-The default 440GP PCI target configuration is minimal -- it assumes that
-the strapping registers are set as necessary. Since the strapping bits
-provide very limited flexibility, you may want to customize the boards
-target configuration. If CONFIG_SYS_PCI_TARGET_INIT is defined, the cpu-specific
-code will call the routine pci_target_init() which you must implement
-in your board-specific code.
-
-Target initialization is completed by the cpu-specific code by
-initializing the subsystem id and subsystem vendor id, and then ensuring
-that the 'enable host configuration' bit in the PCIX0_BRDGOPT2 is set.
-
-The default PCI master initialization maps in 256 MB of pci memory
-starting at PCI address CONFIG_SYS_PCI_MEMBASE. To customize this, define
-PCI_MASTER_INIT. This will call the routine pci_master_init() in your
-board-specific code rather than performing the default master
-initialization.
-
-The decision to perform PCI host configuration must often be determined
-at run time. The ppc440 port differs from most other implementations in
-that it requires the board to determine its host configuration at run
-time rather than by using compile-time flags. This shouldn't create a
-large impact on the board-specific code since the board only needs to
-implement a single routine that returns a zero or non-zero value:
-is_pci_host().
-
-Justification for this becomes clear when considering systems running
-in a cPCI environment:
-
-1. Arbiter strapping: Many cPCI boards provide an external arbiter (often
-part of the PCI-to-PCI bridge). Even though the arbiter is external (the
-arbiter strapping is negated), the CPU may still be required to perform
-local PCI bus configuration.
-
-2. Host only: PPMC boards must sample the MONARCH# signal at run-time.
-Depending on the configuration of the carrier boar, the PPMC board must
-determine if it should configure the PCI bus at run-time. And in most
-cases, access to the MONARCH# signal is board-specific (e.g. via
-board-specific FPGA registers, etc).
-
-In any event, the is_pci_host() routine gives each board the opportunity
-to decide at run-time. If your board is always configured a certain way,
-then just hardcode a return of 1 or 0 as appropriate.
-
-
-Regards,
---Scott
-<smcnutt@artesyncp.com>
* SPDX-License-Identifier: GPL-2.0+
*/
-USB Support for PIP405 and MIP405 (UHCI)
-========================================
+USB Support
+===========
The USB support is implemented on the base of the UHCI Host
controller.
QE_MURAM_SIZE - 2 * sizeof(u32))
#endif /* defined(CONFIG_QE) */
-#if defined(CONFIG_4xx)
-#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_OCM_DATA_ADDR + \
- CONFIG_SYS_BOOTCOUNT_ADDR)
-#endif /* defined(CONFIG_4xx) */
-
#endif /* !defined(CONFIG_SYS_BOOTCOUNT_ADDR) */
/* Now implement the generic default functions */
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
-obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
+++ /dev/null
-/*
- * (C) Copyright 2007-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
- *
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-i2c.h>
-#include <i2c.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static inline struct ppc4xx_i2c *ppc4xx_get_i2c(int hwadapnr)
-{
- unsigned long base;
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + (hwadapnr * 0x100);
-#elif defined(CONFIG_440) || defined(CONFIG_405EX)
-/* all remaining 440 variants */
- base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + (hwadapnr * 0x100);
-#else
-/* all 405 variants */
- base = 0xEF600500 + (hwadapnr * 0x100);
-#endif
- return (struct ppc4xx_i2c *)base;
-}
-
-static void _i2c_bus_reset(struct i2c_adapter *adap)
-{
- struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
- int i;
- u8 dc;
-
- /* Reset status register */
- /* write 1 in SCMP and IRQA to clear these fields */
- out_8(&i2c->sts, 0x0A);
-
- /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
- out_8(&i2c->extsts, 0x8F);
-
- /* Place chip in the reset state */
- out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
-
- /* Check if bus is free */
- dc = in_8(&i2c->directcntl);
- if (!DIRCTNL_FREE(dc)){
- /* Try to set bus free state */
- out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
-
- /* Wait until we regain bus control */
- for (i = 0; i < 100; ++i) {
- dc = in_8(&i2c->directcntl);
- if (DIRCTNL_FREE(dc))
- break;
-
- /* Toggle SCL line */
- dc ^= IIC_DIRCNTL_SCC;
- out_8(&i2c->directcntl, dc);
- udelay(10);
- dc ^= IIC_DIRCNTL_SCC;
- out_8(&i2c->directcntl, dc);
- }
- }
-
- /* Remove reset */
- out_8(&i2c->xtcntlss, 0);
-}
-
-static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
- int val, divisor;
-
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- /*
- * Call board specific i2c bus reset routine before accessing the
- * environment, which might be in a chip on that bus. For details
- * about this problem see doc/I2C_Edge_Conditions.
- */
- i2c_init_board();
-#endif
-
- /* Handle possible failed I2C state */
- /* FIXME: put this into i2c_init_board()? */
- _i2c_bus_reset(adap);
-
- /* clear lo master address */
- out_8(&i2c->lmadr, 0);
-
- /* clear hi master address */
- out_8(&i2c->hmadr, 0);
-
- /* clear lo slave address */
- out_8(&i2c->lsadr, 0);
-
- /* clear hi slave address */
- out_8(&i2c->hsadr, 0);
-
- /* Clock divide Register */
- /* set divisor according to freq_opb */
- divisor = (get_OPB_freq() - 1) / 10000000;
- if (divisor == 0)
- divisor = 1;
- out_8(&i2c->clkdiv, divisor);
-
- /* no interrupts */
- out_8(&i2c->intrmsk, 0);
-
- /* clear transfer count */
- out_8(&i2c->xfrcnt, 0);
-
- /* clear extended control & stat */
- /* write 1 in SRC SRS SWC SWS to clear these fields */
- out_8(&i2c->xtcntlss, 0xF0);
-
- /* Mode Control Register
- Flush Slave/Master data buffer */
- out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
-
- val = in_8(&i2c->mdcntl);
-
- /* Ignore General Call, slave transfers are ignored,
- * disable interrupts, exit unknown bus state, enable hold
- * SCL 100kHz normaly or FastMode for 400kHz and above
- */
-
- val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
- if (speed >= 400000)
- val |= IIC_MDCNTL_FSM;
- out_8(&i2c->mdcntl, val);
-
- /* clear control reg */
- out_8(&i2c->cntl, 0x00);
-}
-
-/*
- * This code tries to use the features of the 405GP i2c
- * controller. It will transfer up to 4 bytes in one pass
- * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
- * is possible to do out16(lhz) transfers.
- *
- * cmd_type is 0 for write 1 for read.
- *
- * addr_len can take any value from 0-255, it is only limited
- * by the char, we could make it larger if needed. If it is
- * 0 we skip the address write cycle.
- *
- * Typical case is a Write of an addr followd by a Read. The
- * IBM FAQ does not cover this. On the last byte of the write
- * we don't set the creg CHT bit but the RPST bit.
- *
- * It does not support address only transfers, there must be
- * a data part. If you want to write the address yourself, put
- * it in the data pointer.
- *
- * It does not support transfer to/from address 0.
- *
- * It does not check XFRCNT.
- */
-static int _i2c_transfer(struct i2c_adapter *adap,
- unsigned char cmd_type,
- unsigned char chip,
- unsigned char addr[],
- unsigned char addr_len,
- unsigned char data[],
- unsigned short data_len)
-{
- struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
- u8 *ptr;
- int reading;
- int tran, cnt;
- int result;
- int status;
- int i;
- u8 creg;
-
- if (data == 0 || data_len == 0) {
- /* Don't support data transfer of no length or to address 0 */
- printf( "i2c_transfer: bad call\n" );
- return IIC_NOK;
- }
- if (addr && addr_len) {
- ptr = addr;
- cnt = addr_len;
- reading = 0;
- } else {
- ptr = data;
- cnt = data_len;
- reading = cmd_type;
- }
-
- /* Clear Stop Complete Bit */
- out_8(&i2c->sts, IIC_STS_SCMP);
-
- /* Check init */
- i = 10;
- do {
- /* Get status */
- status = in_8(&i2c->sts);
- i--;
- } while ((status & IIC_STS_PT) && (i > 0));
-
- if (status & IIC_STS_PT) {
- result = IIC_NOK_TOUT;
- return(result);
- }
-
- /* flush the Master/Slave Databuffers */
- out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
- IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
-
- /* need to wait 4 OPB clocks? code below should take that long */
-
- /* 7-bit adressing */
- out_8(&i2c->hmadr, 0);
- out_8(&i2c->lmadr, chip);
-
- tran = 0;
- result = IIC_OK;
- creg = 0;
-
- while (tran != cnt && (result == IIC_OK)) {
- int bc,j;
-
- /*
- * Control register =
- * Normal transfer, 7-bits adressing, Transfer up to
- * bc bytes, Normal start, Transfer is a sequence of transfers
- */
- creg |= IIC_CNTL_PT;
-
- bc = (cnt - tran) > 4 ? 4 : cnt - tran;
- creg |= (bc - 1) << 4;
- /* if the real cmd type is write continue trans */
- if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
- creg |= IIC_CNTL_CHT;
-
- /* last part of address, prepare for repeated start on read */
- if (cmd_type && (ptr == addr) && ((tran + bc) == cnt))
- creg |= IIC_CNTL_RPST;
-
- if (reading) {
- creg |= IIC_CNTL_READ;
- } else {
- for(j = 0; j < bc; j++) {
- /* Set buffer */
- out_8(&i2c->mdbuf, ptr[tran + j]);
- }
- }
- out_8(&i2c->cntl, creg);
-
- /*
- * Transfer is in progress
- * we have to wait for upto 5 bytes of data
- * 1 byte chip address+r/w bit then bc bytes
- * of data.
- * udelay(10) is 1 bit time at 100khz
- * Doubled for slop. 20 is too small.
- */
- i = 2 * 5 * 8;
- do {
- /* Get status */
- status = in_8(&i2c->sts);
- udelay(10);
- i--;
- } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
- (i > 0));
-
- if (status & IIC_STS_ERR) {
- result = IIC_NOK;
- status = in_8(&i2c->extsts);
- /* Lost arbitration? */
- if (status & IIC_EXTSTS_LA)
- result = IIC_NOK_LA;
- /* Incomplete transfer? */
- if (status & IIC_EXTSTS_ICT)
- result = IIC_NOK_ICT;
- /* Transfer aborted? */
- if (status & IIC_EXTSTS_XFRA)
- result = IIC_NOK_XFRA;
- /* Is bus free?
- * If error happened during combined xfer
- * IIC interface is usually stuck in some strange
- * state without a valid stop condition.
- * Brute, but working: generate stop, then soft reset.
- */
- if ((status & IIC_EXTSTS_BCS_MASK)
- != IIC_EXTSTS_BCS_FREE){
- u8 mdcntl = in_8(&i2c->mdcntl);
-
- /* Generate valid stop condition */
- out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
- out_8(&i2c->directcntl, IIC_DIRCNTL_SCC);
- udelay(10);
- out_8(&i2c->directcntl,
- IIC_DIRCNTL_SCC | IIC_DIRCNTL_SDAC);
- out_8(&i2c->xtcntlss, 0);
-
- ppc4xx_i2c_init(adap, (mdcntl & IIC_MDCNTL_FSM)
- ? 400000 : 100000, 0);
- }
- } else if ( status & IIC_STS_PT) {
- result = IIC_NOK_TOUT;
- }
-
- /* Command is reading => get buffer */
- if ((reading) && (result == IIC_OK)) {
- /* Are there data in buffer */
- if (status & IIC_STS_MDBS) {
- /*
- * even if we have data we have to wait 4OPB
- * clocks for it to hit the front of the FIFO,
- * after that we can just read. We should check
- * XFCNT here and if the FIFO is full there is
- * no need to wait.
- */
- udelay(1);
- for (j = 0; j < bc; j++)
- ptr[tran + j] = in_8(&i2c->mdbuf);
- } else
- result = IIC_NOK_DATA;
- }
- creg = 0;
- tran += bc;
- if (ptr == addr && tran == cnt) {
- ptr = data;
- cnt = data_len;
- tran = 0;
- reading = cmd_type;
- }
- }
- return result;
-}
-
-static int ppc4xx_i2c_probe(struct i2c_adapter *adap, uchar chip)
-{
- uchar buf[1];
-
- buf[0] = 0;
-
- /*
- * What is needed is to send the chip address and verify that the
- * address was <ACK>ed (i.e. there was a chip at that address which
- * drove the data line low).
- */
- return (_i2c_transfer(adap, 1, chip << 1, 0, 0, buf, 1) != 0);
-}
-
-static int ppc4xx_i2c_transfer(struct i2c_adapter *adap, uchar chip, uint addr,
- int alen, uchar *buffer, int len, int read)
-{
- uchar xaddr[4];
- int ret;
-
- if (alen > 4) {
- printf("I2C: addr len %d not supported\n", alen);
- return 1;
- }
-
- if (alen > 0) {
- xaddr[0] = (addr >> 24) & 0xFF;
- xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
- }
-
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
- /*
- * EEPROM chips that implement "address overflow" are ones
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
- * address and the extra bits end up in the "chip address"
- * bit slots. This makes a 24WC08 (1Kbyte) chip look like
- * four 256 byte chips.
- *
- * Note that we consider the length of the address field to
- * still be one byte because the extra address bits are
- * hidden in the chip address.
- */
- if (alen > 0)
- chip |= ((addr >> (alen * 8)) &
- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
-#endif
- ret = _i2c_transfer(adap, read, chip << 1, &xaddr[4 - alen], alen,
- buffer, len);
- if (ret) {
- printf("I2C %s: failed %d\n", read ? "read" : "write", ret);
- return 1;
- }
-
- return 0;
-}
-
-static int ppc4xx_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
- int alen, uchar *buffer, int len)
-{
- return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 1);
-}
-
-static int ppc4xx_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
- int alen, uchar *buffer, int len)
-{
- return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
-}
-
-static unsigned int ppc4xx_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
-{
- if (speed != adap->speed)
- return -1;
- return speed;
-}
-
-/*
- * Register ppc4xx i2c adapters
- */
-#ifdef CONFIG_SYS_I2C_PPC4XX_CH0
-U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_0, ppc4xx_i2c_init, ppc4xx_i2c_probe,
- ppc4xx_i2c_read, ppc4xx_i2c_write,
- ppc4xx_i2c_set_bus_speed,
- CONFIG_SYS_I2C_PPC4XX_SPEED_0,
- CONFIG_SYS_I2C_PPC4XX_SLAVE_0, 0)
-#endif
-#ifdef CONFIG_SYS_I2C_PPC4XX_CH1
-U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_1, ppc4xx_i2c_init, ppc4xx_i2c_probe,
- ppc4xx_i2c_read, ppc4xx_i2c_write,
- ppc4xx_i2c_set_bus_speed,
- CONFIG_SYS_I2C_PPC4XX_SPEED_1,
- CONFIG_SYS_I2C_PPC4XX_SLAVE_1, 1)
-#endif
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*-----------------------------------------------------------------------------+
- *
- * File Name: enetemac.c
- *
- * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
- *
- * Author: Mark Wisner
- *
- * Change Activity-
- *
- * Date Description of Change BY
- * --------- --------------------- ---
- * 05-May-99 Created MKW
- * 27-Jun-99 Clean up JWB
- * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
- * 29-Jul-99 Added Full duplex support MKW
- * 06-Aug-99 Changed names for Mal CR reg MKW
- * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
- * 24-Aug-99 Marked descriptor empty after call_xlc MKW
- * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
- * to avoid chaining maximum sized packets. Push starting
- * RX descriptor address up to the next cache line boundary.
- * 16-Jan-00 Added support for booting with IP of 0x0 MKW
- * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
- * EMAC0_RXM register. JWB
- * 12-Mar-01 anne-sophie.harnois@nextream.fr
- * - Variables are compatible with those already defined in
- * include/net.h
- * - Receive buffer descriptor ring is used to send buffers
- * to the user
- * - Info print about send/received/handled packet number if
- * INFO_405_ENET is set
- * 17-Apr-01 stefan.roese@esd-electronics.com
- * - MAL reset in "eth_halt" included
- * - Enet speed and duplex output now in one line
- * 08-May-01 stefan.roese@esd-electronics.com
- * - MAL error handling added (eth_init called again)
- * 13-Nov-01 stefan.roese@esd-electronics.com
- * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex
- * 04-Jan-02 stefan.roese@esd-electronics.com
- * - Wait for PHY auto negotiation to complete added
- * 06-Feb-02 stefan.roese@esd-electronics.com
- * - Bug fixed in waiting for auto negotiation to complete
- * 26-Feb-02 stefan.roese@esd-electronics.com
- * - rx and tx buffer descriptors now allocated (no fixed address
- * used anymore)
- * 17-Jun-02 stefan.roese@esd-electronics.com
- * - MAL error debug printf 'M' removed (rx de interrupt may
- * occur upon many incoming packets with only 4 rx buffers).
- *-----------------------------------------------------------------------------*
- * 17-Nov-03 travis.sawyer@sandburst.com
- * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
- * in the 440GX. This port should work with the 440GP
- * (2 EMACs) also
- * 15-Aug-05 sr@denx.de
- * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
- now handling all 4xx cpu's.
- *-----------------------------------------------------------------------------*/
-
-#include <config.h>
-#include <common.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-emac.h>
-#include <asm/ppc4xx-mal.h>
-#include <miiphy.h>
-#include <malloc.h>
-#include <linux/compiler.h>
-
-#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-#error "CONFIG_MII has to be defined!"
-#endif
-
-#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
-#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
-
-/* Ethernet Transmit and Receive Buffers */
-/* AS.HARNOIS
- * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
- * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
- */
-#define ENET_MAX_MTU PKTSIZE
-#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
-
-/*-----------------------------------------------------------------------------+
- * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
- * Interrupt Controller).
- *-----------------------------------------------------------------------------*/
-#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
-
-#if defined(CONFIG_HAS_ETH3)
-#if !defined(CONFIG_440GX)
-#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
- UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
-#else
-/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
-#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
-#define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
-#endif /* !defined(CONFIG_440GX) */
-#elif defined(CONFIG_HAS_ETH2)
-#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
- UIC_MASK(ETH_IRQ_NUM(2)))
-#elif defined(CONFIG_HAS_ETH1)
-#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
-#else
-#define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
-#endif
-
-/*
- * Define a default version for UIC_ETHxB for non 440GX so that we can
- * use common code for all 4xx variants
- */
-#if !defined(UIC_ETHxB)
-#define UIC_ETHxB 0
-#endif
-
-#define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
-#define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
-#define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
-#define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
-#define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
-
-#define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
-#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
-
-/*
- * We have 3 different interrupt types:
- * - MAL interrupts indicating successful transfer
- * - MAL error interrupts indicating MAL related errors
- * - EMAC interrupts indicating EMAC related errors
- *
- * All those interrupts can be on different UIC's, but since
- * now at least all interrupts from one type are on the same
- * UIC. Only exception is 440GX where the EMAC interrupts are
- * spread over two UIC's!
- */
-#if defined(CONFIG_440GX)
-#define UIC_BASE_MAL UIC1_DCR_BASE
-#define UIC_BASE_MAL_ERR UIC2_DCR_BASE
-#define UIC_BASE_EMAC UIC2_DCR_BASE
-#define UIC_BASE_EMAC_B UIC3_DCR_BASE
-#else
-#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
-#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
-#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
-#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
-#endif
-
-#undef INFO_4XX_ENET
-
-#define BI_PHYMODE_NONE 0
-#define BI_PHYMODE_ZMII 1
-#define BI_PHYMODE_RGMII 2
-#define BI_PHYMODE_GMII 3
-#define BI_PHYMODE_RTBI 4
-#define BI_PHYMODE_TBI 5
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
-#define BI_PHYMODE_SMII 6
-#define BI_PHYMODE_MII 7
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define BI_PHYMODE_RMII 8
-#endif
-#endif
-#define BI_PHYMODE_SGMII 9
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
-#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
-#else
-#define MAL_RX_CHAN_MUL 1
-#endif
-
-/*--------------------------------------------------------------------+
- * Fixed PHY (PHY-less) support for Ethernet Ports.
- *--------------------------------------------------------------------*/
-
-/*
- * Some boards do not have a PHY for each ethernet port. These ports
- * are known as Fixed PHY (or PHY-less) ports. For such ports, set
- * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
- * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
- * duplex should be for these ports in the board configuration
- * file.
- *
- * For Example:
- * #define CONFIG_FIXED_PHY 0xFFFFFFFF
- *
- * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
- * #define CONFIG_PHY1_ADDR 1
- * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
- * #define CONFIG_PHY3_ADDR 3
- *
- * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
- * {devnum, speed, duplex},
- *
- * #define CONFIG_SYS_FIXED_PHY_PORTS \
- * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
- * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
- */
-
-#ifndef CONFIG_FIXED_PHY
-#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
-#endif
-
-#ifndef CONFIG_SYS_FIXED_PHY_PORTS
-#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
-#endif
-
-struct fixed_phy_port {
- unsigned int devnum; /* ethernet port */
- unsigned int speed; /* specified speed 10,100 or 1000 */
- unsigned int duplex; /* specified duplex FULL or HALF */
-};
-
-static const struct fixed_phy_port fixed_phy_port[] = {
- CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
-};
-
-/*-----------------------------------------------------------------------------+
- * Global variables. TX and RX descriptors and buffers.
- *-----------------------------------------------------------------------------*/
-
-/*
- * Get count of EMAC devices (doesn't have to be the max. possible number
- * supported by the cpu)
- *
- * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
- * EMAC count is possible. As it is needed for the Kilauea/Haleakala
- * 405EX/405EXr eval board, using the same binary.
- */
-#if defined(CONFIG_BOARD_EMAC_COUNT)
-#define LAST_EMAC_NUM board_emac_count()
-#else /* CONFIG_BOARD_EMAC_COUNT */
-#if defined(CONFIG_HAS_ETH3)
-#define LAST_EMAC_NUM 4
-#elif defined(CONFIG_HAS_ETH2)
-#define LAST_EMAC_NUM 3
-#elif defined(CONFIG_HAS_ETH1)
-#define LAST_EMAC_NUM 2
-#else
-#define LAST_EMAC_NUM 1
-#endif
-#endif /* CONFIG_BOARD_EMAC_COUNT */
-
-/* normal boards start with EMAC0 */
-#if !defined(CONFIG_EMAC_NR_START)
-#define CONFIG_EMAC_NR_START 0
-#endif
-
-#define MAL_RX_DESC_SIZE 2048
-#define MAL_TX_DESC_SIZE 2048
-#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
-
-/*-----------------------------------------------------------------------------+
- * Prototypes and externals.
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr);
-
-int enetInt (struct eth_device *dev);
-static void mal_err (struct eth_device *dev, unsigned long isr,
- unsigned long uic, unsigned long maldef,
- unsigned long mal_errr);
-static void emac_err (struct eth_device *dev, unsigned long isr);
-
-extern int phy_setup_aneg (char *devname, unsigned char addr);
-int emac4xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
-int emac4xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 value);
-
-int board_emac_count(void);
-
-static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
-{
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EX)
- u32 val;
-
- mfsdr(SDR0_MFR, val);
- val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
- mtsdr(SDR0_MFR, val);
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
- u32 val;
-
- mfsdr(SDR0_ETH_CFG, val);
- val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
- mtsdr(SDR0_ETH_CFG, val);
-#endif
-}
-
-static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
-{
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EX)
- u32 val;
-
- mfsdr(SDR0_MFR, val);
- val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
- mtsdr(SDR0_MFR, val);
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
- u32 val;
-
- mfsdr(SDR0_ETH_CFG, val);
- val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
- mtsdr(SDR0_ETH_CFG, val);
-#endif
-}
-
-/*-----------------------------------------------------------------------------+
-| ppc_4xx_eth_halt
-| Disable MAL channel, and EMACn
-+-----------------------------------------------------------------------------*/
-static void ppc_4xx_eth_halt (struct eth_device *dev)
-{
- EMAC_4XX_HW_PST hw_p = dev->priv;
- u32 val = 10000;
-
- out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
-
- /* 1st reset MAL channel */
- /* Note: writing a 0 to a channel has no effect */
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
-#else
- mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum));
-#endif
- mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum));
-
- /* wait for reset */
- while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) {
- udelay (1000); /* Delay 1 MS so as not to hammer the register */
- val--;
- if (val == 0)
- break;
- }
-
- /* provide clocks for EMAC internal loopback */
- emac_loopback_enable(hw_p);
-
- /* EMAC RESET */
- out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
-
- /* remove clocks for EMAC internal loopback */
- emac_loopback_disable(hw_p);
-
-#ifndef CONFIG_NETCONSOLE
- hw_p->print_speed = 1; /* print speed message again next time */
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
- mfsdr(SDR0_ETH_CFG, val);
- val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
- mtsdr(SDR0_ETH_CFG, val);
-#endif
-
- return;
-}
-
-#if defined (CONFIG_440GX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
- unsigned long pfc1;
- unsigned long zmiifer;
- unsigned long rmiifer;
-
- mfsdr(SDR0_PFC1, pfc1);
- pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
-
- zmiifer = 0;
- rmiifer = 0;
-
- switch (pfc1) {
- case 1:
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_ZMII;
- bis->bi_phymode[3] = BI_PHYMODE_ZMII;
- break;
- case 2:
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_ZMII;
- bis->bi_phymode[3] = BI_PHYMODE_ZMII;
- break;
- case 3:
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- bis->bi_phymode[2] = BI_PHYMODE_RGMII;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 4:
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_RGMII;
- bis->bi_phymode[3] = BI_PHYMODE_RGMII;
- break;
- case 5:
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_ZMII;
- bis->bi_phymode[3] = BI_PHYMODE_RGMII;
- break;
- case 6:
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_RGMII;
- break;
- case 0:
- default:
- zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
- rmiifer = 0x0;
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_ZMII;
- bis->bi_phymode[3] = BI_PHYMODE_ZMII;
- break;
- }
-
- /* Ensure we setup mdio for this devnum and ONLY this devnum */
- zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
-
- out_be32((void *)ZMII0_FER, zmiifer);
- out_be32((void *)RGMII_FER, rmiifer);
-
- return ((int)pfc1);
-}
-#endif /* CONFIG_440_GX */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
- unsigned long zmiifer=0x0;
- unsigned long pfc1;
-
- mfsdr(SDR0_PFC1, pfc1);
- pfc1 &= SDR0_PFC1_SELECT_MASK;
-
- switch (pfc1) {
- case SDR0_PFC1_SELECT_CONFIG_2:
- /* 1 x GMII port */
- out_be32((void *)ZMII0_FER, 0x00);
- out_be32((void *)RGMII_FER, 0x00000037);
- bis->bi_phymode[0] = BI_PHYMODE_GMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- case SDR0_PFC1_SELECT_CONFIG_4:
- /* 2 x RGMII ports */
- out_be32((void *)ZMII0_FER, 0x00);
- out_be32((void *)RGMII_FER, 0x00000055);
- bis->bi_phymode[0] = BI_PHYMODE_RGMII;
- bis->bi_phymode[1] = BI_PHYMODE_RGMII;
- break;
- case SDR0_PFC1_SELECT_CONFIG_6:
- /* 2 x SMII ports */
- out_be32((void *)ZMII0_FER,
- ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
- ((ZMII_FER_SMII) << ZMII_FER_V(1)));
- out_be32((void *)RGMII_FER, 0x00000000);
- bis->bi_phymode[0] = BI_PHYMODE_SMII;
- bis->bi_phymode[1] = BI_PHYMODE_SMII;
- break;
- case SDR0_PFC1_SELECT_CONFIG_1_2:
- /* only 1 x MII supported */
- out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
- out_be32((void *)RGMII_FER, 0x00000000);
- bis->bi_phymode[0] = BI_PHYMODE_MII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- default:
- break;
- }
-
- /* Ensure we setup mdio for this devnum and ONLY this devnum */
- zmiifer = in_be32((void *)ZMII0_FER);
- zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
- out_be32((void *)ZMII0_FER, zmiifer);
-
- return ((int)0x0);
-}
-#endif /* CONFIG_440EPX */
-
-#if defined(CONFIG_405EX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
- u32 rgmiifer = 0;
-
- /*
- * The 405EX(r)'s RGMII bridge can operate in one of several
- * modes, only one of which (2 x RGMII) allows the
- * simultaneous use of both EMACs on the 405EX.
- */
-
- switch (CONFIG_EMAC_PHY_MODE) {
-
- case EMAC_PHY_MODE_NONE:
- /* No ports */
- rgmiifer |= RGMII_FER_DIS << 0;
- rgmiifer |= RGMII_FER_DIS << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_NONE;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- case EMAC_PHY_MODE_NONE_RGMII:
- /* 1 x RGMII port on channel 0 */
- rgmiifer |= RGMII_FER_RGMII << 0;
- rgmiifer |= RGMII_FER_DIS << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_RGMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- case EMAC_PHY_MODE_RGMII_NONE:
- /* 1 x RGMII port on channel 1 */
- rgmiifer |= RGMII_FER_DIS << 0;
- rgmiifer |= RGMII_FER_RGMII << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_NONE;
- bis->bi_phymode[1] = BI_PHYMODE_RGMII;
- break;
- case EMAC_PHY_MODE_RGMII_RGMII:
- /* 2 x RGMII ports */
- rgmiifer |= RGMII_FER_RGMII << 0;
- rgmiifer |= RGMII_FER_RGMII << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_RGMII;
- bis->bi_phymode[1] = BI_PHYMODE_RGMII;
- break;
- case EMAC_PHY_MODE_NONE_GMII:
- /* 1 x GMII port on channel 0 */
- rgmiifer |= RGMII_FER_GMII << 0;
- rgmiifer |= RGMII_FER_DIS << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_GMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- case EMAC_PHY_MODE_NONE_MII:
- /* 1 x MII port on channel 0 */
- rgmiifer |= RGMII_FER_MII << 0;
- rgmiifer |= RGMII_FER_DIS << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_MII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- case EMAC_PHY_MODE_GMII_NONE:
- /* 1 x GMII port on channel 1 */
- rgmiifer |= RGMII_FER_DIS << 0;
- rgmiifer |= RGMII_FER_GMII << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_NONE;
- bis->bi_phymode[1] = BI_PHYMODE_GMII;
- break;
- case EMAC_PHY_MODE_MII_NONE:
- /* 1 x MII port on channel 1 */
- rgmiifer |= RGMII_FER_DIS << 0;
- rgmiifer |= RGMII_FER_MII << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_NONE;
- bis->bi_phymode[1] = BI_PHYMODE_MII;
- break;
- default:
- break;
- }
-
- /* Ensure we setup mdio for this devnum and ONLY this devnum */
- rgmiifer = in_be32((void *)RGMII_FER);
- rgmiifer |= (1 << (19-devnum));
- out_be32((void *)RGMII_FER, rgmiifer);
-
- return ((int)0x0);
-}
-#endif /* CONFIG_405EX */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
- u32 eth_cfg;
- u32 zmiifer; /* ZMII0_FER reg. */
- u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
- u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
- int mode;
-
- zmiifer = 0;
- rmiifer = 0;
- rmiifer1 = 0;
-
-#if defined(CONFIG_460EX)
- mode = 9;
- mfsdr(SDR0_ETH_CFG, eth_cfg);
- if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
- ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
- mode = 11; /* config SGMII */
-#else
- mode = 10;
- mfsdr(SDR0_ETH_CFG, eth_cfg);
- if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
- ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
- ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
- mode = 12; /* config SGMII */
-#endif
-
- /* TODO:
- * NOTE: 460GT has 2 RGMII bridge cores:
- * emac0 ------ RGMII0_BASE
- * |
- * emac1 -----+
- *
- * emac2 ------ RGMII1_BASE
- * |
- * emac3 -----+
- *
- * 460EX has 1 RGMII bridge core:
- * and RGMII1_BASE is disabled
- * emac0 ------ RGMII0_BASE
- * |
- * emac1 -----+
- */
-
- /*
- * Right now only 2*RGMII is supported. Please extend when needed.
- * sr - 2008-02-19
- * Add SGMII support.
- * vg - 2008-07-28
- */
- switch (mode) {
- case 1:
- /* 1 MII - 460EX */
- /* GMC0 EMAC4_0, ZMII Bridge */
- zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
- bis->bi_phymode[0] = BI_PHYMODE_MII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 2:
- /* 2 MII - 460GT */
- /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
- zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
- bis->bi_phymode[0] = BI_PHYMODE_MII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- bis->bi_phymode[2] = BI_PHYMODE_MII;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 3:
- /* 2 RMII - 460EX */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
- bis->bi_phymode[0] = BI_PHYMODE_RMII;
- bis->bi_phymode[1] = BI_PHYMODE_RMII;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 4:
- /* 4 RMII - 460GT */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
- /* ZMII Bridge */
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_RMII;
- bis->bi_phymode[1] = BI_PHYMODE_RMII;
- bis->bi_phymode[2] = BI_PHYMODE_RMII;
- bis->bi_phymode[3] = BI_PHYMODE_RMII;
- break;
- case 5:
- /* 2 SMII - 460EX */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
- bis->bi_phymode[0] = BI_PHYMODE_SMII;
- bis->bi_phymode[1] = BI_PHYMODE_SMII;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 6:
- /* 4 SMII - 460GT */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
- /* ZMII Bridge */
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_SMII;
- bis->bi_phymode[1] = BI_PHYMODE_SMII;
- bis->bi_phymode[2] = BI_PHYMODE_SMII;
- bis->bi_phymode[3] = BI_PHYMODE_SMII;
- break;
- case 7:
- /* This is the default mode that we want for board bringup - Maple */
- /* 1 GMII - 460EX */
- /* GMC0 EMAC4_0, RGMII Bridge 0 */
- rmiifer |= RGMII_FER_MDIO(0);
-
- if (devnum == 0) {
- rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
- bis->bi_phymode[0] = BI_PHYMODE_GMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- } else {
- rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
- bis->bi_phymode[0] = BI_PHYMODE_NONE;
- bis->bi_phymode[1] = BI_PHYMODE_GMII;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- }
- break;
- case 8:
- /* 2 GMII - 460GT */
- /* GMC0 EMAC4_0, RGMII Bridge 0 */
- /* GMC1 EMAC4_2, RGMII Bridge 1 */
- rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
- rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
- rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
- rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
-
- bis->bi_phymode[0] = BI_PHYMODE_GMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- bis->bi_phymode[2] = BI_PHYMODE_GMII;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 9:
- /* 2 RGMII - 460EX */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
- rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
-
- bis->bi_phymode[0] = BI_PHYMODE_RGMII;
- bis->bi_phymode[1] = BI_PHYMODE_RGMII;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 10:
- /* 4 RGMII - 460GT */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
- /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
- rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
- rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_RGMII;
- bis->bi_phymode[1] = BI_PHYMODE_RGMII;
- bis->bi_phymode[2] = BI_PHYMODE_RGMII;
- bis->bi_phymode[3] = BI_PHYMODE_RGMII;
- break;
- case 11:
- /* 2 SGMII - 460EX */
- bis->bi_phymode[0] = BI_PHYMODE_SGMII;
- bis->bi_phymode[1] = BI_PHYMODE_SGMII;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 12:
- /* 3 SGMII - 460GT */
- bis->bi_phymode[0] = BI_PHYMODE_SGMII;
- bis->bi_phymode[1] = BI_PHYMODE_SGMII;
- bis->bi_phymode[2] = BI_PHYMODE_SGMII;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- default:
- break;
- }
-
- /* Set EMAC for MDIO */
- mfsdr(SDR0_ETH_CFG, eth_cfg);
- eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
- mtsdr(SDR0_ETH_CFG, eth_cfg);
-
- out_be32((void *)RGMII_FER, rmiifer);
-#if defined(CONFIG_460GT)
- out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
-#endif
-
- /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
- mfsdr(SDR0_ETH_CFG, eth_cfg);
- eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
- mtsdr(SDR0_ETH_CFG, eth_cfg);
-
- return 0;
-}
-#endif /* CONFIG_460EX || CONFIG_460GT */
-
-static inline void *malloc_aligned(u32 size, u32 align)
-{
- return (void *)(((u32)malloc(size + align) + align - 1) &
- ~(align - 1));
-}
-
-static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
-{
- int i;
- unsigned long reg = 0;
- unsigned long msr;
- unsigned long speed;
- unsigned long duplex;
- unsigned long failsafe;
- unsigned mode_reg;
- unsigned short devnum;
- unsigned short reg_short;
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- u32 opbfreq;
- sys_info_t sysinfo;
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- __maybe_unused int ethgroup = -1;
-#endif
-#endif
- u32 bd_cached;
- u32 bd_uncached = 0;
-#ifdef CONFIG_4xx_DCACHE
- static u32 last_used_ea = 0;
-#endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- int rgmii_channel;
-#endif
-
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- /* before doing anything, figure out if we have a MAC address */
- /* if not, bail */
- if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
- printf("ERROR: ethaddr not set!\n");
- return -1;
- }
-
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- /* Need to get the OPB frequency so we can access the PHY */
- get_sys_info (&sysinfo);
-#endif
-
- msr = mfmsr ();
- mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
-
- devnum = hw_p->devnum;
-
-#ifdef INFO_4XX_ENET
- /* AS.HARNOIS
- * We should have :
- * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
- * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
- * is possible that new packets (without relationship with
- * current transfer) have got the time to arrived before
- * netloop calls eth_halt
- */
- printf ("About preceding transfer (eth%d):\n"
- "- Sent packet number %d\n"
- "- Received packet number %d\n"
- "- Handled packet number %d\n",
- hw_p->devnum,
- hw_p->stats.pkts_tx,
- hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
-
- hw_p->stats.pkts_tx = 0;
- hw_p->stats.pkts_rx = 0;
- hw_p->stats.pkts_handled = 0;
- hw_p->print_speed = 1; /* print speed message again next time */
-#endif
-
- hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
- hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
-
- hw_p->rx_slot = 0; /* MAL Receive Slot */
- hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
- hw_p->rx_u_index = 0; /* Receive User Queue Index */
-
- hw_p->tx_slot = 0; /* MAL Transmit Slot */
- hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
- hw_p->tx_u_index = 0; /* Transmit User Queue Index */
-
-#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
- /* set RMII mode */
- /* NOTE: 440GX spec states that mode is mutually exclusive */
- /* NOTE: Therefore, disable all other EMACS, since we handle */
- /* NOTE: only one emac at a time */
- reg = 0;
- out_be32((void *)ZMII0_FER, 0);
- udelay (100);
-
-#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
- out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
-#elif defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
-#endif
-
- out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum));
-#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
-#if defined(CONFIG_405EX)
- ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
-#endif
-
- sync();
-
- /* provide clocks for EMAC internal loopback */
- emac_loopback_enable(hw_p);
-
- /* EMAC RESET */
- out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
-
- /* remove clocks for EMAC internal loopback */
- emac_loopback_disable(hw_p);
-
- failsafe = 1000;
- while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) {
- udelay (1000);
- failsafe--;
- }
- if (failsafe <= 0)
- printf("\nProblem resetting EMAC!\n");
-
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- /* Whack the M1 register */
- mode_reg = 0x0;
- mode_reg &= ~0x00000038;
- opbfreq = sysinfo.freqOPB / 1000000;
- if (opbfreq <= 50);
- else if (opbfreq <= 66)
- mode_reg |= EMAC_MR1_OBCI_66;
- else if (opbfreq <= 83)
- mode_reg |= EMAC_MR1_OBCI_83;
- else if (opbfreq <= 100)
- mode_reg |= EMAC_MR1_OBCI_100;
- else
- mode_reg |= EMAC_MR1_OBCI_GT100;
-
- out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
-#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
-
-#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
- defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
- if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
- /*
- * In SGMII mode, GPCS access is needed for
- * communication with the internal SGMII SerDes.
- */
- switch (devnum) {
-#if defined(CONFIG_GPCS_PHY_ADDR)
- case 0:
- reg = CONFIG_GPCS_PHY_ADDR;
- break;
-#endif
-#if defined(CONFIG_GPCS_PHY1_ADDR)
- case 1:
- reg = CONFIG_GPCS_PHY1_ADDR;
- break;
-#endif
-#if defined(CONFIG_GPCS_PHY2_ADDR)
- case 2:
- reg = CONFIG_GPCS_PHY2_ADDR;
- break;
-#endif
-#if defined(CONFIG_GPCS_PHY3_ADDR)
- case 3:
- reg = CONFIG_GPCS_PHY3_ADDR;
- break;
-#endif
- }
-
- mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
- mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
- out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
-
- /* Configure GPCS interface to recommended setting for SGMII */
- miiphy_reset(dev->name, reg);
- miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
- miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
- miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
- }
-#endif /* defined(CONFIG_GPCS_PHY_ADDR) */
-
- /* wait for PHY to complete auto negotiation */
- reg_short = 0;
- switch (devnum) {
- case 0:
- reg = CONFIG_PHY_ADDR;
- break;
-#if defined (CONFIG_PHY1_ADDR)
- case 1:
- reg = CONFIG_PHY1_ADDR;
- break;
-#endif
-#if defined (CONFIG_PHY2_ADDR)
- case 2:
- reg = CONFIG_PHY2_ADDR;
- break;
-#endif
-#if defined (CONFIG_PHY3_ADDR)
- case 3:
- reg = CONFIG_PHY3_ADDR;
- break;
-#endif
- default:
- reg = CONFIG_PHY_ADDR;
- break;
- }
-
- bis->bi_phynum[devnum] = reg;
-
- if (reg == CONFIG_FIXED_PHY)
- goto get_speed;
-
-#if defined(CONFIG_PHY_RESET)
- /*
- * Reset the phy, only if its the first time through
- * otherwise, just check the speeds & feeds
- */
- if (hw_p->first_init == 0) {
-#if defined(CONFIG_M88E1111_PHY)
- miiphy_write (dev->name, reg, 0x14, 0x0ce3);
- miiphy_write (dev->name, reg, 0x18, 0x4101);
- miiphy_write (dev->name, reg, 0x09, 0x0e00);
- miiphy_write (dev->name, reg, 0x04, 0x01e1);
-#if defined(CONFIG_M88E1111_DISABLE_FIBER)
- miiphy_read(dev->name, reg, 0x1b, ®_short);
- reg_short |= 0x8000;
- miiphy_write(dev->name, reg, 0x1b, reg_short);
-#endif
-#endif
-#if defined(CONFIG_M88E1112_PHY)
- if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
- /*
- * Marvell 88E1112 PHY needs to have the SGMII MAC
- * interace (page 2) properly configured to
- * communicate with the 460EX/GT GPCS interface.
- */
-
- /* Set access to Page 2 */
- miiphy_write(dev->name, reg, 0x16, 0x0002);
-
- miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
- miiphy_read(dev->name, reg, 0x1a, ®_short);
- reg_short |= 0x8000; /* bypass Auto-Negotiation */
- miiphy_write(dev->name, reg, 0x1a, reg_short);
- miiphy_reset(dev->name, reg); /* reset MAC interface */
-
- /* Reset access to Page 0 */
- miiphy_write(dev->name, reg, 0x16, 0x0000);
- }
-#endif /* defined(CONFIG_M88E1112_PHY) */
- miiphy_reset (dev->name, reg);
-
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
-
-#if defined(CONFIG_CIS8201_PHY)
- /*
- * Cicada 8201 PHY needs to have an extended register whacked
- * for RGMII mode.
- */
- if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
-#if defined(CONFIG_CIS8201_SHORT_ETCH)
- miiphy_write (dev->name, reg, 23, 0x1300);
-#else
- miiphy_write (dev->name, reg, 23, 0x1000);
-#endif
- /*
- * Vitesse VSC8201/Cicada CIS8201 errata:
- * Interoperability problem with Intel 82547EI phys
- * This work around (provided by Vitesse) changes
- * the default timer convergence from 8ms to 12ms
- */
- miiphy_write (dev->name, reg, 0x1f, 0x2a30);
- miiphy_write (dev->name, reg, 0x08, 0x0200);
- miiphy_write (dev->name, reg, 0x1f, 0x52b5);
- miiphy_write (dev->name, reg, 0x02, 0x0004);
- miiphy_write (dev->name, reg, 0x01, 0x0671);
- miiphy_write (dev->name, reg, 0x00, 0x8fae);
- miiphy_write (dev->name, reg, 0x1f, 0x2a30);
- miiphy_write (dev->name, reg, 0x08, 0x0000);
- miiphy_write (dev->name, reg, 0x1f, 0x0000);
- /* end Vitesse/Cicada errata */
- }
-#endif /* defined(CONFIG_CIS8201_PHY) */
-
-#if defined(CONFIG_ET1011C_PHY)
- /*
- * Agere ET1011c PHY needs to have an extended register whacked
- * for RGMII mode.
- */
- if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
- miiphy_read (dev->name, reg, 0x16, ®_short);
- reg_short &= ~(0x7);
- reg_short |= 0x6; /* RGMII DLL Delay*/
- miiphy_write (dev->name, reg, 0x16, reg_short);
-
- miiphy_read (dev->name, reg, 0x17, ®_short);
- reg_short &= ~(0x40);
- miiphy_write (dev->name, reg, 0x17, reg_short);
-
- miiphy_write(dev->name, reg, 0x1c, 0x74f0);
- }
-#endif /* defined(CONFIG_ET1011C_PHY) */
-
-#endif /* defined(CONFIG_440GX) ... */
- /* Start/Restart autonegotiation */
- phy_setup_aneg (dev->name, reg);
- udelay (1000);
- }
-#endif /* defined(CONFIG_PHY_RESET) */
-
- miiphy_read (dev->name, reg, MII_BMSR, ®_short);
-
- /*
- * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
- */
- if ((reg_short & BMSR_ANEGCAPABLE)
- && !(reg_short & BMSR_ANEGCOMPLETE)) {
- puts ("Waiting for PHY auto negotiation to complete");
- i = 0;
- while (!(reg_short & BMSR_ANEGCOMPLETE)) {
- /*
- * Timeout reached ?
- */
- if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts (" TIMEOUT !\n");
- break;
- }
-
- if ((i++ % 1000) == 0) {
- putc ('.');
- }
- udelay (1000); /* 1 ms */
- miiphy_read (dev->name, reg, MII_BMSR, ®_short);
- }
- puts (" done\n");
- udelay (500000); /* another 500 ms (results in faster booting) */
- }
-
-get_speed:
- if (reg == CONFIG_FIXED_PHY) {
- for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
- if (devnum == fixed_phy_port[i].devnum) {
- speed = fixed_phy_port[i].speed;
- duplex = fixed_phy_port[i].duplex;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(fixed_phy_port)) {
- printf("ERROR: PHY (%s) not configured correctly!\n",
- dev->name);
- return -1;
- }
- } else {
- speed = miiphy_speed(dev->name, reg);
- duplex = miiphy_duplex(dev->name, reg);
- }
-
- if (hw_p->print_speed) {
- hw_p->print_speed = 0;
- printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
- (int) speed, (duplex == HALF) ? "HALF" : "FULL",
- hw_p->devnum);
- }
-
-#if defined(CONFIG_440) && \
- !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
- !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
- !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mfsdr(SDR0_MFR, reg);
- if (speed == 100) {
- reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
- } else {
- reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
- }
- mtsdr(SDR0_MFR, reg);
-#endif
-
- /* Set ZMII/RGMII speed according to the phy link speed */
- reg = in_be32((void *)ZMII0_SSR);
- if ( (speed == 100) || (speed == 1000) )
- out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
- else
- out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));
-
- if ((devnum == 2) || (devnum == 3)) {
- if (speed == 1000)
- reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
- else if (speed == 100)
- reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
- else if (speed == 10)
- reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
- else {
- printf("Error in RGMII Speed\n");
- return -1;
- }
- out_be32((void *)RGMII_SSR, reg);
- }
-#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- if (devnum >= 2)
- rgmii_channel = devnum - 2;
- else
- rgmii_channel = devnum;
-
- if (speed == 1000)
- reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
- else if (speed == 100)
- reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
- else if (speed == 10)
- reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
- else {
- printf("Error in RGMII Speed\n");
- return -1;
- }
- out_be32((void *)RGMII_SSR, reg);
-#if defined(CONFIG_460GT)
- if ((devnum == 2) || (devnum == 3))
- out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
-#endif
-#endif
-
- /* set the Mal configuration reg */
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
- MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
-#else
- mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
- /* Errata 1.12: MAL_1 -- Disable MAL bursting */
- if (get_pvr() == PVR_440GP_RB) {
- mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
- }
-#endif
-
- /*
- * Malloc MAL buffer desciptors, make sure they are
- * aligned on cache line boundary size
- * (401/403/IOP480 = 16, 405 = 32)
- * and doesn't cross cache block boundaries.
- */
- if (hw_p->first_init == 0) {
- debug("*** Allocating descriptor memory ***\n");
-
- bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
- if (!bd_cached) {
- printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
- return -1;
- }
-
-#ifdef CONFIG_4xx_DCACHE
- flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
- if (!last_used_ea)
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
-#else
- bd_uncached = bis->bi_memsize;
-#endif
- else
- bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
-
- last_used_ea = bd_uncached;
- program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
- TLB_WORD2_I_ENABLE);
-#else
- bd_uncached = bd_cached;
-#endif
- hw_p->tx_phys = bd_cached;
- hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
- hw_p->tx = (mal_desc_t *)(bd_uncached);
- hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
- debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx);
- }
-
- for (i = 0; i < NUM_TX_BUFF; i++) {
- hw_p->tx[i].ctrl = 0;
- hw_p->tx[i].data_len = 0;
- if (hw_p->first_init == 0)
- hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
- L1_CACHE_BYTES);
- hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
- if ((NUM_TX_BUFF - 1) == i)
- hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
- hw_p->tx_run[i] = -1;
- debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr);
- }
-
- for (i = 0; i < NUM_RX_BUFF; i++) {
- hw_p->rx[i].ctrl = 0;
- hw_p->rx[i].data_len = 0;
- hw_p->rx[i].data_ptr = (char *)net_rx_packets[i];
- if ((NUM_RX_BUFF - 1) == i)
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
- hw_p->rx_ready[i] = -1;
- debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr);
- }
-
- reg = 0x00000000;
-
- reg |= dev->enetaddr[0]; /* set high address */
- reg = reg << 8;
- reg |= dev->enetaddr[1];
-
- out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);
-
- reg = 0x00000000;
- reg |= dev->enetaddr[2]; /* set low address */
- reg = reg << 8;
- reg |= dev->enetaddr[3];
- reg = reg << 8;
- reg |= dev->enetaddr[4];
- reg = reg << 8;
- reg |= dev->enetaddr[5];
-
- out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);
-
- switch (devnum) {
- case 1:
- /* setup MAL tx & rx channel pointers */
-#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
- mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
-#else
- mtdcr (MAL0_TXCTP1R, hw_p->tx_phys);
-#endif
-#if defined(CONFIG_440)
- mtdcr (MAL0_TXBADDR, 0x0);
- mtdcr (MAL0_RXBADDR, 0x0);
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- mtdcr (MAL0_RXCTP8R, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16);
-#else
- mtdcr (MAL0_RXCTP1R, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16);
-#endif
- break;
-#if defined (CONFIG_440GX)
- case 2:
- /* setup MAL tx & rx channel pointers */
- mtdcr (MAL0_TXBADDR, 0x0);
- mtdcr (MAL0_RXBADDR, 0x0);
- mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
- mtdcr (MAL0_RXCTP2R, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16);
- break;
- case 3:
- /* setup MAL tx & rx channel pointers */
- mtdcr (MAL0_TXBADDR, 0x0);
- mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
- mtdcr (MAL0_RXBADDR, 0x0);
- mtdcr (MAL0_RXCTP3R, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16);
- break;
-#endif /* CONFIG_440GX */
-#if defined (CONFIG_460GT)
- case 2:
- /* setup MAL tx & rx channel pointers */
- mtdcr (MAL0_TXBADDR, 0x0);
- mtdcr (MAL0_RXBADDR, 0x0);
- mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
- mtdcr (MAL0_RXCTP16R, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16);
- break;
- case 3:
- /* setup MAL tx & rx channel pointers */
- mtdcr (MAL0_TXBADDR, 0x0);
- mtdcr (MAL0_RXBADDR, 0x0);
- mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
- mtdcr (MAL0_RXCTP24R, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16);
- break;
-#endif /* CONFIG_460GT */
- case 0:
- default:
- /* setup MAL tx & rx channel pointers */
-#if defined(CONFIG_440)
- mtdcr (MAL0_TXBADDR, 0x0);
- mtdcr (MAL0_RXBADDR, 0x0);
-#endif
- mtdcr (MAL0_TXCTP0R, hw_p->tx_phys);
- mtdcr (MAL0_RXCTP0R, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16);
- break;
- }
-
- /* Enable MAL transmit and receive channels */
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
-#else
- mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
-#endif
- mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
-
- /* set transmit enable & receive enable */
- out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);
-
- mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
-
- /* set rx-/tx-fifo size */
- mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
-
- /* set speed */
- if (speed == _1000BASET) {
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
- unsigned long pfc1;
-
- mfsdr (SDR0_PFC1, pfc1);
- pfc1 |= SDR0_PFC1_EM_1000;
- mtsdr (SDR0_PFC1, pfc1);
-#endif
- mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
- } else if (speed == _100BASET)
- mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
- else
- mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
- if (duplex == FULL)
- mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;
-
- out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
-
- /* Enable broadcast and indvidual address */
- /* TBS: enabling runts as some misbehaved nics will send runts */
- out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
-
- /* we probably need to set the tx mode1 reg? maybe at tx time */
-
- /* set transmit request threshold register */
- out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
-
- /* set receive low/high water mark register */
-#if defined(CONFIG_440)
- /* 440s has a 64 byte burst length */
- out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
-#else
- /* 405s have a 16 byte burst length */
- out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
-#endif /* defined(CONFIG_440) */
- out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);
-
- /* Set fifo limit entry in tx mode 0 */
- out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
- /* Frame gap set */
- out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
-
- /* Set EMAC IER */
- hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
- if (speed == _100BASET)
- hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
-
- out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
- out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);
-
- if (hw_p->first_init == 0) {
- /*
- * Connect interrupt service routines
- */
- irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
- (interrupt_handler_t *) enetInt, dev);
- }
-
- mtmsr (msr); /* enable interrupts again */
-
- hw_p->bis = bis;
- hw_p->first_init = 1;
-
- return 0;
-}
-
-
-static int ppc_4xx_eth_send(struct eth_device *dev, void *ptr, int len)
-{
- struct enet_frame *ef_ptr;
- ulong time_start, time_now;
- unsigned long temp_txm0;
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- ef_ptr = (struct enet_frame *) ptr;
-
- /*-----------------------------------------------------------------------+
- * Copy in our address into the frame.
- *-----------------------------------------------------------------------*/
- (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
-
- /*-----------------------------------------------------------------------+
- * If frame is too long or too short, modify length.
- *-----------------------------------------------------------------------*/
- /* TBS: where does the fragment go???? */
- if (len > ENET_MAX_MTU)
- len = ENET_MAX_MTU;
-
- /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
- memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
- flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
-
- /*-----------------------------------------------------------------------+
- * set TX Buffer busy, and send it
- *-----------------------------------------------------------------------*/
- hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
- EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
- ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
- if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
- hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
-
- hw_p->tx[hw_p->tx_slot].data_len = (short) len;
- hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
-
- sync();
-
- out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
- in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
-#ifdef INFO_4XX_ENET
- hw_p->stats.pkts_tx++;
-#endif
-
- /*-----------------------------------------------------------------------+
- * poll unitl the packet is sent and then make sure it is OK
- *-----------------------------------------------------------------------*/
- time_start = get_timer (0);
- while (1) {
- temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
- /* loop until either TINT turns on or 3 seconds elapse */
- if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
- /* transmit is done, so now check for errors
- * If there is an error, an interrupt should
- * happen when we return
- */
- time_now = get_timer (0);
- if ((time_now - time_start) > 3000) {
- return (-1);
- }
- } else {
- return (len);
- }
- }
-}
-
-int enetInt (struct eth_device *dev)
-{
- int serviced;
- int rc = -1; /* default to not us */
- u32 mal_isr;
- u32 emac_isr = 0;
- u32 mal_eob;
- u32 uic_mal;
- u32 uic_mal_err;
- u32 uic_emac;
- u32 uic_emac_b;
- EMAC_4XX_HW_PST hw_p;
-
- /*
- * Because the mal is generic, we need to get the current
- * eth device
- */
- dev = eth_get_dev();
-
- hw_p = dev->priv;
-
- /* enter loop that stays in interrupt code until nothing to service */
- do {
- serviced = 0;
-
- uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
- uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
- uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
- uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
-
- if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
- && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
- && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
- /* not for us */
- return (rc);
- }
-
- /* get and clear controller status interrupts */
- /* look at MAL and EMAC error interrupts */
- if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
- /* we have a MAL error interrupt */
- mal_isr = mfdcr(MAL0_ESR);
- mal_err(dev, mal_isr, uic_mal_err,
- MAL_UIC_DEF, MAL_UIC_ERR);
-
- /* clear MAL error interrupt status bits */
- mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
- UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
-
- return -1;
- }
-
- /* look for EMAC errors */
- if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
- emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
- emac_err(dev, emac_isr);
-
- /* clear EMAC error interrupt status bits */
- mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
- mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
-
- return -1;
- }
-
- /* handle MAX TX EOB interrupt from a tx */
- if (uic_mal & UIC_MAL_TXEOB) {
- /* clear MAL interrupt status bits */
- mal_eob = mfdcr(MAL0_TXEOBISR);
- mtdcr(MAL0_TXEOBISR, mal_eob);
- mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
-
- /* indicate that we serviced an interrupt */
- serviced = 1;
- rc = 0;
- }
-
- /* handle MAL RX EOB interrupt from a receive */
- /* check for EOB on valid channels */
- if (uic_mal & UIC_MAL_RXEOB) {
- mal_eob = mfdcr(MAL0_RXEOBISR);
- if (mal_eob &
- (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
- /* push packet to upper layer */
- enet_rcv(dev, emac_isr);
-
- /* clear MAL interrupt status bits */
- mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
-
- /* indicate that we serviced an interrupt */
- serviced = 1;
- rc = 0;
- }
- }
-#if defined(CONFIG_405EZ)
- /*
- * On 405EZ the RX-/TX-interrupts are coalesced into
- * one IRQ bit in the UIC. We need to acknowledge the
- * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well.
- */
- mtsdr(SDR0_ICINTSTAT,
- SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
-#endif /* defined(CONFIG_405EZ) */
- } while (serviced);
-
- return (rc);
-}
-
-/*-----------------------------------------------------------------------------+
- * MAL Error Routine
- *-----------------------------------------------------------------------------*/
-static void mal_err (struct eth_device *dev, unsigned long isr,
- unsigned long uic, unsigned long maldef,
- unsigned long mal_errr)
-{
- mtdcr (MAL0_ESR, isr); /* clear interrupt */
-
- /* clear DE interrupt */
- mtdcr (MAL0_TXDEIR, 0xC0000000);
- mtdcr (MAL0_RXDEIR, 0x80000000);
-
-#ifdef INFO_4XX_ENET
- printf("\nMAL error occurred.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx\n",
- isr, uic, maldef, mal_errr);
-#endif
-
- eth_init(); /* start again... */
-}
-
-/*-----------------------------------------------------------------------------+
- * EMAC Error Routine
- *-----------------------------------------------------------------------------*/
-static void emac_err (struct eth_device *dev, unsigned long isr)
-{
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- printf ("EMAC%d error occurred.... ISR = %lx\n", hw_p->devnum, isr);
- out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
-}
-
-/*-----------------------------------------------------------------------------+
- * enet_rcv() handles the ethernet receive data
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr)
-{
- unsigned long data_len;
- unsigned long rx_eob_isr;
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- int handled = 0;
- int i;
- int loop_count = 0;
-
- rx_eob_isr = mfdcr (MAL0_RXEOBISR);
- if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
- /* clear EOB */
- mtdcr (MAL0_RXEOBISR, rx_eob_isr);
-
- /* EMAC RX done */
- while (1) { /* do all */
- i = hw_p->rx_slot;
-
- if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
- || (loop_count >= NUM_RX_BUFF))
- break;
-
- loop_count++;
- handled++;
- data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
- if (data_len) {
- if (data_len > ENET_MAX_MTU) /* Check len */
- data_len = 0;
- else {
- if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
- data_len = 0;
- hw_p->stats.rx_err_log[hw_p->
- rx_err_index]
- = hw_p->rx[i].ctrl;
- hw_p->rx_err_index++;
- if (hw_p->rx_err_index ==
- MAX_ERR_LOG)
- hw_p->rx_err_index =
- 0;
- } /* emac_erros */
- } /* data_len < max mtu */
- } /* if data_len */
- if (!data_len) { /* no data */
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
-
- hw_p->stats.data_len_err++; /* Error at Rx */
- }
-
- /* !data_len */
- /* AS.HARNOIS */
- /* Check if user has already eaten buffer */
- /* if not => ERROR */
- else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
- if (hw_p->is_receiving)
- printf ("ERROR : Receive buffers are full!\n");
- break;
- } else {
- hw_p->stats.rx_frames++;
- hw_p->stats.rx += data_len;
-#ifdef INFO_4XX_ENET
- hw_p->stats.pkts_rx++;
-#endif
- /* AS.HARNOIS
- * use ring buffer
- */
- hw_p->rx_ready[hw_p->rx_i_index] = i;
- hw_p->rx_i_index++;
- if (NUM_RX_BUFF == hw_p->rx_i_index)
- hw_p->rx_i_index = 0;
-
- hw_p->rx_slot++;
- if (NUM_RX_BUFF == hw_p->rx_slot)
- hw_p->rx_slot = 0;
-
- /* AS.HARNOIS
- * free receive buffer only when
- * buffer has been handled (eth_rx)
- rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
- */
- } /* if data_len */
- } /* while */
- } /* if EMACK_RXCHL */
-}
-
-
-static int ppc_4xx_eth_rx (struct eth_device *dev)
-{
- int length;
- int user_index;
- unsigned long msr;
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- hw_p->is_receiving = 1; /* tell driver */
-
- for (;;) {
- /* AS.HARNOIS
- * use ring buffer and
- * get index from rx buffer desciptor queue
- */
- user_index = hw_p->rx_ready[hw_p->rx_u_index];
- if (user_index == -1) {
- length = -1;
- break; /* nothing received - leave for() loop */
- }
-
- msr = mfmsr ();
- mtmsr (msr & ~(MSR_EE));
-
- length = hw_p->rx[user_index].data_len & 0x0fff;
-
- /*
- * Pass the packet up to the protocol layers.
- * net_process_received_packet(net_rx_packets[rxIdx],
- * length - 4);
- * net_process_received_packet(net_rx_packets[i], length);
- */
- invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
- (u32)hw_p->rx[user_index].data_ptr +
- length - 4);
- net_process_received_packet(net_rx_packets[user_index],
- length - 4);
- /* Free Recv Buffer */
- hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
- /* Free rx buffer descriptor queue */
- hw_p->rx_ready[hw_p->rx_u_index] = -1;
- hw_p->rx_u_index++;
- if (NUM_RX_BUFF == hw_p->rx_u_index)
- hw_p->rx_u_index = 0;
-
-#ifdef INFO_4XX_ENET
- hw_p->stats.pkts_handled++;
-#endif
-
- mtmsr (msr); /* Enable IRQ's */
- }
-
- hw_p->is_receiving = 0; /* tell driver */
-
- return length;
-}
-
-int ppc_4xx_eth_initialize (bd_t * bis)
-{
- static int virgin = 0;
- struct eth_device *dev;
- int eth_num = 0;
- EMAC_4XX_HW_PST hw = NULL;
- u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
- u32 hw_addr[4];
- u32 mal_ier;
-
-#if defined(CONFIG_440GX)
- unsigned long pfc1;
-
- mfsdr (SDR0_PFC1, pfc1);
- pfc1 &= ~(0x01e00000);
- pfc1 |= 0x01200000;
- mtsdr (SDR0_PFC1, pfc1);
-#endif
-
- /* first clear all mac-addresses */
- for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
- memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
-
- for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
- int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START;
- switch (eth_num) {
- default: /* fall through */
- case 0:
- eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
- hw_addr[eth_num] = 0x0;
- break;
-#ifdef CONFIG_HAS_ETH1
- case 1:
- eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
- hw_addr[eth_num] = 0x100;
- break;
-#endif
-#ifdef CONFIG_HAS_ETH2
- case 2:
- eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
-#if defined(CONFIG_460GT)
- hw_addr[eth_num] = 0x300;
-#else
- hw_addr[eth_num] = 0x400;
-#endif
- break;
-#endif
-#ifdef CONFIG_HAS_ETH3
- case 3:
- eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
-#if defined(CONFIG_460GT)
- hw_addr[eth_num] = 0x400;
-#else
- hw_addr[eth_num] = 0x600;
-#endif
- break;
-#endif
- }
- }
-
- /* set phy num and mode */
- bis->bi_phynum[0] = CONFIG_PHY_ADDR;
- bis->bi_phymode[0] = 0;
-
-#if defined(CONFIG_PHY1_ADDR)
- bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
- bis->bi_phymode[1] = 0;
-#endif
-#if defined(CONFIG_440GX)
- bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
- bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
- bis->bi_phymode[2] = 2;
- bis->bi_phymode[3] = 2;
-#endif
-
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EX)
- ppc_4xx_eth_setup_bridge(0, bis);
-#endif
-
- for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
- /*
- * See if we can actually bring up the interface,
- * otherwise, skip it
- */
- if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
- bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
- continue;
- }
-
- /* Allocate device structure */
- dev = (struct eth_device *) malloc (sizeof (*dev));
- if (dev == NULL) {
- printf ("ppc_4xx_eth_initialize: "
- "Cannot allocate eth_device %d\n", eth_num);
- return (-1);
- }
- memset(dev, 0, sizeof(*dev));
-
- /* Allocate our private use data */
- hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
- if (hw == NULL) {
- printf ("ppc_4xx_eth_initialize: "
- "Cannot allocate private hw data for eth_device %d",
- eth_num);
- free (dev);
- return (-1);
- }
- memset(hw, 0, sizeof(*hw));
-
- hw->hw_addr = hw_addr[eth_num];
- memcpy (dev->enetaddr, ethaddr[eth_num], 6);
- hw->devnum = eth_num;
- hw->print_speed = 1;
-
- sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
- dev->priv = (void *) hw;
- dev->init = ppc_4xx_eth_init;
- dev->halt = ppc_4xx_eth_halt;
- dev->send = ppc_4xx_eth_send;
- dev->recv = ppc_4xx_eth_rx;
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = emac4xx_miiphy_read;
- mdiodev->write = emac4xx_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
-
- if (0 == virgin) {
- /* set the MAL IER ??? names may change with new spec ??? */
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- mal_ier =
- MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
- MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
-#else
- mal_ier =
- MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
- MAL_IER_OPBE | MAL_IER_PLBE;
-#endif
- mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */
- mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */
- mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */
- mtdcr (MAL0_IER, mal_ier);
-
- /* install MAL interrupt handler */
- irq_install_handler (VECNUM_MAL_SERR,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MAL_TXEOB,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MAL_RXEOB,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MAL_TXDE,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MAL_RXDE,
- (interrupt_handler_t *) enetInt,
- dev);
- virgin = 1;
- }
- } /* end for each supported device */
-
- return 0;
-}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
obj-$(CONFIG_AG7XXX) += ag7xxx.o
obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
ll_temac->ctrladdr = devinf->ctrl_addr;
if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_PLB) {
-#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405)
- if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_DCR) {
- ll_temac_collect_xldcr_sdma_reg_addr(dev);
- ll_temac->in32 = ll_temac_xldcr_in32;
- ll_temac->out32 = ll_temac_xldcr_out32;
- } else
-#endif
- {
- ll_temac_collect_xlplb_sdma_reg_addr(dev);
- ll_temac->in32 = ll_temac_xlplb_in32;
- ll_temac->out32 = ll_temac_xlplb_out32;
- }
+ ll_temac_collect_xlplb_sdma_reg_addr(dev);
+ ll_temac->in32 = ll_temac_xlplb_in32;
+ ll_temac->out32 = ll_temac_xlplb_out32;
ll_temac->ctrlinit = ll_temac_init_sdma;
ll_temac->ctrlhalt = ll_temac_halt_sdma;
ll_temac->ctrlreset = ll_temac_reset_sdma;
*/
static struct rtx_cdmac_bd cdmac_bd __aligned(32);
-#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405)
-
-/*
- * Indirect DCR access operations mi{ft}dcr_xilinx() espacialy
- * for Xilinx PowerPC implementations on FPGA.
- *
- * FIXME: This part should go up to arch/powerpc -- but where?
- */
-#include <asm/processor.h>
-#define XILINX_INDIRECT_DCR_ADDRESS_REG 0
-#define XILINX_INDIRECT_DCR_ACCESS_REG 1
-inline unsigned mifdcr_xilinx(const unsigned dcrn)
-{
- mtdcr(XILINX_INDIRECT_DCR_ADDRESS_REG, dcrn);
- return mfdcr(XILINX_INDIRECT_DCR_ACCESS_REG);
-}
-inline void mitdcr_xilinx(const unsigned dcrn, int val)
-{
- mtdcr(XILINX_INDIRECT_DCR_ADDRESS_REG, dcrn);
- mtdcr(XILINX_INDIRECT_DCR_ACCESS_REG, val);
-}
-
-/* Xilinx Device Control Register (DCR) in/out accessors */
-inline unsigned ll_temac_xldcr_in32(phys_addr_t addr)
-{
- return mifdcr_xilinx((const unsigned)addr);
-}
-inline void ll_temac_xldcr_out32(phys_addr_t addr, unsigned value)
-{
- mitdcr_xilinx((const unsigned)addr, value);
-}
-
-void ll_temac_collect_xldcr_sdma_reg_addr(struct eth_device *dev)
-{
- struct ll_temac *ll_temac = dev->priv;
- phys_addr_t dmac_ctrl = ll_temac->ctrladdr;
- phys_addr_t *ra = ll_temac->sdma_reg_addr;
-
- ra[TX_NXTDESC_PTR] = dmac_ctrl + TX_NXTDESC_PTR;
- ra[TX_CURBUF_ADDR] = dmac_ctrl + TX_CURBUF_ADDR;
- ra[TX_CURBUF_LENGTH] = dmac_ctrl + TX_CURBUF_LENGTH;
- ra[TX_CURDESC_PTR] = dmac_ctrl + TX_CURDESC_PTR;
- ra[TX_TAILDESC_PTR] = dmac_ctrl + TX_TAILDESC_PTR;
- ra[TX_CHNL_CTRL] = dmac_ctrl + TX_CHNL_CTRL;
- ra[TX_IRQ_REG] = dmac_ctrl + TX_IRQ_REG;
- ra[TX_CHNL_STS] = dmac_ctrl + TX_CHNL_STS;
- ra[RX_NXTDESC_PTR] = dmac_ctrl + RX_NXTDESC_PTR;
- ra[RX_CURBUF_ADDR] = dmac_ctrl + RX_CURBUF_ADDR;
- ra[RX_CURBUF_LENGTH] = dmac_ctrl + RX_CURBUF_LENGTH;
- ra[RX_CURDESC_PTR] = dmac_ctrl + RX_CURDESC_PTR;
- ra[RX_TAILDESC_PTR] = dmac_ctrl + RX_TAILDESC_PTR;
- ra[RX_CHNL_CTRL] = dmac_ctrl + RX_CHNL_CTRL;
- ra[RX_IRQ_REG] = dmac_ctrl + RX_IRQ_REG;
- ra[RX_CHNL_STS] = dmac_ctrl + RX_CHNL_STS;
- ra[DMA_CONTROL_REG] = dmac_ctrl + DMA_CONTROL_REG;
-}
-
-#endif /* CONFIG_XILINX_440 || ONFIG_XILINX_405 */
-
/* Xilinx Processor Local Bus (PLB) in/out accessors */
inline unsigned ll_temac_xlplb_in32(phys_addr_t addr)
{
#define DMA_CONTROL_TPE (1 << 2)
#define DMA_CONTROL_RESET (1 << 0)
-#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405)
-
-/* Xilinx Device Control Register (DCR) in/out accessors */
-unsigned ll_temac_xldcr_in32(phys_addr_t addr);
-void ll_temac_xldcr_out32(phys_addr_t addr, unsigned value);
-
-/* collect all register addresses for Xilinx DCR in/out accessors */
-void ll_temac_collect_xldcr_sdma_reg_addr(struct eth_device *dev);
-
-#endif /* CONFIG_XILINX_440 || CONFIG_XILINX_405 */
-
/* Xilinx Processor Local Bus (PLB) in/out accessors */
unsigned ll_temac_xlplb_in32(phys_addr_t base);
void ll_temac_xlplb_out32(phys_addr_t base, unsigned value);
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
-#elif defined(CONFIG_440GX) || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
- defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
-static int \
-indirect_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, int offset, type val) \
-{ \
- u32 b, d,f; \
- b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
- b = b - hose->first_busno; \
- dev = PCI_BDF(b, d, f); \
- if (PCI_BUS(dev) > 0) \
- out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \
- else \
- out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
- cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
- return 0; \
-}
#else
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
}
#endif
-#define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask) \
-static int \
-indirect_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, int offset, type val) \
-{ \
- unsigned int msr = mfmsr(); \
- mtmsr(msr & ~(MSR_EE | MSR_CE)); \
- out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
- cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
- out_le32(hose->cfg_addr, 0x00000000); \
- mtmsr(msr); \
- return 0; \
-}
-
INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3)
INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2)
INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0)
-#ifdef CONFIG_405GP
-INDIRECT_PCI_OP_ERRATA6(write, byte, u8, out_8, 3)
-INDIRECT_PCI_OP_ERRATA6(write, word, u16, out_le16, 2)
-INDIRECT_PCI_OP_ERRATA6(write, dword, u32, out_le32, 0)
-#else
INDIRECT_PCI_OP(write, byte, u8, out_8, 3)
INDIRECT_PCI_OP(write, word, u16, out_le16, 2)
INDIRECT_PCI_OP(write, dword, u32, out_le32, 0)
-#endif
void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
{
#endif
#if defined(CONFIG_CPU_ARM920T) || \
- defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \
defined(CONFIG_SYS_OHCI_USE_NPS)
# define OHCI_USE_NPS /* force NoPowerSwitching mode */
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
-#if defined(CONFIG_405) || \
- defined(CONFIG_405GP) || \
- defined(CONFIG_405EP) || \
- defined(CONFIG_405EZ) || \
- defined(CONFIG_405EX) || \
- defined(CONFIG_440)
- unsigned char bi_s_version[4]; /* Version of this structure */
- unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
- unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
- unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
- unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
- unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
-#endif
#ifdef CONFIG_HAS_ETH1
unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */
unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */
#endif
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
- defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- unsigned int bi_opbfreq; /* OPB clock in Hz */
- int bi_iic_fast[2]; /* Use fast i2c mode */
-#endif
-#if defined(CONFIG_4xx)
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- int bi_phynum[4]; /* Determines phy mapping */
- int bi_phymode[4]; /* Determines phy mode */
-#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440)
- int bi_phynum[2]; /* Determines phy mapping */
- int bi_phymode[2]; /* Determines phy mode */
-#else
- int bi_phynum[1]; /* Determines phy mapping */
- int bi_phymode[1]; /* Determines phy mode */
-#endif
-#endif /* defined(CONFIG_4xx) */
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
#ifdef CONFIG_NR_DRAM_BANKS
#define DBSR_IA3 0x00200000 /* Instr Address Compare 3 Event */
#define DBSR_IA4 0x00100000 /* Instr Address Compare 4 Event */
#endif
-#ifndef CONFIG_440
#define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */
#define DBSR_IA2 0x02000000 /* Instr Address Compare 2 Event */
#define DBSR_IA3 0x00080000 /* Instr Address Compare 3 Event */
#define DBSR_IA4 0x00040000 /* Instr Address Compare 4 Event */
-#endif
struct spr_info {
int spr_val;
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
-
-#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */
-#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_SYS_EEPROM_WREN 1
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (PB0) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (PB1) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * GPIO definitions
- */
-#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */
-#define CONFIG_SYS_SELF_RST (0x80000000 >> 14) /* GPIO14 */
-#define CONFIG_SYS_PB_LED (0x80000000 >> 16) /* GPIO16 */
-#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
-#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
-#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-
-#define CONFIG_SUPPORT_VFAT
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING /* add command line history */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
-
-#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-#define CONFIG_PRAM 0 /* use pram variable to overwrite */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
-
-#else /* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-#endif
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0, 1) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_LED_ADDR 0xF0000380
-
-/* Memory Bank 3 (CompactFlash IDE) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (NVRAM/RTC) initialization */
-/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
-#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
-#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 5 (optional Quart) initialization */
-#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 6 (FPGA internal) initialization */
-#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE 0x00
-#define CONFIG_SYS_FPGA_STATUS 0x02
-#define CONFIG_SYS_FPGA_TS 0x04
-#define CONFIG_SYS_FPGA_TS_LOW 0x06
-#define CONFIG_SYS_FPGA_TS_CAP0 0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
-#define CONFIG_SYS_FPGA_TS_CAP1 0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
-#define CONFIG_SYS_FPGA_TS_CAP2 0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
-#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
-#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
-#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/***********************************************************
- * High Level Configuration Options
- * (easy to change)
- ***********************************************************/
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-/***********************************************************
- * Note that it may also be a MIP405T board which is a subset of the
- * MIP405
- ***********************************************************/
-/***********************************************************
- * WARNING:
- * CONFIG_BOOT_PCI is only used for first boot-up and should
- * NOT be enabled for production bootloader
- ***********************************************************/
-/*#define CONFIG_BOOT_PCI 1*/
-/***********************************************************
- * Clock
- ***********************************************************/
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-
-/**************************************************************
- * I2C Stuff:
- * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
- * 0x53.
- * The Atmel EEPROM uses 16Bit addressing.
- ***************************************************************/
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
- /* 64 byte page write mode using*/
- /* last 6 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
-
-/***************************************************************
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- ***************************************************************/
-/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
-#define SDRAM_EEPROM_READ_ADDRESS 0xA1
-*/
-/**************************************************************
- * Environment definitions
- **************************************************************/
-/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
-
-#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
-#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
-
-#define CONFIG_IPADDR 10.0.0.100
-#define CONFIG_SERVERIP 10.0.0.1
-#define CONFIG_PREBOOT
-/***************************************************************
- * defines if an overwrite_console function exists
- *************************************************************/
-/***************************************************************
- * defines if the overwrite_console should be stored in the
- * environment
- **************************************************************/
-
-/**************************************************************
- * loads config
- *************************************************************/
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MISC_INIT_R
-/***********************************************************
- * Miscellaneous configurable options
- **********************************************************/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 916667
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
- /* resource configuration */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_UPDATE_FLASH_SIZE
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=mip405-0"
-#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
-*/
-
-/*-----------------------------------------------------------------------
- * Logbuffer Configuration
- */
-#undef CONFIG_LOGBUFFER /* supported but not enabled */
-/*-----------------------------------------------------------------------
- * Bootcountlimit Configuration
- */
-#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
-
-/*-----------------------------------------------------------------------
- * POST Configuration
- */
-#if 0 /* enable this if POST is desired (is supported but not enabled) */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_I2C)
-
-#endif
-/*
- * Init Memory Controller:
- */
-#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
-#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/* Peripheral Bus Mapping */
-#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
-#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
-#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
-
-#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
-#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in On Chip SRAM)
- */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* reserve some memory for POST and BOOT limit info */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
-#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
-#endif
-
-/***********************************************************************
- * External peripheral base address
- ***********************************************************************/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
-
-/***********************************************************************
- * Last Stage Init
- ***********************************************************************/
-#define CONFIG_LAST_STAGE_INIT
-/************************************************************
- * Ethernet Stuff
- ***********************************************************/
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
-#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
-/************************************************************
- * RTC
- ***********************************************************/
-#define CONFIG_RTC_MC146818
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/************************************************************
- * IDE/ATA stuff
- ************************************************************/
-#if defined(CONFIG_TARGET_MIP405T)
-#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
-#else
-#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
-#endif
-
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET /* reset for ide supported... */
-#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
-#define CONFIG_SUPPORT_VFAT
-/************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI /* enable ATAPI Support */
-
-/************************************************************
- * DISK Partition support
- ************************************************************/
-
-/************************************************************
- * Video support
- ************************************************************/
-#define CONFIG_VIDEO_LOGO
-#undef CONFIG_VIDEO_ONBOARD
-/************************************************************
- * USB support EXPERIMENTAL
- ************************************************************/
-#if !defined(CONFIG_TARGET_MIP405T)
-#define CONFIG_USB_UHCI
-
-/* Enable needed helper functions */
-#endif
-/************************************************************
- * Debug support
- ************************************************************/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/************************************************************
- * support BZIP2 compression
- ************************************************************/
-#define CONFIG_BZIP2 1
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/***********************************************************
- * High Level Configuration Options
- * (easy to change)
- ***********************************************************/
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_PIP405 1 /* ...on a PIP405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-/***********************************************************
- * Clock
- ***********************************************************/
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
-#define CONFIG_SCSI
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SAVES
-
-/**************************************************************
- * I2C Stuff:
- * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
- * 0x53.
- * Caution: on the same bus is the SPD (Serial Presens Detect
- * EEPROM of the SDRAM
- * The Atmel EEPROM uses 16Bit addressing.
- ***************************************************************/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
-
-#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
- /* 64 byte page write mode using*/
- /* last 6 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/***************************************************************
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- ***************************************************************/
-#define SPD_EEPROM_ADDRESS 0x50
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/**************************************************************
- * Environment definitions
- **************************************************************/
-
-/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
-
-#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
-#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
-
-#define CONFIG_IPADDR 10.0.0.100
-#define CONFIG_SERVERIP 10.0.0.1
-#define CONFIG_PREBOOT
-/***************************************************************
- * defines if an overwrite_console function exists
- *************************************************************/
-/***************************************************************
- * defines if the overwrite_console should be stored in the
- * environment
- **************************************************************/
-
-/**************************************************************
- * loads config
- *************************************************************/
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MISC_INIT_R
-/***********************************************************
- * Miscellaneous configurable options
- **********************************************************/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
- /* resource configuration */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_UPDATE_FLASH_SIZE
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-/*
- * Init Memory Controller:
- */
-#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
-#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF4000000
-#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in On Chip SRAM)
- */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/***********************************************************************
- * External peripheral base address
- ***********************************************************************/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
-
-/***********************************************************************
- * Last Stage Init
- ***********************************************************************/
-#define CONFIG_LAST_STAGE_INIT
-/************************************************************
- * Ethernet Stuff
- ***********************************************************/
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-/************************************************************
- * RTC
- ***********************************************************/
-#define CONFIG_RTC_MC146818
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/************************************************************
- * IDE/ATA stuff
- ************************************************************/
-#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET /* reset for ide supported... */
-#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
-#define CONFIG_SUPPORT_VFAT
-
-/************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI /* enable ATAPI Support */
-
-/************************************************************
- * SCSI support (experimental) only SYM53C8xx supported
- ************************************************************/
-#define CONFIG_SCSI_SYM53C8XX
-#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
-#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
-#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
-
-/************************************************************
- * Disk-On-Chip configuration
- ************************************************************/
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
-/************************************************************
- * DISK Partition support
- ************************************************************/
-
-/************************************************************
- * Video support
- ************************************************************/
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_USB_UHCI
-
-/* Enable needed helper functions */
-
-/************************************************************
- * Debug support
- ************************************************************/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/************************************************************
- * support BZIP2 compression
- ************************************************************/
-#define CONFIG_BZIP2 1
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_PLU405 1 /* ...on a PLU405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
-
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SUPPORT_VFAT
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*
- * NAND-FLASH stuff
- */
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US 25
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_QUIET 1
-
-/*
- * PCI stuff
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */
-
-/*
- * IDE/ATA stuff
- */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-/* max. 1 drives per IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
-
-/*
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */
-#define CONFIG_ENV_SIZE 0x700
-
-/*
- * I2C EEPROM (24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */
-#define CONFIG_SYS_EEPROM_WREN 1
-
-/* 24WC16 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */
- /* 16 byte page write mode using */
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CAN0_BA 0xF0000000 /* CAN0 Base Address */
-#define CAN1_BA 0xF0000100 /* CAN1 Base Address */
-#define DUART0_BA 0xF0000400 /* DUART Base Address */
-#define DUART1_BA 0xF0000408 /* DUART Base Address */
-#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
-#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-/* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-/* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-/* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB1CR 0xF4018000
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0
-/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
-/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0
-/* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000
-
-/*
- * FPGA stuff
- */
-#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
-
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_CTRL 0x000
-
-/* FPGA Control Reg */
-#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
-#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x00000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0x77FE0014
-
-#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
-#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in MHz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 1
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-#endif
-
-/*
- * PCI OHCI controller
- */
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_PCI_OHCI 1
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
-
-/*
- * UBI
- */
-#define CONFIG_RBTREE
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
-
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-#define CONFIG_PRAM 0
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-#define CONFIG_SYS_BASE_BAUD 691200
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-
-/*
- * PCI stuff
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-/*
- * PCI identification
- */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
-#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
-#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
-#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
-#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
-
-#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
-
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
-#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xfe000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-
-/*
- * Environment in EEPROM setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0x100
-#define CONFIG_ENV_SIZE 0x700
-
-/*
- * I2C EEPROM (24W16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_SYS_EEPROM_WREN 1
-
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
-#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
-
-/*
- * RTC
- */
-#define CONFIG_RTC_RX8025
-
-/*
- * External Bus Controller (EBC) Setup
- * (max. 55MHZ EBC clock)
- */
-/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB0AP 0x03017200
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
-
-/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_CPLD_BASE 0xef000000
-#define CONFIG_SYS_EBC_PB1AP 0x00800000
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-/* inside SDRAM */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
-/* End of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
-} \
-}
-
-#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
-#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
-#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
-#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
-#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
-#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
-#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
-#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
-#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
-#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#undef CONFIG_SYS_FCPU333MHZ
-#define CONFIG_SYS_FCPU266MHZ
-#undef CONFIG_SYS_FCPU133MHZ
-
-#if defined(CONFIG_SYS_FCPU333MHZ)
-/*
- * CPU: 333MHz
- * PLB/SDRAM/MAL: 111MHz
- * OPB: 55MHz
- * EBC: 55MHz
- * PCI: 55MHz (111MHz on M66EN=1)
- */
-#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-#endif
-
-#if defined(CONFIG_SYS_FCPU266MHZ)
-/*
- * CPU: 266MHz
- * PLB/SDRAM/MAL: 133MHz
- * OPB: 66MHz
- * EBC: 44MHz
- * PCI: 44MHz (66MHz on M66EN=1)
- */
-#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#endif
-
-#if defined(CONFIG_SYS_FCPU133MHZ)
-/*
- * CPU: 133MHz
- * PLB/SDRAM/MAL: 133MHz
- * OPB: 66MHz
- * EBC: 44MHz
- * PCI: 44MHz (66MHz on M66EN=1)
- */
-#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- * Based on the sequoia configuration file.
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * PMC440.h - configuration for esd PMC440 boards
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_440 1 /* ... PPC440 family */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF90000
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 33333400
-
-#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
-#define CONFIG_4xx_DCACHE /* enable dcache */
-#endif
-
-#define CONFIG_MISC_INIT_F 1
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
-
-#define CONFIG_PRAM 0 /* use pram variable to overwrite */
-
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
-#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-#define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */
-
-#define CONFIG_SYS_USB2D0_BASE 0xe0000100
-#define CONFIG_SYS_USB_DEVICE 0xe0000000
-#define CONFIG_SYS_USB_HOST 0xe0000400
-#define CONFIG_SYS_FPGA_BASE0 0xef000000 /* 32 bit */
-#define CONFIG_SYS_FPGA_BASE1 0xef100000 /* 16 bit */
-#define CONFIG_SYS_RESET_BASE 0xef200000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
-
-/*-----------------------------------------------------------------------
- * RTC
- *----------------------------------------------------------------------*/
-#define CONFIG_RTC_RX8025
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_I2C_ENV_EEPROM_BUS 0
-#define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
-#endif
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
- /* 440EPx errata CHIP 11 */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_PPC4XX_CH1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
-
-#define CONFIG_SYS_EEPROM_WREN 1
-#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
-
-#define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \
- "\\\"painit\\\" to preboot command"
-
-#undef CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#define CONFIG_HOSTNAME pmc440
-#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0"
-#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_SYS_BOOTFILE \
- CONFIG_SYS_ROOTPATH \
- "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \
- "netdev=eth0\0" \
- "ethrotate=no\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
- "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
- "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
- "nand_boot_fdt=run nandargs addip addtty addmisc;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${fdt_addr_r} ${fdt_file};" \
- "run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "kernel_addr=ffc00000\0" \
- "kernel_addr_r=200000\0" \
- "fpga_addr=fff00000\0" \
- "fdt_addr=fff80000\0" \
- "fdt_addr_r=800000\0" \
- "fpga=fpga loadb 0 ${fpga_addr}\0" \
- "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
- "update=protect off fff90000 ffffffff;era fff90000 ffffffff;" \
- "cp.b 200000 fff90000 70000\0" \
- ""
-
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
-
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 1
-#define CONFIG_RESET_PHY_R 1
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-/* Partitions */
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_FPU | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_SPR)
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
-
-#define CONFIG_PCI_BOOTDELAY 0
-
-/* PCI identification */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
-#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
-/* for weak __pci_target_init() */
-#define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
-#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
-#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- *----------------------------------------------------------------------*/
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN2
-#define CONFIG_FPGA_SPARTAN3
-
-#define CONFIG_FPGA_COUNT 2
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-
-/*
- * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
- */
-#define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x03017200
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 2 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x018003c0
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-
-/* Memory Bank 1 (RESET) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
-
-/* Memory Bank 4 (FPGA / 32Bit) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
-#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */
-
-/* Memory Bank 5 (FPGA / 16Bit) initialization */
-#define CONFIG_SYS_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
-#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * NAND FLASH
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_VOM405 1 /* ...on a VOM405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-/*
- * Command line configuration.
- */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-#undef CONFIG_PRAM /* no "protected RAM" */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-
-#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CONFIG_SYS_RAMBOOT 1
-#else
-# undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/*
- * FPGA stuff
- */
-#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
-/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
-/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
-/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * acadia.h - configuration for AMCC Acadia (405EZ)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_ACADIA 1 /* Board is Acadia */
-#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME acadia
-#include "amcc-common.h"
-
-/* Detect Acadia PLL input clock automatically via CPLD bit */
-#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
- 66666666 : 33333000)
-
-#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
-
-#define CONFIG_NO_SERIAL_EEPROM
-/*#undef CONFIG_NO_SERIAL_EEPROM*/
-
-#ifdef CONFIG_NO_SERIAL_EEPROM
-/*----------------------------------------------------------------------------
- * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
- * assuming a 66MHz input clock to the 405EZ.
- *---------------------------------------------------------------------------*/
-/* #define PLLMR0_100_100_12 */
-#define PLLMR0_200_133_66
-/* #define PLLMR0_266_160_80 */
-/* #define PLLMR0_333_166_83 */
-#endif
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xfe000000
-#define CONFIG_SYS_CPLD_BASE 0x80000000
-#define CONFIG_SYS_NAND_ADDR 0xd0000000
-#define CONFIG_SYS_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM 1 /* OCM as init ram */
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xf8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*-----------------------------------------------------------------------
- * RAM (CRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_RAM 64 /* 64MB */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_HAS_ETH0 1
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_PPC_OLD \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fff10000\0" \
- "ramdisk_addr=fff20000\0" \
- "kozio=bootm ffc60000\0" \
- ""
-
-#define CONFIG_USB_OHCI
-
-/* Partitions */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_NAND
-
-/*-----------------------------------------------------------------------
- * NAND FLASH
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NAND_CS 3
-/* Memory Bank 0 (Flash) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x03337200
-#define CONFIG_SYS_EBC_PB0CR 0xfe0bc000
-
-/* Memory Bank 3 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x018003c0
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-
-/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
-/* Memory Bank 1 (CRAM) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x030400c0
-#define CONFIG_SYS_EBC_PB1CR 0x000bc000
-
-/* Memory Bank 2 (CRAM) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x030400c0
-#define CONFIG_SYS_EBC_PB2CR 0x020bc000
-
-/* Memory Bank 4 (CPLD) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x04006000
-#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CPLD_BASE | 0x18000)
-
-#define CONFIG_SYS_EBC_CFG 0xf8400000
-
-/*-----------------------------------------------------------------------
- * GPIO Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_GPIO_CRAM_CLK 8
-#define CONFIG_SYS_GPIO_CRAM_WAIT 9 /* GPIO-In */
-#define CONFIG_SYS_GPIO_CRAM_ADV 10
-#define CONFIG_SYS_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO_0 setup (PPC405EZ specific)
- *
- * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
- * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
- * GPIO0[4] - External Bus Controller Hold Input
- * GPIO0[5] - External Bus Controller Priority Input
- * GPIO0[6] - External Bus Controller HLDA Output
- * GPIO0[7] - External Bus Controller Bus Request Output
- * GPIO0[8] - CRAM Clk Output
- * GPIO0[9] - External Bus Controller Ready Input
- * GPIO0[10] - CRAM Adv Output
- * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
- * GPIO0[25] - External DMA Request Input
- * GPIO0[26] - External DMA EOT I/O
- * GPIO0[25] - External DMA Ack_n Output
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[28-30] - Trace Outputs / PWM Inputs
- * GPIO0[31] - PWM_8 I/O
- */
-#define CONFIG_SYS_GPIO0_TCR 0xC0A00000
-#define CONFIG_SYS_GPIO0_OSRL 0x50004400
-#define CONFIG_SYS_GPIO0_OSRH 0x02000055
-#define CONFIG_SYS_GPIO0_ISR1L 0x00001000
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000055
-#define CONFIG_SYS_GPIO0_TSRL 0x02000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000055
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO_1 setup (PPC405EZ specific)
- *
- * GPIO1[0-6] - PWM_9 to PWM_15 I/O
- * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
- * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
- * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
- * GPIO1[10-12] - UART0 Control Inputs
- * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
- * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
- * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
- * GPIO1[16] - SPI_SS_1_N Output
- * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
- */
-#define CONFIG_SYS_GPIO1_TCR 0xFFFF8414
-#define CONFIG_SYS_GPIO1_OSRL 0x40000110
-#define CONFIG_SYS_GPIO1_OSRH 0x55455555
-#define CONFIG_SYS_GPIO1_ISR1L 0x15555445
-#define CONFIG_SYS_GPIO1_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO1_TSRL 0x00000000
-#define CONFIG_SYS_GPIO1_TSRH 0x00000000
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2008, 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Common configuration options for all AMCC boards
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __AMCC_COMMON_H
-#define __AMCC_COMMON_H
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
-#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
-
-/*
- * UART
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#endif
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-/*
- * Ethernet/EMAC/PHY
- */
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#if defined(CONFIG_440)
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* number of eth rx buffers */
-#else
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* number of eth rx buffers */
-#endif
-
-/*
- * Commands
- */
-#if defined(CONFIG_440)
-#endif
-#define CONFIG_CMD_REGINFO
-
-/*
- * Miscellaneous configurable options
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the 40x Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-
-/*
- * Internal Definitions
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
-#endif
-
-/* Update size in "reg" property of NOR FLASH device tree nodes */
-#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-
-/*
- * Booting and default environment
- */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * Only very few boards have default console not on ttyS0 (like Taishan)
- */
-#if !defined(CONFIG_USE_TTY)
-#define CONFIG_USE_TTY ttyS0
-#endif
-
-/*
- * Only very few boards have default netdev not set to eth0 (like Arches)
- */
-#if !defined(CONFIG_USE_NETDEV)
-#define CONFIG_USE_NETDEV eth0
-#endif
-
-/*
- * Only some 4xx PPC's are equipped with an FPU
- */
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define CONFIG_AMCC_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_AMCC_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
-#endif
-
-/*
- * Only some boards need to extend the bootargs by some additional
- * parameters (like Makalu)
- */
-#if !defined(CONFIG_ADDMISC)
-#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0"
-#endif
-
-/*
- * General common environment variables shared on all AMCC eval boards
- */
-#define CONFIG_AMCC_DEF_ENV \
- "netdev=" __stringify(CONFIG_USE_NETDEV) "\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=" __stringify(CONFIG_USE_TTY) ",${baudrate}\0" \
- CONFIG_ADDMISC \
- "initrd_high=30000000\0" \
- "kernel_addr_r=1000000\0" \
- "fdt_addr_r=1800000\0" \
- "ramdisk_addr_r=1900000\0" \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
- "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
- CONFIG_AMCC_DEF_ENV_ROOTPATH
-
-/*
- * Default environment for arch/powerpc booting
- * for boards that are ported to arch/powerpc
- */
-#define CONFIG_AMCC_DEF_ENV_POWERPC \
- "flash_self=run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; " \
- "run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${fdt_addr_r} ${fdt_file};" \
- "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "net_self=run net_self_load;" \
- "run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
- "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" __stringify(CONFIG_HOSTNAME) ".dtb\0"
-
-/*
- * Default environment for arch/ppc booting,
- * for boards that are not ported to arch/powerpc yet
- */
-#define CONFIG_AMCC_DEF_ENV_PPC \
- "flash_self=run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
- "run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr_r}\0"
-
-/*
- * Default environment for arch/ppc booting (old version),
- * for boards that are ported to arch/ppc and arch/powerpc
- */
-#define CONFIG_AMCC_DEF_ENV_PPC_OLD \
- "flash_self_old=run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs_old=run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
- "run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr_r}\0"
-
-#define CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
- "era " __stringify(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
- "cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
- "upd=run load update\0" \
-
-#endif /* __AMCC_COMMON_H */
+++ /dev/null
-/*
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * bamboo.h - configuration for BAMBOO board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
-#define CONFIG_440EP 1 /* Specific PPC440EP support */
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME bamboo
-#include "amcc-common.h"
-
-/* Reclaim some space. */
-#undef CONFIG_SYS_LONGHELP
-
-/*
- * Please note that, if NAND support is enabled, the 2nd ethernet port
- * can't be used because of pin multiplexing. So, if you want to use the
- * 2nd ethernet port you have to "undef" the following define.
- */
-#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
-#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-/*Don't change either of these*/
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
-/*Don't change either of these*/
-
-#define CONFIG_SYS_USB_DEVICE 0x50000000
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
-#define CONFIG_SYS_NAND_ADDR 0x90000000
-#define CONFIG_SYS_NAND2_ADDR 0x94000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
- * The DS1558 code assumes this condition
- *
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_ADDR0 0x555
-#define CONFIG_SYS_FLASH_ADDR1 0x2aa
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
-
-#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
-#define CONFIG_SYS_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NAND FLASH
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
-#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-#define CONFIG_SYS_NAND_CS 1
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------------- */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#undef CONFIG_DDR_ECC /* don't use ECC */
-#define CONFIG_SYS_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
-#define SPD_EEPROM_ADDRESS {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
-#define CONFIG_SYS_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
-#define CONFIG_PROG_SDRAM_TLB
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
-#define CONFIG_ENV_OFFSET 0x0
-#endif /* CONFIG_ENV_IS_IN_EEPROM */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_PPC_OLD \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fff00000\0" \
- "ramdisk_addr=fff10000\0" \
- ""
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
-#define CONFIG_PHY1_ADDR 1
-
-#ifndef CONFIG_BAMBOO_NAND
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#endif /* CONFIG_BAMBOO_NAND */
-
-#ifdef CONFIG_440EP
-/* USB */
-#define CONFIG_USB_OHCI
-
-/*Comment this out to enable USB 1.1 device*/
-#define USB_2_0_DEVICE
-#endif /*CONFIG_440EP*/
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#ifdef CONFIG_BAMBOO_NAND
-#define CONFIG_CMD_NAND
-#endif
-
-#define CONFIG_SUPPORT_VFAT
-
-/* Partitions */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME bubinga
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_NO_SERIAL_EEPROM
-/*#undef CONFIG_NO_SERIAL_EEPROM*/
-/*----------------------------------------------------------------------------*/
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-------------------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-! are plugged in the board will be utilized as non-ECC DIMMs.
-!-------------------------------------------------------------------------------
-*/
-#define AUTO_MEMORY_CONFIG
-#define DIMM_READ_ADDR 0xAB
-#define DIMM_WRITE_ADDR 0xAA
-
-/*
-!-------------------------------------------------------------------------------
-! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
-! assuming a 33MHz input clock to the 405EP from the C9531.
-!-------------------------------------------------------------------------------
-*/
-#define PLLMR0_DEFAULT PLLMR0_266_133_66
-#define PLLMR1_DEFAULT PLLMR1_266_133_66
-
-#endif
-/*----------------------------------------------------------------------------*/
-
-/*
- * Define here the location of the environment variables (FLASH or NVRAM).
- * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
- * supported for backward compatibility.
- */
-#if 1
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#endif
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_PPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fff80000\0" \
- "ramdisk_addr=fff90000\0" \
- ""
-
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
-
-#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/*-----------------------------------------------------------------------
- * I2C stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
-
-#if defined(CONFIG_CMD_EEPROM)
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
- /* resource configuration */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
-#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- */
-#define CONFIG_SYS_SRAM_BASE 0xFFF00000
-#define CONFIG_SYS_SRAM_SIZE (256 << 10)
-#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_ADDR0 0x5555
-#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash/SRAM) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x04006000
-#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 1 (NVRAM/RTC) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x04041000
-#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (not used) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x00000000
-#define CONFIG_SYS_EBC_PB2CR 0x00000000
-
-/* Memory Bank 2 (not used) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x00000000
-#define CONFIG_SYS_EBC_PB3CR 0x00000000
-
-/* Memory Bank 4 (FPGA regs) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x01815000
-#define CONFIG_SYS_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x55
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x55555555
-#define CONFIG_SYS_GPIO0_OSRH 0x40000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xFFFF8014
-
-/*-----------------------------------------------------------------------
- * Some BUBINGA stuff...
- */
-#define NVRAM_BASE 0xF0000000
-#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
-#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
-#define NVRVFY1 0x4f532d4f /* used to determine if state data in */
-#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
-
-#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
-#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
-#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
-#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
-#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
-#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
-
-#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
-#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
-#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
-#define FPGA_REG1_CLOCK_BIT_SHIFT 4
-#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
-#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
-#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
-#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * canyonlands.h - configuration for Canyonlands (460EX)
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/kconfig.h>
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-/*
- * This config file is used for Canyonlands (460EX) Glacier (460GT)
- * and Arches dual (460GT)
- */
-#ifdef CONFIG_CANYONLANDS
-#define CONFIG_460EX /* Specific PPC460EX */
-#define CONFIG_HOSTNAME canyonlands
-#else
-#define CONFIG_460GT /* Specific PPC460GT */
-#ifdef CONFIG_GLACIER
-#define CONFIG_HOSTNAME glacier
-#else
-#define CONFIG_HOSTNAME arches
-#define CONFIG_USE_NETDEV eth1
-#define CONFIG_BD_NUM_CPUS 2
-#endif
-#endif
-
-#define CONFIG_440
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
-#define CONFIG_MISC_INIT_R /* Call misc_init_r */
-#define CONFIG_BOARD_TYPES /* support board types */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
-
-#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
-#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
-#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
-
-#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
-#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
-#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
-#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
-
-/*
- * BCSR bits as defined in the Canyonlands board user manual.
- */
-#define BCSR_USBCTRL_OTG_RST 0x32
-#define BCSR_USBCTRL_HOST_RST 0x01
-#define BCSR_SELECT_PCIE 0x10
-
-#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
-
-/* EBC stuff */
-#if !defined(CONFIG_ARCHES)
-#define CONFIG_SYS_BCSR_BASE 0xE1000000
-#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped to this addr */
-#define CONFIG_SYS_FLASH_SIZE (64 << 20)
-#else
-#define CONFIG_SYS_FPGA_BASE 0xE1000000
-#define CONFIG_SYS_CPLD_ADDR (CONFIG_SYS_FPGA_BASE + 0x00080000)
-#define CONFIG_SYS_CPLD_DATA (CONFIG_SYS_FPGA_BASE + 0x00080002)
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* later mapped to this addr */
-#define CONFIG_SYS_FLASH_SIZE (32 << 20)
-#endif
-
-#define CONFIG_SYS_NAND_ADDR 0xE0000000
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
-#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
-#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
- (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-
-#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
-#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
-#define CONFIG_SYS_SRAM_SIZE (256 << 10)
-#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
-
-#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals */
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in OCM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH).
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
-#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-
-/*------------------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------------*/
-#if !defined(CONFIG_ARCHES)
-/*
- * NAND booting U-Boot version uses a fixed initialization, since the whole
- * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
- * code.
- */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
-#define CONFIG_DDR_ECC /* with ECC support */
-#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
-
-#else /* defined(CONFIG_ARCHES) */
-
-#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
-
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
-#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
-#undef CONFIG_PPC4xx_DDR_METHOD_A
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-/* Memory Queue */
-#define CONFIG_SYS_SDRAM_R0BAS 0x0000f000
-#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
-#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
-#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
-#define CONFIG_SYS_SDRAM_CONF1LL 0x00001080
-#define CONFIG_SYS_SDRAM_CONF1HB 0x00001080
-#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
-
-/* SDRAM Controller */
-#define CONFIG_SYS_SDRAM0_MB0CF 0x00000701
-#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
-#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
-#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
-#define CONFIG_SYS_SDRAM0_MCOPT1 0x05322000
-#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0 0x01000000
-#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
-#define CONFIG_SYS_SDRAM0_CODT 0x00800021
-#define CONFIG_SYS_SDRAM0_RTR 0x06180000
-#define CONFIG_SYS_SDRAM0_INITPLR0 0xb5380000
-#define CONFIG_SYS_SDRAM0_INITPLR1 0x82100400
-#define CONFIG_SYS_SDRAM0_INITPLR2 0x80820000
-#define CONFIG_SYS_SDRAM0_INITPLR3 0x80830000
-#define CONFIG_SYS_SDRAM0_INITPLR4 0x80810040
-#define CONFIG_SYS_SDRAM0_INITPLR5 0x80800532
-#define CONFIG_SYS_SDRAM0_INITPLR6 0x82100400
-#define CONFIG_SYS_SDRAM0_INITPLR7 0x8a080000
-#define CONFIG_SYS_SDRAM0_INITPLR8 0x8a080000
-#define CONFIG_SYS_SDRAM0_INITPLR9 0x8a080000
-#define CONFIG_SYS_SDRAM0_INITPLR10 0x8a080000
-#define CONFIG_SYS_SDRAM0_INITPLR11 0x80000432
-#define CONFIG_SYS_SDRAM0_INITPLR12 0x808103c0
-#define CONFIG_SYS_SDRAM0_INITPLR13 0x80810040
-#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
-#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
-#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
-#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
-#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
-#define CONFIG_SYS_SDRAM0_DLCR 0x03000091
-#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
-#define CONFIG_SYS_SDRAM0_WRDTR 0x82000823
-#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
-#define CONFIG_SYS_SDRAM0_SDTR2 0x42204243
-#define CONFIG_SYS_SDRAM0_SDTR3 0x090c0d1a
-#define CONFIG_SYS_SDRAM0_MMODE 0x00000432
-#define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
-#endif /* !defined(CONFIG_ARCHES) */
-
-#define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#if defined(CONFIG_ARCHES)
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
-#else
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
-#endif
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-
-#if !defined(CONFIG_ARCHES)
-/* RTC configuration */
-#define CONFIG_RTC_M41T62
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#endif
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#define CONFIG_IBM_EMAC4_V4
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-
-#if !defined(CONFIG_ARCHES)
-#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
-#define CONFIG_PHY1_ADDR 1
-/* Only Glacier (460GT) has 4 EMAC interfaces */
-#ifdef CONFIG_460GT
-#define CONFIG_PHY2_ADDR 2
-#define CONFIG_PHY3_ADDR 3
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#else /* defined(CONFIG_ARCHES) */
-
-#define CONFIG_FIXED_PHY 0xFFFFFFFF
-#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
-#define CONFIG_PHY1_ADDR 0
-#define CONFIG_PHY2_ADDR 1
-#define CONFIG_HAS_ETH2
-
-#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
- {devnum, speed, duplex}
-#define CONFIG_SYS_FIXED_PHY_PORTS \
- CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
-
-#define CONFIG_M88E1112_PHY
-
-/*
- * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
- * used by CONFIG_PHYx_ADDR
- */
-#define CONFIG_GPCS_PHY_ADDR 0xA
-#define CONFIG_GPCS_PHY1_ADDR 0xB
-#define CONFIG_GPCS_PHY2_ADDR 0xC
-#endif /* !defined(CONFIG_ARCHES) */
-
-#define CONFIG_PHY_RESET /* reset phy upon startup */
-#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
-#define CONFIG_PHY_DYNAMIC_ANEG
-
-/*-----------------------------------------------------------------------
- * USB-OHCI
- *----------------------------------------------------------------------*/
-/* Only Canyonlands (460EX) has USB */
-#ifdef CONFIG_460EX
-#define CONFIG_USB_OHCI_NEW
-#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
-#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT
-#endif
-
-/*
- * Default environment variables
- */
-#if !defined(CONFIG_ARCHES)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:RP\0" \
- ""
-#else /* defined(CONFIG_ARCHES) */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fe000000\0" \
- "fdt_addr=fe1e0000\0" \
- "ramdisk_addr=fe200000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:RP\0" \
- "ethprime=ppc_4xx_eth1\0" \
- ""
-#endif /* !defined(CONFIG_ARCHES) */
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#if defined(CONFIG_ARCHES)
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-#elif defined(CONFIG_CANYONLANDS)
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SATA
-#define CONFIG_CMD_SDRAM
-#elif defined(CONFIG_GLACIER)
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-#else
-#error "board type not defined"
-#endif
-
-/* Partitions */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-#undef CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
-#ifdef CONFIG_460GT
-#if defined(CONFIG_ARCHES)
-/*-----------------------------------------------------------------------
- * RapidIO I/O and Registers
- *----------------------------------------------------------------------*/
-#define CONFIG_RAPIDIO
-#define CONFIG_SYS_460GT_SRIO_ERRATA_1
-
-#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */
-#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */
-#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */
-#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */
-#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
-
-#define CONFIG_SYS_SRGPL0_REG_BAR 0xAA000000 /* 16MB */
-#define CONFIG_SYS_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */
-#define CONFIG_SYS_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */
-#define CONFIG_SYS_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
-
-#define CONFIG_SYS_I2ODMA_BASE 0xCF000000
-#define CONFIG_SYS_I2ODMA_PHYS_ADDR 0x0000000400100000ull
-
-#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
-#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
-#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
-#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
-#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
-#endif /* CONFIG_ARCHES */
-#endif /* CONFIG_460GT */
-
-/*
- * SATA driver setup
- */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SATA_DWC
-#define CONFIG_LIBATA
-#define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */
-#define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */
-#define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */
-/* Convert sectorsize to wordsize */
-#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-
-/*
- * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
- * boot EBC mapping only supports a maximum of 16MBytes
- * (4.ff00.0000 - 4.ffff.ffff).
- * To solve this problem, the FLASH has to get remapped to another
- * EBC address which accepts bigger regions:
- *
- * 0xfc00.0000 -> 4.cc00.0000
- *
- * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
- * remapped to:
- *
- * 0xfe00.0000 -> 4.ce00.0000
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x10055e00
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
-
-#if !defined(CONFIG_ARCHES)
-/* Memory Bank 3 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x018003c0
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
-#endif
-
-#if !defined(CONFIG_ARCHES)
-/* Memory Bank 2 (CPLD) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x00804240
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
-
-#else /* defined(CONFIG_ARCHES) */
-
-/* Memory Bank 1 (FPGA) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x7f8ffe80
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
-#endif /* !defined(CONFIG_ARCHES) */
-
-#define CONFIG_SYS_EBC_CFG 0xbfc00000
-
-/*
- * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
- * pin multiplexing correctly
- */
-#if defined(CONFIG_ARCHES)
-#define GPIO43_USE GPIO_SEL /* On Arches this pin is used as GPIO */
-#else
-#define GPIO43_USE GPIO_ALT1 /* On Glacier this pin is used as ALT1 -> PerCS3 */
-#endif
-
-/*
- * PPC4xx GPIO Configuration
- */
-#ifdef CONFIG_460EX
-/* 460EX: Use USB configuration */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
-{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
-} \
-}
-#else
-/* 460GT: Use EMAC2+3 configuration */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
-{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
-} \
-}
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME dlvsion-10g
-#include "amcc-common.h"
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-/*
- * Configure PLL
- */
-#define PLLMR0_DEFAULT PLLMR0_266_133_66
-#define PLLMR1_DEFAULT PLLMR1_266_133_66
-
-#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- ""
-
-#define CONFIG_PHY_ADDR 4 /* PHY address */
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
-#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/*
- * I2C stuff
- */
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_IHS
-#define CONFIG_SYS_I2C_IHS_DUAL
-#define CONFIG_SYS_I2C_IHS_CH0
-#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
-#define CONFIG_SYS_I2C_IHS_CH1
-#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
-#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
-
-#define CONFIG_SYS_SPD_BUS_NUM 4
-
-/* Temp sensor/hwmon/dtt */
-
-#define CONFIG_SYS_ICS8N3QV01_I2C {1, 3}
-#define CONFIG_SYS_SIL1178_I2C {0, 2}
-#define CONFIG_SYS_DP501_I2C {0, 2}
-
-/* EBC peripherals */
-
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_FPGA0_BASE 0x7f100000
-#define CONFIG_SYS_FPGA1_BASE 0x7f200000
-#define CONFIG_SYS_LATCH_BASE 0x7f300000
-
-#define CONFIG_SYS_FPGA_BASE(k) \
- (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
-
-#define CONFIG_SYS_FPGA_DONE(k) \
- (k ? 0x2000 : 0x1000)
-
-#define CONFIG_SYS_FPGA_COUNT 2
-
-#define CONFIG_SYS_FPGA_PTR { \
- (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
- (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
-
-#define CONFIG_SYS_FPGA_COMMON
-
-#define CONFIG_SYS_LATCH0_RESET 0xffff
-#define CONFIG_SYS_LATCH0_BOOT 0xffff
-#define CONFIG_SYS_LATCH1_RESET 0xffbf
-#define CONFIG_SYS_LATCH1_BOOT 0xffff
-
-#define CONFIG_SYS_FPGA_NO_RFL_HI
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*
- * PPC405 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
-} \
-}
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-flash) */
-#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
- EBC_BXAP_FWT_ENCODE(8) | \
- EBC_BXAP_BWT_ENCODE(7) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(2) | \
- EBC_BXAP_WBN_ENCODE(2) | \
- EBC_BXAP_WBF_ENCODE(2) | \
- EBC_BXAP_TH_ENCODE(4) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
- EBC_BXCR_BS_64MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 1 (FPGA0) */
-#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(5) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(2) | \
- EBC_BXAP_WBN_ENCODE(1) | \
- EBC_BXAP_WBF_ENCODE(1) | \
- EBC_BXAP_TH_ENCODE(0) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
- EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 2 (FPGA1) */
-#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(6) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(2) | \
- EBC_BXAP_WBN_ENCODE(1) | \
- EBC_BXAP_WBF_ENCODE(1) | \
- EBC_BXAP_TH_ENCODE(0) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
- EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 3 (Latches) */
-#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
- EBC_BXAP_FWT_ENCODE(8) | \
- EBC_BXAP_BWT_ENCODE(4) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(1) | \
- EBC_BXAP_WBN_ENCODE(1) | \
- EBC_BXAP_WBF_ENCODE(1) | \
- EBC_BXAP_TH_ENCODE(2) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
- EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/*
- * OSD Setup
- */
-#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
-#define CONFIG_SYS_DP501_DIFFERENTIAL
-#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_DLVISION 1 /* on a Neo board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME dlvision
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R /* call misc_init_r */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-/*
- * Configure PLL
- */
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-
-#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- ""
-
-#define CONFIG_PHY_ADDR 4 /* PHY address */
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
-#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/*
- * I2C stuff
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*
- * PPC405 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
-} \
-}
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
-
-/* Memory Bank 1 (NVRAM) initializatio */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB1CR 0xFB858000
-
-/* Memory Bank 2 (UART) initialization */
-#define CONFIG_UART_BASE 0x7f100000
-#define CONFIG_SYS_EBC_PB2AP 0x92015480
-/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB2CR 0x7f118000
-
-/* Memory Bank 3 (Latches) initialization */
-#define CONFIG_SYS_LATCH_BASE 0x7f200000
-#define CONFIG_SYS_EBC_PB3AP 0x92015480
-/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on include/configs/yosemite.h
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_440GR 1 /* Specific PPC440GR support */
-#define CONFIG_HOSTNAME gdppc440etx
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-/*Don't change either of these*/
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */
-/*Don't change either of these*/
-
-#define CONFIG_SYS_USB_DEVICE 0x50000000
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
-
-/*
- * Initial RAM & stack pointer (placed in SDRAM)
- */
-#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
-
-/*
- * Environment
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*
- * DDR SDRAM
- */
-#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/
-#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */
-#define CONFIG_SYS_SDRAM_BANKS (2)
-
-#define CONFIG_SDRAM_BANK0
-#define CONFIG_SDRAM_BANK1
-
-#define CONFIG_SYS_SDRAM0_TR0 0x410a4012
-#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000
-#define CONFIG_SYS_SDRAM0_RTR 0x04080000
-#define CONFIG_SYS_SDRAM0_CFG0 0x80000000
-
-#undef CONFIG_SDRAM_ECC
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "ramdisk_addr=fc180000\0" \
- ""
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY_ADDR 1
-#define CONFIG_PHY1_ADDR 3
-
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#endif
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-
-/*
- * PCI stuff
- */
-
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \
- CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x03017200
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * icon.h - configuration for Mosaixtech ICON (440SPe)
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ICON 1 /* Board is icon */
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_440SPE 1 /* Specifc SPe support */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME icon
-#include "amcc-common.h"
-
-#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */
-#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
-
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
-
-#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
-#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */
-#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
-
-#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
-#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
-#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
-#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
-#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
-#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
-
-#define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */
-#define CONFIG_SYS_ACE_BASE_PHYS_H 0x4
-#define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000
-
-#define CONFIG_SYS_FLASH_SIZE (64 << 20)
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
-#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
-#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
- (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-
-/*
- * Initial RAM & stack pointer (placed in internal SRAM)
- */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* size of used area */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-
-/*
- * DDR2 SDRAM
- */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */
-#define CONFIG_DDR_ECC /* with ECC support */
-#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-
-#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11
-#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
-
-/*
- * Video options
- */
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_VIDEO_SM501_PCI
-#define VIDEO_FB_LITTLE_ENDIAN
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CFG_CONSOLE_IS_IN_ENV
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:RP:RP\0" \
- ""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */
-#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_RESET /* reset phy upon startup */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */
-#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */
-
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-#define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-#undef CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
-/*
- * Xilinx System ACE support
- */
-#define CONFIG_SYSTEMACE /* Enable SystemACE support */
-#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
-#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash) initialization */
-#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(7) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(0) | \
- EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(0) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
- EBC_BXCR_BS_64MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 1 (Xilinx System ACE controller) initialization */
-#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(4) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(0) | \
- EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(0) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \
- EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/*
- * Initialize EBC CONFIG -
- * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
- * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
- */
-#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
- EBC_CFG_PTD_ENABLE | \
- EBC_CFG_RTC_16PERCLK | \
- EBC_CFG_ATC_PREVIOUS | \
- EBC_CFG_DTC_PREVIOUS | \
- EBC_CFG_CTC_PREVIOUS | \
- EBC_CFG_OEO_PREVIOUS | \
- EBC_CFG_EMC_DEFAULT | \
- EBC_CFG_PME_DISABLE | \
- EBC_CFG_PR_16)
-
-/*
- * GPIO Setup
- */
-#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
-#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
-#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
-#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
-
-#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
- GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
- GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
- GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
-#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
-#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
-#define CONFIG_SYS_GPIO_ODR 0
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on include/configs/canyonlands.h
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-/*
- * This config file is used for CompactCenter(codename intip) and DevCon-Center
- */
-#define CONFIG_460EX 1 /* Specific PPC460EX */
-#ifdef CONFIG_DEVCONCENTER
-#define CONFIG_HOSTNAME devconcenter
-#else
-#define CONFIG_HOSTNAME intip
-#endif
-#define CONFIG_440 1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CFG_ALT_MEMTEST
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
-
-/* EBC stuff */
-#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */
-#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* later mapped here */
-#define CONFIG_SYS_FLASH_SIZE (128 << 20)
-#else
-#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */
-#define CONFIG_SYS_FLASH_SIZE (64 << 20)
-#endif
-
-#define CONFIG_SYS_NVRAM_BASE 0xE0000000
-#define CONFIG_SYS_UART_BASE 0xE0100000
-#define CONFIG_SYS_IO_BASE 0xE0200000
-
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
-#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
-#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */
-#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
-#endif
-#define CONFIG_SYS_FLASH_BASE_PHYS \
- (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
- | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-
-#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
-#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
-#define CONFIG_SYS_SRAM_SIZE (256 << 10)
-#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
-
-#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */
-
-/*
- * Initial RAM & stack pointer (placed in OCM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-
-/*
- * Environment
- */
-/*
- * Define here the location of the environment variables (FLASH).
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#ifdef CONFIG_DEVCONCENTER
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max num of sectors per chip*/
-#else
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
-#endif
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buff'd writes (20x faster) */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*
- * DDR SDRAM
- */
-
-#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
-
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
-#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
-#undef CONFIG_PPC4xx_DDR_METHOD_A
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-/* Memory Queue */
-#define CONFIG_SYS_SDRAM_R0BAS 0x0000f800
-#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
-#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
-#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
-#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00
-#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
-#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
-
-/* SDRAM Controller */
-#define CONFIG_SYS_SDRAM0_MB0CF 0x00000201
-#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
-#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
-#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
-#define CONFIG_SYS_SDRAM0_MCOPT1 0x05120000
-#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
-#define CONFIG_SYS_SDRAM0_CODT 0x00000020
-#define CONFIG_SYS_SDRAM0_RTR 0x06180000
-#define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000
-#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
-#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
-#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
-#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002
-#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552
-#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
-#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452
-#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382
-#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002
-#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
-#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
-#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
-#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
-#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
-#define CONFIG_SYS_SDRAM0_DLCR 0x00000000
-#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
-#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823
-#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
-#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
-#define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15
-#define CONFIG_SYS_SDRAM0_MMODE 0x00000452
-#define CONFIG_SYS_SDRAM0_MEMODE 0x00000002
-
-#define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-
-/* RTC configuration */
-#define CONFIG_RTC_DS1337 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Ethernet
- */
-#define CONFIG_IBM_EMAC4_V4 1
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
-#define CONFIG_PHY1_ADDR 3
-
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_PHY_DYNAMIC_ANEG 1
-
-/*
- * USB-OHCI
- */
-#define CONFIG_USB_OHCI_NEW
-#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors*/
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
-#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:RP\0" \
- ""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-/* Partitions */
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-#define CONFIG_PCI_DISABLE_PCIE
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-#undef CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/*
- * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
- * boot EBC mapping only supports a maximum of 16MBytes
- * (4.ff00.0000 - 4.ffff.ffff).
- * To solve this problem, the FLASH has to get remapped to another
- * EBC address which accepts bigger regions:
- *
- * 0xfc00.0000 -> 4.cc00.0000
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x10055e00
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
-
-/* Memory Bank 1 (NVRAM) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x02815480
-/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000)
-
-/* Memory Bank 2 (UART) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x02815480
-/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000)
-
-/* Memory Bank 3 (IO) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x02815480
-/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000)
-
-/*
- * PPC4xx GPIO Configuration
- */
-/* 460EX: Use USB configuration */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
-{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 USB_SERVICE_SUSPEND_N */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51 SPI_CSS_N */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 FPGA_PROGRAM_UC_N */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 FPGA_INIT_UC_N */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54 WD_STROBE */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 LED_2_OUT */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56 LED_1_OUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61 STARTUP_FINISHED_N */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62 STARTUP_FINISHED */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 SERVICE_PORT_ACTIVE */ \
-} \
-}
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_IO 1 /* on a Io board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME io
-#include "amcc-common.h"
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-/*
- * Configure PLL
- */
-#define PLLMR0_DEFAULT PLLMR0_266_133_66
-#define PLLMR1_DEFAULT PLLMR1_266_133_66
-
-#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- ""
-
-#define CONFIG_PHY_ADDR 4 /* PHY address */
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
-#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/*
- * I2C stuff
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-
-/* Temp sensor/hwmon/dtt */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/* Gbit PHYs */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-#define CONFIG_BITBANGMII_MULTI
-
-#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13) /* our MDIO is GPIO0 */
-#define CONFIG_SYS_MDC_PIN (0x80000000 >> 7) /* our MDC is GPIO7 */
-
-#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy"
-
-/*
- * PPC405 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
-} \
-}
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0xa382a880
-/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
-
-/* Memory Bank 1 (NVRAM) initializatio */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB1CR 0x7f318000
-
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA0_BASE 0x7f100000
-#define CONFIG_SYS_EBC_PB2AP 0x02025080
-/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
-
-#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
-#define CONFIG_SYS_FPGA_DONE(k) 0x0010
-
-#define CONFIG_SYS_FPGA_COUNT 1
-
-#define CONFIG_SYS_FPGA_PTR \
- { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
-
-#define CONFIG_SYS_FPGA_COMMON
-
-/* Memory Bank 3 (Latches) initialization */
-#define CONFIG_SYS_LATCH_BASE 0x7f200000
-#define CONFIG_SYS_EBC_PB3AP 0xa2015480
-/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
-
-#define CONFIG_SYS_LATCH0_RESET 0xffff
-#define CONFIG_SYS_LATCH0_BOOT 0xffff
-#define CONFIG_SYS_LATCH1_RESET 0xffbf
-#define CONFIG_SYS_LATCH1_BOOT 0xffff
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * based on kilauea.h
- * by Stefan Roese, DENX Software Engineering, sr@denx.de.
- * and Grant Erickson <gerickson@nuovations.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_IO64 1 /* Board is Io64 */
-#define CONFIG_405EX 1 /* Specifc 405EX support*/
-#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-#endif
-
-/*
- * CHIP_21 errata
- */
-#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME io64
-#include "amcc-common.h"
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_NVRAM_BASE 0xF0000000
-#define CONFIG_SYS_FPGA0_BASE 0xF0100000
-#define CONFIG_SYS_FPGA1_BASE 0xF0108000
-#define CONFIG_SYS_LATCH_BASE 0xF0200000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & Stack Pointer Configuration Options
- *
- * There are traditionally three options for the primordial
- * (i.e. initial) stack usage on the 405-series:
- *
- * 1) On-chip Memory (OCM) (i.e. SRAM)
- * 2) Data cache
- * 3) SDRAM
- *
- * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
- * the latter of which is less than desireable since it requires
- * setting up the SDRAM and ECC in assembly code.
- *
- * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
- * select on the External Bus Controller (EBC) and then select a
- * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
- * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
- * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
- * physical SDRAM to use (3).
- *-----------------------------------------------------------------------*/
-
-#define CONFIG_SYS_INIT_DCACHE_CS 4
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-#define CONFIG_SYS_INIT_RAM_ADDR \
- (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR \
- (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-#define CONFIG_SYS_INIT_RAM_SIZE \
- (4 << 10) /* 4 KiB */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * If the data cache is being used for the primordial stack and global
- * data area, the POST word must be placed somewhere else. The General
- * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
- * its compare and mask register contents across reset, so it is used
- * for the POST word.
- */
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-# define CONFIG_SYS_POST_WORD_ADDR \
- (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
-#else
-# define CONFIG_SYS_INIT_EXTRA_SIZE 16
-# define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
-# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/* Gbit PHYs */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-#define CONFIG_BITBANGMII_MULTI
-
-#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */
-#define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */
-
-#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0"
-
-#define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */
-#define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */
-
-#define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1"
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */
-
-/*
- * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
- *
- * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
- * SDRAM Controller DDR autocalibration values and takes a lot longer
- * to run than Method_B.
- * (See the Method_A and Method_B algorithm discription in the file:
- * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
- * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
- *
- * DDR Autocalibration Method_B is the default.
- */
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
-#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
-#undef CONFIG_PPC4xx_DDR_METHOD_A
-
-#define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE)
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
- SDRAM_RXBAS_SDSZ_128MB | \
- SDRAM_RXBAS_SDAM_MODE2 | \
- SDRAM_RXBAS_SDBE_ENABLE)
-#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
- SDRAM_MCOPT1_4_BANKS | \
- SDRAM_MCOPT1_DDR2_TYPE | \
- SDRAM_MCOPT1_QDEP | \
- SDRAM_MCOPT1_DCOO_DISABLED)
-#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
- SDRAM_MODT_EB0R_ENABLE)
-#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
-#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
- SDRAM_CODT_CKLZ_36OHM | \
- SDRAM_CODT_DQS_1_8_V_DDR2 | \
- SDRAM_CODT_IO_NMODE)
-#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
-#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(80) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
-#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(3) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
-#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
- SDRAM_INITPLR_IMA_ENCODE(0))
-#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
- JEDEC_MA_EMR_RTT_75OHM))
-#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
- JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
- JEDEC_MA_MR_BLEN_4 | \
- JEDEC_MA_MR_DLL_RESET))
-#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(3) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
- SDRAM_INITPLR_IBA_ENCODE(0x0) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
- JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
- JEDEC_MA_MR_BLEN_4))
-#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
- JEDEC_MA_EMR_RDQS_DISABLE | \
- JEDEC_MA_EMR_DQS_DISABLE | \
- JEDEC_MA_EMR_RTT_DISABLED | \
- JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
- JEDEC_MA_EMR_RDQS_DISABLE | \
- JEDEC_MA_EMR_DQS_DISABLE | \
- JEDEC_MA_EMR_RTT_DISABLED | \
- JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
-#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
-#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
- SDRAM_RQDC_RQFD_ENCODE(56))
-#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
-#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
-#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
- SDRAM_DLCR_DLCS_CONT_DONE | \
- SDRAM_DLCR_DLCV_ENCODE(165))
-#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
-#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
-#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
- SDRAM_SDTR1_RTW_2_CLK | \
- SDRAM_SDTR1_WTWO_1_CLK | \
- SDRAM_SDTR1_RTRO_1_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
- SDRAM_SDTR2_WTR_2_CLK | \
- SDRAM_SDTR2_XSNR_32_CLK | \
- SDRAM_SDTR2_WPC_4_CLK | \
- SDRAM_SDTR2_RPC_2_CLK | \
- SDRAM_SDTR2_RP_3_CLK | \
- SDRAM_SDTR2_RRD_2_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
- SDRAM_SDTR3_RC_ENCODE(12) | \
- SDRAM_SDTR3_XCS | \
- SDRAM_SDTR3_RFC_ENCODE(21))
-#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
- SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
- SDRAM_MMODE_BLEN_4)
-#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
- SDRAM_MEMODE_RTT_75OHM)
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_PCA9698 1 /* NXP PCA9698 */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#define CONFIG_M88E1111_PHY 1
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
-#define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */
-
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0 1
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 0x13
-
-/* Debug messages for the DDR autocalibration */
-#define CONFIG_AUTOCALIB "silent\0"
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_PPC_OLD \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "logversion=2\0" \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:RP\0" \
- ""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY_ON | \
- CONFIG_SYS_POST_UART)
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
- CONFIG_SYS_NS16550_COM2 }
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-
-/* Memory Bank 0 (NOR-flash) */
-#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(11) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(1) | \
- EBC_BXAP_WBF_ENCODE(2) | \
- EBC_BXAP_TH_ENCODE(2) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
- EBC_BXCR_BS_64MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 1 (NVRAM/Uart) */
-#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \
- EBC_BXAP_FWT_ENCODE(8) | \
- EBC_BXAP_BWT_ENCODE(4) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(1) | \
- EBC_BXAP_WBN_ENCODE(1) | \
- EBC_BXAP_WBF_ENCODE(1) | \
- EBC_BXAP_TH_ENCODE(2) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
- EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_8BIT)
-
-/* Memory Bank 2 (FPGA) */
-#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(5) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(2) | \
- EBC_BXAP_WBN_ENCODE(1) | \
- EBC_BXAP_WBF_ENCODE(1) | \
- EBC_BXAP_TH_ENCODE(0) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
- EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 3 (Latches) */
-#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
- EBC_BXAP_FWT_ENCODE(8) | \
- EBC_BXAP_BWT_ENCODE(4) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(1) | \
- EBC_BXAP_WBN_ENCODE(1) | \
- EBC_BXAP_WBF_ENCODE(1) | \
- EBC_BXAP_TH_ENCODE(2) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
- EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/* EBC peripherals */
-
-#define CONFIG_SYS_FPGA_BASE(k) \
- (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
-
-#define CONFIG_SYS_FPGA_DONE(k) \
- (k ? 0x0040 : 0x0080)
-
-#define CONFIG_SYS_FPGA_COUNT 2
-
-#define CONFIG_SYS_FPGA_PTR { \
- (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
- (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
-
-#define CONFIG_SYS_FPGA_COMMON
-
-#define CONFIG_SYS_LATCH0_RESET 0xffff
-#define CONFIG_SYS_LATCH0_BOOT 0xffff
-#define CONFIG_SYS_LATCH1_RESET 0xffbf
-#define CONFIG_SYS_LATCH1_BOOT 0xffff
-
-/*-----------------------------------------------------------------------
- * GPIO Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \
-} \
-}
-
-#define CONFIG_SYS_GPIO_STARTUP_FINISHED 15
-#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_IOCON 1 /* on a IoCon board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME iocon
-#include "amcc-common.h"
-
-/* Reclaim some space. */
-#undef CONFIG_SYS_LONGHELP
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-/*
- * Configure PLL
- */
-#define PLLMR0_DEFAULT PLLMR0_266_133_66
-#define PLLMR1_DEFAULT PLLMR1_266_133_66
-
-#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- ""
-
-#define CONFIG_PHY_ADDR 4 /* PHY address */
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
-#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/*
- * I2C stuff
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_IHS
-
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_SPD_BUS_NUM 4
-
-#define CONFIG_PCA953X /* NXP PCA9554 */
-#define CONFIG_PCA9698 /* NXP PCA9698 */
-
-#define CONFIG_SYS_I2C_IHS_CH0
-#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_IHS_CH1
-#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
-#define CONFIG_SYS_I2C_IHS_CH2
-#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
-#define CONFIG_SYS_I2C_IHS_CH3
-#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-#define I2C_SOFT_DECLARATIONS2
-#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
-#define I2C_SOFT_DECLARATIONS3
-#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
-#define I2C_SOFT_DECLARATIONS4
-#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
-
-#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
-#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
-#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
-
-#ifndef __ASSEMBLY__
-void fpga_gpio_set(unsigned int bus, int pin);
-void fpga_gpio_clear(unsigned int bus, int pin);
-int fpga_gpio_get(unsigned int bus, int pin);
-#endif
-
-#define I2C_ACTIVE { }
-#define I2C_TRISTATE { }
-#define I2C_READ \
- (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
-#define I2C_SDA(bit) \
- do { \
- if (bit) \
- fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
- else \
- fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
- } while (0)
-#define I2C_SCL(bit) \
- do { \
- if (bit) \
- fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
- else \
- fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
- } while (0)
-#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*
- * PPC405 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
-} \
-}
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0xa382a880
-#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
-
-/* Memory Bank 1 (NVRAM) initializatio */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFB858000
-
-/* Memory Bank 2 (FPGA0) initialization */
-#define CONFIG_SYS_FPGA0_BASE 0x7f100000
-#define CONFIG_SYS_EBC_PB2AP 0x02825080
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
-
-#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
-#define CONFIG_SYS_FPGA_DONE(k) 0x0010
-
-#define CONFIG_SYS_FPGA_COUNT 1
-
-#define CONFIG_SYS_MCLINK_MAX 3
-
-#define CONFIG_SYS_FPGA_PTR \
- { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
-
-/* Memory Bank 3 (Latches) initialization */
-#define CONFIG_SYS_LATCH_BASE 0x7f200000
-#define CONFIG_SYS_EBC_PB3AP 0x02025080
-#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
-
-#define CONFIG_SYS_LATCH0_RESET 0xffef
-#define CONFIG_SYS_LATCH0_BOOT 0xffff
-#define CONFIG_SYS_LATCH1_RESET 0xffff
-#define CONFIG_SYS_LATCH1_BOOT 0xffff
-
-/*
- * OSD Setup
- */
-#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_OSD_SCREENS 1
-#define CONFIG_SYS_DP501_DIFFERENTIAL
-#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
-
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-#define CONFIG_BITBANGMII_MULTI
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * katmai.h - configuration for AMCC Katmai (440SPe)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_KATMAI 1 /* Board is Katmai */
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_440SPE 1 /* Specifc SPe support */
-#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-
-/*
- * Enable this board for more than 2GB of SDRAM
- */
-#define CONFIG_VERY_BIG_RAM
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME katmai
-#include "amcc-common.h"
-
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
-#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
-
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
-
-#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
-#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
-#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
-
-#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
-#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
-#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
-#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
-#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
-#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
-
-#define CONFIG_SYS_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
-#define CONFIG_DDR_ECC 1 /* with ECC support */
-#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
-#undef CONFIG_STRESS
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-
-#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
-
-#define IIC0_BOOTPROM_ADDR 0x50
-#define IIC0_ALT_BOOTPROM_ADDR 0x54
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0x50)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=ff000000\0" \
- "fdt_addr=ff1e0000\0" \
- "ramdisk_addr=ff200000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:RP:RP\0" \
- ""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
-#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-#undef CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-/* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */
-
-/*
- * NETWORK Support (PCI):
- */
-/* Support for Intel 82557/82559/82559ER chips. */
-#define CONFIG_EEPRO100
-
-/*-----------------------------------------------------------------------
- * Xilinx System ACE support
- *----------------------------------------------------------------------*/
-#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
-#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
-#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-
-/* Memory Bank 0 (Flash) initialization */
-#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(7) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(0) | \
- EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(0) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
- EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 1 (Xilinx System ACE controller) initialization */
-#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(4) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(0) | \
- EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(0) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_NONDELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE) | \
- EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/*-------------------------------------------------------------------------
- * Initialize EBC CONFIG -
- * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
- * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
- *-------------------------------------------------------------------------*/
-#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
- EBC_CFG_PTD_ENABLE | \
- EBC_CFG_RTC_16PERCLK | \
- EBC_CFG_ATC_PREVIOUS | \
- EBC_CFG_DTC_PREVIOUS | \
- EBC_CFG_CTC_PREVIOUS | \
- EBC_CFG_OEO_PREVIOUS | \
- EBC_CFG_EMC_DEFAULT | \
- EBC_CFG_PME_DISABLE | \
- EBC_CFG_PR_16)
-
-/*-----------------------------------------------------------------------
- * GPIO Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
-#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
-#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
-#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
-
-#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
- GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
- GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
- GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
-#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
-#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
-#define CONFIG_SYS_GPIO_ODR 0
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- * Grant Erickson <gerickson@nuovations.com>
- *
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * kilauea.h - configuration for AMCC Kilauea (405EX)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_KILAUEA 1 /* Board is Kilauea */
-#define CONFIG_405EX 1 /* Specifc 405EX support*/
-#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-#endif
-
-/*
- * CHIP_21 errata - you must set this to match your exact CPU, else your
- * board will not boot. DO NOT enable this unless you have JTAG available
- * for recovery, in the event you get it wrong.
- *
- * Kilauea uses the 405EX, while Haleakala uses the 405EXr. Either board
- * may be equipped for security or not. You must look at the CPU part
- * number to be sure what you have.
- */
-/* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */
-/* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */
-/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */
-/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME kilauea
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_BOARD_TYPES
-#define CONFIG_BOARD_EMAC_COUNT
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_NAND_ADDR 0xF8000000
-#define CONFIG_SYS_FPGA_BASE 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & Stack Pointer Configuration Options
- *
- * There are traditionally three options for the primordial
- * (i.e. initial) stack usage on the 405-series:
- *
- * 1) On-chip Memory (OCM) (i.e. SRAM)
- * 2) Data cache
- * 3) SDRAM
- *
- * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
- * the latter of which is less than desireable since it requires
- * setting up the SDRAM and ECC in assembly code.
- *
- * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
- * select on the External Bus Controller (EBC) and then select a
- * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
- * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
- * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
- * physical SDRAM to use (3).
- *-----------------------------------------------------------------------*/
-
-#define CONFIG_SYS_INIT_DCACHE_CS 4
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) /* 4 KiB */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * If the data cache is being used for the primordial stack and global
- * data area, the POST word must be placed somewhere else. The General
- * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
- * its compare and mask register contents across reset, so it is used
- * for the POST word.
- */
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
-#else
-# define CONFIG_SYS_INIT_EXTRA_SIZE 16
-# define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
-# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NAND FLASH
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
-
-/*
- * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
- *
- * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
- * SDRAM Controller DDR autocalibration values and takes a lot longer
- * to run than Method_B.
- * (See the Method_A and Method_B algorithm discription in the file:
- * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
- * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
- *
- * DDR Autocalibration Method_B is the default.
- */
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
-#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
-#undef CONFIG_PPC4xx_DDR_METHOD_A
-
-#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
- SDRAM_RXBAS_SDSZ_256MB | \
- SDRAM_RXBAS_SDAM_MODE7 | \
- SDRAM_RXBAS_SDBE_ENABLE)
-#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
- SDRAM_MCOPT1_8_BANKS | \
- SDRAM_MCOPT1_DDR2_TYPE | \
- SDRAM_MCOPT1_QDEP | \
- SDRAM_MCOPT1_DCOO_DISABLED)
-#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
- SDRAM_MODT_EB0R_ENABLE)
-#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
-#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
- SDRAM_CODT_CKLZ_36OHM | \
- SDRAM_CODT_DQS_1_8_V_DDR2 | \
- SDRAM_CODT_IO_NMODE)
-#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
-#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(80) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
-#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(3) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
-#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
- SDRAM_INITPLR_IMA_ENCODE(0))
-#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
- JEDEC_MA_EMR_RTT_75OHM))
-#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
- JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
- JEDEC_MA_MR_BLEN_4 | \
- JEDEC_MA_MR_DLL_RESET))
-#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(3) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
- SDRAM_INITPLR_IBA_ENCODE(0x0) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
- JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
- JEDEC_MA_MR_BLEN_4))
-#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
- JEDEC_MA_EMR_RDQS_DISABLE | \
- JEDEC_MA_EMR_DQS_DISABLE | \
- JEDEC_MA_EMR_RTT_DISABLED | \
- JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
- JEDEC_MA_EMR_RDQS_DISABLE | \
- JEDEC_MA_EMR_DQS_DISABLE | \
- JEDEC_MA_EMR_RTT_DISABLED | \
- JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
-#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
-#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
- SDRAM_RQDC_RQFD_ENCODE(56))
-#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
-#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
-#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
- SDRAM_DLCR_DLCS_CONT_DONE | \
- SDRAM_DLCR_DLCV_ENCODE(165))
-#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
-#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
-#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
- SDRAM_SDTR1_RTW_2_CLK | \
- SDRAM_SDTR1_RTRO_1_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
- SDRAM_SDTR2_WTR_2_CLK | \
- SDRAM_SDTR2_XSNR_32_CLK | \
- SDRAM_SDTR2_WPC_4_CLK | \
- SDRAM_SDTR2_RPC_2_CLK | \
- SDRAM_SDTR2_RP_3_CLK | \
- SDRAM_SDTR2_RRD_2_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
- SDRAM_SDTR3_RC_ENCODE(11) | \
- SDRAM_SDTR3_XCS | \
- SDRAM_SDTR3_RFC_ENCODE(26))
-#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
- SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
- SDRAM_MMODE_BLEN_4)
-#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
- SDRAM_MEMODE_RTT_75OHM)
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-
-/* RTC configuration */
-#define CONFIG_RTC_DS1338 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#define CONFIG_M88E1111_PHY 1
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
-#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0 1
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 2
-
-/* Debug messages for the DDR autocalibration */
-#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_PPC_OLD \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "logversion=2\0" \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:RP\0" \
- ""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-
-#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY_ON | \
- CONFIG_SYS_POST_UART)
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
- CONFIG_SYS_NS16550_COM2 }
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/*-----------------------------------------------------------------------
- * PCIe stuff
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
-#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
-
-#define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000 /* remote access */
-#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 /* local access */
-#define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
-
-#define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000 /* remote access */
-#define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000 /* local access */
-#define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
-
-#define CONFIG_SYS_PCIE0_UTLBASE 0xef502000
-#define CONFIG_SYS_PCIE1_UTLBASE 0xef503000
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x05806500
-#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 1 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x018003c0
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
-
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \
- EBC_BXAP_FWT_ENCODE(6) | \
- EBC_BXAP_BWT_ENCODE(1) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(0) | \
- EBC_BXAP_WBN_ENCODE(3) | \
- EBC_BXAP_WBF_ENCODE(1) | \
- EBC_BXAP_TH_ENCODE(4) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x18000)
-
-#define CONFIG_SYS_EBC_CFG 0x7FC00000 /* EBC0_CFG */
-
-/*-----------------------------------------------------------------------
- * GPIO Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
-} \
-}
-
-/*-----------------------------------------------------------------------
- * Some Kilauea stuff..., mainly fpga registers
- */
-#define CONFIG_SYS_FPGA_REG_BASE CONFIG_SYS_FPGA_BASE
-#define CONFIG_SYS_FPGA_FIFO_BASE (CONFIG_SYS_FPGA_BASE | (1 << 10))
-
-/* interrupt */
-#define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT 0x80000000
-#define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT 0x40000000
-#define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT 0x20000000
-#define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT 0x10000000
-#define CONFIG_SYS_FPGA_PHY0_INT 0x08000000
-#define CONFIG_SYS_FPGA_PHY1_INT 0x04000000
-#define CONFIG_SYS_FPGA_SLIC0_INT 0x02000000
-#define CONFIG_SYS_FPGA_SLIC1_INT 0x01000000
-
-/* DPRAM setting */
-/* 00: 32B; 01: 64B; 10: 128B; 11: 256B */
-#define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */
-#define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */
-#define CONFIG_SYS_FPGA_DPRAM_RW_TYPE 0x00080000
-#define CONFIG_SYS_FPGA_DPRAM_RST 0x00040000
-#define CONFIG_SYS_FPGA_UART0_FO 0x00020000
-#define CONFIG_SYS_FPGA_UART1_FO 0x00010000
-
-/* loopback */
-#define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK 0x00004000
-#define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK 0x00008000
-#define CONFIG_SYS_FPGA_SLIC0_ENABLE 0x00002000
-#define CONFIG_SYS_FPGA_SLIC1_ENABLE 0x00001000
-#define CONFIG_SYS_FPGA_SLIC0_CS 0x00000800
-#define CONFIG_SYS_FPGA_SLIC1_CS 0x00000400
-#define CONFIG_SYS_FPGA_USER_LED0 0x00000200
-#define CONFIG_SYS_FPGA_USER_LED1 0x00000100
-
-#define CONFIG_SYS_FPGA_MAGIC_MASK 0xffff0000
-#define CONFIG_SYS_FPGA_MAGIC 0xabcd0000
-#define CONFIG_SYS_FPGA_VER_MASK 0x0000ff00
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- * John Otken, jotken@softadvances.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * luan.h - configuration for LUAN board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_LUAN 1 /* Board is Luan */
-#define CONFIG_440SP 1 /* Specific PPC440SP support */
-#define CONFIG_440 1
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME luan
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
-#define CONFIG_SYS_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
-#define CONFIG_SYS_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
-#define CONFIG_SYS_SRAM_SIZE (1 << 20)
-#define CONFIG_SYS_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */
-
-#define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
-
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-
-#if CONFIG_SYS_LARGE_FLASH == 0xffc00000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LARGE_FLASH
-#else
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SMALL_FLASH
-#endif
-
-#if CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_KBYTES_SDRAM 1024*2
-#else
-#define CONFIG_SYS_KBYTES_SDRAM 1024
-#endif
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE (8 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_FLASH_ADDR0 0x555
-#define CONFIG_SYS_FLASH_ADDR1 0x2aa
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
-#define CONFIG_DDR_ECC 1 /* with ECC support */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_PPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "ramdisk_addr=fc100000\0" \
- ""
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_ADDR 1
-#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#else
-#define CONFIG_HW_WATCHDOG /* watchdog */
-#endif
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_PCI)
-
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#undef CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
-
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * lwmon5.h - configuration for lwmon5 board
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_LWMON5 1 /* Board is lwmon5 */
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_440 1 /* ... PPC440 family */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-#define CONFIG_HOSTNAME lwmon5
-
-#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
-
-#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
-
-#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
-#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
-#define CONFIG_MISC_INIT_R /* Call misc_init_r */
-#define CONFIG_BOARD_RESET /* Call board_reset */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
-
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
-#define CONFIG_SYS_LIME_BASE_0 0xc0000000
-#define CONFIG_SYS_LIME_BASE_1 0xc1000000
-#define CONFIG_SYS_LIME_BASE_2 0xc2000000
-#define CONFIG_SYS_LIME_BASE_3 0xc3000000
-#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
-#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
-#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
-#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
-#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
-
-#define CONFIG_SYS_USB2D0_BASE 0xe0000100
-#define CONFIG_SYS_USB_DEVICE 0xe0000000
-#define CONFIG_SYS_USB_HOST 0xe0000400
-
-/*
- * Initial RAM & stack pointer
- *
- * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
- * the POST_WORD from OCM to a 440EPx register that preserves it's
- * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
- * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
- */
-#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* unused GPT0 COMP reg */
-#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
-#define CONFIG_SYS_OCM_SIZE (16 << 10)
-/* 440EPx errata CHIP 11: don't use last 4kbytes */
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
-
-/* Additional registers for watchdog timer post test */
-#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
-#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
-#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
-#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
-#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
-#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
-#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
-#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
-#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
-#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH0 0xFC000000
-#define CONFIG_SYS_FLASH1 0xF8000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
-
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * DDR SDRAM
- */
-#define CONFIG_SYS_MBYTES_SDRAM 256
-#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
-#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#define CONFIG_DDR_ECC /* enable ECC */
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ECC | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_FPU | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_OCM | \
- CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_SPR | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_SYSMON | \
- CONFIG_SYS_POST_WATCHDOG | \
- CONFIG_SYS_POST_DSP | \
- CONFIG_SYS_POST_BSPEC1 | \
- CONFIG_SYS_POST_BSPEC2 | \
- CONFIG_SYS_POST_BSPEC3 | \
- CONFIG_SYS_POST_BSPEC4 | \
- CONFIG_SYS_POST_BSPEC5)
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
- CONFIG_SYS_NS16550_COM2 }
-
-#define CONFIG_POST_UART { \
- "UART test", \
- "uart", \
- "This test verifies the UART operation.", \
- POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
- &uart_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_UART \
- }
-
-#define CONFIG_POST_WATCHDOG { \
- "Watchdog timer test", \
- "watchdog", \
- "This test checks the watchdog timer.", \
- POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
- &lwmon5_watchdog_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_WATCHDOG \
- }
-
-#define CONFIG_POST_BSPEC1 { \
- "dsPIC init test", \
- "dspic_init", \
- "This test returns result of dsPIC READY test run earlier.", \
- POST_RAM | POST_ALWAYS, \
- &dspic_init_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_BSPEC1 \
- }
-
-#define CONFIG_POST_BSPEC2 { \
- "dsPIC test", \
- "dspic", \
- "This test gets result of dsPIC POST and dsPIC version.", \
- POST_RAM | POST_ALWAYS, \
- &dspic_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_BSPEC2 \
- }
-
-#define CONFIG_POST_BSPEC3 { \
- "FPGA test", \
- "fpga", \
- "This test checks FPGA registers and memory.", \
- POST_RAM | POST_ALWAYS | POST_MANUAL, \
- &fpga_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_BSPEC3 \
- }
-
-#define CONFIG_POST_BSPEC4 { \
- "GDC test", \
- "gdc", \
- "This test checks GDC registers and memory.", \
- POST_RAM | POST_ALWAYS | POST_MANUAL,\
- &gdc_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_BSPEC4 \
- }
-
-#define CONFIG_POST_BSPEC5 { \
- "SYSMON1 test", \
- "sysmon1", \
- "This test checks GPIO_62_EPX pin indicating power failure.", \
- POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
- &sysmon1_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_BSPEC5 \
- }
-
-#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
-#define CONFIG_LOGBUFFER
-/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
-#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
-#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
-#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
-#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
-#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
-#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
-#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
-#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
- /* 64 byte page write mode using*/
- /* last 6 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-
-#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
-#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
-#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
-
-#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
- CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
- CONFIG_SYS_I2C_DSPIC_ADDR, \
- CONFIG_SYS_I2C_DSPIC_2_ADDR, \
- CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
- CONFIG_SYS_I2C_DSPIC_IO_ADDR }
-
-/* Update size in "reg" property of NOR FLASH device tree nodes */
-#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-
-#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
-
-#define CONFIG_PREBOOT "setenv bootdelay 15"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hostname=lwmon5\0" \
- "netdev=eth0\0" \
- "unlock=yes\0" \
- "logversion=2\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
- "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
- "flash_nfs=run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};" \
- "run nfsargs addip addtty addmisc;bootm\0" \
- "rootpath=/opt/eldk/ppc_4xxFP\0" \
- "bootfile=/tftpboot/lwmon5/uImage\0" \
- "kernel_addr=FC000000\0" \
- "ramdisk_addr=FC180000\0" \
- "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
- "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
- "cp.b 200000 FFF80000 80000\0" \
- "upd=run load update\0" \
- "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
- "autoscr 200000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
-
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_RESET_DELAY 300
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 1
-
-/* Video console */
-#define CONFIG_VIDEO_MB862xx
-#define CONFIG_VIDEO_MB862xx_ACCEL
-#define CONFIG_VIDEO_LOGO
-#define VIDEO_FB_16BPP_PIXEL_SWAP
-#define VIDEO_FB_16BPP_WORD_SWAP
-
-#define CONFIG_SPLASH_SCREEN
-
-/*
- * USB/EHCI
- */
-#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
-#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
-#define CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
-
-/* Partitions */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-
-#ifdef CONFIG_440EPX
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-
-#ifndef DEBUG
-#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
-#endif
-#define CONFIG_WD_PERIOD 40000 /* in usec */
-#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the 40x Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x03000280
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
-
-/* Memory Bank 1 (Lime) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x01004380
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
-
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x01004400
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
-
-/* Memory Bank 3 (FPGA2) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x01004400
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
-
-#define CONFIG_SYS_EBC_CFG 0xb8400000
-
-/*
- * Graphics (Fujitsu Lime)
- */
-/* SDRAM Clock frequency adjustment register */
-#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
-#if 1 /* 133MHz is not tested enough, use 100MHz for now */
-/* Lime Clock frequency is to set 100MHz */
-#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
-#else
-/* Lime Clock frequency for 133MHz */
-#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
-#endif
-
-/* SDRAM Parameter register */
-#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
-/*
- * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
- * and pixel flare on display when 133MHz was configured. According to
- * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
- * Grade
- */
-#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
-#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
-#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
-#else
-#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
-#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
-#endif
-
-/*
- * GPIO Setup
- */
-#define CONFIG_SYS_GPIO_PHY1_RST 12
-#define CONFIG_SYS_GPIO_FLASH_WP 14
-#define CONFIG_SYS_GPIO_PHY0_RST 22
-#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
-#define CONFIG_SYS_GPIO_DSPIC_READY 51
-#define CONFIG_SYS_GPIO_CAN_ENABLE 53
-#define CONFIG_SYS_GPIO_LSB_ENABLE 54
-#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
-#define CONFIG_SYS_GPIO_HIGHSIDE 56
-#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
-#define CONFIG_SYS_GPIO_BOARD_RESET 58
-#define CONFIG_SYS_GPIO_LIME_S 59
-#define CONFIG_SYS_GPIO_LIME_RST 60
-#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
-#define CONFIG_SYS_GPIO_WATCHDOG 63
-
-#define GPIO49_VAL 1
-
-/*
- * PPC440 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
-} \
-}
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- * Grant Erickson <gerickson@nuovations.com>
- *
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * makalu.h - configuration for AMCC Makalu (405EX)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_MAKALU 1 /* Board is Makalu */
-#define CONFIG_405EX 1 /* Specifc 405EX support*/
-#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME makalu
-#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_FPGA_BASE 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & Stack Pointer Configuration Options
- *
- * There are traditionally three options for the primordial
- * (i.e. initial) stack usage on the 405-series:
- *
- * 1) On-chip Memory (OCM) (i.e. SRAM)
- * 2) Data cache
- * 3) SDRAM
- *
- * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
- * the latter of which is less than desireable since it requires
- * setting up the SDRAM and ECC in assembly code.
- *
- * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
- * select on the External Bus Controller (EBC) and then select a
- * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
- * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
- * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
- * physical SDRAM to use (3).
- *-----------------------------------------------------------------------*/
-
-#define CONFIG_SYS_INIT_DCACHE_CS 4
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) /* 4 KiB */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * If the data cache is being used for the primordial stack and global
- * data area, the POST word must be placed somewhere else. The General
- * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
- * its compare and mask register contents across reset, so it is used
- * for the POST word.
- */
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
-#else
-# define CONFIG_SYS_INIT_EXTRA_SIZE 16
-# define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
-# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no ext. clk */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
-
-#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM0_MB1CF_BASE ((128 << 20) + CONFIG_SYS_SDRAM_BASE)
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
- SDRAM_RXBAS_SDSZ_128MB | \
- SDRAM_RXBAS_SDAM_MODE2 | \
- SDRAM_RXBAS_SDBE_ENABLE)
-#define CONFIG_SYS_SDRAM0_MB1CF ((CONFIG_SYS_SDRAM0_MB1CF_BASE >> 3) | \
- SDRAM_RXBAS_SDSZ_128MB | \
- SDRAM_RXBAS_SDAM_MODE2 | \
- SDRAM_RXBAS_SDBE_ENABLE)
-#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MCOPT1 0x04322000
-#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0 0x01800000
-#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
-#define CONFIG_SYS_SDRAM0_CODT 0x0080f837
-#define CONFIG_SYS_SDRAM0_RTR 0x06180000
-#define CONFIG_SYS_SDRAM0_INITPLR0 0xa8380000
-#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
-#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
-#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
-#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010404
-#define CONFIG_SYS_SDRAM0_INITPLR5 0x81000542
-#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
-#define CONFIG_SYS_SDRAM0_INITPLR7 0x8D080000
-#define CONFIG_SYS_SDRAM0_INITPLR8 0x8D080000
-#define CONFIG_SYS_SDRAM0_INITPLR9 0x8D080000
-#define CONFIG_SYS_SDRAM0_INITPLR10 0x8D080000
-#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442
-#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010780
-#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010400
-#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
-#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
-#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
-#define CONFIG_SYS_SDRAM0_RFDC 0x00000209
-#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
-#define CONFIG_SYS_SDRAM0_DLCR 0x030000a5
-#define CONFIG_SYS_SDRAM0_CLKTR 0x80000000
-#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
-#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
-#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
-#define CONFIG_SYS_SDRAM0_SDTR3 0x080b0d1a
-#define CONFIG_SYS_SDRAM0_MMODE 0x00000442
-#define CONFIG_SYS_SDRAM0_MEMODE 0x00000404
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-
-/* RTC configuration */
-#define CONFIG_RTC_X1205 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#define CONFIG_M88E1111_PHY 1
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
-#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */
-
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0 1
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 0
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_PPC_OLD \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:RP\0" \
- ""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_UART)
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
- CONFIG_SYS_NS16550_COM2 }
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/*-----------------------------------------------------------------------
- * PCIe stuff
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
-#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
-
-#define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000 /* remote access */
-#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 /* local access */
-#define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
-
-#define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000 /* remote access */
-#define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000 /* local access */
-#define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
-
-#define CONFIG_SYS_PCIE0_UTLBASE 0xef502000
-#define CONFIG_SYS_PCIE1_UTLBASE 0xef503000
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x08033700
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 2 (CPLD) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x9400C800
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
-
-#define CONFIG_SYS_EBC_CFG 0x7FC00000 /* EBC0_CFG */
-
-/*-----------------------------------------------------------------------
- * GPIO Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
-{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
-} \
-}
-
-#define CONFIG_SYS_GPIO_PCIE_RST 23
-#define CONFIG_SYS_GPIO_PCIE_CLKREQ 27
-#define CONFIG_SYS_GPIO_PCIE_WAKE 28
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_NEO 1 /* on a Neo board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME neo
-#include "amcc-common.h"
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-/*
- * Configure PLL
- */
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-
-#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- ""
-
-#define CONFIG_PHY_ADDR 4 /* PHY address */
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
-#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/*
- * I2C stuff
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-
-/* RTC */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR 0xFFF00000
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*
- * PPC405 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
-} \
-}
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (NVRAM) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA0_BASE 0x7f100000
-#define CONFIG_SYS_EBC_PB2AP 0x92015480
-#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
-
-#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
-
-#define CONFIG_SYS_FPGA_COUNT 1
-
-#define CONFIG_SYS_FPGA_PTR \
- { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
-
-#define CONFIG_SYS_FPGA_COMMON
-
-/* Memory Bank 3 (Latches) initialization */
-#define CONFIG_SYS_LATCH_BASE 0x7f200000
-#define CONFIG_SYS_EBC_PB3AP 0x92015480
-#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
-
-#define CONFIG_SYS_LATCH0_RESET 0xffff
-#define CONFIG_SYS_LATCH0_BOOT 0xffff
-#define CONFIG_SYS_LATCH1_RESET 0xffbf
-#define CONFIG_SYS_LATCH1_BOOT 0xffff
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Configuration for AMCC 460SX Ref (redwood)
- *
- * (C) Copyright 2008
- * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_440 1 /* ... PPC460 family */
-#define CONFIG_460SX 1 /* ... PPC460 family */
-
-#define CONFIG_SYS_TEXT_BASE 0xfffb0000
-
-/*-----------------------------------------------------------------------
- * Include common defines/options for all AMCC boards
- *----------------------------------------------------------------------*/
-#define CONFIG_HOSTNAME redwood
-
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
-#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
-
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-
-#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
-#define CONFIG_SYS_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */
-#define CONFIG_SYS_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */
-#define CONFIG_SYS_PCIE_MEMSIZE 0x01000000
-
-#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000
-#define CONFIG_SYS_PCIE1_XCFGBASE 0xb2000000
-#define CONFIG_SYS_PCIE2_XCFGBASE 0xb4000000
-#define CONFIG_SYS_PCIE0_CFGBASE 0xb6000000
-#define CONFIG_SYS_PCIE1_CFGBASE 0xb8000000
-#define CONFIG_SYS_PCIE2_CFGBASE 0xba000000
-
-/* PCIe mapped UTL registers */
-#define CONFIG_SYS_PCIE0_REGBASE 0xd0000000
-#define CONFIG_SYS_PCIE1_REGBASE 0xd0010000
-#define CONFIG_SYS_PCIE2_REGBASE 0xd0020000
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
-
-#define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */
-#define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
-#define CONFIG_DDR_ECC 1 /* with ECC support */
-
-#define CONFIG_SYS_SPD_MAX_DIMMS 2
-
-/* SPD i2c spd addresses */
-#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
-#define IIC0_DIMM0_ADDR 0x53
-#define IIC0_DIMM1_ADDR 0x52
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define IIC0_BOOTPROM_ADDR 0x50
-#define IIC0_ALT_BOOTPROM_ADDR 0x54
-
-/* Don't probe these addrs */
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#undef CONFIG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
-#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- ""
-
-/*----------------------------------------------------------------------------+
-| Commands in addition to amcc-common.h
-+----------------------------------------------------------------------------*/
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_M88E1141_PHY 1 /* Enable phy */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
-#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR 0xfffa0000
-#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*---------------------------------------------------------------------------*/
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2006-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * sequoia.h - configuration for Sequoia & Rainier boards
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
-#ifndef CONFIG_RAINIER
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_HOSTNAME sequoia
-#else
-#define CONFIG_440GRX 1 /* Specific PPC440GRx */
-#define CONFIG_HOSTNAME rainier
-#endif
-#define CONFIG_440 1 /* ... PPC440 family */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-
-/* Detect Sequoia PLL input clock automatically via CPLD bit */
-#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
- 33333333 : 33000000)
-
-/*
- * Define this if you want support for video console with radeon 9200 pci card
- * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
- */
-
-#ifdef CONFIG_VIDEO
-/*
- * 44x dcache supported is working now on sequoia, but we don't enable
- * it yet since it needs further testing
- */
-#define CONFIG_4xx_DCACHE /* enable dcache */
-#endif
-
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*
- * Base addresses -- Note these are effective addresses where the actual
- * resources get mapped (not physical addresses).
- */
-#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
-#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
-#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-#define CONFIG_SYS_USB2D0_BASE 0xe0000100
-#define CONFIG_SYS_USB_DEVICE 0xe0000000
-#define CONFIG_SYS_USB_HOST 0xe0000400
-#define CONFIG_SYS_BCSR_BASE 0xc0000000
-
-/*
- * Initial RAM & stack pointer
- */
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
-
-/*
- * Environment
- */
-#if defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
-#define CONFIG_ENV_SIZE (8 << 10)
-#else
-#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
-#endif
-
-#if defined(CONFIG_CMD_FLASH)
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-#endif /* CONFIG_CMD_FLASH */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*
- * DDR SDRAM
- */
-#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
-#if !defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#endif
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
- /* 440EPx errata CHIP 11 */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_PPC_OLD \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=FC000000\0" \
- "ramdisk_addr=FC180000\0" \
- ""
-
-#define CONFIG_M88E1111_PHY 1
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
-
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 1
-
-/* USB */
-#ifdef CONFIG_440EPX
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_PPC4XX
-#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#else /* CONFIG_USB_EHCI_HCD */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#endif
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-#endif /* CONFIG_440EPX */
-
-/* Partitions */
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#ifdef CONFIG_440EPX
-#endif
-
-#ifndef CONFIG_RAINIER
-#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
-#else
-#define CONFIG_SYS_POST_FPU_ON 0
-#endif
-
-/*
- * Don't run the memory POST on the NAND-booting version. It will
- * overwrite part of the U-Boot image which is already loaded from NAND
- * to SDRAM.
- */
-#if defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_SYS_POST_MEMORY_ON 0
-#else
-#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
-#endif
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_FPU_ON | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY_ON | \
- CONFIG_SYS_POST_SPR | \
- CONFIG_SYS_POST_UART)
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
- /* CONFIG_SYS_PCI_MEMBASE */
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/*
- * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
- */
-#if !defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x03017200
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 3 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x018003c0
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-#else
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-/* Memory Bank 3 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x03017200
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
-
-/* Memory Bank 2 (CPLD) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x24814580
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
-
-#define CONFIG_SYS_BCSR5_PCI66EN 0x80
-
-/*
- * NAND FLASH
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-
-/*
- * PPC440 GPIO Configuration
- */
-/* test-only: take GPIO init from pcs440ep ???? in config file */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
-} \
-}
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
-#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
-#define VIDEO_IO_OFFSET 0xe8000000
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SPLASH_SCREEN
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * t3corp.h - configuration for T3CORP (460GT)
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_460GT 1 /* Specific PPC460GT */
-#define CONFIG_440 1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-#endif
-
-#define CONFIG_HOSTNAME t3corp
-
-/*
- * Include common defines/options for all AMCC/APM eval boards
- */
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CFG_ALT_MEMTEST
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
-
-#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe mem */
-#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe */
-#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
-
-#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
-#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
-#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
-#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
-
-#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit phys addr */
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit phys addr */
-
-/* EBC stuff */
-#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */
-#define CONFIG_SYS_FLASH_SIZE (64 << 20)
-
-#define CONFIG_SYS_FPGA1_BASE 0xe0000000
-#define CONFIG_SYS_FPGA2_BASE 0xe2000000
-#define CONFIG_SYS_FPGA3_BASE 0xe4000000
-
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
-#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
-#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
-#define CONFIG_SYS_FLASH_BASE_PHYS \
- (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
- | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-
-#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */
-#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
-#define CONFIG_SYS_SRAM_SIZE (256 << 10)
-#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
-
-/*
- * Initial RAM & stack pointer (placed in OCM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-
-/*
- * Environment
- */
-/*
- * Define here the location of the environment variables (flash).
- */
-#define CONFIG_ENV_IS_IN_FLASH /* use flash for environment vars */
-
-/*
- * Flash related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
-#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
- (CONFIG_SYS_FPGA1_BASE + 0x01000000) }
-#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff, /* don't set */ \
- 0xbddf } /* set async read mode */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buff'd writes (20x faster)*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* sector size */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* env sector size */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * DDR2 SDRAM
- */
-#define CONFIG_SYS_MBYTES_SDRAM 256
-#define CONFIG_DDR_ECC
-#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
-#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
-#undef CONFIG_PPC4xx_DDR_METHOD_A
-#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-/* Memory Queue */
-#define CONFIG_SYS_SDRAM_R0BAS (SDRAM_RXBAS_SDBA_ENCODE(0) | \
- SDRAM_RXBAS_SDSZ_256)
-#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
-#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
-#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
-#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00
-#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
-#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
-
-#define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-#define CONFIG_SYS_SDRAM0_MB0CF (SDRAM_RXBAS_SDAM_MODE7 | \
- SDRAM_RXBAS_SDBE_ENABLE)
-#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_MCHK_GEN | \
- SDRAM_MCOPT1_PMU_OPEN | \
- SDRAM_MCOPT1_DMWD_32 | \
- SDRAM_MCOPT1_8_BANKS | \
- SDRAM_MCOPT1_DDR2_TYPE | \
- SDRAM_MCOPT1_QDEP | \
- SDRAM_MCOPT1_RWOO_DISABLED | \
- SDRAM_MCOPT1_WOOO_DISABLED | \
- SDRAM_MCOPT1_DREF_NORMAL)
-#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0 SDRAM_MODT_EB0W_ENABLE
-#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
-#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
-#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
- SDRAM_CODT_DQS_1_8_V_DDR2 | \
- SDRAM_CODT_IO_NMODE)
-#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
-#define CONFIG_SYS_SDRAM0_INITPLR0 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(80) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
-#define CONFIG_SYS_SDRAM0_INITPLR1 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(3) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR2 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
-#define CONFIG_SYS_SDRAM0_INITPLR3 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
- SDRAM_INITPLR_IMA_ENCODE(0))
-#define CONFIG_SYS_SDRAM0_INITPLR4 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE | \
- JEDEC_MA_EMR_RTT_150OHM))
-#define CONFIG_SYS_SDRAM0_INITPLR5 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(200) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
- CAS_LATENCY | \
- JEDEC_MA_MR_BLEN_4 | \
- JEDEC_MA_MR_DLL_RESET))
-#define CONFIG_SYS_SDRAM0_INITPLR6 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(3) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
- SDRAM_INITPLR_IBA_ENCODE(0x0) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR7 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR8 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR9 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR10 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(26) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR11 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
- CAS_LATENCY | \
- JEDEC_MA_MR_BLEN_4))
-#define CONFIG_SYS_SDRAM0_INITPLR12 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
- JEDEC_MA_EMR_RDQS_DISABLE | \
- JEDEC_MA_EMR_DQS_ENABLE | \
- JEDEC_MA_EMR_RTT_150OHM | \
- JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR13 \
- (SDRAM_INITPLR_ENABLE | \
- SDRAM_INITPLR_IMWT_ENCODE(2) | \
- SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
- SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
- SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
- JEDEC_MA_EMR_RDQS_DISABLE | \
- JEDEC_MA_EMR_DQS_ENABLE | \
- JEDEC_MA_EMR_RTT_150OHM | \
- JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR14 SDRAM_INITPLR_DISABLE
-#define CONFIG_SYS_SDRAM0_INITPLR15 SDRAM_INITPLR_DISABLE
-#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
- SDRAM_RQDC_RQFD_ENCODE(56))
-#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(599)
-#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
-#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
- SDRAM_DLCR_DLCS_CONT_DONE | \
- SDRAM_DLCR_DLCV_ENCODE(155))
-#define CONFIG_SYS_SDRAM0_CLKTR SDRAM_CLKTR_CLKP_90_DEG_ADV
-#define CONFIG_SYS_SDRAM0_WRDTR SDRAM_WRDTR_WTR_90_DEG_ADV
-#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
- SDRAM_SDTR1_RTW_2_CLK | \
- SDRAM_SDTR1_RTRO_1_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
- SDRAM_SDTR2_WTR_2_CLK | \
- SDRAM_SDTR2_XSNR_32_CLK | \
- SDRAM_SDTR2_WPC_4_CLK | \
- SDRAM_SDTR2_RPC_2_CLK | \
- SDRAM_SDTR2_RP_3_CLK | \
- SDRAM_SDTR2_RRD_2_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
- SDRAM_SDTR3_RC_ENCODE(11) | \
- SDRAM_SDTR3_XCS | \
- SDRAM_SDTR3_RFC_ENCODE(26))
-#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
- CAS_LATENCY | \
- SDRAM_MMODE_BLEN_4)
-#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_ENABLE | \
- SDRAM_MEMODE_RTT_150OHM)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-
-/*
- * Ethernet
- */
-#define CONFIG_IBM_EMAC4_V4 1
-
-#define CONFIG_HAS_ETH0
-
-#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CONFIG_M88E1111_PHY
-/* Disable fiber since fiber/copper auto-selection doesn't seem to work */
-#define CONFIG_M88E1111_DISABLE_FIBER
-
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_PHY_DYNAMIC_ANEG 1
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:RP\0" \
- "unlock=yes\0" \
- ""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/* Board-specific PCI, no PCI support, only PCIe */
-#undef CONFIG_SYS_PCI_TARGET_INIT
-#undef CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/*
- * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
- * boot EBC mapping only supports a maximum of 16MBytes
- * (4.ff00.0000 - 4.ffff.ffff).
- * To solve this problem, the flash has to get remapped to another
- * EBC address which accepts bigger regions:
- *
- * 0xfc00.0000 -> 4.cc00.0000
- */
-
-/* Memory Bank 0 (NOR-flash) */
-#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(16) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(1) | \
- EBC_BXAP_OEN_ENCODE(1) | \
- EBC_BXAP_WBN_ENCODE(1) | \
- EBC_BXAP_WBF_ENCODE(1) | \
- EBC_BXAP_TH_ENCODE(7) | \
- EBC_BXAP_RE_DISABLED | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \
- EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 1 (FPGA 1) */
-#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(5) | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(3) | \
- EBC_BXAP_WBN_ENCODE(0) | \
- EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(1) | \
- EBC_BXAP_RE_ENABLED | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_RW | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
- EBC_BXCR_BS_32MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_32BIT)
-
-/* Memory Bank 2 (FPGA 2) */
-#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(5) | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(3) | \
- EBC_BXAP_WBN_ENCODE(0) | \
- EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(1) | \
- EBC_BXAP_RE_ENABLED | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_RW | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
- EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_32BIT)
-
-/* Memory Bank 3 (FPGA 3) */
-#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(5) | \
- EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(3) | \
- EBC_BXAP_WBN_ENCODE(0) | \
- EBC_BXAP_WBF_ENCODE(0) | \
- EBC_BXAP_TH_ENCODE(1) | \
- EBC_BXAP_RE_ENABLED | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_RW | \
- EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
- EBC_BXCR_BS_16MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_32BIT)
-
-/*
- * PPC4xx GPIO Configuration
- */
-
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
-{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
-} \
-}
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000-2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
- /* ...or on a SYCAMORE board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME walnut
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_PPC_OLD \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fff80000\0" \
- "ramdisk_addr=fff80000\0" \
- ""
-
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_HAS_ETH0 1
-
-#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/*-----------------------------------------------------------------------
- * I2C stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
- /* resource configuration */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- */
-#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-
-/*
- * Define here the location of the environment variables (FLASH or NVRAM).
- * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
- * supported for backward compatibility.
- */
-#if 1
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_FLASH_ADDR0 0x5555
-#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x9B015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
-
-#define CONFIG_SYS_EBC_PB1AP 0x02815480
-#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-#define CONFIG_SYS_EBC_PB2AP 0x04815A80
-#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
-
-#define CONFIG_SYS_EBC_PB3AP 0x01815280
-#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
-
-#define CONFIG_SYS_EBC_PB7AP 0x01815280
-#define CONFIG_SYS_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
-#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- *
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- *
- * (C) Copyright 2008
- * Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_GEN_H
-#define __CONFIG_GEN_H
-
-#include "../board/xilinx/ppc405-generic/xparameters.h"
-
-#define CONFIG_405 1
-#define CONFIG_XILINX_405 1
-
-/* sdram */
-#define CONFIG_SYS_SDRAM_SIZE_MB 256
-
-/* environment */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_SYS_ENV_OFFSET 0x3F0000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
-#define CONFIG_ENV_OVERWRITE 1
-
-/*Misc*/
-#define CONFIG_PREBOOT "echo U-Boot is up and running;"
-
-/*Flash*/
-#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
-#define CONFIG_SYS_FLASH_SIZE (128*1024*1024)
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define MTDIDS_DEFAULT "nor0=flash"
-#define MTDPARTS_DEFAULT "mtdparts=flash:-(user)"
-
-#include <configs/xilinx-ppc.h>
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* CPU */
-#define CONFIG_440 1
-#define CONFIG_XILINX_440 1
-#define CONFIG_XILINX_PPC440_GENERIC 1
-#include "../board/xilinx/ppc440-generic/xparameters.h"
-
-/* Mem Map */
-#define CONFIG_SYS_SDRAM_SIZE_MB 256
-
-/* Env */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_OFFSET 0x340000
-#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
-
-/* Misc */
-#define CONFIG_PREBOOT "echo U-Boot is up and running;"
-
-/* Flash */
-#define CONFIG_SYS_FLASH_SIZE (128*1024*1024)
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-#define MTDIDS_DEFAULT "nor0=flash"
-#define MTDPARTS_DEFAULT "mtdparts=flash:-(user)"
-
-/* Net */
-#ifdef XPAR_LLTEMAC_0_BASEADDR
-#define CONFIG_XILINX_LL_TEMAC
-#define CONFIG_MII
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MARVELL
-#define CONFIG_NET_RANDOM_ETHADDR
-#define CONFIG_LIB_RAND
-#endif
-
-/* Generic Configs */
-#include <configs/xilinx-ppc.h>
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * config for XPedite1000 from XES Inc.
- * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
- * (C) Copyright 2003 Sandburst Corporation
- * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_XPEDITE1000 1
-#define CONFIG_SYS_BOARD_NAME "XPedite1000"
-#define CONFIG_SYS_FORM_PMC 1
-#define CONFIG_440 1
-#define CONFIG_440GX 1 /* 440 GX */
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-/*
- * DDR config
- */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
-#define CONFIG_VERY_BIG_RAM 1
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-
-/*
- * Diagnostics
- */
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_START 0x0400000
-#define CONFIG_SYS_MEMTEST_END 0x0C00000
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_I2C)
-
-/*
- * LED support
- */
-#define USR_LED0 0x00000080
-#define USR_LED1 0x00000100
-#define USR_LED2 0x00000200
-#define USR_LED3 0x00000400
-
-#ifndef __ASSEMBLY__
-extern unsigned long in32(unsigned int);
-extern void out32(unsigned int, unsigned long);
-
-#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
-#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
-#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
-#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
-
-#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
-#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
-#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
-#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
-#endif
-
-/*
- * Use internal SRAM for initial stack
- */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * NOR flash configuration
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 3
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 }
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7f
-
-/* I2C EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C RTC: STMicro M41T00 */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-
-/*
- * PCI
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
-
-/*
- * Networking options
- */
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_ETHPRIME "ppc_4xx_eth2"
-#define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */
-#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
-#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
-#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
-#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command configuration
- */
-#define CONFIG_CMD_PCI
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
-#define CONFIG_PREBOOT /* enable preboot variable */
-#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
-#define CONFIG_ENV_SIZE 0x8000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
-
-/*
- * Flash memory map:
- * fff80000 - ffffffff U-Boot (512 KB)
- * fff40000 - fff7ffff U-Boot Environment (256 KB)
- * fff00000 - fff3ffff FDT (256KB)
- * ffc00000 - ffefffff OS image (3MB)
- * ff000000 - ffbfffff OS Use/Filesystem (12MB)
- */
-
-#define CONFIG_UBOOT_ENV_ADDR __stringify(CONFIG_SYS_TEXT_BASE)
-#define CONFIG_FDT_ENV_ADDR __stringify(0xfff00000)
-#define CONFIG_OS_ENV_ADDR __stringify(0xffc00000)
-
-#define CONFIG_PROG_UBOOT \
- "$download_cmd $loadaddr $ubootfile; " \
- "if test $? -eq 0; then " \
- "protect off "CONFIG_UBOOT_ENV_ADDR" +80000; " \
- "erase "CONFIG_UBOOT_ENV_ADDR" +80000; " \
- "cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; " \
- "protect on "CONFIG_UBOOT_ENV_ADDR" +80000; " \
- "cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; " \
- "if test $? -ne 0; then " \
- "echo PROGRAM FAILED; " \
- "else; " \
- "echo PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_BOOT_OS_NET \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "if test -n $fdtaddr; then " \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "bootm $osaddr - $fdtaddr; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi; " \
- "else; " \
- "bootm $osaddr; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_OS \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_OS_ENV_ADDR" +$filesize; " \
- "cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
- "cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo OS PROGRAM FAILED; " \
- "else; " \
- "echo OS PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_FDT \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_FDT_ENV_ADDR" +$filesize;" \
- "cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
- "cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo FDT PROGRAM FAILED; " \
- "else; " \
- "echo FDT PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=yes\0" \
- "download_cmd=tftp\0" \
- "console_args=console=ttyS0,115200\0" \
- "root_args=root=/dev/nfs rw\0" \
- "misc_args=ip=on\0" \
- "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
- "bootfile=/home/user/file\0" \
- "osfile=/home/user/board.uImage\0" \
- "fdtfile=/home/user/board.dtb\0" \
- "ubootfile=/home/user/u-boot.bin\0" \
- "fdtaddr=0x1e00000\0" \
- "osaddr=0x1000000\0" \
- "loadaddr=0x1000000\0" \
- "prog_uboot="CONFIG_PROG_UBOOT"\0" \
- "prog_os="CONFIG_PROG_OS"\0" \
- "prog_fdt="CONFIG_PROG_FDT"\0" \
- "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
- "bootcmd_flash=run set_bootargs; " \
- "bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0" \
- "bootcmd=run bootcmd_flash\0"
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * yosemite.h - configuration for Yosemite & Yellowstone boards
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
-#ifndef CONFIG_YELLOWSTONE
-#define CONFIG_440EP 1 /* Specific PPC440EP support */
-#define CONFIG_HOSTNAME yosemite
-#else
-#define CONFIG_440GR 1 /* Specific PPC440GR support */
-#define CONFIG_HOSTNAME yellowstone
-#endif
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-#define CONFIG_BOARD_RESET 1 /* call board_reset() */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-/*Don't change either of these*/
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
-/*Don't change either of these*/
-
-#define CONFIG_SYS_USB_DEVICE 0x50000000
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
-#define CONFIG_SYS_BCSR_BASE (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000)
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#if 1
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
-#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */
-#define CONFIG_SYS_SDRAM_BANKS (2)
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
-#define CONFIG_ENV_OFFSET 0x0
-#endif /* CONFIG_ENV_IS_IN_EEPROM */
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_PPC_OLD \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "ramdisk_addr=fc180000\0" \
- ""
-
-#define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CONFIG_PHY1_ADDR 3
-
-/* Partitions */
-
-#ifdef CONFIG_440EP
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_PERIPHERAL_BASE | 0x1000)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-#define CONFIG_SUPPORT_VFAT
-#endif /* CONFIG_440EP */
-
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#else
-#define CONFIG_HW_WATCHDOG /* watchdog */
-#endif
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-
-#ifdef CONFIG_440EP
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CPLD 0x80000000
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x03017300
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000)
-
-/* Memory Bank 2 (CPLD) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x04814500
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD | 0x18000)
-
-#define CONFIG_SYS_BCSR5_PCI66EN 0x80
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * 1 january 2005 Alain Saurel <asaurel@amcc.com>
- * Adapted to current Das U-Boot source
- ***********************************************************************/
-/************************************************************************
- * yucca.h - configuration for AMCC 440SPe Ref (yucca)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_440SPE 1 /* Specifc SPe support */
-#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-#define EXTCLK_33_33 33333333
-#define EXTCLK_66_66 66666666
-#define EXTCLK_50 50000000
-#define EXTCLK_83 83333333
-
-#define CONFIG_SYS_TEXT_BASE 0xfffb0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME yucca
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#undef CONFIG_SHOW_BOOT_PROGRESS
-#undef CONFIG_STRESS
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
-#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
-
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
-
-#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
-#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
-#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
-
-#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
-#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
-#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
-#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
-#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
-#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000400000000ULL
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
-
-#define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */
-#define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
-
-/* #define CONFIG_SYS_NVRAM_BASE_ADDR 0x08000000 */
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-/* #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
-#define CONFIG_DDR_ECC 1 /* with ECC support */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-
-#define IIC0_BOOTPROM_ADDR 0x50
-#define IIC0_ALT_BOOTPROM_ADDR 0x54
-
-/* Don't probe these addrs */
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
-
-/* #if defined(CONFIG_CMD_EEPROM) */
-/* #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* #endif */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/* #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
-
-#undef CONFIG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
-#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_PPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=E7F10000\0" \
- "ramdisk_addr=E7F20000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:EP:EP\0" \
- ""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_ADDR0 0x5555
-#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
-
-#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */
-#define CONFIG_SYS_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR 0xfffa0000
-/* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
-#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-#undef CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-/* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */
-
-/*
- * NETWORK Support (PCI):
- */
-/* Support for Intel 82557/82559/82559ER chips. */
-#define CONFIG_EEPRO100
-
-/* FB Divisor selection */
-#define FPGA_FB_DIV_6 6
-#define FPGA_FB_DIV_10 10
-#define FPGA_FB_DIV_12 12
-#define FPGA_FB_DIV_20 20
-
-/* VCO Divisor selection */
-#define FPGA_VCO_DIV_4 4
-#define FPGA_VCO_DIV_6 6
-#define FPGA_VCO_DIV_8 8
-#define FPGA_VCO_DIV_10 10
-
-/*----------------------------------------------------------------------------+
-| FPGA registers and bit definitions
-+----------------------------------------------------------------------------*/
-/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
-/* TLB initialization makes it correspond to logical address 0xE2000000. */
-/* => Done init_chip.s in bootlib */
-#define FPGA_REG_BASE_ADDR 0xE2000000
-#define FPGA_GPIO_BASE_ADDR 0xE2010000
-#define FPGA_INT_BASE_ADDR 0xE2020000
-
-/*----------------------------------------------------------------------------+
-| Display
-+----------------------------------------------------------------------------*/
-#define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR
-
-#define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06)
-#define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04)
-#define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02)
-#define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00)
-/*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
-/*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/
-
-/*----------------------------------------------------------------------------+
-| ethernet/reset/boot Register 1
-+----------------------------------------------------------------------------*/
-#define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10)
-
-#define FPGA_REG10_10MHZ_ENABLE 0x8000
-#define FPGA_REG10_100MHZ_ENABLE 0x4000
-#define FPGA_REG10_GIGABIT_ENABLE 0x2000
-#define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/
-#define FPGA_REG10_RESET_ETH 0x0800
-#define FPGA_REG10_AUTO_NEG_DIS 0x0400
-#define FPGA_REG10_INTP_ETH 0x0200
-
-#define FPGA_REG10_RESET_HISR 0x0080
-#define FPGA_REG10_ENABLE_DISPLAY 0x0040
-#define FPGA_REG10_RESET_SDRAM 0x0020
-#define FPGA_REG10_OPER_BOOT 0x0010
-#define FPGA_REG10_SRAM_BOOT 0x0008
-#define FPGA_REG10_SMALL_BOOT 0x0004
-#define FPGA_REG10_FORCE_COLA 0x0002
-#define FPGA_REG10_COLA_MANUAL 0x0001
-
-#define FPGA_REG10_SDRAM_ENABLE 0x0020
-
-#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
-#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
-
-/*----------------------------------------------------------------------------+
-| MUX control
-+----------------------------------------------------------------------------*/
-#define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12)
-
-#define FPGA_REG12_EBC_CTL 0x8000
-#define FPGA_REG12_UART1_CTS_RTS 0x4000
-#define FPGA_REG12_UART0_RX_ENABLE 0x2000
-#define FPGA_REG12_UART1_RX_ENABLE 0x1000
-#define FPGA_REG12_UART2_RX_ENABLE 0x0800
-#define FPGA_REG12_EBC_OUT_ENABLE 0x0400
-#define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200
-#define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100
-#define FPGA_REG12_GPIO_SELECT 0x0010
-#define FPGA_REG12_GPIO_CHREG 0x0008
-#define FPGA_REG12_GPIO_CLK_CHREG 0x0004
-#define FPGA_REG12_GPIO_OETRI 0x0002
-#define FPGA_REG12_EBC_ERROR 0x0001
-
-/*----------------------------------------------------------------------------+
-| PCI Clock control
-+----------------------------------------------------------------------------*/
-#define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16)
-
-#define FPGA_REG16_PCI_CLK_CTL0 0x8000
-#define FPGA_REG16_PCI_CLK_CTL1 0x4000
-#define FPGA_REG16_PCI_CLK_CTL2 0x2000
-#define FPGA_REG16_PCI_CLK_CTL3 0x1000
-#define FPGA_REG16_PCI_CLK_CTL4 0x0800
-#define FPGA_REG16_PCI_CLK_CTL5 0x0400
-#define FPGA_REG16_PCI_CLK_CTL6 0x0200
-#define FPGA_REG16_PCI_CLK_CTL7 0x0100
-#define FPGA_REG16_PCI_CLK_CTL8 0x0080
-#define FPGA_REG16_PCI_CLK_CTL9 0x0040
-#define FPGA_REG16_PCI_EXT_ARB0 0x0020
-#define FPGA_REG16_PCI_MODE_1 0x0010
-#define FPGA_REG16_PCI_TARGET_MODE 0x0008
-#define FPGA_REG16_PCI_INTP_MODE 0x0004
-
-/* FB1 Divisor selection */
-#define FPGA_REG16_FB2_DIV_MASK 0x1000
-#define FPGA_REG16_FB2_DIV_LOW 0x0000
-#define FPGA_REG16_FB2_DIV_HIGH 0x1000
-/* FB2 Divisor selection */
-/* S3 switch on Board */
-#define FPGA_REG16_FB1_DIV_MASK 0x2000
-#define FPGA_REG16_FB1_DIV_LOW 0x0000
-#define FPGA_REG16_FB1_DIV_HIGH 0x2000
-/* PCI0 Clock Selection */
-/* S3 switch on Board */
-#define FPGA_REG16_PCI0_CLK_MASK 0x0c00
-#define FPGA_REG16_PCI0_CLK_33_33 0x0000
-#define FPGA_REG16_PCI0_CLK_66_66 0x0800
-#define FPGA_REG16_PCI0_CLK_100 0x0400
-#define FPGA_REG16_PCI0_CLK_133_33 0x0c00
-/* VCO Divisor selection */
-/* S3 switch on Board */
-#define FPGA_REG16_VCO_DIV_MASK 0xc000
-#define FPGA_REG16_VCO_DIV_4 0x0000
-#define FPGA_REG16_VCO_DIV_8 0x4000
-#define FPGA_REG16_VCO_DIV_6 0x8000
-#define FPGA_REG16_VCO_DIV_10 0xc000
-/* Master Clock Selection */
-/* S3, S4 switches on Board */
-#define FPGA_REG16_MASTER_CLK_MASK 0x01c0
-#define FPGA_REG16_MASTER_CLK_EXT 0x0000
-#define FPGA_REG16_MASTER_CLK_66_66 0x0040
-#define FPGA_REG16_MASTER_CLK_50 0x0080
-#define FPGA_REG16_MASTER_CLK_33_33 0x00c0
-#define FPGA_REG16_MASTER_CLK_25 0x0100
-
-/*----------------------------------------------------------------------------+
-| PCI Miscellaneous
-+----------------------------------------------------------------------------*/
-#define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18)
-
-#define FPGA_REG18_PCI_PRSNT1 0x8000
-#define FPGA_REG18_PCI_PRSNT2 0x4000
-#define FPGA_REG18_PCI_INTA 0x2000
-#define FPGA_REG18_PCI_SLOT0_INTP 0x1000
-#define FPGA_REG18_PCI_SLOT1_INTP 0x0800
-#define FPGA_REG18_PCI_SLOT2_INTP 0x0400
-#define FPGA_REG18_PCI_SLOT3_INTP 0x0200
-#define FPGA_REG18_PCI_PCI0_VC 0x0100
-#define FPGA_REG18_PCI_PCI0_VTH1 0x0080
-#define FPGA_REG18_PCI_PCI0_VTH2 0x0040
-#define FPGA_REG18_PCI_PCI0_VTH3 0x0020
-
-/*----------------------------------------------------------------------------+
-| PCIe Miscellaneous
-+----------------------------------------------------------------------------*/
-#define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A)
-
-#define FPGA_REG1A_PE0_GLED 0x8000
-#define FPGA_REG1A_PE1_GLED 0x4000
-#define FPGA_REG1A_PE2_GLED 0x2000
-#define FPGA_REG1A_PE0_YLED 0x1000
-#define FPGA_REG1A_PE1_YLED 0x0800
-#define FPGA_REG1A_PE2_YLED 0x0400
-#define FPGA_REG1A_PE0_PWRON 0x0200
-#define FPGA_REG1A_PE1_PWRON 0x0100
-#define FPGA_REG1A_PE2_PWRON 0x0080
-#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
-#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
-#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
-#define FPGA_REG1A_PE_SPREAD0 0x0008
-#define FPGA_REG1A_PE_SPREAD1 0x0004
-#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
-#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
-
-#define FPGA_REG1A_GLED_ENCODE(n) (FPGA_REG1A_PE0_GLED >> (n))
-#define FPGA_REG1A_YLED_ENCODE(n) (FPGA_REG1A_PE0_YLED >> (n))
-#define FPGA_REG1A_PWRON_ENCODE(n) (FPGA_REG1A_PE0_PWRON >> (n))
-#define FPGA_REG1A_REFCLK_ENCODE(n) (FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
-
-/*----------------------------------------------------------------------------+
-| PCIe Miscellaneous
-+----------------------------------------------------------------------------*/
-#define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C)
-
-#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
-#define FPGA_REG1C_PE1_ENDPOINT 0x4000
-#define FPGA_REG1C_PE2_ENDPOINT 0x2000
-#define FPGA_REG1C_PE0_PRSNT 0x1000
-#define FPGA_REG1C_PE1_PRSNT 0x0800
-#define FPGA_REG1C_PE2_PRSNT 0x0400
-#define FPGA_REG1C_PE0_WAKE 0x0080
-#define FPGA_REG1C_PE1_WAKE 0x0040
-#define FPGA_REG1C_PE2_WAKE 0x0020
-#define FPGA_REG1C_PE0_PERST 0x0010
-#define FPGA_REG1C_PE1_PERST 0x0008
-#define FPGA_REG1C_PE2_PERST 0x0004
-
-#define FPGA_REG1C_ROOTPOINT_ENCODE(n) (FPGA_REG1C_PE0_ROOTPOINT >> (n))
-#define FPGA_REG1C_PERST_ENCODE(n) (FPGA_REG1C_PE0_PERST >> (n))
-
-/*----------------------------------------------------------------------------+
-| Defines
-+----------------------------------------------------------------------------*/
-#define PERIOD_133_33MHZ 7500 /* 7,5ns */
-#define PERIOD_100_00MHZ 10000 /* 10ns */
-#define PERIOD_83_33MHZ 12000 /* 12ns */
-#define PERIOD_75_00MHZ 13333 /* 13,333ns */
-#define PERIOD_66_66MHZ 15000 /* 15ns */
-#define PERIOD_50_00MHZ 20000 /* 20ns */
-#define PERIOD_33_33MHZ 30000 /* 30ns */
-#define PERIOD_25_00MHZ 40000 /* 40ns */
-
-#endif /* __CONFIG_H */
#include <asm/immap_86xx.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \
offsetof(ccsr_pic_t, tfrr))
-
-#elif defined (CONFIG_4xx)
-#define _POST_WORD_ADDR \
- (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#endif
#ifndef _POST_WORD_ADDR
extern struct serial_device serial_scc_device;
extern struct serial_device *default_serial_console(void);
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_405EX) || defined(CONFIG_440) || \
- defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || \
defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
defined(CONFIG_MICROBLAZE)
* Prototypes from $(CPU)/cpu.c.
*/
-/* AMCC 4xx */
-#if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
- void reset_4xx_watchdog(void);
-#endif
-
#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
void hw_watchdog_init(void);
#endif
obj-y += drivers/
obj-$(CONFIG_PPC) += lib_powerpc/
obj-$(CONFIG_MPC83xx) += cpu/mpc83xx/
-obj-$(CONFIG_4xx) += cpu/ppc4xx/
-ifneq ($(filter lwmon5 pdm360ng,$(BOARD)),)
-obj-y += board/$(BOARD)/
-endif
+++ /dev/null
-#
-# (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
-#
-# Developed for DENX Software Engineering GmbH
-#
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o
+++ /dev/null
-/*
- * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
- *
- * Developed for DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include <post.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_DSP
-#include <asm/io.h>
-
-/* This test verifies DSP status bits in FPGA */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DSP_STATUS_REG 0xC4000008
-#define FPGA_STATUS_REG 0xC400000C
-
-int dsp_post_test(int flags)
-{
- uint old_value;
- uint read_value;
- int ret;
-
- /* momorize fpga status */
- old_value = in_be32((void *)FPGA_STATUS_REG);
- /* enable outputs */
- out_be32((void *)FPGA_STATUS_REG, 0x30);
-
- /* generate sync signal */
- out_be32((void *)DSP_STATUS_REG, 0x300);
- udelay(5);
- out_be32((void *)DSP_STATUS_REG, 0);
- udelay(500);
-
- /* read status */
- ret = 0;
- read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
- if (read_value != 0x03) {
- post_log("\nDSP status read %08X\n", read_value);
- ret = 1;
- }
-
- /* restore fpga status */
- out_be32((void *)FPGA_STATUS_REG, old_value);
-
- return ret;
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_DSP */
+++ /dev/null
-/*
- * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
- *
- * Developed for DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/* There are two tests for dsPIC currently implemented:
- * 1. dsPIC ready test. Done in board_early_init_f(). Only result verified here.
- * 2. dsPIC POST result test. This test gets dsPIC POST codes and version.
- */
-
-#include <post.h>
-
-#include <i2c.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DSPIC_POST_ERROR_REG 0x800
-#define DSPIC_SYS_ERROR_REG 0x802
-#define DSPIC_SYS_VERSION_REG 0x804
-#define DSPIC_FW_VERSION_REG 0x808
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
-
-/* Verify that dsPIC ready test done early at hw init passed ok */
-int dspic_init_post_test(int flags)
-{
- if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) &
- CONFIG_SYS_DSPIC_TEST_MASK) {
- post_log("dsPIC init test failed\n");
- return 1;
- }
-
- return 0;
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC1 */
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
-/* Read a register from the dsPIC. */
-int dspic_read(ushort reg, ushort *data)
-{
- uchar buf[sizeof(*data)];
- int rval;
-
- if (i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, 2, buf, 2))
- return -1;
- rval = i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, sizeof(reg),
- buf, sizeof(*data));
- *data = (buf[0] << 8) | buf[1];
-
- return rval;
-}
-
-/* Verify error codes regs, display version */
-int dspic_post_test(int flags)
-{
- ushort data;
- int ret = 0;
-
- post_log("\n");
-
- /* read dspic FW-Version */
- if (dspic_read(DSPIC_FW_VERSION_REG, &data)) {
- post_log("dsPIC: failed read FW-Version\n");
- ret = 1;
- } else {
- post_log("dsPIC FW-Version: %u.%u\n",
- (data >> 8) & 0xFF, data & 0xFF);
- }
-
- /* read dspic SYS-Version */
- if (dspic_read(DSPIC_SYS_VERSION_REG, &data)) {
- post_log("dsPIC: failed read version\n");
- ret = 1;
- } else {
- post_log("dsPIC SYS-Version: %u.%u\n",
- (data >> 8) & 0xFF, data & 0xFF);
- }
-
- /* read dspic POST error code */
- if (dspic_read(DSPIC_POST_ERROR_REG, &data)) {
- post_log("dsPIC: failed read POST code\n");
- ret = 1;
- } else {
- post_log("dsPIC POST-ERROR code: 0x%04X\n", data);
- }
-
- /* read dspic SYS error code */
- if ((data = dspic_read(DSPIC_SYS_ERROR_REG, &data))) {
- post_log("dsPIC: failed read system error\n");
- ret = 1;
- } else {
- post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
- }
-
- return ret;
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC2 */
+++ /dev/null
-/*
- * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
- *
- * Developed for DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-
-/* This test performs testing of FPGA SCRATCH register,
- * gets FPGA version and run get_ram_size() on FPGA memory
- */
-
-#include <post.h>
-#include <watchdog.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FPGA_SCRATCH_REG 0xC4000050
-#define FPGA_VERSION_REG 0xC4000040
-#define FPGA_RAM_START 0xC4200000
-#define FPGA_RAM_END 0xC4203FFF
-#define FPGA_STAT 0xC400000C
-#define FPGA_BUFFER 0x00800000
-#define FPGA_RAM_SIZE (FPGA_RAM_END - FPGA_RAM_START + 1)
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
-
-const static unsigned long pattern[] = {
- 0xffffffff,
- 0xaaaaaaaa,
- 0xcccccccc,
- 0xf0f0f0f0,
- 0xff00ff00,
- 0xffff0000,
- 0x0000ffff,
- 0x00ff00ff,
- 0x0f0f0f0f,
- 0x33333333,
- 0x55555555,
- 0x00000000,
-};
-
-const static unsigned long otherpattern = 0x01234567;
-
-static int one_scratch_test(uint value)
-{
- uint read_value;
- int ret = 0;
-
- out_be32((void *)FPGA_SCRATCH_REG, value);
- /* read other location (protect against data lines capacity) */
- ret = in_be16((void *)FPGA_VERSION_REG);
- /* verify test pattern */
- read_value = in_be32((void *)FPGA_SCRATCH_REG);
- if (read_value != value) {
- post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
- value, read_value);
- ret = -1;
- }
-
- return ret;
-}
-
-static int fpga_post_test1(ulong *start, ulong size, ulong val)
-{
- int ret = 0;
- ulong i = 0;
- ulong *mem = start;
- ulong readback;
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- mem[i] = val;
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- readback = mem[i];
- if (readback != val) {
- post_log("FPGA Memory error at %08x, "
- "wrote %08x, read %08x !\n",
- mem + i, val, readback);
- ret = -1;
- break;
- }
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
- return ret;
-}
-
-static int fpga_post_test2(ulong *start, ulong size)
-{
- int ret = 0;
- ulong i = 0;
- ulong *mem = start;
- ulong readback;
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- mem[i] = 1 << (i % 32);
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- readback = mem[i];
- if (readback != 1 << (i % 32)) {
- post_log("FPGA Memory error at %08x, "
- "wrote %08x, read %08x !\n",
- mem + i, 1 << (i % 32), readback);
- ret = -1;
- break;
- }
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- return ret;
-}
-
-static int fpga_post_test3(ulong *start, ulong size)
-{
- int ret = 0;
- ulong i = 0;
- ulong *mem = start;
- ulong readback;
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- mem[i] = i;
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- readback = mem[i];
- if (readback != i) {
- post_log("FPGA Memory error at %08x, "
- "wrote %08x, read %08x !\n",
- mem + i, i, readback);
- ret = -1;
- break;
- }
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- return ret;
-}
-
-static int fpga_post_test4(ulong *start, ulong size)
-{
- int ret = 0;
- ulong i = 0;
- ulong *mem = start;
- ulong readback;
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- mem[i] = ~i;
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- readback = mem[i];
- if (readback != ~i) {
- post_log("FPGA Memory error at %08x, "
- "wrote %08x, read %08x !\n",
- mem + i, ~i, readback);
- ret = -1;
- break;
- }
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- return ret;
-}
-
-/* FPGA Memory-pattern-test */
-static int fpga_mem_test(void)
-{
- int ret = 0;
- ulong* start = (ulong *)FPGA_RAM_START;
- ulong size = FPGA_RAM_SIZE;
-
- if (ret == 0)
- ret = fpga_post_test1(start, size, 0x00000000);
-
- if (ret == 0)
- ret = fpga_post_test1(start, size, 0xffffffff);
-
- if (ret == 0)
- ret = fpga_post_test1(start, size, 0x55555555);
-
- if (ret == 0)
- ret = fpga_post_test1(start, size, 0xaaaaaaaa);
-
- WATCHDOG_RESET();
-
- if (ret == 0)
- ret = fpga_post_test2(start, size);
-
- if (ret == 0)
- ret = fpga_post_test3(start, size);
-
- if (ret == 0)
- ret = fpga_post_test4(start, size);
-
- return ret;
-}
-
-/* Verify FPGA addresslines */
-static int fpga_post_addrline(ulong *address, ulong *base, ulong size)
-{
- unsigned long *target;
- unsigned long *end;
- unsigned long readback;
- unsigned long xor;
- int ret = 0;
-
- end = (ulong *)((ulong)base + size);
- xor = 0;
-
- for (xor = sizeof(ulong); xor > 0; xor <<= 1) {
- target = (ulong*)((ulong)address ^ xor);
- if ((target >= base) && (target < end)) {
- *address = ~*target;
- readback = *target;
-
- if (readback == *address) {
- post_log("Memory (address line) error at %08x"
- "XOR value %08x !\n",
- address, target, xor);
- ret = -1;
- break;
- }
- }
- }
-
- return ret;
-}
-
-/* Verify FPGA addresslines */
-static int fpga_post_dataline(ulong *address)
-{
- unsigned long temp32 = 0;
- int i = 0;
- int ret = 0;
-
- for (i = 0; i < ARRAY_SIZE(pattern); i++) {
- *address = pattern[i];
- /*
- * Put a different pattern on the data lines: otherwise they
- * may float long enough to read back what we wrote.
- */
- *(address + 1) = otherpattern;
- temp32 = *address;
-
- if (temp32 != pattern[i]){
- post_log("Memory (date line) error at %08x, "
- "wrote %08x, read %08x !\n",
- address, pattern[i], temp32);
- ret = 1;
- }
- }
-
- return ret;
-}
-
-/* Verify FPGA, get version & memory size */
-int fpga_post_test(int flags)
-{
- uint old_value;
- uint version;
- uint read_value;
- int ret = 0;
-
- post_log("\n");
- old_value = in_be32((void *)FPGA_SCRATCH_REG);
-
- if (one_scratch_test(0x55555555))
- ret = 1;
- if (one_scratch_test(0xAAAAAAAA))
- ret = 1;
-
- out_be32((void *)FPGA_SCRATCH_REG, old_value);
-
- version = in_be32((void *)FPGA_VERSION_REG);
- post_log("FPGA version %u.%u\n",
- (version >> 8) & 0xFF, version & 0xFF);
-
- /* Enable write to FPGA RAM */
- out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
-
- /* get RAM size */
- read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, FPGA_RAM_SIZE);
- post_log("FPGA RAM size %d bytes\n", read_value);
- WATCHDOG_RESET();
-
- /* copy fpga memory to DDR2 RAM*/
- memcpy((void *)FPGA_BUFFER,(void *)FPGA_RAM_START, FPGA_RAM_SIZE);
- WATCHDOG_RESET();
-
- /* Test datalines */
- if (fpga_post_dataline((ulong *)FPGA_RAM_START)) {
- ret = 1;
- goto out;
- }
- WATCHDOG_RESET();
-
- /* Test addresslines */
- if (fpga_post_addrline((ulong *)FPGA_RAM_START,
- (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
- ret = 1;
- goto out;
- }
- WATCHDOG_RESET();
- if (fpga_post_addrline((ulong *)FPGA_RAM_END - sizeof(long),
- (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
- ret = 1;
- goto out;
- }
- WATCHDOG_RESET();
-
- /* Memory Pattern Test */
- if (fpga_mem_test()) {
- ret = 1;
- goto out;
- }
- WATCHDOG_RESET();
-
- /* restore memory */
- memcpy((void *)FPGA_RAM_START,(void *)FPGA_BUFFER, FPGA_RAM_SIZE);
- WATCHDOG_RESET();
-
-out:
- /* Disable write to RAM */
- out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) & 0xEFFF);
- return ret;
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC3 */
+++ /dev/null
-/*
- * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
- *
- * Developed for DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-
-/* This test attempts to verify board GDC. A scratch register tested, then
- * simple memory test (get_ram_size()) run over GDC memory.
- */
-
-#include <post.h>
-#include <watchdog.h>
-#include <asm/io.h>
-#include <video.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define GDC_SCRATCH_REG 0xC1FF8044
-#define GDC_VERSION_REG 0xC1FF8084
-#define GDC_HOST_BASE 0xC1FC0000
-#define GDC_RAM_START 0xC0000000
-#define GDC_RAM_END (GDC_HOST_BASE - 1)
-#define GDC_RAM_SIZE (GDC_RAM_END - GDC_RAM_START)
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
-
-const static unsigned long pattern[] = {
- 0xffffffff,
- 0xaaaaaaaa,
- 0xcccccccc,
- 0xf0f0f0f0,
- 0xff00ff00,
- 0xffff0000,
- 0x0000ffff,
- 0x00ff00ff,
- 0x0f0f0f0f,
- 0x33333333,
- 0x55555555,
- 0x00000000
-};
-
-const static unsigned long otherpattern = 0x01234567;
-
-/* test write/read og a given LIME Register */
-static int gdc_test_reg_one(uint value)
-{
- uint read_value;
-
- /* write test pattern */
- out_be32((void *)GDC_SCRATCH_REG, value);
- /* read other location (protect against data lines capacity) */
- in_be32((void *)GDC_RAM_START);
- /* verify test pattern */
- read_value = in_be32((void *)GDC_SCRATCH_REG);
- if (read_value != value) {
- post_log("GDC SCRATCH test failed write %08X, read %08X\n",
- value, read_value);
- }
-
- return (read_value != value);
-}
-
-/* test with a given static 32 bit pattern in a given memory addressrange */
-static int gdc_post_test1(ulong *start, ulong size, ulong val)
-{
- int ret = 0;
- ulong i = 0;
- ulong *mem = start;
- ulong readback;
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- mem[i] = val;
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- readback = mem[i];
- if (readback != val) {
- post_log("GDC Memory error at %08x, "
- "wrote %08x, read %08x !\n",
- mem + i, val, readback);
- ret = -1;
- break;
- }
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- return ret;
-}
-
-/* test with dynamic 32 bit pattern in a given memory addressrange */
-static int gdc_post_test2(ulong *start, ulong size)
-{
- int ret = 0;
- ulong i = 0;
- ulong *mem = start;
- ulong readback;
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- mem[i] = 1 << (i % 32);
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- readback = mem[i];
- if (readback != 1 << (i % 32)) {
- post_log("GDC Memory error at %08x, "
- "wrote %08x, read %08x !\n",
- mem + i, 1 << (i % 32), readback);
- ret = -1;
- break;
- }
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- return ret;
-}
-
-/* test with dynamic 32 bit pattern in a given memory addressrange */
-static int gdc_post_test3(ulong *start, ulong size)
-{
- int ret = 0;
- ulong i = 0;
- ulong *mem = start;
- ulong readback;
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- mem[i] = i;
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- readback = mem[i];
- if (readback != i) {
- post_log("GDC Memory error at %08x, "
- "wrote %08x, read %08x !\n",
- mem + i, i, readback);
- ret = -1;
- break;
- }
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- return ret;
-}
-
-/* test with dynamic 32 bit pattern in a given memory addressrange */
-static int gdc_post_test4(ulong *start, ulong size)
-{
- int ret = 0;
- ulong i = 0;
- ulong *mem = start;
- ulong readback;
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- mem[i] = ~i;
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- for (i = 0; i < size / sizeof(ulong); i++) {
- readback = mem[i];
- if (readback != ~i) {
- post_log("GDC Memory error at %08x, "
- "wrote %08x, read %08x !\n",
- mem + i, ~i, readback);
- ret = -1;
- break;
- }
- if (i % 1024 == 0)
- WATCHDOG_RESET();
- }
-
- return ret;
-}
-
-/* do some patterntests in a given addressrange */
-int gdc_mem_test(ulong *start, ulong size)
-{
- int ret = 0;
-
- /*
- * check addressrange and do different static and dynamic
- * pattern tests with it.
- */
- if (((void *)start) + size <= (void *)GDC_RAM_END) {
- if (ret == 0)
- ret = gdc_post_test1(start, size, 0x00000000);
-
- if (ret == 0)
- ret = gdc_post_test1(start, size, 0xffffffff);
-
- if (ret == 0)
- ret = gdc_post_test1(start, size, 0x55555555);
-
- if (ret == 0)
- ret = gdc_post_test1(start, size, 0xaaaaaaaa);
-
- if (ret == 0)
- ret = gdc_post_test2(start, size);
-
- if (ret == 0)
- ret = gdc_post_test3(start, size);
-
- if (ret == 0)
- ret = gdc_post_test4(start, size);
- }
-
- return ret;
-}
-
-/* test function of gdc memory addresslines*/
-static int gdc_post_addrline(ulong *address, ulong *base, ulong size)
-{
- ulong *target;
- ulong *end;
- ulong readback = 0;
- ulong xor = 0;
- int ret = 0;
-
- end = (ulong *)((ulong)base + size);
-
- for (xor = sizeof(long); xor > 0; xor <<= 1) {
- target = (ulong *)((ulong)address ^ xor);
- if ((target >= base) && (target < end)) {
- *address = ~*target;
- readback = *target;
- }
-
- if (readback == *address) {
- post_log("GDC Memory (address line) error at %08x"
- "XOR value %08x !\n",
- address, target , xor);
- ret = -1;
- break;
- }
- }
-
- return ret;
-}
-
-static int gdc_post_dataline(ulong *address)
-{
- unsigned long temp32 = 0;
- int i = 0;
- int ret = 0;
-
- for (i = 0; i < ARRAY_SIZE(pattern); i++) {
- *address = pattern[i];
- /*
- * Put a different pattern on the data lines: otherwise they
- * may float long enough to read back what we wrote.
- */
- *(address + 1) = otherpattern;
- temp32 = *address;
-
- if (temp32 != pattern[i]){
- post_log("GDC Memory (date line) error at %08x, "
- "wrote %08x, read %08x !\n",
- address, pattern[i], temp32);
- ret = 1;
- }
- }
-
- return ret;
-}
-
-/* Verify GDC, get memory size, verify GDC memory */
-int gdc_post_test(int flags)
-{
- uint old_value;
- int i = 0;
- int ret = 0;
-
- post_log("\n");
- old_value = in_be32((void *)GDC_SCRATCH_REG);
-
- /*
- * GPIOC2 register behaviour: the LIME graphics processor has a
- * maximum of 5 GPIO ports that can be used in this hardware
- * configuration. Thus only the bits for these 5 GPIOs can be
- * activated in the GPIOC2 register. All other bits will always be
- * read as zero.
- */
- if (gdc_test_reg_one(0x00150015))
- ret = 1;
- if (gdc_test_reg_one(0x000A000A))
- ret = 1;
-
- out_be32((void *)GDC_SCRATCH_REG, old_value);
-
- old_value = in_be32((void *)GDC_VERSION_REG);
- post_log("GDC chip version %u.%u, year %04X\n",
- (old_value >> 8) & 0xFF, old_value & 0xFF,
- (old_value >> 16) & 0xFFFF);
-
- old_value = get_ram_size((void *)GDC_RAM_START,
- 0x02000000);
-
- debug("GDC RAM size (ist): %d bytes\n", old_value);
- debug("GDC RAM size (soll): %d bytes\n", GDC_RAM_SIZE);
- post_log("GDC RAM size: %d bytes\n", old_value);
-
- /* Test SDRAM datalines */
- if (gdc_post_dataline((ulong *)GDC_RAM_START)) {
- ret = 1;
- goto out;
- }
- WATCHDOG_RESET();
-
- /* Test SDRAM adresslines */
- if (gdc_post_addrline((ulong *)GDC_RAM_START,
- (ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
- ret = 1;
- goto out;
- }
- WATCHDOG_RESET();
- if (gdc_post_addrline((ulong *)GDC_RAM_END - sizeof(long),
- (ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
- ret = 1;
- goto out;
- }
- WATCHDOG_RESET();
-
- /* memory pattern test */
- debug("GDC Memory test (flags %8x:%8x)\n", flags,
- POST_SLOWTEST | POST_MANUAL);
-
- if (flags & POST_MANUAL) {
- debug("Full memory test\n");
- if (gdc_mem_test((ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
- ret = 1;
- goto out;
- }
- /* load splashscreen again */
- } else {
- debug("smart memory test\n");
- for (i = 0; i < (GDC_RAM_SIZE >> 20) && ret == 0; i++) {
- if (ret == 0)
- ret = gdc_mem_test((ulong *)(GDC_RAM_START +
- (i << 20)),
- 0x800);
- if (ret == 0)
- ret = gdc_mem_test((ulong *)(GDC_RAM_START +
- (i << 20) + 0xff800),
- 0x800);
- }
- }
- WATCHDOG_RESET();
-
-out:
- return ret;
-}
-#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC4 */
+++ /dev/null
-/*
- * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
- *
- * Developed for DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <post.h>
-#include <common.h>
-
-/*
- * SYSMON test
- *
- * This test performs the system hardware monitoring.
- * The test passes when all the following voltages and temperatures
- * are within allowed ranges:
- *
- * Temperature -40 .. +90 C
- * +5V +4.50 .. +5.50 V
- * +5V standby +3.50 .. +5.50 V
- *
- * LCD backlight is not enabled if temperature values are not within
- * allowed ranges (-30 .. + 80). The brightness of backlite can be
- * controlled by setting "brightness" environment variable. Default value is 50%
- *
- * See the list of all parameters in the sysmon_table below
- */
-
-#include <post.h>
-#include <watchdog.h>
-#include <i2c.h>
-
-#if defined(CONFIG_VIDEO)
-#include <mb862xx.h>
-#endif
-
-#if CONFIG_POST & CONFIG_SYS_POST_SYSMON
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* from dspic.c */
-extern int dspic_read(ushort reg, ushort *data);
-
-#define REG_TEMPERATURE 0x12BC
-#define REG_VOLTAGE_5V 0x12CA
-#define REG_VOLTAGE_5V_STANDBY 0x12C6
-
-#define TEMPERATURE_MIN (-40) /* degr. C */
-#define TEMPERATURE_MAX (+90) /* degr. C */
-#define TEMPERATURE_DISPLAY_MIN (-35) /* degr. C */
-#define TEMPERATURE_DISPLAY_MAX (+85) /* degr. C */
-
-#define VOLTAGE_5V_MIN (+4500) /* mV */
-#define VOLTAGE_5V_MAX (+5500) /* mV */
-
-#define VOLTAGE_5V_STANDBY_MIN (+3500) /* mV */
-#define VOLTAGE_5V_STANDBY_MAX (+5500) /* mV */
-
-typedef struct sysmon_s sysmon_t;
-typedef struct sysmon_table_s sysmon_table_t;
-
-static void sysmon_dspic_init(sysmon_t *this);
-static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val);
-static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val);
-static void sysmon_backlight_disable(sysmon_table_t *this);
-
-struct sysmon_s {
- uchar chip;
- void (*init)(sysmon_t *);
- int (*read)(sysmon_t *, uint, int *);
-};
-
-static sysmon_t sysmon_dspic = {
- CONFIG_SYS_I2C_DSPIC_IO_ADDR,
- sysmon_dspic_init,
- sysmon_dspic_read
-};
-
-static sysmon_t sysmon_dspic_sgn = {
- CONFIG_SYS_I2C_DSPIC_IO_ADDR,
- sysmon_dspic_init,
- sysmon_dspic_read_sgn
-};
-
-static sysmon_t *sysmon_list[] = {
- &sysmon_dspic,
- NULL
-};
-
-struct sysmon_table_s {
- char *name;
- char *unit_name;
- sysmon_t *sysmon;
- void (*exec_before)(sysmon_table_t *);
- void (*exec_after)(sysmon_table_t *);
-
- int unit_precision;
- int unit_div;
- int unit_min;
- int unit_max;
- uint val_mask;
- uint val_min;
- uint val_max;
- int val_valid;
- uint val_min_alt;
- uint val_max_alt;
- int val_valid_alt;
- uint addr;
-};
-
-static sysmon_table_t sysmon_table[] = {
- {
- "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
- 1, 1, -32768, 32767, 0xFFFF,
- 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
- 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
- REG_TEMPERATURE,
- },
-
- {
- "+ 5 V", "V", &sysmon_dspic, NULL, NULL,
- 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
- 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
- 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
- REG_VOLTAGE_5V,
- },
-
- {
- "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
- 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
- 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
- 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
- REG_VOLTAGE_5V_STANDBY,
- },
-
- {
- "Temperature", "°C", &sysmon_dspic_sgn, NULL, sysmon_backlight_disable,
- 1, 1, -32768, 32767, 0xFFFF,
- 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
- 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
- REG_TEMPERATURE,
- },
-};
-
-int sysmon_init_f(void)
-{
- sysmon_t **l;
-
- for (l = sysmon_list; *l; l++)
- (*l)->init(*l);
-
- return 0;
-}
-
-void sysmon_reloc(void)
-{
- /* Do nothing for now, sysmon_reloc() is required by the sysmon post */
-}
-
-static char *sysmon_unit_value(sysmon_table_t *s, uint val)
-{
- static char buf[32];
- char *p, sign;
- int decimal, frac;
- int unit_val;
-
- unit_val = s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask;
-
- if (val == -1)
- return "I/O ERROR";
-
- if (unit_val < 0) {
- sign = '-';
- unit_val = -unit_val;
- } else {
- sign = '+';
- }
-
- p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div);
-
- frac = unit_val % s->unit_div;
- frac /= (s->unit_div / s->unit_precision);
-
- decimal = s->unit_precision;
-
- if (decimal != 1)
- *p++ = '.';
- for (decimal /= 10; decimal != 0; decimal /= 10)
- *p++ = '0' + (frac / decimal) % 10;
- strcpy(p, s->unit_name);
-
- return buf;
-}
-
-static void sysmon_dspic_init(sysmon_t *this)
-{
-}
-
-static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val)
-{
- ushort data;
-
- if (dspic_read(addr, &data) == 0){
- /* To fit into the table range we should add 0x8000 */
- *val = data + 0x8000;
- return 0;
- }
-
- return -1;
-}
-
-static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val)
-{
- ushort data;
-
- if (dspic_read(addr, &data) == 0){
- /* To fit into the table range we should add 0x8000 */
- *val = (signed short)data + 0x8000;
- return 0;
- }
-
- return -1;
-}
-
-static void sysmon_backlight_disable(sysmon_table_t *this)
-{
-#if defined(CONFIG_VIDEO)
- board_backlight_switch(this->val_valid_alt);
-#endif
-}
-
-int sysmon_post_test(int flags)
-{
- int res = 0;
- sysmon_table_t * t;
- int val;
-
- for (t = sysmon_table; t < sysmon_table + ARRAY_SIZE(sysmon_table); t++) {
- t->val_valid = 1;
- if (t->exec_before)
- t->exec_before(t);
-
- if (t->sysmon->read(t->sysmon, t->addr, &val) != 0) {
- t->val_valid = 0;
- t->val_valid_alt = 0;
- post_log(": read failed\n");
- res = 1;
- break;
- }
-
- if (t->val_valid != 0) {
- t->val_valid = val >= t->val_min && val <= t->val_max;
- t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
- }
-
- if (t->exec_after)
- t->exec_after(t);
-
- if ((!t->val_valid) || (flags)) {
- post_log("\n\t%-17s = %-10s ", t->name, sysmon_unit_value(t, val));
- post_log("allowed range");
- post_log(" %-8s ..", sysmon_unit_value(t, t->val_min));
- post_log(" %-8s", sysmon_unit_value(t, t->val_max));
- post_log(" %s", t->val_valid ? "OK" : "FAIL");
- }
-
- if (!t->val_valid) {
- res = 1;
- break;
- }
- }
- post_log("\n");
-
- return res;
-}
-#endif /* CONFIG_POST & CONFIG_SYS_POST_SYSMON */
+++ /dev/null
-/*
- * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
- *
- * Developed for DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/* This test verifies if the reason of last reset was an abnormal voltage
- * condition, than it performs watchdog test, measuing time required to
- * trigger watchdog reset.
- */
-
-#include <post.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG
-
-#include <watchdog.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-
-static uint watchdog_magic_read(void)
-{
- return in_be32((void *)CONFIG_SYS_WATCHDOG_FLAGS_ADDR) &
- CONFIG_SYS_WATCHDOG_MAGIC_MASK;
-}
-
-static void watchdog_magic_write(uint value)
-{
- out_be32((void *)CONFIG_SYS_WATCHDOG_FLAGS_ADDR, value |
- (in_be32((void *)CONFIG_SYS_WATCHDOG_FLAGS_ADDR) &
- ~CONFIG_SYS_WATCHDOG_MAGIC_MASK));
-}
-
-int sysmon1_post_test(int flags)
-{
- if (gpio_read_in_bit(CONFIG_SYS_GPIO_SYSMON_STATUS) == 0) {
- /*
- * 3.1. GPIO62 is low
- * Assuming system voltage failure.
- */
- post_log("sysmon1 Abnormal voltage detected (GPIO62)\n");
- post_log("POST sysmon1 FAILED\n");
- return 1;
- } else {
- post_log("sysmon1 PASSED\n");
- }
-
- return 0;
-}
-
-int lwmon5_watchdog_post_test(int flags)
-{
- /* On each reset scratch register 1 should be tested,
- * but first test GPIO62:
- */
- if (!(flags & POST_MANUAL) && sysmon1_post_test(flags)) {
- /* 3.1. GPIO62 is low
- * Assuming system voltage failure.
- */
- /* 3.1.1. Set scratch register 1 to 0x0000xxxx */
- watchdog_magic_write(0);
- /* 3.1.2. Mark test as failed due to voltage?! */
- return 1;
- }
-
- if (watchdog_magic_read() != CONFIG_SYS_WATCHDOG_MAGIC) {
- /* 3.2. Scratch register 1 differs from magic value 0x1248xxxx
- * Assuming PowerOn
- */
- int ints;
- ulong base;
- ulong time;
-
- /* 3.2.1. Set magic value to scratch register */
- watchdog_magic_write(CONFIG_SYS_WATCHDOG_MAGIC);
-
- ints = disable_interrupts ();
- /* 3.2.2. strobe watchdog once */
- WATCHDOG_RESET();
- out_be32((void *)CONFIG_SYS_WATCHDOG_TIME_ADDR, 0);
- /* 3.2.3. save time of strobe in scratch register 2 */
- base = post_time_ms (0);
-
- /* 3.2.4. Wait for 150 ms (enough for reset to happen) */
- while ((time = post_time_ms (base)) < 150)
- out_be32((void *)CONFIG_SYS_WATCHDOG_TIME_ADDR, time);
- if (ints)
- enable_interrupts ();
-
- /* 3.2.5. Reset didn't happen. - Set 0x0000xxxx
- * into scratch register 1
- */
- watchdog_magic_write(0);
- /* 3.2.6. Mark test as failed. */
- post_log("hw watchdog time : %u ms, failed ", time);
- return 2;
- } else {
- /* 3.3. Scratch register matches magic value 0x1248xxxx
- * Assume this is watchdog-initiated reset
- */
- ulong time;
- /* 3.3.1. So, the test succeed, save measured time to syslog. */
- time = in_be32((void *)CONFIG_SYS_WATCHDOG_TIME_ADDR);
- if (time > 90 ) { /* ms*/
- post_log("hw watchdog time : %u ms, passed ", time);
- /* 3.3.2. Set scratch register 1 to 0x0000xxxx */
- watchdog_magic_write(0);
- return 0;
- } else {
- /*test minimum watchdogtime */
- post_log("hw watchdog time : %u ms, failed ", time);
- return 2;
- }
- }
- return -1;
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_WATCHDOG */
+++ /dev/null
-#
-# (C) Copyright 2002-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cache_4xx.o
-obj-y += cache.o
-obj-y += denali_ecc.o
-obj-y += ether.o
-obj-y += fpu.o
-obj-y += ocm.o
-obj-y += spr.o
-obj-y += uart.o
-obj-y += watchdog.o
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Author: Igor Lisitsin <igor@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/* Cache test
- *
- * This test verifies the CPU data and instruction cache using
- * several test scenarios.
- */
-
-#include <post.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_CACHE
-
-#include <asm/mmu.h>
-#include <watchdog.h>
-
-#define CACHE_POST_SIZE 1024
-
-int cache_post_test1 (int tlb, void *p, int size);
-int cache_post_test2 (int tlb, void *p, int size);
-int cache_post_test3 (int tlb, void *p, int size);
-int cache_post_test4 (int tlb, void *p, int size);
-int cache_post_test5 (int tlb, void *p, int size);
-int cache_post_test6 (int tlb, void *p, int size);
-
-#ifdef CONFIG_440
-static unsigned char testarea[CACHE_POST_SIZE]
-__attribute__((__aligned__(CACHE_POST_SIZE)));
-#endif
-
-int cache_post_test (int flags)
-{
- void *virt = (void *)CONFIG_SYS_POST_CACHE_ADDR;
- int ints;
- int res = 0;
- int tlb = -1; /* index to the victim TLB entry */
-
- /*
- * All 44x variants deal with cache management differently
- * because they have the address translation always enabled.
- * The 40x ppc's don't use address translation in U-Boot at all,
- * so we have to distinguish here between 40x and 44x.
- */
-#ifdef CONFIG_440
- int word0, i;
-
- /*
- * Allocate a new TLB entry, since we are going to modify
- * the write-through and caching inhibited storage attributes.
- */
- program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
- TLB_WORD2_I_ENABLE);
-
- /* Find the TLB entry */
- for (i = 0;; i++) {
- if (i >= PPC4XX_TLB_SIZE) {
- printf ("Failed to program tlb entry\n");
- return -1;
- }
- word0 = mftlb1(i);
- if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
- tlb = i;
- break;
- }
- }
-#endif
- ints = disable_interrupts ();
-
- WATCHDOG_RESET ();
- if (res == 0)
- res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
- WATCHDOG_RESET ();
- if (res == 0)
- res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
- WATCHDOG_RESET ();
- if (res == 0)
- res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
- WATCHDOG_RESET ();
- if (res == 0)
- res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
- WATCHDOG_RESET ();
- if (res == 0)
- res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
- WATCHDOG_RESET ();
- if (res == 0)
- res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
-
- if (ints)
- enable_interrupts ();
-
-#ifdef CONFIG_440
- remove_tlb((u32)virt, CACHE_POST_SIZE);
-#endif
-
- return res;
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Author: Igor Lisitsin <igor@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-#include <post.h>
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_CACHE
-
- .text
-
- /*
- * All 44x variants deal with cache management differently
- * because they have the address translation always enabled.
- * The 40x ppc's don't use address translation in U-Boot at all,
- * so we have to distinguish here between 40x and 44x.
- */
-#ifdef CONFIG_440
-/* void cache_post_disable (int tlb)
- */
-cache_post_disable:
- tlbre r0, r3, 0x0002
- ori r0, r0, TLB_WORD2_I_ENABLE@l
- tlbwe r0, r3, 0x0002
- sync
- isync
- blr
-
-/* void cache_post_wt (int tlb)
- */
-cache_post_wt:
- tlbre r0, r3, 0x0002
- ori r0, r0, TLB_WORD2_W_ENABLE@l
- andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
- tlbwe r0, r3, 0x0002
- sync
- isync
- blr
-
-/* void cache_post_wb (int tlb)
- */
-cache_post_wb:
- tlbre r0, r3, 0x0002
- andi. r0, r0, ~TLB_WORD2_W_ENABLE@l
- andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
- tlbwe r0, r3, 0x0002
- sync
- isync
- blr
-#else
-/* void cache_post_disable (int tlb)
- */
-cache_post_disable:
- lis r0, 0x0000
- ori r0, r0, 0x0000
- mtdccr r0
- sync
- isync
- blr
-
-/* void cache_post_wt (int tlb)
- */
-cache_post_wt:
- lis r0, 0x8000
- ori r0, r0, 0x0000
- mtdccr r0
- lis r0, 0x8000
- ori r0, r0, 0x0000
- mtdcwr r0
- sync
- isync
- blr
-
-/* void cache_post_wb (int tlb)
- */
-cache_post_wb:
- lis r0, 0x8000
- ori r0, r0, 0x0000
- mtdccr r0
- lis r0, 0x0000
- ori r0, r0, 0x0000
- mtdcwr r0
- sync
- isync
- blr
-#endif
-
-/* void cache_post_dinvalidate (void *p, int size)
- */
-cache_post_dinvalidate:
- dcbi r0, r3
- addi r3, r3, CONFIG_SYS_CACHELINE_SIZE
- subic. r4, r4, CONFIG_SYS_CACHELINE_SIZE
- bgt cache_post_dinvalidate
- sync
- blr
-
-/* void cache_post_dstore (void *p, int size)
- */
-cache_post_dstore:
- dcbst r0, r3
- addi r3, r3, CONFIG_SYS_CACHELINE_SIZE
- subic. r4, r4, CONFIG_SYS_CACHELINE_SIZE
- bgt cache_post_dstore
- sync
- blr
-
-/* void cache_post_dtouch (void *p, int size)
- */
-cache_post_dtouch:
- dcbt r0, r3
- addi r3, r3, CONFIG_SYS_CACHELINE_SIZE
- subic. r4, r4, CONFIG_SYS_CACHELINE_SIZE
- bgt cache_post_dtouch
- sync
- blr
-
-/* void cache_post_iinvalidate (void)
- */
-cache_post_iinvalidate:
- iccci r0, r0
- sync
- blr
-
-/* void cache_post_memset (void *p, int val, int size)
- */
-cache_post_memset:
- mtctr r5
-1:
- stb r4, 0(r3)
- addi r3, r3, 1
- bdnz 1b
- blr
-
-/* int cache_post_check (void *p, int size)
- */
-cache_post_check:
- mtctr r4
-1:
- lbz r0, 0(r3)
- addi r3, r3, 1
- cmpwi r0, 0xff
- bne 2f
- bdnz 1b
- li r3, 0
- blr
-2:
- li r3, -1
- blr
-
-#define CACHE_POST_DISABLE() \
- mr r3, r10; \
- bl cache_post_disable
-
-#define CACHE_POST_WT() \
- mr r3, r10; \
- bl cache_post_wt
-
-#define CACHE_POST_WB() \
- mr r3, r10; \
- bl cache_post_wb
-
-#define CACHE_POST_DINVALIDATE() \
- mr r3, r11; \
- mr r4, r12; \
- bl cache_post_dinvalidate
-
-#define CACHE_POST_DFLUSH() \
- mr r3, r11; \
- mr r4, r12; \
- bl cache_post_dflush
-
-#define CACHE_POST_DSTORE() \
- mr r3, r11; \
- mr r4, r12; \
- bl cache_post_dstore
-
-#define CACHE_POST_DTOUCH() \
- mr r3, r11; \
- mr r4, r12; \
- bl cache_post_dtouch
-
-#define CACHE_POST_IINVALIDATE() \
- bl cache_post_iinvalidate
-
-#define CACHE_POST_MEMSET(val) \
- mr r3, r11; \
- li r4, val; \
- mr r5, r12; \
- bl cache_post_memset
-
-#define CACHE_POST_CHECK() \
- mr r3, r11; \
- mr r4, r12; \
- bl cache_post_check; \
- mr r13, r3
-
-/*
- * Write and read 0xff pattern with caching enabled.
- */
- .global cache_post_test1
-cache_post_test1:
- mflr r9
- mr r10, r3 /* tlb */
- mr r11, r4 /* p */
- mr r12, r5 /* size */
-
- CACHE_POST_WB()
- CACHE_POST_DINVALIDATE()
-
- /* Write the negative pattern to the test area */
- CACHE_POST_MEMSET(0xff)
-
- /* Read the test area */
- CACHE_POST_CHECK()
-
- CACHE_POST_DINVALIDATE()
- CACHE_POST_DISABLE()
-
- mr r3, r13
- mtlr r9
- blr
-
-/*
- * Write zeroes with caching enabled.
- * Write 0xff pattern with caching disabled.
- * Read 0xff pattern with caching enabled.
- */
- .global cache_post_test2
-cache_post_test2:
- mflr r9
- mr r10, r3 /* tlb */
- mr r11, r4 /* p */
- mr r12, r5 /* size */
-
- CACHE_POST_WB()
- CACHE_POST_DINVALIDATE()
-
- /* Write the zero pattern to the test area */
- CACHE_POST_MEMSET(0)
-
- CACHE_POST_DINVALIDATE()
- CACHE_POST_DISABLE()
-
- /* Write the negative pattern to the test area */
- CACHE_POST_MEMSET(0xff)
-
- CACHE_POST_WB()
-
- /* Read the test area */
- CACHE_POST_CHECK()
-
- CACHE_POST_DINVALIDATE()
- CACHE_POST_DISABLE()
-
- mr r3, r13
- mtlr r9
- blr
-
-/*
- * Write-through mode test.
- * Write zeroes, store the cache, write 0xff pattern.
- * Invalidate the cache.
- * Check that 0xff pattern is read.
- */
- .global cache_post_test3
-cache_post_test3:
- mflr r9
- mr r10, r3 /* tlb */
- mr r11, r4 /* p */
- mr r12, r5 /* size */
-
- CACHE_POST_WT()
- CACHE_POST_DINVALIDATE()
-
- /* Cache the test area */
- CACHE_POST_DTOUCH()
-
- /* Write the zero pattern to the test area */
- CACHE_POST_MEMSET(0)
-
- CACHE_POST_DSTORE()
-
- /* Write the negative pattern to the test area */
- CACHE_POST_MEMSET(0xff)
-
- CACHE_POST_DINVALIDATE()
- CACHE_POST_DISABLE()
-
- /* Read the test area */
- CACHE_POST_CHECK()
-
- mr r3, r13
- mtlr r9
- blr
-
-/*
- * Write-back mode test.
- * Write 0xff pattern, store the cache, write zeroes.
- * Invalidate the cache.
- * Check that 0xff pattern is read.
- */
- .global cache_post_test4
-cache_post_test4:
- mflr r9
- mr r10, r3 /* tlb */
- mr r11, r4 /* p */
- mr r12, r5 /* size */
-
- CACHE_POST_WB()
- CACHE_POST_DINVALIDATE()
-
- /* Cache the test area */
- CACHE_POST_DTOUCH()
-
- /* Write the negative pattern to the test area */
- CACHE_POST_MEMSET(0xff)
-
- CACHE_POST_DSTORE()
-
- /* Write the zero pattern to the test area */
- CACHE_POST_MEMSET(0)
-
- CACHE_POST_DINVALIDATE()
- CACHE_POST_DISABLE()
-
- /* Read the test area */
- CACHE_POST_CHECK()
-
- mr r3, r13
- mtlr r9
- blr
-
-/*
- * Load the test instructions into the instruction cache.
- * Replace the test instructions.
- * Check that the original instructions are executed.
- */
- .global cache_post_test5
-cache_post_test5:
- mflr r9
- mr r10, r3 /* tlb */
- mr r11, r4 /* p */
- mr r12, r5 /* size */
-
- CACHE_POST_WT()
- CACHE_POST_IINVALIDATE()
-
- /* Compute r13 = cache_post_test_inst */
- bl cache_post_test5_reloc
-cache_post_test5_reloc:
- mflr r13
- lis r0, (cache_post_test_inst - cache_post_test5_reloc)@h
- ori r0, r0, (cache_post_test_inst - cache_post_test5_reloc)@l
- add r13, r13, r0
-
- /* Copy the test instructions to the test area */
- lwz r0, 0(r13)
- stw r0, 0(r11)
- lwz r0, 8(r13)
- stw r0, 4(r11)
- sync
-
- /* Invalidate the cache line */
- icbi r0, r11
- sync
- isync
-
- /* Execute the test instructions */
- mtlr r11
- blrl
-
- /* Replace the test instruction */
- lwz r0, 4(r13)
- stw r0, 0(r11)
- sync
-
- /* Do not invalidate the cache line */
- isync
-
- /* Execute the test instructions */
- mtlr r11
- blrl
- mr r13, r3
-
- CACHE_POST_IINVALIDATE()
- CACHE_POST_DINVALIDATE()
- CACHE_POST_DISABLE()
-
- mr r3, r13
- mtlr r9
- blr
-
-/*
- * Load the test instructions into the instruction cache.
- * Replace the test instructions and invalidate the cache.
- * Check that the replaced instructions are executed.
- */
- .global cache_post_test6
-cache_post_test6:
- mflr r9
- mr r10, r3 /* tlb */
- mr r11, r4 /* p */
- mr r12, r5 /* size */
-
- CACHE_POST_WT()
- CACHE_POST_IINVALIDATE()
-
- /* Compute r13 = cache_post_test_inst */
- bl cache_post_test6_reloc
-cache_post_test6_reloc:
- mflr r13
- lis r0, (cache_post_test_inst - cache_post_test6_reloc)@h
- ori r0, r0, (cache_post_test_inst - cache_post_test6_reloc)@l
- add r13, r13, r0
-
- /* Copy the test instructions to the test area */
- lwz r0, 4(r13)
- stw r0, 0(r11)
- lwz r0, 8(r13)
- stw r0, 4(r11)
- sync
-
- /* Invalidate the cache line */
- icbi r0, r11
- sync
- isync
-
- /* Execute the test instructions */
- mtlr r11
- blrl
-
- /* Replace the test instruction */
- lwz r0, 0(r13)
- stw r0, 0(r11)
- sync
-
- /* Invalidate the cache line */
- icbi r0, r11
- sync
- isync
-
- /* Execute the test instructions */
- mtlr r11
- blrl
- mr r13, r3
-
- CACHE_POST_IINVALIDATE()
- CACHE_POST_DINVALIDATE()
- CACHE_POST_DISABLE()
-
- mr r3, r13
- mtlr r9
- blr
-
-/* Test instructions.
- */
-cache_post_test_inst:
- li r3, 0
- li r3, -1
- blr
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Developed for DENX Software Engineering GmbH.
- *
- * Author: Pavel Kolesnikov <concord@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <watchdog.h>
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-#include <post.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_ECC
-
-/*
- * MEMORY ECC test
- *
- * This test performs the checks ECC facility of memory.
- */
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/ppc440.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(DEBUG)
-const static uint8_t syndrome_codes[] = {
- 0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
- 0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
- 0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
- 0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
- 0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
- 0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
- 0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
- 0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
- 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
-};
-#endif
-
-#define ECC_START_ADDR 0x10
-#define ECC_STOP_ADDR 0x2000
-#define ECC_PATTERN 0x01010101
-#define ECC_PATTERN_CORR 0x11010101
-#define ECC_PATTERN_UNCORR 0x61010101
-
-inline static void disable_ecc(void)
-{
- uint32_t value;
-
- sync(); /* Wait for any pending memory accesses to complete. */
- mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
- | DDR0_22_CTRL_RAW_ECC_DISABLE);
-}
-
-inline static void clear_and_enable_ecc(void)
-{
- uint32_t value;
-
- sync(); /* Wait for any pending memory accesses to complete. */
- mfsdram(DDR0_00, value);
- mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
- mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
- | DDR0_22_CTRL_RAW_ECC_ENABLE);
-}
-
-static uint32_t get_ecc_status(void)
-{
- uint32_t int_status;
-#if defined(DEBUG)
- uint8_t syndrome;
- uint32_t hdata, ldata, haddr, laddr;
- uint32_t value;
-#endif
-
- mfsdram(DDR0_00, int_status);
- int_status &= DDR0_00_INT_STATUS_MASK;
-
-#if defined(DEBUG)
- if (int_status & (DDR0_00_INT_STATUS_BIT0 | DDR0_00_INT_STATUS_BIT1)) {
- mfsdram(DDR0_32, laddr);
- mfsdram(DDR0_33, haddr);
- haddr &= 0x00000001;
- if (int_status & DDR0_00_INT_STATUS_BIT1)
- debug("Multiple accesses");
- else
- debug("A single access");
-
- debug(" outside the defined physical memory space detected\n"
- " addr = 0x%01x%08x\n", haddr, laddr);
- }
- if (int_status & (DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT3)) {
- unsigned int bit;
-
- mfsdram(DDR0_23, value);
- syndrome = (value >> 16) & 0xff;
- for (bit = 0; bit < sizeof(syndrome_codes); bit++)
- if (syndrome_codes[bit] == syndrome)
- break;
-
- mfsdram(DDR0_38, laddr);
- mfsdram(DDR0_39, haddr);
- haddr &= 0x00000001;
- mfsdram(DDR0_40, ldata);
- mfsdram(DDR0_41, hdata);
- if (int_status & DDR0_00_INT_STATUS_BIT3)
- debug("Multiple correctable ECC events");
- else
- debug("Single correctable ECC event");
-
- debug(" detected\n 0x%01x%08x - 0x%08x%08x, bit - %d\n",
- haddr, laddr, hdata, ldata, bit);
- }
- if (int_status & (DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT5)) {
- mfsdram(DDR0_23, value);
- syndrome = (value >> 8) & 0xff;
- mfsdram(DDR0_34, laddr);
- mfsdram(DDR0_35, haddr);
- haddr &= 0x00000001;
- mfsdram(DDR0_36, ldata);
- mfsdram(DDR0_37, hdata);
- if (int_status & DDR0_00_INT_STATUS_BIT5)
- debug("Multiple uncorrectable ECC events");
- else
- debug("Single uncorrectable ECC event");
-
- debug(" detected\n 0x%01x%08x - 0x%08x%08x, "
- "syndrome - 0x%02x\n",
- haddr, laddr, hdata, ldata, syndrome);
- }
- if (int_status & DDR0_00_INT_STATUS_BIT6)
- debug("DRAM initialization complete\n");
-#endif /* defined(DEBUG) */
-
- return int_status;
-}
-
-static int test_ecc(uint32_t ecc_addr)
-{
- uint32_t value;
- volatile uint32_t *const ecc_mem = (volatile uint32_t *)ecc_addr;
- int ret = 0;
-
- WATCHDOG_RESET();
-
- debug("Entering test_ecc(0x%08x)\n", ecc_addr);
- /* Set up correct ECC in memory */
- disable_ecc();
- clear_and_enable_ecc();
- out_be32(ecc_mem, ECC_PATTERN);
- out_be32(ecc_mem + 1, ECC_PATTERN);
- ppcDcbf((u32)ecc_mem);
-
- /* Verify no ECC error reading back */
- value = in_be32(ecc_mem);
- disable_ecc();
- if (ECC_PATTERN != value) {
- debug("Data read error (no-error case): "
- "expected 0x%08x, read 0x%08x\n", ECC_PATTERN, value);
- ret = 1;
- }
- value = get_ecc_status();
- if (0x00000000 != value) {
- /* Expected no ECC status reported */
- debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
- 0x00000000, value);
- ret = 1;
- }
-
- /* Test for correctable error by creating a one-bit error */
- out_be32(ecc_mem, ECC_PATTERN_CORR);
- ppcDcbf((u32)ecc_mem);
- clear_and_enable_ecc();
- value = in_be32(ecc_mem);
- disable_ecc();
- /* Test that the corrected data was read */
- if (ECC_PATTERN != value) {
- debug("Data read error (correctable-error case): "
- "expected 0x%08x, read 0x%08x\n", ECC_PATTERN, value);
- ret = 1;
- }
- value = get_ecc_status();
- if ((DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT7) != value) {
- /* Expected a single correctable error reported */
- debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
- DDR0_00_INT_STATUS_BIT2, value);
- ret = 1;
- }
-
- /* Test for uncorrectable error by creating a two-bit error */
- out_be32(ecc_mem, ECC_PATTERN_UNCORR);
- ppcDcbf((u32)ecc_mem);
- clear_and_enable_ecc();
- value = in_be32(ecc_mem);
- disable_ecc();
- /* Test that the corrected data was read */
- if (ECC_PATTERN_UNCORR != value) {
- debug("Data read error (uncorrectable-error case): "
- "expected 0x%08x, read 0x%08x\n", ECC_PATTERN_UNCORR,
- value);
- ret = 1;
- }
- value = get_ecc_status();
- if ((DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT7) != value) {
- /* Expected a single uncorrectable error reported */
- debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
- DDR0_00_INT_STATUS_BIT4, value);
- ret = 1;
- }
-
- /* Remove error from SDRAM and enable ECC. */
- out_be32(ecc_mem, ECC_PATTERN);
- ppcDcbf((u32)ecc_mem);
- clear_and_enable_ecc();
-
- return ret;
-}
-
-int ecc_post_test(int flags)
-{
- int ret = 0;
- uint32_t value;
- uint32_t iaddr;
-
- mfsdram(DDR0_22, value);
- if (0x3 != DDR0_22_CTRL_RAW_DECODE(value)) {
- debug("SDRAM ECC not enabled, skipping ECC POST.\n");
- return 0;
- }
-
- /* Mask all interrupts. */
- mfsdram(DDR0_01, value);
- mtsdram(DDR0_01, (value & ~DDR0_01_INT_MASK_MASK)
- | DDR0_01_INT_MASK_ALL_OFF);
-
- for (iaddr = ECC_START_ADDR; iaddr <= ECC_STOP_ADDR; iaddr += iaddr) {
- ret = test_ecc(iaddr);
- if (ret)
- break;
- }
- /*
- * Clear possible errors resulting from ECC testing. (If not done, we
- * we could get an interrupt later on when exceptions are enabled.)
- */
- set_mcsr(get_mcsr());
- debug("ecc_post_test() returning %d\n", ret);
- return ret;
-}
-#endif /* CONFIG_POST & CONFIG_SYS_POST_ECC */
-#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Author: Igor Lisitsin <igor@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/*
- * Ethernet test
- *
- * The Ethernet Media Access Controllers (EMAC) are tested in the
- * internal loopback mode.
- * The controllers are configured accordingly and several packets
- * are transmitted. The configurable test parameters are:
- * MIN_PACKET_LENGTH - minimum size of packet to transmit
- * MAX_PACKET_LENGTH - maximum size of packet to transmit
- * CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
- * is tested with a different frame length. Starting with
- * MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
- * Defaults to 10 and can be overridden in the board config header.
- */
-
-#include <post.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_ETHER
-
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-mal.h>
-#include <asm/ppc4xx-emac.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Get count of EMAC devices (doesn't have to be the max. possible number
- * supported by the cpu)
- *
- * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
- * EMAC count is possible. As it is needed for the Kilauea/Haleakala
- * 405EX/405EXr eval board, using the same binary.
- */
-#if defined(CONFIG_BOARD_EMAC_COUNT)
-#define LAST_EMAC_NUM board_emac_count()
-#else /* CONFIG_BOARD_EMAC_COUNT */
-#if defined(CONFIG_HAS_ETH3)
-#define LAST_EMAC_NUM 4
-#elif defined(CONFIG_HAS_ETH2)
-#define LAST_EMAC_NUM 3
-#elif defined(CONFIG_HAS_ETH1)
-#define LAST_EMAC_NUM 2
-#else
-#define LAST_EMAC_NUM 1
-#endif
-#endif /* CONFIG_BOARD_EMAC_COUNT */
-
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
-#endif
-
-#define MIN_PACKET_LENGTH 64
-#define MAX_PACKET_LENGTH 1514
-#ifndef CONFIG_SYS_POST_ETH_LOOPS
-#define CONFIG_SYS_POST_ETH_LOOPS 10
-#endif
-#define PACKET_INCR ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
- CONFIG_SYS_POST_ETH_LOOPS)
-
-static volatile mal_desc_t tx __cacheline_aligned;
-static volatile mal_desc_t rx __cacheline_aligned;
-static char *tx_buf;
-static char *rx_buf;
-
-int board_emac_count(void);
-
-static void ether_post_init (int devnum, int hw_addr)
-{
- int i;
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
- unsigned mode_reg;
- sys_info_t sysinfo;
-#endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
- unsigned long mfr;
-#endif
-
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
- /* Need to get the OPB frequency so we can access the PHY */
- get_sys_info (&sysinfo);
-#endif
-
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
- /* provide clocks for EMAC internal loopback */
- mfsdr (SDR0_MFR, mfr);
- mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
- mtsdr (SDR0_MFR, mfr);
- sync ();
-#endif
- /* reset emac */
- out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
- sync ();
-
- for (i = 0;; i++) {
- if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST))
- break;
- if (i >= 1000) {
- printf ("Timeout resetting EMAC\n");
- break;
- }
- udelay (1000);
- }
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
- /* Whack the M1 register */
- mode_reg = 0x0;
- if (sysinfo.freqOPB <= 50000000);
- else if (sysinfo.freqOPB <= 66666667)
- mode_reg |= EMAC_MR1_OBCI_66;
- else if (sysinfo.freqOPB <= 83333333)
- mode_reg |= EMAC_MR1_OBCI_83;
- else if (sysinfo.freqOPB <= 100000000)
- mode_reg |= EMAC_MR1_OBCI_100;
- else
- mode_reg |= EMAC_MR1_OBCI_GT100;
-
- out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg);
-
-#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
-
- /* set the Mal configuration reg */
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
- mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
- MAL_CR_PLBLT_DEFAULT | 0x00330000);
-#else
- mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
- /* Errata 1.12: MAL_1 -- Disable MAL bursting */
- if (get_pvr() == PVR_440GP_RB) {
- mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
- }
-#endif
- /* setup buffer descriptors */
- tx.ctrl = MAL_TX_CTRL_WRAP;
- tx.data_len = 0;
- tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
-
- rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
- rx.data_len = 0;
- rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
- flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
- flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
-
- switch (devnum) {
- case 1:
- /* setup MAL tx & rx channel pointers */
-#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
- mtdcr (MAL0_TXCTP2R, &tx);
-#else
- mtdcr (MAL0_TXCTP1R, &tx);
-#endif
-#if defined(CONFIG_440)
- mtdcr (MAL0_TXBADDR, 0x0);
- mtdcr (MAL0_RXBADDR, 0x0);
-#endif
- mtdcr (MAL0_RXCTP1R, &rx);
- /* set RX buffer size */
- mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16);
- break;
- case 0:
- default:
- /* setup MAL tx & rx channel pointers */
-#if defined(CONFIG_440)
- mtdcr (MAL0_TXBADDR, 0x0);
- mtdcr (MAL0_RXBADDR, 0x0);
-#endif
- mtdcr (MAL0_TXCTP0R, &tx);
- mtdcr (MAL0_RXCTP0R, &rx);
- /* set RX buffer size */
- mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16);
- break;
- }
-
- /* Enable MAL transmit and receive channels */
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2)));
-#else
- mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum));
-#endif
- mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum));
-
- /* set internal loopback mode */
-#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
- out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 |
- EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
- EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
- in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
-#else
- out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE |
- EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
- EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
- in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
-#endif
-
- /* set transmit enable & receive enable */
- out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE);
-
- /* enable broadcast address */
- out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE);
-
- /* set transmit request threshold register */
- out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */
-
- /* set receive low/high water mark register */
-#if defined(CONFIG_440)
- /* 440s has a 64 byte burst length */
- out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000);
-#else
- /* 405s have a 16 byte burst length */
- out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
-#endif /* defined(CONFIG_440) */
- out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000);
-
- /* Set fifo limit entry in tx mode 0 */
- out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003);
- /* Frame gap set */
- out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008);
- sync ();
-}
-
-static void ether_post_halt (int devnum, int hw_addr)
-{
- int i = 0;
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
- unsigned long mfr;
-#endif
-
- /* 1st reset MAL channel */
- /* Note: writing a 0 to a channel has no effect */
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2));
-#else
- mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum);
-#endif
- mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum);
-
- /* wait for reset */
- while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) {
- if (i++ >= 1000)
- break;
- udelay (1000);
- }
- /* emac reset */
- out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
-
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
- /* remove clocks for EMAC internal loopback */
- mfsdr (SDR0_MFR, mfr);
- mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
- mtsdr (SDR0_MFR, mfr);
-#endif
-}
-
-static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
-{
- int i = 0;
-
- while (tx.ctrl & MAL_TX_CTRL_READY) {
- if (i++ > 100) {
- printf ("TX timeout\n");
- return;
- }
- udelay (1000);
- invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
- }
- tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
- EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
- tx.data_len = length;
- memcpy (tx.data_ptr, packet, length);
- flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
- flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
- sync ();
-
- out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0);
- sync ();
-}
-
-static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
-{
- int length;
- int i = 0;
-
- while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
- if (i++ > 100) {
- printf ("RX timeout\n");
- return 0;
- }
- udelay (1000);
- invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
- }
- length = rx.data_len - 4;
- if (length <= max_length) {
- invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
- memcpy(packet, rx.data_ptr, length);
- }
- sync ();
-
- rx.ctrl |= MAL_RX_CTRL_EMPTY;
- flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
- sync ();
-
- return length;
-}
-
- /*
- * Test routines
- */
-
-static void packet_fill (char *packet, int length)
-{
- char c = (char) length;
- int i;
-
- /* set up ethernet header */
- memset (packet, 0xff, 14);
-
- for (i = 14; i < length; i++) {
- packet[i] = c++;
- }
-}
-
-static int packet_check (char *packet, int length)
-{
- char c = (char) length;
- int i;
-
- for (i = 14; i < length; i++) {
- if (packet[i] != c++)
- return -1;
- }
-
- return 0;
-}
-
- char packet_send[MAX_PACKET_LENGTH];
- char packet_recv[MAX_PACKET_LENGTH];
-static int test_ctlr (int devnum, int hw_addr)
-{
- int res = -1;
- int length;
- int l;
-
- ether_post_init (devnum, hw_addr);
-
- for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH;
- l -= PACKET_INCR) {
- packet_fill (packet_send, l);
-
- ether_post_send (devnum, hw_addr, packet_send, l);
-
- length = ether_post_recv (devnum, hw_addr, packet_recv,
- sizeof (packet_recv));
-
- if (length != l || packet_check (packet_recv, length) < 0) {
- goto Done;
- }
- }
-
- res = 0;
-
-Done:
-
- ether_post_halt (devnum, hw_addr);
-
- if (res != 0) {
- post_log ("EMAC%d test failed\n", devnum);
- }
-
- return res;
-}
-
-int ether_post_test (int flags)
-{
- int res = 0;
- int i;
-
- /* Allocate tx & rx packet buffers */
- tx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
- rx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
-
- if (!tx_buf || !rx_buf) {
- printf ("Failed to allocate packet buffers\n");
- res = -1;
- goto out_free;
- }
-
- for (i = 0; i < LAST_EMAC_NUM; i++) {
- if (test_ctlr (i, i*0x100))
- res = -1;
- }
-
-out_free:
- free (tx_buf);
- free (rx_buf);
-
- return res;
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Author: Sergei Poselenov <sposelenov@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-#if defined(CONFIG_440EP) || \
- defined(CONFIG_440EPX)
-
-#include <asm/processor.h>
-#include <asm/ppc4xx.h>
-
-
-int fpu_status(void)
-{
- if (mfspr(SPRN_CCR0) & CCR0_DAPUIB)
- return 0; /* Disabled */
- else
- return 1; /* Enabled */
-}
-
-
-void fpu_disable(void)
-{
- mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) | CCR0_DAPUIB);
- mtmsr(mfmsr() & ~MSR_FP);
-}
-
-
-void fpu_enable(void)
-{
- mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) & ~CCR0_DAPUIB);
- mtmsr(mfmsr() | MSR_FP);
-}
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2008 Ilya Yanok, EmCraft Systems, yanok@emcraft.com
- *
- * Developed for DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-
-/*
- * This test attempts to verify on-chip memory (OCM). Result is written
- * to the scratch register and if test succeed it won't be run till next
- * power on.
- */
-
-#include <post.h>
-
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define OCM_TEST_PATTERN1 0x55555555
-#define OCM_TEST_PATTERN2 0xAAAAAAAA
-
-#if CONFIG_POST & CONFIG_SYS_POST_OCM
-
-static uint ocm_status_read(void)
-{
- return in_be32((void *)CONFIG_SYS_OCM_STATUS_ADDR) &
- CONFIG_SYS_OCM_STATUS_MASK;
-}
-
-static void ocm_status_write(uint value)
-{
- out_be32((void *)CONFIG_SYS_OCM_STATUS_ADDR, value |
- (in_be32((void *)CONFIG_SYS_OCM_STATUS_ADDR) &
- ~CONFIG_SYS_OCM_STATUS_MASK));
-}
-
-static inline int ocm_test_word(uint value, uint *address)
-{
- uint read_value;
-
- *address = value;
- sync();
- read_value = *address;
-
- return (read_value != value);
-}
-
-int ocm_post_test(int flags)
-{
- uint old_value;
- int ret = 0;
- uint *address = (uint*)CONFIG_SYS_OCM_BASE;
-
- if (ocm_status_read() == CONFIG_SYS_OCM_STATUS_OK)
- return 0;
- for (; address < (uint*)(CONFIG_SYS_OCM_BASE + CONFIG_SYS_OCM_SIZE); address++) {
- old_value = *address;
- if (ocm_test_word(OCM_TEST_PATTERN1, address) ||
- ocm_test_word(OCM_TEST_PATTERN2, address)) {
- ret = 1;
- *address = old_value;
- printf("OCM POST failed at %p!\n", address);
- break;
- }
- *address = old_value;
- }
- ocm_status_write(ret ? CONFIG_SYS_OCM_STATUS_FAIL : CONFIG_SYS_OCM_STATUS_OK);
- return ret;
-}
-#endif /* CONFIG_POST & CONFIG_SYS_POST_OCM */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Author: Igor Lisitsin <igor@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/*
- * SPR test
- *
- * The test checks the contents of Special Purpose Registers (SPR) listed
- * in the spr_test_list array below.
- * Each SPR value is read using mfspr instruction, some bits are masked
- * according to the table and the resulting value is compared to the
- * corresponding table value.
- */
-
-#include <post.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_SPR
-
-#include <asm/processor.h>
-
-#ifdef CONFIG_4xx_DCACHE
-#include <asm/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-static struct {
- int number;
- char * name;
- unsigned long mask;
- unsigned long value;
-} spr_test_list [] = {
- /* Standard Special-Purpose Registers */
-
- {0x001, "XER", 0x00000000, 0x00000000},
- {0x008, "LR", 0x00000000, 0x00000000},
- {0x009, "CTR", 0x00000000, 0x00000000},
- {0x016, "DEC", 0x00000000, 0x00000000},
- {0x01a, "SRR0", 0x00000000, 0x00000000},
- {0x01b, "SRR1", 0x00000000, 0x00000000},
- {0x110, "SPRG0", 0x00000000, 0x00000000},
- {0x111, "SPRG1", 0x00000000, 0x00000000},
- {0x112, "SPRG2", 0x00000000, 0x00000000},
- {0x113, "SPRG3", 0x00000000, 0x00000000},
- {0x11f, "PVR", 0x00000000, 0x00000000},
-
- /* Additional Special-Purpose Registers.
- * The values must match the initialization
- * values from arch/powerpc/cpu/ppc4xx/start.S
- */
- {0x30, "PID", 0x00000000, 0x00000000},
- {0x3a, "CSRR0", 0x00000000, 0x00000000},
- {0x3b, "CSRR1", 0x00000000, 0x00000000},
- {0x3d, "DEAR", 0x00000000, 0x00000000},
- {0x3e, "ESR", 0x00000000, 0x00000000},
-#ifdef CONFIG_440
- {0x3f, "IVPR", 0xffff0000, 0x00000000},
-#endif
- {0x100, "USPRG0", 0x00000000, 0x00000000},
- {0x104, "SPRG4", 0x00000000, 0x00000000},
- {0x105, "SPRG5", 0x00000000, 0x00000000},
- {0x106, "SPRG6", 0x00000000, 0x00000000},
- {0x107, "SPRG7", 0x00000000, 0x00000000},
- {0x10c, "TBL", 0x00000000, 0x00000000},
- {0x10d, "TBU", 0x00000000, 0x00000000},
-#ifdef CONFIG_440
- {0x11e, "PIR", 0x0000000f, 0x00000000},
-#endif
- {0x130, "DBSR", 0x00000000, 0x00000000},
- {0x134, "DBCR0", 0x00000000, 0x00000000},
- {0x135, "DBCR1", 0x00000000, 0x00000000},
- {0x136, "DBCR2", 0x00000000, 0x00000000},
- {0x138, "IAC1", 0x00000000, 0x00000000},
- {0x139, "IAC2", 0x00000000, 0x00000000},
- {0x13a, "IAC3", 0x00000000, 0x00000000},
- {0x13b, "IAC4", 0x00000000, 0x00000000},
- {0x13c, "DAC1", 0x00000000, 0x00000000},
- {0x13d, "DAC2", 0x00000000, 0x00000000},
- {0x13e, "DVC1", 0x00000000, 0x00000000},
- {0x13f, "DVC2", 0x00000000, 0x00000000},
- {0x150, "TSR", 0x00000000, 0x00000000},
- {0x154, "TCR", 0x00000000, 0x00000000},
-#ifdef CONFIG_440
- {0x190, "IVOR0", 0x0000fff0, 0x00000100},
- {0x191, "IVOR1", 0x0000fff0, 0x00000200},
- {0x192, "IVOR2", 0x0000fff0, 0x00000300},
- {0x193, "IVOR3", 0x0000fff0, 0x00000400},
- {0x194, "IVOR4", 0x0000fff0, 0x00000500},
- {0x195, "IVOR5", 0x0000fff0, 0x00000600},
- {0x196, "IVOR6", 0x0000fff0, 0x00000700},
- {0x197, "IVOR7", 0x0000fff0, 0x00000800},
- {0x198, "IVOR8", 0x0000fff0, 0x00000c00},
- {0x199, "IVOR9", 0x00000000, 0x00000000},
- {0x19a, "IVOR10", 0x0000fff0, 0x00000900},
- {0x19b, "IVOR11", 0x00000000, 0x00000000},
- {0x19c, "IVOR12", 0x00000000, 0x00000000},
- {0x19d, "IVOR13", 0x0000fff0, 0x00001300},
- {0x19e, "IVOR14", 0x0000fff0, 0x00001400},
- {0x19f, "IVOR15", 0x0000fff0, 0x00002000},
-#endif
- {0x23a, "MCSRR0", 0x00000000, 0x00000000},
- {0x23b, "MCSRR1", 0x00000000, 0x00000000},
- {0x23c, "MCSR", 0x00000000, 0x00000000},
- {0x370, "INV0", 0x00000000, 0x00000000},
- {0x371, "INV1", 0x00000000, 0x00000000},
- {0x372, "INV2", 0x00000000, 0x00000000},
- {0x373, "INV3", 0x00000000, 0x00000000},
- {0x374, "ITV0", 0x00000000, 0x00000000},
- {0x375, "ITV1", 0x00000000, 0x00000000},
- {0x376, "ITV2", 0x00000000, 0x00000000},
- {0x377, "ITV3", 0x00000000, 0x00000000},
- {0x378, "CCR1", 0x00000000, 0x00000000},
- {0x390, "DNV0", 0x00000000, 0x00000000},
- {0x391, "DNV1", 0x00000000, 0x00000000},
- {0x392, "DNV2", 0x00000000, 0x00000000},
- {0x393, "DNV3", 0x00000000, 0x00000000},
- {0x394, "DTV0", 0x00000000, 0x00000000},
- {0x395, "DTV1", 0x00000000, 0x00000000},
- {0x396, "DTV2", 0x00000000, 0x00000000},
- {0x397, "DTV3", 0x00000000, 0x00000000},
-#ifdef CONFIG_440
- {0x398, "DVLIM", 0x0fc1f83f, 0x0001f800},
- {0x399, "IVLIM", 0x0fc1f83f, 0x0001f800},
-#endif
- {0x39b, "RSTCFG", 0x00000000, 0x00000000},
- {0x39c, "DCDBTRL", 0x00000000, 0x00000000},
- {0x39d, "DCDBTRH", 0x00000000, 0x00000000},
- {0x39e, "ICDBTRL", 0x00000000, 0x00000000},
- {0x39f, "ICDBTRH", 0x00000000, 0x00000000},
- {0x3b2, "MMUCR", 0x00000000, 0x00000000},
- {0x3b3, "CCR0", 0x00000000, 0x00000000},
- {0x3d3, "ICDBDR", 0x00000000, 0x00000000},
- {0x3f3, "DBDR", 0x00000000, 0x00000000},
-};
-
-static int spr_test_list_size = ARRAY_SIZE(spr_test_list);
-
-int spr_post_test (int flags)
-{
- int ret = 0;
- int i;
-
- unsigned long code[] = {
- 0x7c6002a6, /* mfspr r3,SPR */
- 0x4e800020 /* blr */
- };
- unsigned long (*get_spr) (void) = (void *) code;
-
-#ifdef CONFIG_4xx_DCACHE
- /* disable cache */
- change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
-#endif
- for (i = 0; i < spr_test_list_size; i++) {
- int num = spr_test_list[i].number;
-
- /* mfspr r3,num */
- code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
-
- asm volatile ("isync");
-
- if ((get_spr () & spr_test_list[i].mask) !=
- (spr_test_list[i].value & spr_test_list[i].mask)) {
- post_log ("The value of %s special register "
- "is incorrect: 0x%08X\n",
- spr_test_list[i].name, get_spr ());
- ret = -1;
- }
- }
-#ifdef CONFIG_4xx_DCACHE
- /* enable cache */
- change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
-#endif
-
- return ret;
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Author: Igor Lisitsin <igor@emcraft.com>
- *
- * Copyright 2010, Stefan Roese, DENX Software Engineering, sr@denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <serial.h>
-
-/*
- * UART test
- *
- * The controllers are configured to loopback mode and several
- * characters are transmitted.
- */
-
-#include <post.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_UART
-
-/*
- * This table defines the UART's that should be tested and can
- * be overridden in the board config file
- */
-#ifndef CONFIG_SYS_POST_UART_TABLE
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
- CONFIG_SYS_NS16550_COM2, CONFIG_SYS_NS16550_COM3, \
- CONFIG_SYS_NS16550_COM4 }
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int test_ctlr (struct NS16550 *com_port, int index)
-{
- int res = -1;
- char test_str[] = "*** UART Test String ***\r\n";
- int i;
- int divisor;
-
- divisor = (get_serial_clock() + (gd->baudrate * (16 / 2))) /
- (16 * gd->baudrate);
- NS16550_init(com_port, divisor);
-
- /*
- * Set internal loopback mode in UART
- */
- out_8(&com_port->mcr, in_8(&com_port->mcr) | UART_MCR_LOOP);
-
- /* Reset FIFOs */
- out_8(&com_port->fcr, UART_FCR_RXSR | UART_FCR_TXSR);
- udelay(100);
-
- /* Flush RX-FIFO */
- while (NS16550_tstc(com_port))
- NS16550_getc(com_port);
-
- for (i = 0; i < sizeof (test_str) - 1; i++) {
- NS16550_putc(com_port, test_str[i]);
- if (NS16550_getc(com_port) != test_str[i])
- goto done;
- }
- res = 0;
-done:
- if (res)
- post_log ("uart%d test failed\n", index);
-
- return res;
-}
-
-int uart_post_test (int flags)
-{
- int i, res = 0;
- static unsigned long base[] = CONFIG_SYS_POST_UART_TABLE;
-
- for (i = 0; i < ARRAY_SIZE(base); i++) {
- if (test_ctlr((struct NS16550 *)base[i], i))
- res = -1;
- }
- serial_reinit_all ();
-
- return res;
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_UART */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Author: Igor Lisitsin <igor@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/*
- * Watchdog test
- *
- * The test verifies the watchdog timer operation.
- * On the first iteration, the test routine disables interrupts and
- * makes a 10-second delay. If the system does not reboot during this delay,
- * the watchdog timer is not operational and the test fails. If the system
- * reboots, on the second iteration the test routine reports a success.
- */
-
-#include <post.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG
-
-#include <watchdog.h>
-
-int watchdog_post_test (int flags)
-{
- if (flags & POST_REBOOT) {
- /* Test passed */
- return 0;
- }
- else {
- /* 10-second delay */
- int ints = disable_interrupts ();
- ulong base = post_time_ms (0);
-
- while (post_time_ms (base) < 10000)
- ;
- if (ints)
- enable_interrupts ();
-
- /*
- * If we have reached this point, the watchdog timer
- * does not work
- */
- return -1;
- }
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_WATCHDOG */
WATCHDOG_RESET();
if (ic)
icache_disable ();
-#ifdef CONFIG_4xx_DCACHE
- /* disable cache */
- change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
-#endif
if (ret == 0)
ret = cpu_post_test_cmp ();
if (ic)
icache_enable ();
-#ifdef CONFIG_4xx_DCACHE
- /* enable cache */
- change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
-#endif
WATCHDOG_RESET();
CONFIG_16BIT
CONFIG_33
CONFIG_400MHZ_MODE
-CONFIG_405
-CONFIG_405EP
-CONFIG_405EX
-CONFIG_405EX_CHIP21_ECID3_REV_D
-CONFIG_405EX_CHIP21_PVR_REV_C
-CONFIG_405EX_CHIP21_PVR_REV_D
-CONFIG_405EZ
-CONFIG_405GP
-CONFIG_440
-CONFIG_440EP
-CONFIG_440EPX
-CONFIG_440GP
-CONFIG_440GR
-CONFIG_440GRX
-CONFIG_440GX
-CONFIG_440SP
-CONFIG_440SPE
-CONFIG_440SPE_REVA
-CONFIG_440_GX
CONFIG_4430SDP
-CONFIG_460EX
-CONFIG_460GT
-CONFIG_460SX
-CONFIG_4xx_CONFIG_BLOCKSIZE
-CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR
-CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET
-CONFIG_4xx_DCACHE
CONFIG_533MHZ_MODE
CONFIG_64BIT_PHYS_ADDR
CONFIG_66
CONFIG_88F5182
CONFIG_A003399_NOR_WORKAROUND
CONFIG_A008044_WORKAROUND
-CONFIG_ACADIA
CONFIG_ACX517AKN
CONFIG_ACX544AKN
-CONFIG_ADCIOP
-CONFIG_ADDMISC
CONFIG_ADDRESS
CONFIG_ADDR_AUTO_INCR_BIT
CONFIG_ADDR_MAP
CONFIG_ALTERA_SPI_IDLE_VAL
CONFIG_ALTIVEC
CONFIG_ALT_LB_ADDR
-CONFIG_ALT_LH_ADDR
CONFIG_ALU
CONFIG_AM335X_LCD
CONFIG_AM335X_USB0
CONFIG_AM335X_USB1
CONFIG_AM335X_USB1_MODE
CONFIG_AM437X_USB2PHY2_HOST
-CONFIG_AMCC_DEF_ENV
-CONFIG_AMCC_DEF_ENV_NOR_UPD
-CONFIG_AMCC_DEF_ENV_POWERPC
-CONFIG_AMCC_DEF_ENV_PPC
-CONFIG_AMCC_DEF_ENV_PPC_OLD
-CONFIG_AMCC_DEF_ENV_ROOTPATH
CONFIG_AMCORE
CONFIG_ANDES_PCU
CONFIG_ANDES_PCU_BASE
CONFIG_ATSTK1000_16MB_SDRAM
CONFIG_ATSTK1002
CONFIG_AT_TRANS
-CONFIG_AUTOCALIB
CONFIG_AUTONEG_TIMEOUT
CONFIG_AUTO_COMPLETE
CONFIG_AUTO_ZRELADDR
CONFIG_BACKSIDE_L2_CACHE
-CONFIG_BAMBOO
-CONFIG_BAMBOO_NAND
CONFIG_BARIX_IPAM390
CONFIG_BAT_CMD
CONFIG_BAT_PAIR
CONFIG_BCM_SF2_ETH
CONFIG_BCM_SF2_ETH_DEFAULT_PORT
CONFIG_BCM_SF2_ETH_GMAC
-CONFIG_BD_NUM_CPUS
CONFIG_BIOSEMU
CONFIG_BITBANGMII_MULTI
CONFIG_BL1_OFFSET
CONFIG_BOARD_COMMON
CONFIG_BOARD_EARLY_INIT_R
CONFIG_BOARD_ECC_SUPPORT
-CONFIG_BOARD_EMAC_COUNT
CONFIG_BOARD_H2200
CONFIG_BOARD_IS_OPENRD_BASE
CONFIG_BOARD_IS_OPENRD_CLIENT
CONFIG_BOARD_IS_OPENRD_ULTIMATE
CONFIG_BOARD_NAME
CONFIG_BOARD_POSTCLK_INIT
-CONFIG_BOARD_RESET
CONFIG_BOARD_REVISION_TAG
CONFIG_BOARD_SIZE_LIMIT
CONFIG_BOARD_TAURUS
CONFIG_BOOTSCRIPT_HDR_ADDR
CONFIG_BOOTSCRIPT_KEY_HASH
CONFIG_BOOT_DIR
-CONFIG_BOOT_FROM_XMD
CONFIG_BOOT_MODE_BIT
CONFIG_BOOT_OS_NET
CONFIG_BOOT_PARAMS_ADDR
-CONFIG_BOOT_PCI
CONFIG_BOOT_RETRY_MIN
CONFIG_BOOT_RETRY_TIME
CONFIG_BOUNCE_BUFFER
CONFIG_BS_HDR_SIZE
CONFIG_BS_SIZE
CONFIG_BTB
-CONFIG_BUBINGA
CONFIG_BUFNO_AUTO_INCR_BIT
CONFIG_BUILD_ENVCRC
CONFIG_BUILD_TARGET
CONFIG_CHIP_SELECTS_PER_CTRL
CONFIG_CHIP_SELECT_QUAD_CAPABLE
CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
-CONFIG_CIS8201_PHY
CONFIG_CI_UDC_HAS_HOSTPC
CONFIG_CLK0_DIV
CONFIG_CLK0_EN
CONFIG_CORE_COUNT
CONFIG_CORTINA_FW_ADDR
CONFIG_CORTINA_FW_LENGTH
-CONFIG_CPCI405
-CONFIG_CPCI405_6U
-CONFIG_CPCI405_VER2
CONFIG_CPLD_BR_PRELIM
CONFIG_CPLD_OR_PRELIM
CONFIG_CPM2
CONFIG_DA850_EVM_MAX_CPU_CLK
CONFIG_DA850_LOWLEVEL
CONFIG_DA8XX_GPIO
-CONFIG_DASA_SIM
CONFIG_DAVINCI_SPI
CONFIG_DBAU1000
CONFIG_DBAU1X00
CONFIG_DDR_32BIT
CONFIG_DDR_64BIT
CONFIG_DDR_CLK_FREQ
-CONFIG_DDR_DATA_EYE
CONFIG_DDR_DEFAULT_CL
CONFIG_DDR_ECC
CONFIG_DDR_ECC_CMD
CONFIG_DDR_MT47H32M16
CONFIG_DDR_MT47H64M16
CONFIG_DDR_PLL2
-CONFIG_DDR_RFDC_FIXED
-CONFIG_DDR_RQDC_FIXED
CONFIG_DDR_SPD
CONFIG_DEBUG
CONFIG_DEBUG_FS
CONFIG_DELAY_ENVIRONMENT
CONFIG_DESIGNWARE_ETH
CONFIG_DESIGNWARE_WATCHDOG
-CONFIG_DEVCONCENTER
CONFIG_DEVELOP
CONFIG_DEVICE_TREE_LIST
CONFIG_DEV_USB_PHY_BASE
CONFIG_DIRECT_NOR_BOOT
CONFIG_DISABLE_CONSOLE
CONFIG_DISABLE_IMAGE_LEGACY
-CONFIG_DISABLE_PISE_TEST
CONFIG_DISCONTIGMEM
CONFIG_DISCOVER_PHY
CONFIG_DISPLAY_AER_xxxx
CONFIG_DISPLAY_BOARDINFO_LATE
-CONFIG_DLVISION
CONFIG_DLVISION_10G
CONFIG_DM9000_BASE
CONFIG_DM9000_BYTE_SWAPPED
CONFIG_E1000_NO_NVM
CONFIG_E300
CONFIG_E5500
-CONFIG_EBC_PPC4xx_IBM_VER1
CONFIG_ECC
CONFIG_ECC_INIT_VIA_DDRCONTROLLER
CONFIG_ECC_MODE_MASK
CONFIG_EHCI_MXS_PORT0
CONFIG_EHCI_MXS_PORT1
CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
-CONFIG_EMAC_NR_START
-CONFIG_EMAC_PHY_MODE
CONFIG_EMIF4
CONFIG_EMMC_BOOT
CONFIG_EMU
CONFIG_FDT2_ENV_ADDR
CONFIG_FDTADDR
CONFIG_FDTFILE
-CONFIG_FDT_ENV_ADDR
-CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
CONFIG_FDT_FIXUP_PCI_IRQ
CONFIG_FEATURE_CLEAN_UP
CONFIG_FEATURE_COMMAND_EDITING
CONFIG_FPGA_COUNT
CONFIG_FPGA_DELAY
CONFIG_FPGA_SOCFPGA
-CONFIG_FPGA_SPARTAN2
CONFIG_FPGA_SPARTAN3
CONFIG_FPGA_STRATIX_V
CONFIG_FPGA_ZYNQPL
CONFIG_FTUART010_03_BASE
CONFIG_FTWDT010_BASE
CONFIG_FTWDT010_WATCHDOG
-CONFIG_FUNC_ISRAM_ADDR
CONFIG_FZOTG266HD0A_BASE
CONFIG_GATEWAYIP
CONFIG_GCOV_KERNEL
CONFIG_GMII
CONFIG_GOOD_SESH4
CONFIG_GPCNTRL
-CONFIG_GPCS_PHY1_ADDR
-CONFIG_GPCS_PHY2_ADDR
-CONFIG_GPCS_PHY3_ADDR
-CONFIG_GPCS_PHY_ADDR
CONFIG_GPIO
CONFIG_GPIO_ENABLE_SPI_FLASH
CONFIG_GPIO_LED_INVERTED_TABLE
CONFIG_G_DNL_UMS_VENDOR_NUM
CONFIG_H264_FREQ
CONFIG_H8300
-CONFIG_HALEAKALA
CONFIG_HARD_SPI
CONFIG_HAS_DATAFLASH
CONFIG_HAS_ETH0
CONFIG_I2C_REPEATED_START
CONFIG_I2C_RTC_ADDR
CONFIG_I2C_TIMEOUT
-CONFIG_IBM_EMAC4_V4
CONFIG_ICACHE
-CONFIG_ICON
CONFIG_ICS307_REFCLK_HZ
CONFIG_IDE_INIT_POSTRESET
CONFIG_IDE_LED
CONFIG_IDE_PREINIT
CONFIG_IDE_REG_CS
CONFIG_IDE_RESET
-CONFIG_IDE_RESET_ROUTINE
CONFIG_IDE_SWAP_IO
CONFIG_IDS8313
CONFIG_IDT8T49N222A
CONFIG_INITRD_TAG
CONFIG_INIT_CRITICAL
CONFIG_INIT_IGNORE_ERROR
-CONFIG_INIT_TLB
CONFIG_INI_ALLOW_MULTILINE
CONFIG_INI_CASE_INSENSITIVE
CONFIG_INI_MAX_LINE
CONFIG_INTEGRITY
CONFIG_INTEL_ICH6_GPIO
CONFIG_INTERRUPTS
-CONFIG_INTIB
CONFIG_IO
CONFIG_IO64
CONFIG_IOCON
CONFIG_IRDA_BASE
CONFIG_IS_BUILTIN
CONFIG_IS_ENABLED
-CONFIG_IS_INVALID
CONFIG_IS_MODULE
-CONFIG_IS_VALID
CONFIG_JFFS2_CMDLINE
CONFIG_JFFS2_DEV
CONFIG_JFFS2_LZO
CONFIG_JRSTARTR_JR0
CONFIG_JTAG_CONSOLE
CONFIG_KASAN
-CONFIG_KATMAI
CONFIG_KCLK_DIS
CONFIG_KEEP_SERVERADDR
CONFIG_KERNEL_OFFSET
CONFIG_KEY_REVOCATION
CONFIG_KGDB_BAUDRATE
CONFIG_KGDB_SER_INDEX
-CONFIG_KILAUEA
CONFIG_KIRKWOOD_EGIGA_INIT
CONFIG_KIRKWOOD_GPIO
CONFIG_KIRKWOOD_PCIE_INIT
CONFIG_LS102XA_STREAM_ID
CONFIG_LSCHLV2
CONFIG_LSXHL
-CONFIG_LUAN
-CONFIG_LWMON5
-CONFIG_LXT971_NO_SLEEP
CONFIG_LYNXKDI
CONFIG_M41T94_SPI_CS
CONFIG_M520x
CONFIG_M54418TWR
CONFIG_M54451EVB
CONFIG_M54455EVB
-CONFIG_M88E1111_DISABLE_FIBER
-CONFIG_M88E1111_PHY
-CONFIG_M88E1112_PHY
-CONFIG_M88E1141_PHY
CONFIG_MACB0_PHY
CONFIG_MACB1_PHY
CONFIG_MACB2_PHY
CONFIG_MACRESET_TIMEOUT
CONFIG_MAC_ADDR_IN_EEPROM
CONFIG_MAC_ADDR_IN_SPIFLASH
-CONFIG_MAKALU
CONFIG_MALLOC_F_ADDR
CONFIG_MALTA
CONFIG_MARCO_MEMSET
CONFIG_NAND_SPL
CONFIG_NAND_U_BOOT
CONFIG_NATSEMI
-CONFIG_NB
CONFIG_NCEL2C100_BASE
CONFIG_NCEMIC100_BASE
CONFIG_NDS_DLM1_BASE
CONFIG_NON_SECURE
CONFIG_NORBOOT
CONFIG_NORFLASH_PS32BIT
-CONFIG_NOT_SELECTED
CONFIG_NO_ETH
CONFIG_NO_RELOCATION
-CONFIG_NO_SERIAL_EEPROM
CONFIG_NO_WAIT
CONFIG_NR_CPUS
CONFIG_NR_DRAM_BANKS
CONFIG_ORIGEN
CONFIG_OS1_ENV_ADDR
CONFIG_OS2_ENV_ADDR
-CONFIG_OS_ENV_ADDR
CONFIG_OTHBOOTARGS
CONFIG_OVERWRITE_ETHADDR_ONCE
CONFIG_PAGE_CNT_MASK
CONFIG_PCISLAVE
CONFIG_PCIX_CHECK
CONFIG_PCI_33M
-CONFIG_PCI_4xx_PTM_OVERWRITE
CONFIG_PCI_66M
CONFIG_PCI_BOOTDELAY
CONFIG_PCI_CLK_FREQ
CONFIG_PCI_CONFIG_HOST_BRIDGE
-CONFIG_PCI_DISABLE_PCIE
CONFIG_PCI_EHCI_DEVICE
CONFIG_PCI_EHCI_DEVNO
CONFIG_PCI_ENUM_ONLY
CONFIG_PCI_FIXUP_DEV
CONFIG_PCI_GT64120
-CONFIG_PCI_HOST
CONFIG_PCI_INDIRECT_BRIDGE
CONFIG_PCI_IO_BUS
CONFIG_PCI_IO_PHYS
CONFIG_PCI_SCAN_SHOW
CONFIG_PCI_SKIP_HOST_BRIDGE
CONFIG_PCI_SYS_BUS
-CONFIG_PCI_SYS_MEM_BUS
-CONFIG_PCI_SYS_MEM_PHYS
-CONFIG_PCI_SYS_MEM_SIZE
CONFIG_PCI_SYS_PHYS
CONFIG_PCI_SYS_SIZE
CONFIG_PCMCIA
CONFIG_PERIF2_FREQ
CONFIG_PERIF3_FREQ
CONFIG_PERIF4_FREQ
-CONFIG_PHY1_ADDR
-CONFIG_PHY2_ADDR
-CONFIG_PHY3_ADDR
CONFIG_PHYSMEM
CONFIG_PHY_ADDR
CONFIG_PHY_BASE_ADR
CONFIG_PHY_BCM5421S
-CONFIG_PHY_CLK_FREQ
-CONFIG_PHY_CMD_DELAY
-CONFIG_PHY_DYNAMIC_ANEG
CONFIG_PHY_ET1011C_TX_CLK_FIX
CONFIG_PHY_ID
CONFIG_PHY_INTERFACE_MODE
CONFIG_PHY_MODE_NEED_CHANGE
CONFIG_PHY_RESET
CONFIG_PHY_RESET_DELAY
-CONFIG_PHYx_ADDR
CONFIG_PICOSAM
CONFIG_PIGGY_MAC_ADRESS_OFFSET
-CONFIG_PIP405
CONFIG_PIXIS_BRDCFG0_SPI
CONFIG_PIXIS_BRDCFG0_USB2
CONFIG_PIXIS_BRDCFG1_AUDCLK_11
CONFIG_PLL
CONFIG_PLL1_CLK_FREQ
CONFIG_PLL1_DIV2_CLK_FREQ
-CONFIG_PLU405
CONFIG_PM
CONFIG_PM9261
CONFIG_PM9263
CONFIG_PM9G45
-CONFIG_PMC405DE
CONFIG_PMC_BR_PRELIM
CONFIG_PMC_OR_PRELIM
CONFIG_PMECC_CAP
CONFIG_PMW_BASE
CONFIG_PM_SLEEP
CONFIG_PORTMUX_PIO
-CONFIG_PORT_ADDR
-CONFIG_PORT_AP
-CONFIG_PORT_BEM
-CONFIG_PORT_BME
-CONFIG_PORT_BS
-CONFIG_PORT_BU
-CONFIG_PORT_BW
-CONFIG_PORT_CR
-CONFIG_PORT_CSN
-CONFIG_PORT_OEN
-CONFIG_PORT_PEN
-CONFIG_PORT_RE
-CONFIG_PORT_SOR
-CONFIG_PORT_TH
-CONFIG_PORT_TWE
-CONFIG_PORT_WBF
-CONFIG_PORT_WBN
CONFIG_POST
CONFIG_POSTBOOTMENU
CONFIG_POST_ALT_LIST
CONFIG_POST_BSPEC4
CONFIG_POST_BSPEC5
CONFIG_POST_EXTERNAL_WORD_FUNCS
-CONFIG_POST_KEY_MAGIC
CONFIG_POST_SKIP_ENV_FLAGS
CONFIG_POST_STD_LIST
CONFIG_POST_UART
CONFIG_POWER_TPS65217
CONFIG_POWER_TPS65218
CONFIG_POWER_TPS65910
-CONFIG_PPC4XX_RAPIDIO_DEBUG
-CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
-CONFIG_PPC4XX_RAPIDIO_LOOPBACK
-CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
-CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
-CONFIG_PPC4xx_DDR_AUTOCALIBRATION
-CONFIG_PPC4xx_DDR_METHOD_A
-CONFIG_PPC4xx_EMAC
CONFIG_PPC64BRIDGE
CONFIG_PPC_CLUSTER_START
CONFIG_PPC_SPINTABLE_COMPATIBLE
CONFIG_PROC_FS
CONFIG_PROFILE_ALL_BRANCHES
CONFIG_PROFILING
-CONFIG_PROG_FDT
CONFIG_PROG_FDT1
CONFIG_PROG_FDT2
-CONFIG_PROG_OS
CONFIG_PROG_OS1
CONFIG_PROG_OS2
-CONFIG_PROG_SDRAM_TLB
-CONFIG_PROG_UBOOT
CONFIG_PROG_UBOOT1
CONFIG_PROG_UBOOT2
CONFIG_PROOF_POINTS
CONFIG_R8A7792
CONFIG_R8A7793
CONFIG_R8A7794
-CONFIG_RAINIER
CONFIG_RAMBOOT
CONFIG_RAMBOOTCOMMAND
CONFIG_RAMBOOTCOMMAND_TFTP
CONFIG_RAM_BOOT
CONFIG_RAM_BOOT_PHYS
CONFIG_RANDOM_UUID
-CONFIG_RAPIDIO
CONFIG_RCAR_BOARD_STRING
CONFIG_RD_LVL
CONFIG_REALMODE_DEBUG
CONFIG_RTC_DS1374
CONFIG_RTC_DS1388
CONFIG_RTC_DS1388_TCR_VAL
-CONFIG_RTC_DS1556
-CONFIG_RTC_DS174x
CONFIG_RTC_DS3231
CONFIG_RTC_FTRTC010
CONFIG_RTC_IMXDI
CONFIG_RTC_M41T11
CONFIG_RTC_M41T60
CONFIG_RTC_M41T62
-CONFIG_RTC_M48T35A
CONFIG_RTC_MC13XXX
CONFIG_RTC_MC146818
CONFIG_RTC_MCFRRTC
CONFIG_RTC_PCF8563
CONFIG_RTC_PT7C4338
CONFIG_RTC_RX8025
-CONFIG_RTC_X1205
CONFIG_RUN_FROM_DDR0
CONFIG_RUN_FROM_DDR1
CONFIG_RUN_FROM_IRAM_ONLY
CONFIG_SAR_REG
CONFIG_SATA1
CONFIG_SATA2
-CONFIG_SATA_DWC
CONFIG_SATA_MV
CONFIG_SATA_SIL
CONFIG_SATA_SIL3114
CONFIG_SCSI_SYM53C8XX
CONFIG_SC_TIMER_CLK
CONFIG_SDCARD
-CONFIG_SDRAM_BANK0
-CONFIG_SDRAM_BANK1
-CONFIG_SDRAM_ECC
CONFIG_SDRAM_OFFSET_FOR_RT
-CONFIG_SDRAM_PPC4xx_DENALI_DDR2
-CONFIG_SDRAM_PPC4xx_IBM_DDR
-CONFIG_SDRAM_PPC4xx_IBM_DDR2
-CONFIG_SDRAM_PPC4xx_IBM_SDRAM
CONFIG_SDRC
CONFIG_SD_BOOT_QSPI
CONFIG_SECBOOT
CONFIG_SECURITY
CONFIG_SEC_DEQ_TIMEOUT
CONFIG_SEC_FW_SIZE
-CONFIG_SELECTED
-CONFIG_SEQUOIA
CONFIG_SERIAL0
CONFIG_SERIAL1
CONFIG_SERIAL2
CONFIG_SOFT_I2C_READ_REPEATED_START
CONFIG_SOURCE
CONFIG_SPARSE_RCU_POINTER
-CONFIG_SPDDRAM_SILENT
CONFIG_SPD_EEPROM
CONFIG_SPEAR300
CONFIG_SPEAR310
CONFIG_STM32_HSE_HZ
CONFIG_STM32_HZ
CONFIG_STM32_SERIAL
-CONFIG_STRESS
CONFIG_STRIDER
CONFIG_STRIDER_CON
CONFIG_STRIDER_CON_DP
CONFIG_SYSMGR_ISWGRP_HANDOFF
CONFIG_SYSTEMACE
CONFIG_SYS_33MHZ
-CONFIG_SYS_405_UART_ERRATA_59
-CONFIG_SYS_460GT_SRIO_ERRATA_1
-CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
-CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
-CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
-CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
-CONFIG_SYS_4xx_CHIP_21_ERRATA
-CONFIG_SYS_4xx_GPIO_TABLE
-CONFIG_SYS_4xx_RESET_TYPE
CONFIG_SYS_64BIT
CONFIG_SYS_64BIT_LBA
CONFIG_SYS_64BIT_VSPRINTF
CONFIG_SYS_66MHZ
CONFIG_SYS_8313ERDB_BROKEN_PMC
CONFIG_SYS_83XX_DDR_USES_CS0
-CONFIG_SYS_ACE_BASE
-CONFIG_SYS_ACE_BASE_PHYS_H
-CONFIG_SYS_ACE_BASE_PHYS_L
CONFIG_SYS_ACR_APARK
CONFIG_SYS_ACR_PARKM
CONFIG_SYS_ACR_PIPE_DEP
CONFIG_SYS_ACR_RPTCNT
CONFIG_SYS_ADDRESS_MAP_A
CONFIG_SYS_ADV7611_I2C
-CONFIG_SYS_AHB_BASE
CONFIG_SYS_ALT_BOOT
CONFIG_SYS_ALT_FLASH
CONFIG_SYS_ALT_MEMTEST
CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
CONFIG_SYS_AUXCORE_BOOTDATA
CONFIG_SYS_BARGSIZE
-CONFIG_SYS_BASE_BAUD
CONFIG_SYS_BAUDRATE_TABLE
CONFIG_SYS_BCSR
-CONFIG_SYS_BCSR3_PCIE
-CONFIG_SYS_BCSR5_PCI66EN
CONFIG_SYS_BCSR_ADDR
CONFIG_SYS_BCSR_BASE
CONFIG_SYS_BCSR_BASE_PHYS
CONFIG_SYS_BOOTCOUNT_BE
CONFIG_SYS_BOOTCOUNT_LE
CONFIG_SYS_BOOTCOUNT_SINGLEWORD
-CONFIG_SYS_BOOTFILE
CONFIG_SYS_BOOTFILE_PREFIX
CONFIG_SYS_BOOTMAPSZ
CONFIG_SYS_BOOTM_LEN
CONFIG_SYS_BOOTPARAMS_LEN
CONFIG_SYS_BOOTSZ
-CONFIG_SYS_BOOT_BASE_ADDR
CONFIG_SYS_BOOT_BLOCK
-CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS
CONFIG_SYS_BOOT_GET_CMDLINE
CONFIG_SYS_BOOT_GET_KBD
CONFIG_SYS_BOOT_RAMDISK_HIGH
CONFIG_SYS_CORTINA_FW_IN_REMOTE
CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
CONFIG_SYS_CPC_REINIT_F
-CONFIG_SYS_CPLD
-CONFIG_SYS_CPLD_ADDR
CONFIG_SYS_CPLD_AMASK
CONFIG_SYS_CPLD_BASE
CONFIG_SYS_CPLD_BASE_PHYS
CONFIG_SYS_CPLD_CSOR
CONFIG_SYS_CPLD_CSPR
CONFIG_SYS_CPLD_CSPR_EXT
-CONFIG_SYS_CPLD_DATA
CONFIG_SYS_CPLD_FTIM0
CONFIG_SYS_CPLD_FTIM1
CONFIG_SYS_CPLD_FTIM2
CONFIG_SYS_DBAT7U
CONFIG_SYS_DCACHE_INV
CONFIG_SYS_DCACHE_LINESZ
-CONFIG_SYS_DCACHE_SACR_VALUE
CONFIG_SYS_DCSRBAR
CONFIG_SYS_DCSRBAR_PHYS
CONFIG_SYS_DCSR_COP_CCP_ADDR
CONFIG_SYS_DDR_BASE
CONFIG_SYS_DDR_BLOCK1_SIZE
CONFIG_SYS_DDR_BLOCK2_BASE
-CONFIG_SYS_DDR_CACHED_ADDR
CONFIG_SYS_DDR_CDR_1
CONFIG_SYS_DDR_CDR_2
CONFIG_SYS_DDR_CFG_1A
CONFIG_SYS_DEBUG
CONFIG_SYS_DEBUG_SERVER_FW_ADDR
CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-CONFIG_SYS_DECREMENT_PATTERNS
CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
CONFIG_SYS_DEFAULT_VIDEO_MODE
CONFIG_SYS_DEF_EEPROM_ADDR
CONFIG_SYS_DM36x_PLL1_PREDIV
CONFIG_SYS_DM36x_PLL2_PREDIV
CONFIG_SYS_DMA_USE_INTSRAM
-CONFIG_SYS_DOC_SHORT_TIMEOUT
-CONFIG_SYS_DOC_SUPPORT_2000
-CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
CONFIG_SYS_DP501_BASE
CONFIG_SYS_DP501_DIFFERENTIAL
CONFIG_SYS_DP501_I2C
CONFIG_SYS_DRAM_BASE
CONFIG_SYS_DRAM_SIZE
CONFIG_SYS_DRAM_TEST
-CONFIG_SYS_DSPIC_TEST_ADDR
-CONFIG_SYS_DSPIC_TEST_MASK
CONFIG_SYS_DSPI_CS0
CONFIG_SYS_DSPI_CS2
CONFIG_SYS_DSPI_CTAR0
CONFIG_SYS_DSPI_CTAR5
CONFIG_SYS_DSPI_CTAR6
CONFIG_SYS_DSPI_CTAR7
-CONFIG_SYS_DUART_RST
CONFIG_SYS_DV_CLKMODE
CONFIG_SYS_DV_NOR_BOOT_CFG
-CONFIG_SYS_EBC_CFG
-CONFIG_SYS_EBC_PB0AP
-CONFIG_SYS_EBC_PB0CR
-CONFIG_SYS_EBC_PB1AP
-CONFIG_SYS_EBC_PB1CR
-CONFIG_SYS_EBC_PB2AP
-CONFIG_SYS_EBC_PB2CR
-CONFIG_SYS_EBC_PB3AP
-CONFIG_SYS_EBC_PB3CR
-CONFIG_SYS_EBC_PB4AP
-CONFIG_SYS_EBC_PB4CR
-CONFIG_SYS_EBC_PB5AP
-CONFIG_SYS_EBC_PB5CR
-CONFIG_SYS_EBC_PB6AP
-CONFIG_SYS_EBC_PB6CR
-CONFIG_SYS_EBC_PB7AP
-CONFIG_SYS_EBC_PB7CR
CONFIG_SYS_EBI_CFGR_VAL
CONFIG_SYS_EBI_CSA_VAL
CONFIG_SYS_EEPROM_BASE
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
CONFIG_SYS_EEPROM_SIZE
-CONFIG_SYS_EEPROM_WP
CONFIG_SYS_EEPROM_WREN
CONFIG_SYS_EHCI_USB1_ADDR
CONFIG_SYS_ELBC_BASE
CONFIG_SYS_ENABLE_PADS_ALL
CONFIG_SYS_ENET_BD_BASE
CONFIG_SYS_ENV_ADDR
-CONFIG_SYS_ENV_OFFSET
CONFIG_SYS_ENV_SECT_SIZE
CONFIG_SYS_EPLD_BASE
CONFIG_SYS_ETHOC_BASE
CONFIG_SYS_ETHOC_BUFFER_ADDR
-CONFIG_SYS_ETH_IOBASE
CONFIG_SYS_ETVPE_CLK
CONFIG_SYS_EXCEPTION_VECTORS_HIGH
CONFIG_SYS_EXTBDINFO
CONFIG_SYS_EXTRA_ENV_RELOC
-CONFIG_SYS_EXT_SERIAL_CLOCK
CONFIG_SYS_FAST_CLK
CONFIG_SYS_FAULT_ECHO_LINK_DOWN
CONFIG_SYS_FAULT_MII_ADDR
CONFIG_SYS_FCC_PSMR
-CONFIG_SYS_FCPU133MHZ
-CONFIG_SYS_FCPU266MHZ
-CONFIG_SYS_FCPU333MHZ
CONFIG_SYS_FDC_DRIVE_NUMBER
CONFIG_SYS_FDC_HW_INIT
CONFIG_SYS_FDT_ADDR
CONFIG_SYS_FIXED_PHY_ADDR
CONFIG_SYS_FIXED_PHY_PORT
CONFIG_SYS_FIXED_PHY_PORTS
-CONFIG_SYS_FLASH
CONFIG_SYS_FLASH0
CONFIG_SYS_FLASH0_BASE
CONFIG_SYS_FLASH1
CONFIG_SYS_FLASH1_BASE_PHYS
CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
CONFIG_SYS_FLASHBOOT
-CONFIG_SYS_FLASH_2ND_16BIT_DEV
-CONFIG_SYS_FLASH_2ND_ADDR
-CONFIG_SYS_FLASH_ADDR0
-CONFIG_SYS_FLASH_ADDR1
CONFIG_SYS_FLASH_ADDR_BASE
CONFIG_SYS_FLASH_AMD_CHECK_DQ7
CONFIG_SYS_FLASH_AUTOPROTECT_LIST
CONFIG_SYS_FLASH_BASE2
CONFIG_SYS_FLASH_BASE_PHYS
CONFIG_SYS_FLASH_BASE_PHYS_EARLY
-CONFIG_SYS_FLASH_BASE_PHYS_H
-CONFIG_SYS_FLASH_BASE_PHYS_L
CONFIG_SYS_FLASH_BASE_PHYS_LOW
CONFIG_SYS_FLASH_BR_PRELIM
CONFIG_SYS_FLASH_CFI
CONFIG_SYS_FLASH_PARMSECT_SZ
CONFIG_SYS_FLASH_PROTECTION
CONFIG_SYS_FLASH_QUIET_TEST
-CONFIG_SYS_FLASH_READ0
-CONFIG_SYS_FLASH_READ1
-CONFIG_SYS_FLASH_READ2
CONFIG_SYS_FLASH_SECT_SIZE
CONFIG_SYS_FLASH_SECT_SZ
CONFIG_SYS_FLASH_SIZE
CONFIG_SYS_FLASH_UNLOCK_TOUT
CONFIG_SYS_FLASH_USE_BUFFER_WRITE
CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE
-CONFIG_SYS_FLASH_WORD_SIZE
CONFIG_SYS_FLASH_WRITE_TOUT
CONFIG_SYS_FLYCNFG_VAL
CONFIG_SYS_FM1_10GEC1_PHY_ADDR
CONFIG_SYS_FORM_XMC
CONFIG_SYS_FPGA0_BASE
CONFIG_SYS_FPGA0_SIZE
-CONFIG_SYS_FPGA1_BASE
-CONFIG_SYS_FPGA2_BASE
-CONFIG_SYS_FPGA3_BASE
CONFIG_SYS_FPGAREG_DATE
CONFIG_SYS_FPGAREG_DIPSW
CONFIG_SYS_FPGAREG_FREQ
CONFIG_SYS_FPGAREG_RESET_CODE
CONFIG_SYS_FPGA_AMASK
CONFIG_SYS_FPGA_BASE
-CONFIG_SYS_FPGA_BASE0
-CONFIG_SYS_FPGA_BASE1
-CONFIG_SYS_FPGA_BASE_0
-CONFIG_SYS_FPGA_BASE_1
-CONFIG_SYS_FPGA_BASE_ADDR
CONFIG_SYS_FPGA_BASE_PHYS
CONFIG_SYS_FPGA_CHECK_BUSY
CONFIG_SYS_FPGA_CHECK_CTRLC
CONFIG_SYS_FPGA_CHECK_ERROR
-CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK
-CONFIG_SYS_FPGA_CLK
-CONFIG_SYS_FPGA_COMMON
CONFIG_SYS_FPGA_COUNT
CONFIG_SYS_FPGA_CSOR
CONFIG_SYS_FPGA_CSPR
CONFIG_SYS_FPGA_CSPR_EXT
-CONFIG_SYS_FPGA_CTRL
-CONFIG_SYS_FPGA_CTRL_CF_RESET
-CONFIG_SYS_FPGA_CTRL_PS2_RESET
-CONFIG_SYS_FPGA_CTRL_WDI
-CONFIG_SYS_FPGA_DATA
CONFIG_SYS_FPGA_DONE
-CONFIG_SYS_FPGA_DPRAM_RST
-CONFIG_SYS_FPGA_DPRAM_RW_TYPE
-CONFIG_SYS_FPGA_DPRAM_R_INT_LINE
-CONFIG_SYS_FPGA_DPRAM_W_INT_LINE
-CONFIG_SYS_FPGA_FIFO_BASE
CONFIG_SYS_FPGA_FTIM0
CONFIG_SYS_FPGA_FTIM1
CONFIG_SYS_FPGA_FTIM2
CONFIG_SYS_FPGA_FTIM3
-CONFIG_SYS_FPGA_INIT
CONFIG_SYS_FPGA_IS_PROTO
-CONFIG_SYS_FPGA_LINESIDE_LOOPBACK
-CONFIG_SYS_FPGA_MAGIC
-CONFIG_SYS_FPGA_MAGIC_MASK
-CONFIG_SYS_FPGA_MAX_SIZE
-CONFIG_SYS_FPGA_MODE
-CONFIG_SYS_FPGA_MODE_CF_RESET
-CONFIG_SYS_FPGA_MODE_DUART_RESET
-CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT
-CONFIG_SYS_FPGA_MODE_TS_CLEAR
-CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR
-CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE
CONFIG_SYS_FPGA_NO_RFL_HI
-CONFIG_SYS_FPGA_PHY0_INT
-CONFIG_SYS_FPGA_PHY1_INT
-CONFIG_SYS_FPGA_PRG
CONFIG_SYS_FPGA_PROG
CONFIG_SYS_FPGA_PROG_FEEDBACK
CONFIG_SYS_FPGA_PROG_TIME
CONFIG_SYS_FPGA_PTR
-CONFIG_SYS_FPGA_REG_BASE
-CONFIG_SYS_FPGA_REG_BASE_ADDR
CONFIG_SYS_FPGA_SIZE
-CONFIG_SYS_FPGA_SLIC0_CS
-CONFIG_SYS_FPGA_SLIC0_ENABLE
-CONFIG_SYS_FPGA_SLIC0_INT
-CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT
-CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT
-CONFIG_SYS_FPGA_SLIC1_CS
-CONFIG_SYS_FPGA_SLIC1_ENABLE
-CONFIG_SYS_FPGA_SLIC1_INT
-CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT
-CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT
-CONFIG_SYS_FPGA_SPARTAN2
-CONFIG_SYS_FPGA_STATUS
-CONFIG_SYS_FPGA_STATUS_DIP0
-CONFIG_SYS_FPGA_STATUS_DIP1
-CONFIG_SYS_FPGA_STATUS_DIP2
-CONFIG_SYS_FPGA_STATUS_FLASH
-CONFIG_SYS_FPGA_STATUS_TS_IRQ
-CONFIG_SYS_FPGA_TS
-CONFIG_SYS_FPGA_TS_CAP0
-CONFIG_SYS_FPGA_TS_CAP0_LOW
-CONFIG_SYS_FPGA_TS_CAP1
-CONFIG_SYS_FPGA_TS_CAP1_LOW
-CONFIG_SYS_FPGA_TS_CAP2
-CONFIG_SYS_FPGA_TS_CAP2_LOW
-CONFIG_SYS_FPGA_TS_CAP3
-CONFIG_SYS_FPGA_TS_CAP3_LOW
-CONFIG_SYS_FPGA_TS_LOW
-CONFIG_SYS_FPGA_UART0_FO
-CONFIG_SYS_FPGA_UART1_FO
-CONFIG_SYS_FPGA_USER_LED0
-CONFIG_SYS_FPGA_USER_LED1
-CONFIG_SYS_FPGA_VER_MASK
CONFIG_SYS_FPGA_WAIT
CONFIG_SYS_FPGA_WAIT_BUSY
CONFIG_SYS_FPGA_WAIT_CONFIG
CONFIG_SYS_FPGA_WAIT_INIT
-CONFIG_SYS_FPGA_xxx
CONFIG_SYS_FSL_AIOP1_BASE
CONFIG_SYS_FSL_AIOP1_SIZE
CONFIG_SYS_FSL_B4860QDS_XFI_ERR
CONFIG_SYS_GPDR1_VAL
CONFIG_SYS_GPDR2_VAL
CONFIG_SYS_GPDR3_VAL
-CONFIG_SYS_GPIO0_ISR1H
-CONFIG_SYS_GPIO0_ISR1L
-CONFIG_SYS_GPIO0_ISR2H
-CONFIG_SYS_GPIO0_ISR2L
-CONFIG_SYS_GPIO0_ODR
-CONFIG_SYS_GPIO0_OR
-CONFIG_SYS_GPIO0_OSRH
-CONFIG_SYS_GPIO0_OSRL
-CONFIG_SYS_GPIO0_TCR
-CONFIG_SYS_GPIO0_TSRH
-CONFIG_SYS_GPIO0_TSRL
CONFIG_SYS_GPIO1_DAT
CONFIG_SYS_GPIO1_DIR
CONFIG_SYS_GPIO1_EN
CONFIG_SYS_GPIO1_FUNC
-CONFIG_SYS_GPIO1_ISR1H
-CONFIG_SYS_GPIO1_ISR1L
CONFIG_SYS_GPIO1_LED
-CONFIG_SYS_GPIO1_OSRH
-CONFIG_SYS_GPIO1_OSRL
CONFIG_SYS_GPIO1_OUT
CONFIG_SYS_GPIO1_PRELIM
-CONFIG_SYS_GPIO1_TCR
-CONFIG_SYS_GPIO1_TSRH
-CONFIG_SYS_GPIO1_TSRL
CONFIG_SYS_GPIO2_DAT
CONFIG_SYS_GPIO2_DIR
CONFIG_SYS_GPIO2_PRELIM
CONFIG_SYS_GPIO_0_ADDR
-CONFIG_SYS_GPIO_BASE
-CONFIG_SYS_GPIO_BOARD_RESET
-CONFIG_SYS_GPIO_CAN_ENABLE
-CONFIG_SYS_GPIO_CRAM_ADV
-CONFIG_SYS_GPIO_CRAM_CLK
-CONFIG_SYS_GPIO_CRAM_CRE
-CONFIG_SYS_GPIO_CRAM_WAIT
-CONFIG_SYS_GPIO_DSPIC_READY
-CONFIG_SYS_GPIO_EEPROM_EXT_WP
-CONFIG_SYS_GPIO_EEPROM_INT_WP
-CONFIG_SYS_GPIO_EEPROM_WP
CONFIG_SYS_GPIO_EN
-CONFIG_SYS_GPIO_EREADY
-CONFIG_SYS_GPIO_FLASH_WP
CONFIG_SYS_GPIO_FUNC
-CONFIG_SYS_GPIO_HIGHSIDE
-CONFIG_SYS_GPIO_HWREV_MASK
-CONFIG_SYS_GPIO_HWREV_SHIFT
CONFIG_SYS_GPIO_I2C_SCL
CONFIG_SYS_GPIO_I2C_SDA
-CONFIG_SYS_GPIO_LEDA_N
-CONFIG_SYS_GPIO_LEDB_N
-CONFIG_SYS_GPIO_LEDRUN_N
-CONFIG_SYS_GPIO_LIME_RST
-CONFIG_SYS_GPIO_LIME_S
-CONFIG_SYS_GPIO_LSB_ENABLE
-CONFIG_SYS_GPIO_M66EN
-CONFIG_SYS_GPIO_MONARCH_N
-CONFIG_SYS_GPIO_ODR
-CONFIG_SYS_GPIO_OR
CONFIG_SYS_GPIO_OUT
-CONFIG_SYS_GPIO_PCIE_CLKREQ
-CONFIG_SYS_GPIO_PCIE_PRESENT0
-CONFIG_SYS_GPIO_PCIE_PRESENT1
-CONFIG_SYS_GPIO_PCIE_PRESENT2
-CONFIG_SYS_GPIO_PCIE_RST
-CONFIG_SYS_GPIO_PCIE_WAKE
-CONFIG_SYS_GPIO_PERM_VOLT_FEED
-CONFIG_SYS_GPIO_PHY0_RST
-CONFIG_SYS_GPIO_PHY1_RST
CONFIG_SYS_GPIO_PHY_RST
-CONFIG_SYS_GPIO_RS232_FORCEOFF
-CONFIG_SYS_GPIO_SELFRST_N
-CONFIG_SYS_GPIO_STARTUP_FINISHED
-CONFIG_SYS_GPIO_STARTUP_FINISHED_N
-CONFIG_SYS_GPIO_SYSMON_STATUS
-CONFIG_SYS_GPIO_TCR
-CONFIG_SYS_GPIO_WATCHDOG
CONFIG_SYS_GPR1
CONFIG_SYS_GPSR0_VAL
CONFIG_SYS_GPSR1_VAL
CONFIG_SYS_I2C_BASE3
CONFIG_SYS_I2C_BASE4
CONFIG_SYS_I2C_BASE5
-CONFIG_SYS_I2C_BOOT_EEPROM_ADDR
CONFIG_SYS_I2C_BUSES
CONFIG_SYS_I2C_BUS_MAX
CONFIG_SYS_I2C_CLK_OFFSET
CONFIG_SYS_I2C_DAVINCI
CONFIG_SYS_I2C_DIRECT_BUS
-CONFIG_SYS_I2C_DSPIC_2_ADDR
-CONFIG_SYS_I2C_DSPIC_ADDR
-CONFIG_SYS_I2C_DSPIC_IO_ADDR
-CONFIG_SYS_I2C_DSPIC_KEYB_ADDR
CONFIG_SYS_I2C_DVI_ADDR
CONFIG_SYS_I2C_DVI_BUS_NUM
CONFIG_SYS_I2C_EARLY_INIT
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
CONFIG_SYS_I2C_EEPROM_BUS
CONFIG_SYS_I2C_EEPROM_CCID
-CONFIG_SYS_I2C_EEPROM_CPU_ADDR
-CONFIG_SYS_I2C_EEPROM_MB_ADDR
CONFIG_SYS_I2C_EEPROM_NXID
CONFIG_SYS_I2C_EEPROM_NXID_MAC
CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS
CONFIG_SYS_I2C_IHS_SPEED_3
CONFIG_SYS_I2C_IHS_SPEED_3_1
CONFIG_SYS_I2C_INIT_BOARD
-CONFIG_SYS_I2C_KEYBD_ADDR
CONFIG_SYS_I2C_KONA
CONFIG_SYS_I2C_LDI_ADDR
CONFIG_SYS_I2C_LM75_ADDR
CONFIG_SYS_I2C_PINMUX_REG
CONFIG_SYS_I2C_PINMUX_SET
CONFIG_SYS_I2C_POWERIC_ADDR
-CONFIG_SYS_I2C_PPC4XX
-CONFIG_SYS_I2C_PPC4XX_CH0
-CONFIG_SYS_I2C_PPC4XX_CH1
-CONFIG_SYS_I2C_PPC4XX_SLAVE_0
-CONFIG_SYS_I2C_PPC4XX_SLAVE_1
-CONFIG_SYS_I2C_PPC4XX_SPEED_0
-CONFIG_SYS_I2C_PPC4XX_SPEED_1
CONFIG_SYS_I2C_PXA
CONFIG_SYS_I2C_QIXIS_ADDR
CONFIG_SYS_I2C_RCAR
CONFIG_SYS_I2C_ZYNQ
CONFIG_SYS_I2C_ZYNQ_SLAVE
CONFIG_SYS_I2C_ZYNQ_SPEED
-CONFIG_SYS_I2ODMA_BASE
-CONFIG_SYS_I2ODMA_PHYS_ADDR
CONFIG_SYS_IBAT
CONFIG_SYS_IBAT0L
CONFIG_SYS_IBAT0U
CONFIG_SYS_IBAT7U
CONFIG_SYS_ICACHE_INV
CONFIG_SYS_ICACHE_LINESZ
-CONFIG_SYS_ICACHE_SACR_VALUE
CONFIG_SYS_ICS8N3QV01_I2C
CONFIG_SYS_IDE_MAXBUS
CONFIG_SYS_IDE_MAXDEVICE
CONFIG_SYS_IFC_CCR
CONFIG_SYS_IMMR
CONFIG_SYS_INIT_DBCR
-CONFIG_SYS_INIT_DCACHE_CS
-CONFIG_SYS_INIT_DCACHE_PBxAR
-CONFIG_SYS_INIT_DCACHE_PBxCR
-CONFIG_SYS_INIT_EXTRA_SIZE
CONFIG_SYS_INIT_L2CSR0
CONFIG_SYS_INIT_L2_ADDR
CONFIG_SYS_INIT_L2_ADDR_PHYS
CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW
CONFIG_SYS_INIT_RAM_CTRL
-CONFIG_SYS_INIT_RAM_DCACHE
CONFIG_SYS_INIT_RAM_LOCK
-CONFIG_SYS_INIT_RAM_PATTERN
CONFIG_SYS_INIT_RAM_SIZE
CONFIG_SYS_INIT_SP_ADDR
CONFIG_SYS_INIT_SP_OFFSET
CONFIG_SYS_INPUT_CLKSRC
-CONFIG_SYS_INTA_FAKE
CONFIG_SYS_INTEL_BOOT
CONFIG_SYS_INTERLAKEN
CONFIG_SYS_INTRAM_BASE
CONFIG_SYS_INT_FLASH_BASE
CONFIG_SYS_INT_FLASH_ENABLE
CONFIG_SYS_IO_BASE
-CONFIG_SYS_IR_REG_BASE_ADDR
CONFIG_SYS_ISA_BASE
CONFIG_SYS_ISA_IO
CONFIG_SYS_ISA_IO_BASE_ADDRESS
CONFIG_SYS_ISA_IO_OFFSET
CONFIG_SYS_ISA_IO_STRIDE
CONFIG_SYS_ISA_MEM
-CONFIG_SYS_ISRAM_BASE
CONFIG_SYS_IVM_EEPROM_ADR
CONFIG_SYS_IVM_EEPROM_MAX_LEN
CONFIG_SYS_IVM_EEPROM_PAGE_LEN
CONFIG_SYS_JFFS2_MEM_NAND
CONFIG_SYS_JFFS2_NUM_BANKS
CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-CONFIG_SYS_KBYTES_SDRAM
-CONFIG_SYS_KEY_REG_BASE_ADDR
CONFIG_SYS_KMBEC_FPGA_BASE
CONFIG_SYS_KMBEC_FPGA_SIZE
CONFIG_SYS_KWD_CONFIG
CONFIG_SYS_L2_PL310
CONFIG_SYS_L2_SIZE
CONFIG_SYS_L3_SIZE
-CONFIG_SYS_LARGE_FLASH
-CONFIG_SYS_LATCH0_BOOT
-CONFIG_SYS_LATCH0_RESET
-CONFIG_SYS_LATCH1_BOOT
-CONFIG_SYS_LATCH1_RESET
CONFIG_SYS_LATCH_ADDR
-CONFIG_SYS_LATCH_BASE
CONFIG_SYS_LBAPP1_BASE
CONFIG_SYS_LBAPP1_BASE_PHYS
CONFIG_SYS_LBAPP1_BR_PRELIM
CONFIG_SYS_LBLAWBAR6_PRELIM
CONFIG_SYS_LBLAWBAR7_PRELIM
CONFIG_SYS_LB_SDRAM
-CONFIG_SYS_LCD0_RST
-CONFIG_SYS_LCD1_RST
CONFIG_SYS_LCD_BASE
-CONFIG_SYS_LCD_ENDIAN
CONFIG_SYS_LCRR_CLKDIV
CONFIG_SYS_LCRR_DBYP
CONFIG_SYS_LCRR_EADC
CONFIG_SYS_LDB_CLOCK
CONFIG_SYS_LDSCRIPT
-CONFIG_SYS_LED_ADDR
CONFIG_SYS_LED_BASE
CONFIG_SYS_LED_DISP_BASE
CONFIG_SYS_LIME_BASE
-CONFIG_SYS_LIME_BASE_0
-CONFIG_SYS_LIME_BASE_1
-CONFIG_SYS_LIME_BASE_2
-CONFIG_SYS_LIME_BASE_3
-CONFIG_SYS_LIME_CLOCK_100MHZ
-CONFIG_SYS_LIME_CLOCK_133MHZ
-CONFIG_SYS_LIME_MMR
-CONFIG_SYS_LIME_SDRAM_CLOCK
CONFIG_SYS_LIME_SIZE
CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE
CONFIG_SYS_LOADS_BAUD_CHANGE
CONFIG_SYS_LOAD_ADDR
CONFIG_SYS_LOAD_ADDR2
-CONFIG_SYS_LOCAL_CONF_REGS
CONFIG_SYS_LONGHELP
CONFIG_SYS_LOW
CONFIG_SYS_LOWBOOT
CONFIG_SYS_MAXARGS
CONFIG_SYS_MAX_DATAFLASH_BANKS
CONFIG_SYS_MAX_DDR_BAT_SIZE
-CONFIG_SYS_MAX_DOC_DEVICE
CONFIG_SYS_MAX_FLASH_BANKS
CONFIG_SYS_MAX_FLASH_BANKS_DETECT
CONFIG_SYS_MAX_FLASH_SECT
CONFIG_SYS_MB862xx_MMR
CONFIG_SYS_MBAR
CONFIG_SYS_MBAR2
-CONFIG_SYS_MBYTES_RAM
CONFIG_SYS_MBYTES_SDRAM
CONFIG_SYS_MCATT0_VAL
CONFIG_SYS_MCATT1_VAL
CONFIG_SYS_MMC_U_BOOT_OFFS
CONFIG_SYS_MMC_U_BOOT_SIZE
CONFIG_SYS_MMC_U_BOOT_START
-CONFIG_SYS_MM_TOP_HIDE
CONFIG_SYS_MONITOR_
CONFIG_SYS_MONITOR_BASE
CONFIG_SYS_MONITOR_BASE_EARLY
CONFIG_SYS_MXC_I2C4_SLAVE
CONFIG_SYS_MXC_I2C4_SPEED
CONFIG_SYS_MXS_VDD5V_ONLY
-CONFIG_SYS_NAND2_ADDR
CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
CONFIG_SYS_NAND_4_ADDR_CYCLE
CONFIG_SYS_NAND_5_ADDR_CYCLE
CONFIG_SYS_NAND_BOOT
CONFIG_SYS_NAND_BR_PRELIM
CONFIG_SYS_NAND_BUSWIDTH_16
-CONFIG_SYS_NAND_CE
CONFIG_SYS_NAND_CLE
CONFIG_SYS_NAND_CS
CONFIG_SYS_NAND_CSOR
CONFIG_SYS_NAND_PAGE_COUNT
CONFIG_SYS_NAND_PAGE_SIZE
CONFIG_SYS_NAND_QUIET
-CONFIG_SYS_NAND_RDY
CONFIG_SYS_NAND_READY_PIN
CONFIG_SYS_NAND_REGS_BASE
CONFIG_SYS_NAND_SELECT_DEVICE
CONFIG_SYS_NAND_SIZE
-CONFIG_SYS_NAND_SKIP_BAD_DOT_I
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
CONFIG_SYS_NAND_SPL_SIZE
CONFIG_SYS_NAND_USE_FLASH_BBT
CONFIG_SYS_NOR_AMASK
CONFIG_SYS_NOR_AMASK_EARLY
CONFIG_SYS_NOR_BR_PRELIM
-CONFIG_SYS_NOR_CS
CONFIG_SYS_NOR_CSOR
CONFIG_SYS_NOR_CSPR
CONFIG_SYS_NOR_CSPR_EXT
CONFIG_SYS_NUM_I2C_BUSES
CONFIG_SYS_NUM_IRQS
CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-CONFIG_SYS_NVRAM_BASE
CONFIG_SYS_NVRAM_BASE_ADDR
CONFIG_SYS_NVRAM_SIZE
CONFIG_SYS_OBIR
-CONFIG_SYS_OCM_BASE
-CONFIG_SYS_OCM_DATA_ADDR
-CONFIG_SYS_OCM_DATA_SIZE
-CONFIG_SYS_OCM_SIZE
-CONFIG_SYS_OCM_STATUS_ADDR
-CONFIG_SYS_OCM_STATUS_FAIL
-CONFIG_SYS_OCM_STATUS_MASK
-CONFIG_SYS_OCM_STATUS_OK
CONFIG_SYS_OHCI_BE_CONTROLLER
CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-CONFIG_SYS_OHCI_USE_NPS
CONFIG_SYS_OMAP24_I2C_SLAVE
CONFIG_SYS_OMAP24_I2C_SLAVE1
CONFIG_SYS_OMAP24_I2C_SLAVE2
CONFIG_SYS_ONENAND_BASE
CONFIG_SYS_ONENAND_BLOCK_SIZE
CONFIG_SYS_ONENAND_PAGE_SIZE
-CONFIG_SYS_OPER_FLASH
CONFIG_SYS_OR0_64M
CONFIG_SYS_OR0_8M
CONFIG_SYS_OR0_PRELIM
CONFIG_SYS_PBI_FLASH_BASE
CONFIG_SYS_PBI_FLASH_WINDOW
CONFIG_SYS_PBSIZE
-CONFIG_SYS_PB_LED
CONFIG_SYS_PCA953X_BRD_CFG0
CONFIG_SYS_PCA953X_BRD_CFG1
CONFIG_SYS_PCA953X_BRD_CFG2
CONFIG_SYS_PCDAT
CONFIG_SYS_PCDDR
CONFIG_SYS_PCI
-CONFIG_SYS_PCI0_IO_SPACE
CONFIG_SYS_PCI1_ADDR
CONFIG_SYS_PCI1_IO_BASE
CONFIG_SYS_PCI1_IO_BUS
CONFIG_SYS_PCI2_MMIO_PHYS
CONFIG_SYS_PCI2_MMIO_SIZE
CONFIG_SYS_PCI64_MEMORY_BUS
-CONFIG_SYS_PCI9054_IOBASE
CONFIG_SYS_PCIE
-CONFIG_SYS_PCIE0_CFGBASE
-CONFIG_SYS_PCIE0_CFGMASK
-CONFIG_SYS_PCIE0_MEMBASE
-CONFIG_SYS_PCIE0_REGBASE
-CONFIG_SYS_PCIE0_UTLBASE
-CONFIG_SYS_PCIE0_XCFGBASE
CONFIG_SYS_PCIE1_ADDR
CONFIG_SYS_PCIE1_BASE
-CONFIG_SYS_PCIE1_CFGBASE
-CONFIG_SYS_PCIE1_CFGMASK
CONFIG_SYS_PCIE1_CFG_BASE
CONFIG_SYS_PCIE1_CFG_SIZE
CONFIG_SYS_PCIE1_IO_BASE
CONFIG_SYS_PCIE1_IO_PHYS_LOW
CONFIG_SYS_PCIE1_IO_SIZE
CONFIG_SYS_PCIE1_IO_VIRT
-CONFIG_SYS_PCIE1_MEMBASE
CONFIG_SYS_PCIE1_MEM_BASE
CONFIG_SYS_PCIE1_MEM_BUS
CONFIG_SYS_PCIE1_MEM_PHYS
CONFIG_SYS_PCIE1_PHYS_ADDR
CONFIG_SYS_PCIE1_PHYS_BASE
CONFIG_SYS_PCIE1_PHYS_SIZE
-CONFIG_SYS_PCIE1_REGBASE
-CONFIG_SYS_PCIE1_UTLBASE
CONFIG_SYS_PCIE1_VIRT_ADDR
-CONFIG_SYS_PCIE1_XCFGBASE
CONFIG_SYS_PCIE2_ADDR
CONFIG_SYS_PCIE2_BASE
-CONFIG_SYS_PCIE2_CFGBASE
CONFIG_SYS_PCIE2_CFG_BASE
CONFIG_SYS_PCIE2_CFG_SIZE
CONFIG_SYS_PCIE2_IO_BASE
CONFIG_SYS_PCIE2_PHYS_ADDR
CONFIG_SYS_PCIE2_PHYS_BASE
CONFIG_SYS_PCIE2_PHYS_SIZE
-CONFIG_SYS_PCIE2_REGBASE
CONFIG_SYS_PCIE2_VIRT_ADDR
-CONFIG_SYS_PCIE2_XCFGBASE
CONFIG_SYS_PCIE3_ADDR
CONFIG_SYS_PCIE3_IO_BUS
CONFIG_SYS_PCIE3_IO_PHYS
CONFIG_SYS_PCIE4_NAME
CONFIG_SYS_PCIE4_PHYS_ADDR
CONFIG_SYS_PCIE4_PHYS_SIZE
-CONFIG_SYS_PCIE_ADDR_HIGH
-CONFIG_SYS_PCIE_BASE
-CONFIG_SYS_PCIE_INBOUND_BASE
-CONFIG_SYS_PCIE_MEMBASE
-CONFIG_SYS_PCIE_MEMSIZE
CONFIG_SYS_PCIE_MMAP_SIZE
-CONFIG_SYS_PCIE_NR_PORTS
CONFIG_SYS_PCIE_PHYS
CONFIG_SYS_PCIE_VIRT
CONFIG_SYS_PCI_64BIT
CONFIG_SYS_PCI_BAR3
CONFIG_SYS_PCI_BAR4
CONFIG_SYS_PCI_BAR5
-CONFIG_SYS_PCI_BASE
-CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
CONFIG_SYS_PCI_CACHE_LINE_SIZE
CONFIG_SYS_PCI_CFG_BASE
CONFIG_SYS_PCI_CFG_BUS
CONFIG_SYS_PCI_CFG_PHYS
CONFIG_SYS_PCI_CFG_SIZE
-CONFIG_SYS_PCI_CLASSCODE
-CONFIG_SYS_PCI_CLASSCODE_MONARCH
-CONFIG_SYS_PCI_CLASSCODE_NONMONARCH
CONFIG_SYS_PCI_EP_MEMORY_BASE
-CONFIG_SYS_PCI_FORCE_PCI_CONV
CONFIG_SYS_PCI_IO_BASE
CONFIG_SYS_PCI_IO_BUS
CONFIG_SYS_PCI_IO_PHYS
CONFIG_SYS_PCI_IO_SIZE
CONFIG_SYS_PCI_MAP_END
CONFIG_SYS_PCI_MAP_START
-CONFIG_SYS_PCI_MASTER_INIT
-CONFIG_SYS_PCI_MEMBASE
-CONFIG_SYS_PCI_MEMBASE1
-CONFIG_SYS_PCI_MEMBASE2
-CONFIG_SYS_PCI_MEMBASE3
CONFIG_SYS_PCI_MEMORY_BUS
CONFIG_SYS_PCI_MEMORY_PHYS
CONFIG_SYS_PCI_MEMORY_SIZE
-CONFIG_SYS_PCI_MEMSIZE
CONFIG_SYS_PCI_MEM_BASE
CONFIG_SYS_PCI_MEM_BUS
CONFIG_SYS_PCI_MEM_PHYS
CONFIG_SYS_PCI_MMIO_SIZE
CONFIG_SYS_PCI_NR_INBOUND_WIN
CONFIG_SYS_PCI_PHYS
-CONFIG_SYS_PCI_PTM1LA
-CONFIG_SYS_PCI_PTM1MS
-CONFIG_SYS_PCI_PTM1PCI
-CONFIG_SYS_PCI_PTM2LA
-CONFIG_SYS_PCI_PTM2MS
-CONFIG_SYS_PCI_PTM2PCI
CONFIG_SYS_PCI_SLV_MEM_BUS
CONFIG_SYS_PCI_SLV_MEM_LOCAL
CONFIG_SYS_PCI_SLV_MEM_SIZE
-CONFIG_SYS_PCI_SUBSYS_DEVICEID
-CONFIG_SYS_PCI_SUBSYS_DEVICEID2
-CONFIG_SYS_PCI_SUBSYS_ID
-CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
-CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH
CONFIG_SYS_PCI_SUBSYS_VENDORID
CONFIG_SYS_PCI_SYS_MEM_BUS
CONFIG_SYS_PCI_SYS_MEM_PHYS
CONFIG_SYS_PCI_SYS_MEM_SIZE
-CONFIG_SYS_PCI_TARGBASE
-CONFIG_SYS_PCI_TARGET_INIT
CONFIG_SYS_PCI_TBATR0
CONFIG_SYS_PCI_TBATR1
CONFIG_SYS_PCI_TBATR2
CONFIG_SYS_PDCNT
CONFIG_SYS_PEHLPAR
CONFIG_SYS_PEPAR
-CONFIG_SYS_PERIPHERAL_BASE
-CONFIG_SYS_PFC0
CONFIG_SYS_PFPAR
CONFIG_SYS_PHYS_ADDR_HIGH
CONFIG_SYS_PHY_UBOOT_BASE
CONFIG_SYS_PLL_BYPASS
CONFIG_SYS_PLL_FDR
CONFIG_SYS_PLL_ODR
-CONFIG_SYS_PLL_RECONFIG
CONFIG_SYS_PLL_SETTLING_TIME
CONFIG_SYS_PLUG_BASE
CONFIG_SYS_PMAN
CONFIG_SYS_POST_BSPEC4
CONFIG_SYS_POST_BSPEC5
CONFIG_SYS_POST_CACHE
-CONFIG_SYS_POST_CACHE_ADDR
CONFIG_SYS_POST_CODEC
CONFIG_SYS_POST_COPROC
CONFIG_SYS_POST_CPU
CONFIG_SYS_POST_DSP
CONFIG_SYS_POST_ECC
CONFIG_SYS_POST_ETHER
-CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
-CONFIG_SYS_POST_ETH_LOOPS
CONFIG_SYS_POST_FLASH
CONFIG_SYS_POST_FLASH_END
CONFIG_SYS_POST_FLASH_NUM
CONFIG_SYS_POST_FLASH_START
CONFIG_SYS_POST_FPU
-CONFIG_SYS_POST_FPU_ON
CONFIG_SYS_POST_HOTKEYS_GPIO
CONFIG_SYS_POST_I2C
CONFIG_SYS_POST_I2C_ADDRS
CONFIG_SYS_POST_I2C_IGNORES
CONFIG_SYS_POST_MEMORY
-CONFIG_SYS_POST_MEMORY_ON
CONFIG_SYS_POST_MEM_REGIONS
CONFIG_SYS_POST_OCM
CONFIG_SYS_POST_PREREL
CONFIG_SYS_POST_SPR
CONFIG_SYS_POST_SYSMON
CONFIG_SYS_POST_UART
-CONFIG_SYS_POST_UART_TABLE
CONFIG_SYS_POST_USB
CONFIG_SYS_POST_WATCHDOG
CONFIG_SYS_POST_WORD_ADDR
CONFIG_SYS_POWER_MANAGER
-CONFIG_SYS_PPC4XX_USB_ADDR
CONFIG_SYS_PPC_DDR_WIMGE
CONFIG_SYS_PQSPAR
CONFIG_SYS_PRELIM_OR_AM
CONFIG_SYS_REDUNDAND_ENVIRONMENT
CONFIG_SYS_RESET_ADDR
CONFIG_SYS_RESET_ADDRESS
-CONFIG_SYS_RESET_BASE
CONFIG_SYS_RESET_SCTRL
CONFIG_SYS_RFD
CONFIG_SYS_RGMII1_PHY_ADDR
CONFIG_SYS_RIO_MEM_SIZE
CONFIG_SYS_RIO_MEM_VIRT
CONFIG_SYS_ROM_BASE
-CONFIG_SYS_ROOTPATH
CONFIG_SYS_RSTC_RMR_VAL
CONFIG_SYS_RTC_BUS_NUM
CONFIG_SYS_RTC_CNT
CONFIG_SYS_SDIO_BASE2
CONFIG_SYS_SDIO_BASE3
CONFIG_SYS_SDRAM
-CONFIG_SYS_SDRAM0_CFG0
-CONFIG_SYS_SDRAM0_CLKTR
-CONFIG_SYS_SDRAM0_CODT
-CONFIG_SYS_SDRAM0_DLCR
-CONFIG_SYS_SDRAM0_INITPLR0
-CONFIG_SYS_SDRAM0_INITPLR1
-CONFIG_SYS_SDRAM0_INITPLR10
-CONFIG_SYS_SDRAM0_INITPLR11
-CONFIG_SYS_SDRAM0_INITPLR12
-CONFIG_SYS_SDRAM0_INITPLR13
-CONFIG_SYS_SDRAM0_INITPLR14
-CONFIG_SYS_SDRAM0_INITPLR15
-CONFIG_SYS_SDRAM0_INITPLR2
-CONFIG_SYS_SDRAM0_INITPLR3
-CONFIG_SYS_SDRAM0_INITPLR4
-CONFIG_SYS_SDRAM0_INITPLR5
-CONFIG_SYS_SDRAM0_INITPLR6
-CONFIG_SYS_SDRAM0_INITPLR7
-CONFIG_SYS_SDRAM0_INITPLR8
-CONFIG_SYS_SDRAM0_INITPLR9
-CONFIG_SYS_SDRAM0_MB0CF
-CONFIG_SYS_SDRAM0_MB0CF_BASE
-CONFIG_SYS_SDRAM0_MB1CF
-CONFIG_SYS_SDRAM0_MB1CF_BASE
-CONFIG_SYS_SDRAM0_MB2CF
-CONFIG_SYS_SDRAM0_MB3CF
-CONFIG_SYS_SDRAM0_MCOPT1
-CONFIG_SYS_SDRAM0_MCOPT2
-CONFIG_SYS_SDRAM0_MEMODE
-CONFIG_SYS_SDRAM0_MMODE
-CONFIG_SYS_SDRAM0_MODT0
-CONFIG_SYS_SDRAM0_MODT1
-CONFIG_SYS_SDRAM0_MODT2
-CONFIG_SYS_SDRAM0_MODT3
-CONFIG_SYS_SDRAM0_RDCC
-CONFIG_SYS_SDRAM0_RFDC
-CONFIG_SYS_SDRAM0_RQDC
-CONFIG_SYS_SDRAM0_RTR
-CONFIG_SYS_SDRAM0_SDTR1
-CONFIG_SYS_SDRAM0_SDTR2
-CONFIG_SYS_SDRAM0_SDTR3
-CONFIG_SYS_SDRAM0_TR0
-CONFIG_SYS_SDRAM0_WDDCTR
-CONFIG_SYS_SDRAM0_WRDTR
CONFIG_SYS_SDRAM1
-CONFIG_SYS_SDRAM_BANKS
CONFIG_SYS_SDRAM_BASE
CONFIG_SYS_SDRAM_BASE0
CONFIG_SYS_SDRAM_BASE1
CONFIG_SYS_SDRAM_BASE1xx
CONFIG_SYS_SDRAM_BASE2
-CONFIG_SYS_SDRAM_CASL
CONFIG_SYS_SDRAM_CFG
CONFIG_SYS_SDRAM_CFG1
CONFIG_SYS_SDRAM_CFG2
-CONFIG_SYS_SDRAM_CL
-CONFIG_SYS_SDRAM_CONF1HB
-CONFIG_SYS_SDRAM_CONF1LL
-CONFIG_SYS_SDRAM_CONFPATHB
-CONFIG_SYS_SDRAM_CTP
CONFIG_SYS_SDRAM_CTRL
CONFIG_SYS_SDRAM_DRVSTRENGTH
CONFIG_SYS_SDRAM_DRV_STRENGTH
CONFIG_SYS_SDRAM_EMOD
-CONFIG_SYS_SDRAM_LDF
CONFIG_SYS_SDRAM_LOWER
CONFIG_SYS_SDRAM_MODE
-CONFIG_SYS_SDRAM_PLBADDUHB
-CONFIG_SYS_SDRAM_PLBADDULL
-CONFIG_SYS_SDRAM_PTA
-CONFIG_SYS_SDRAM_R0BAS
-CONFIG_SYS_SDRAM_R1BAS
-CONFIG_SYS_SDRAM_R2BAS
-CONFIG_SYS_SDRAM_R3BAS
-CONFIG_SYS_SDRAM_RCD
-CONFIG_SYS_SDRAM_RFTA
CONFIG_SYS_SDRAM_SIZE
CONFIG_SYS_SDRAM_SIZE0
CONFIG_SYS_SDRAM_SIZE1
CONFIG_SYS_SDRAM_SIZE_LAW
-CONFIG_SYS_SDRAM_SIZE_MB
-CONFIG_SYS_SDRAM_TABLE
CONFIG_SYS_SDRAM_UPPER
CONFIG_SYS_SDRAM_VAL
CONFIG_SYS_SDRAM_VAL1
CONFIG_SYS_SDRAM_VAL7
CONFIG_SYS_SDRAM_VAL8
CONFIG_SYS_SDRAM_VAL9
-CONFIG_SYS_SDRAM_tRC
-CONFIG_SYS_SDRAM_tRCD
-CONFIG_SYS_SDRAM_tRFC
-CONFIG_SYS_SDRAM_tRP
CONFIG_SYS_SDRC_CR_VAL
CONFIG_SYS_SDRC_MDR_VAL
CONFIG_SYS_SDRC_MR_VAL
CONFIG_SYS_SD_VOLTAGE
CONFIG_SYS_SEC_MON_ADDR
CONFIG_SYS_SEC_MON_OFFSET
-CONFIG_SYS_SELF_RST
CONFIG_SYS_SERIAL0
CONFIG_SYS_SERIAL1
CONFIG_SYS_SERIAL2
CONFIG_SYS_SICRH
CONFIG_SYS_SICRL
CONFIG_SYS_SIL1178_I2C
-CONFIG_SYS_SIMULATE_SPD_EEPROM
CONFIG_SYS_SJA1000_BASE
-CONFIG_SYS_SMALL_FLASH
CONFIG_SYS_SMC0_CYCLE0_VAL
CONFIG_SYS_SMC0_MODE0_VAL
CONFIG_SYS_SMC0_PULSE0_VAL
CONFIG_SYS_SPCR_TSEC2EP
CONFIG_SYS_SPCR_TSECEP
CONFIG_SYS_SPD_BUS_NUM
-CONFIG_SYS_SPD_MAX_DIMMS
CONFIG_SYS_SPI0
CONFIG_SYS_SPI0_NUM_CS
CONFIG_SYS_SPI1
CONFIG_SYS_SPL_LEN
CONFIG_SYS_SPL_MALLOC_SIZE
CONFIG_SYS_SPL_MALLOC_START
-CONFIG_SYS_SPL_MAX_LEN
CONFIG_SYS_SPR
CONFIG_SYS_SRAM_BASE
CONFIG_SYS_SRAM_SIZE
CONFIG_SYS_SRAM_START
-CONFIG_SYS_SRGPL0_CFG_BAR
-CONFIG_SYS_SRGPL0_MNT_BAR
-CONFIG_SYS_SRGPL0_MSG_BAR
-CONFIG_SYS_SRGPL0_REG_BAR
CONFIG_SYS_SRIO
CONFIG_SYS_SRIO1_MEM_BASE
CONFIG_SYS_SRIO1_MEM_BUS
CONFIG_SYS_SYSTEMACE_WIDTH
CONFIG_SYS_TBIPA_VALUE
CONFIG_SYS_TCLK
-CONFIG_SYS_TEMP_STACK_OCM
CONFIG_SYS_TEXT_ADDR
CONFIG_SYS_TEXT_BASE_NOR
CONFIG_SYS_TEXT_BASE_SPL
CONFIG_SYS_TIMER_COUNTS_DOWN
CONFIG_SYS_TIMER_PRESCALER
CONFIG_SYS_TIMER_RATE
-CONFIG_SYS_TLB_FOR_BOOT_FLASH
CONFIG_SYS_TMPVIRT
CONFIG_SYS_TMRINTR_MASK
CONFIG_SYS_TMRINTR_NO
CONFIG_SYS_UNIFY_CACHE
CONFIG_SYS_UNSPEC_PHYID
CONFIG_SYS_UNSPEC_STRID
-CONFIG_SYS_UPDATE_FLASH_SIZE
-CONFIG_SYS_USB2D0_BASE
CONFIG_SYS_USBCTRL
CONFIG_SYS_USBD_BASE
-CONFIG_SYS_USB_DEVICE
CONFIG_SYS_USB_EHCI_CPU_INIT
CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
CONFIG_SYS_USB_EHCI_REGS_BASE
CONFIG_SYS_VSC7385_OR_PRELIM
CONFIG_SYS_VSC7385_SIZE
CONFIG_SYS_VXWORKS_MAC_PTR
-CONFIG_SYS_WATCHDOG_FLAGS_ADDR
CONFIG_SYS_WATCHDOG_FREQ
-CONFIG_SYS_WATCHDOG_MAGIC
-CONFIG_SYS_WATCHDOG_MAGIC_MASK
-CONFIG_SYS_WATCHDOG_TIME_ADDR
CONFIG_SYS_WATCHDOG_VALUE
CONFIG_SYS_WDTC_WDMR_VAL
CONFIG_SYS_WDTTIMERBASE
CONFIG_SYS_XHCI_USB3_ADDR
CONFIG_SYS_XILINX_SPI_LIST
CONFIG_SYS_XIMG_LEN
-CONFIG_SYS_XSVF_DEFAULT_ADDR
CONFIG_SYS_XWAY_EBU_BOOTCFG
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_TX_DESCR_NUM
CONFIG_TZSW_RESERVED_DRAM_SIZE
CONFIG_T_SH7706LSR
-CONFIG_UART_BASE
CONFIG_UART_BR_PRELIM
CONFIG_UART_OR_PRELIM
CONFIG_UBIBLOCK
CONFIG_UBOOT2_ENV_ADDR
CONFIG_UBOOTPATH
CONFIG_UBOOT_ENABLE_PADS_ALL
-CONFIG_UBOOT_ENV_ADDR
CONFIG_UBOOT_SECTOR_COUNT
CONFIG_UBOOT_SECTOR_START
CONFIG_UCP1020
CONFIG_USB_EHCI_MXC
CONFIG_USB_EHCI_MXS
CONFIG_USB_EHCI_PCI
-CONFIG_USB_EHCI_PPC4XX
CONFIG_USB_EHCI_RMOBILE
CONFIG_USB_EHCI_SPEAR
CONFIG_USB_EHCI_SUNXI
CONFIG_USB_TI_CPPI_DMA
CONFIG_USB_TTY
CONFIG_USB_TUSB_OMAP_DMA
-CONFIG_USB_UHCI
CONFIG_USB_ULPI_TIMEOUT
CONFIG_USB_XHCI_EXYNOS
CONFIG_USB_XHCI_FSL
CONFIG_USE_FDT
CONFIG_USE_INTERRUPT
CONFIG_USE_NAND
-CONFIG_USE_NETDEV
CONFIG_USE_NOR
CONFIG_USE_ONENAND_BOARD_INIT
CONFIG_USE_SPIFLASH
CONFIG_USE_STDINT
-CONFIG_USE_TTY
CONFIG_UTBIPAR_INIT_TBIPA
CONFIG_U_BOOT_HDR_ADDR
CONFIG_U_BOOT_HDR_SIZE
CONFIG_VIDEO_MXS_MODE_SYSTEM
CONFIG_VIDEO_OMAP3
CONFIG_VIDEO_ONBOARD
-CONFIG_VIDEO_SM501
-CONFIG_VIDEO_SM501_32BPP
CONFIG_VIDEO_SM501_PCI
CONFIG_VIDEO_STD_TIMINGS
CONFIG_VIDEO_SUNXI
CONFIG_VOL_MONITOR_INA220
CONFIG_VOL_MONITOR_IR36021_READ
CONFIG_VOL_MONITOR_IR36021_SET
-CONFIG_VOM405
CONFIG_VSC7385_ENET
CONFIG_VSC7385_IMAGE
CONFIG_VSC7385_IMAGE_SIZE
CONFIG_VSC9953
CONFIG_VSC_CROSSBAR
-CONFIG_WALNUT
CONFIG_WATCHDOG
CONFIG_WATCHDOG_BASEADDR
CONFIG_WATCHDOG_IRQ
CONFIG_WATCHDOG_RC
CONFIG_WATCHDOG_TIMEOUT
CONFIG_WATCHDOG_TIMEOUT_MSECS
-CONFIG_WD_MAX_RATE
CONFIG_WD_PERIOD
CONFIG_X600
CONFIG_X86EMU_DEBUG
CONFIG_X86_REFCODE_ADDR
CONFIG_X86_REFCODE_RUN_ADDR
CONFIG_XGI_XG22_BASE
-CONFIG_XILINX_405
-CONFIG_XILINX_440
CONFIG_XILINX_GPIO
-CONFIG_XILINX_LL_TEMAC
CONFIG_XILINX_LL_TEMAC_CLK
-CONFIG_XILINX_PPC440_GENERIC
CONFIG_XILINX_SPI_IDLE_VAL
CONFIG_XILINX_TB_WATCHDOG
-CONFIG_XPEDITE1000
CONFIG_XPEDITE5140
CONFIG_XPEDITE5200
CONFIG_XPEDITE550X
CONFIG_YAFFS_UNICODE
CONFIG_YAFFS_UTIL
CONFIG_YAFFS_WINCE
-CONFIG_YELLOWSTONE
CONFIG_YELLOW_LED
-CONFIG_YOSEMITE
CONFIG_ZC770_XM010
CONFIG_ZC770_XM011
CONFIG_ZC770_XM012
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