iomux-v3: Add support for mx6sl LVE bit

On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL
register that can enable or disable low voltage on the pad.

LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the
calculation easier we can define it as a flag in bit 1, since this bit is unused.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index b59b802830677b240af7ce915394b41a8a1a1831..6e46ea8dcdeb0d762626faec9c8e3d649e9f9b17 100644 (file)
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
                (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
        u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 
+#if defined CONFIG_MX6SL
+       /* Check whether LVE bit needs to be set */
+       if (pad_ctrl & PAD_CTL_LVE) {
+               pad_ctrl &= ~PAD_CTL_LVE;
+               pad_ctrl |= PAD_CTL_LVE_BIT;
+       }
+#endif
+
        if (mux_ctrl_ofs)
                __raw_writel(mux_mode, base + mux_ctrl_ofs);
 

diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index dec11a133044bd54bf54a92a876ca3c0cc04cfa3..cca920b28ecfd1e527ec66a66ce729bf4741ec1f 100644 (file)
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -111,6 +111,11 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_DSE_40ohm      (6 << 3)
 #define PAD_CTL_DSE_34ohm      (7 << 3)
 
+#if defined CONFIG_MX6SL
+#define PAD_CTL_LVE            (1 << 1)
+#define PAD_CTL_LVE_BIT                (1 << 22)
+#endif
+
 #elif defined(CONFIG_VF610)
 
 #define PAD_MUX_MODE_SHIFT     20