prompt "Select STMicroelectronics STM32MPxxx Soc"
default STM32MP15x
+config STM32MP13x
+ bool "Support STMicroelectronics STM32MP13x Soc"
+ select ARM_SMCCC
+ select CPU_V7A
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select OF_BOARD
+ select OF_BOARD_SETUP
+ select PINCTRL_STM32
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SERIAL
+ select SYS_ARCH_TIMER
+ imply CMD_NVEDIT_INFO
+ help
+ support of STMicroelectronics SOC STM32MP13x family
+ STMicroelectronics MPU with core ARMv7
+
config STM32MP15x
bool "Support STMicroelectronics STM32MP15x Soc"
select ARCH_SUPPORT_PSCI
config STM32_ETZPC
bool "STM32 Extended TrustZone Protection"
- depends on STM32MP15x
+ depends on STM32MP15x || STM32MP13x
default y
imply BOOTP_SERVERIP
help
This command is used to evaluate the secure boot on stm32mp SOC,
it is deactivated by default in real products.
+source "arch/arm/mach-stm32mp/Kconfig.13x"
source "arch/arm/mach-stm32mp/Kconfig.15x"
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
--- /dev/null
+if STM32MP13x
+
+choice
+ prompt "STM32MP13x board select"
+ optional
+
+config TARGET_ST_STM32MP13x
+ bool "STMicroelectronics STM32MP13x boards"
+ imply BOOTSTAGE
+ imply CMD_BOOTSTAGE
+ imply CMD_CLS if CMD_BMP
+ imply DISABLE_CONSOLE
+ imply PRE_CONSOLE_BUFFER
+ imply SILENT_CONSOLE
+ help
+ target the STMicroelectronics board with SOC STM32MP13x
+ managed by board/st/stm32mp1.
+ The difference between board are managed with devicetree
+
+endchoice
+
+config SYS_TEXT_BASE
+ default 0xC0000000
+
+config PRE_CON_BUF_ADDR
+ default 0xC0800000
+
+config PRE_CON_BUF_SZ
+ default 4096
+
+config BOOTSTAGE_STASH_ADDR
+ default 0xC3000000
+
+if BOOTCOUNT_GENERIC
+config SYS_BOOTCOUNT_SINGLEWORD
+ default y
+
+# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(31)
+config SYS_BOOTCOUNT_ADDR
+ default 0x5C00A17C
+endif
+
+if DEBUG_UART
+
+# debug on UART4 by default
+config DEBUG_UART_BASE
+ default 0x40010000
+
+# clock source is HSI on reset
+config DEBUG_UART_CLOCK
+ default 48000000 if STM32_FPGA
+ default 64000000
+endif
+
+source "board/st/stm32mp1/Kconfig"
+
+endif
obj-y += syscon.o
obj-y += bsec.o
+obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
ifdef CONFIG_SPL_BUILD
enum dcache_option option;
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+/* STM32_SYSRAM_BASE exist only when SPL is supported */
+#ifdef CONFIG_SPL
start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
+#endif
} else if (gd->flags & GD_FLG_RELOC) {
/* bd->bi_dram is available only after relocation */
start = bd->bi_dram[bank].start;
u32 pkg, cpu;
char name[SOC_NAME_SIZE];
+ if (IS_ENABLED(CONFIG_STM32MP13x))
+ return 0;
+
soc = fdt_path_offset(blob, "/soc");
/* when absent, nothing to do */
if (soc == -FDT_ERR_NOTFOUND)
#define STM32_RCC_BASE 0x50000000
#define STM32_PWR_BASE 0x50001000
#define STM32_SYSCFG_BASE 0x50020000
+#ifdef CONFIG_STM32MP15x
#define STM32_DBGMCU_BASE 0x50081000
+#endif
#define STM32_FMC2_BASE 0x58002000
#define STM32_DDRCTRL_BASE 0x5A003000
#define STM32_DDRPHYC_BASE 0x5A004000
#define STM32_STGEN_BASE 0x5C008000
#define STM32_TAMP_BASE 0x5C00A000
+#ifdef CONFIG_STM32MP15x
#define STM32_USART1_BASE 0x5C000000
#define STM32_USART2_BASE 0x4000E000
+#endif
+#ifdef CONFIG_STM32MP13x
+#define STM32_USART1_BASE 0x4c000000
+#define STM32_USART2_BASE 0x4c001000
+#endif
#define STM32_USART3_BASE 0x4000F000
#define STM32_UART4_BASE 0x40010000
#define STM32_UART5_BASE 0x40011000
#define STM32_SDMMC2_BASE 0x58007000
#define STM32_SDMMC3_BASE 0x48004000
+#ifdef CONFIG_STM32MP15x
#define STM32_SYSRAM_BASE 0x2FFC0000
#define STM32_SYSRAM_SIZE SZ_256K
+#endif
#define STM32_DDR_BASE 0xC0000000
#define STM32_DDR_SIZE SZ_1G
/* TAMP registers */
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
+
+#ifdef CONFIG_STM32MP15x
#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
#define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17)
#define TAMP_COPRO_STATE_CSTOP 3
#define TAMP_COPRO_STATE_STANDBY 4
#define TAMP_COPRO_STATE_CRASH 5
+#endif
+
+#ifdef CONFIG_STM32MP13x
+#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31)
+#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30)
+#endif
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
#define TAMP_BOOT_MODE_SHIFT 8
#define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4)
/* BSEC OTP index */
+#ifdef CONFIG_STM32MP15x
#define BSEC_OTP_RPN 1
#define BSEC_OTP_SERIAL 13
#define BSEC_OTP_PKG 16
#define BSEC_OTP_MAC 57
#define BSEC_OTP_BOARD 59
+#endif
+#ifdef CONFIG_STM32MP13x
+#define BSEC_OTP_RPN 1
+#define BSEC_OTP_SERIAL 13
+#define BSEC_OTP_MAC 57
+#define BSEC_OTP_BOARD 60
+#endif
#endif /* __ASSEMBLY__ */
#endif /* _MACH_STM32_H_ */
* Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
*/
-/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) */
+/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */
#define CPU_STM32MP157Cxx 0x05000000
#define CPU_STM32MP157Axx 0x05000001
#define CPU_STM32MP153Cxx 0x05000024
#define CPU_STM32MP151Fxx 0x050000AE
#define CPU_STM32MP151Dxx 0x050000AF
+#define CPU_STM32MP135Cxx 0x05010000
+#define CPU_STM32MP135Axx 0x05010001
+#define CPU_STM32MP133Cxx 0x050100C0
+#define CPU_STM32MP133Axx 0x050100C1
+#define CPU_STM32MP131Cxx 0x050106C8
+#define CPU_STM32MP131Axx 0x050106C9
+#define CPU_STM32MP135Fxx 0x05010800
+#define CPU_STM32MP135Dxx 0x05010801
+#define CPU_STM32MP133Fxx 0x050108C0
+#define CPU_STM32MP133Dxx 0x050108C1
+#define CPU_STM32MP131Fxx 0x05010EC8
+#define CPU_STM32MP131Dxx 0x05010EC9
+
/* return CPU_STMP32MP...Xxx constants */
u32 get_cpu_type(void);
#define CPU_DEV_STM32MP15 0x500
+#define CPU_DEV_STM32MP13 0x501
/* return CPU_DEV constants */
u32 get_cpu_dev(void);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <common.h>
+#include <log.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+
+/* SYSCFG register */
+#define SYSCFG_IDC_OFFSET 0x380
+#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0)
+#define SYSCFG_IDC_DEV_ID_SHIFT 0
+#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16)
+#define SYSCFG_IDC_REV_ID_SHIFT 16
+
+/* Device Part Number (RPN) = OTP_DATA1 lower 11 bits */
+#define RPN_SHIFT 0
+#define RPN_MASK GENMASK(11, 0)
+
+static u32 read_idc(void)
+{
+ void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+ return readl(syscfg + SYSCFG_IDC_OFFSET);
+}
+
+u32 get_cpu_dev(void)
+{
+ return (read_idc() & SYSCFG_IDC_DEV_ID_MASK) >> SYSCFG_IDC_DEV_ID_SHIFT;
+}
+
+u32 get_cpu_rev(void)
+{
+ return (read_idc() & SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT;
+}
+
+/* Get Device Part Number (RPN) from OTP */
+static u32 get_cpu_rpn(void)
+{
+ return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
+}
+
+u32 get_cpu_type(void)
+{
+ return (get_cpu_dev() << 16) | get_cpu_rpn();
+}
+
+void get_soc_name(char name[SOC_NAME_SIZE])
+{
+ char *cpu_s, *cpu_r;
+
+ /* MPUs Part Numbers */
+ switch (get_cpu_type()) {
+ case CPU_STM32MP135Fxx:
+ cpu_s = "135F";
+ break;
+ case CPU_STM32MP135Dxx:
+ cpu_s = "135D";
+ break;
+ case CPU_STM32MP135Cxx:
+ cpu_s = "135C";
+ break;
+ case CPU_STM32MP135Axx:
+ cpu_s = "135A";
+ break;
+ case CPU_STM32MP133Fxx:
+ cpu_s = "133F";
+ break;
+ case CPU_STM32MP133Dxx:
+ cpu_s = "133D";
+ break;
+ case CPU_STM32MP133Cxx:
+ cpu_s = "133C";
+ break;
+ case CPU_STM32MP133Axx:
+ cpu_s = "133A";
+ break;
+ case CPU_STM32MP131Fxx:
+ cpu_s = "131F";
+ break;
+ case CPU_STM32MP131Dxx:
+ cpu_s = "131D";
+ break;
+ case CPU_STM32MP131Cxx:
+ cpu_s = "131C";
+ break;
+ case CPU_STM32MP131Axx:
+ cpu_s = "131A";
+ break;
+ default:
+ cpu_s = "????";
+ break;
+ }
+
+ /* REVISION */
+ switch (get_cpu_rev()) {
+ case CPU_REV1:
+ cpu_r = "A";
+ break;
+ case CPU_REV1_1:
+ cpu_r = "Z";
+ break;
+ default:
+ cpu_r = "?";
+ break;
+ }
+
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s Rev.%s", cpu_s, cpu_r);
+}
source "board/st/common/Kconfig"
endif
+
+if TARGET_ST_STM32MP13x
+
+config SYS_BOARD
+ default "stm32mp1"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_CONFIG_NAME
+ default "stm32mp13_st_common"
+
+source "board/st/common/Kconfig"
+
+endif
F: configs/stm32mp15_defconfig
F: configs/stm32mp15_basic_defconfig
F: configs/stm32mp15_trusted_defconfig
+F: include/configs/stm32mp13_common.h
+F: include/configs/stm32mp13_st_common.h
F: include/configs/stm32mp15_common.h
F: include/configs/stm32mp15_st_common.h
CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_CMD_STM32KEY=y
-CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_TYPEC_STUSB160X=y
+CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_CMD_STM32PROG=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
CONFIG_CMD_STM32KEY=y
-CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_TYPEC_STUSB160X=y
+CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_ENV_OFFSET_REDUND=0x4C0000
CONFIG_CMD_STM32PROG=y
# CONFIG_ARMV7_NONSEC is not set
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
CONFIG_CMD_STM32KEY=y
+CONFIG_TYPEC_STUSB160X=y
CONFIG_STM32MP15x_STM32IMAGE=y
CONFIG_TARGET_ST_STM32MP15x=y
-CONFIG_TYPEC_STUSB160X=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_CMD_STM32PROG=y
# CONFIG_ARMV7_NONSEC is not set
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STM32MP13x CPU
+ */
+
+#ifndef __CONFIG_STM32MP13_COMMMON_H
+#define __CONFIG_STM32MP13_COMMMON_H
+#include <linux/sizes.h>
+#include <asm/arch/stm32.h>
+
+/*
+ * Configuration of the external SRAM memory used by U-Boot
+ */
+#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
+
+/*
+ * For booting Linux, use the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ SZ_256M
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN SZ_32M
+
+/*MMC SD*/
+#define CONFIG_SYS_MMC_MAX_DEVICE 2
+
+/* NAND support */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/*****************************************************************************/
+#ifdef CONFIG_DISTRO_DEFAULTS
+/*****************************************************************************/
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0)
+#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1)
+#else
+#define BOOT_TARGET_MMC0(func)
+#define BOOT_TARGET_MMC1(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_MMC1(func) \
+ BOOT_TARGET_MMC0(func)
+
+/*
+ * default bootcmd for stm32mp13:
+ * for mmc boot (eMMC, SD card), distro boot on the same mmc device
+ */
+#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
+ "echo \"Boot over ${boot_device}${boot_instance}!\";" \
+ "run env_check;" \
+ "if test ${boot_device} = mmc;" \
+ "then env set boot_targets \"mmc${boot_instance}\"; fi;" \
+ "run distro_bootcmd;" \
+ "fi;\0"
+
+#define STM32MP_EXTRA \
+ "env_check=if env info -p -d -q; then env save; fi\0" \
+ "boot_net_usb_start=true\0"
+
+#ifndef STM32MP_BOARD_EXTRA_ENV
+#define STM32MP_BOARD_EXTRA_ENV
+#endif
+
+#include <config_distro_bootcmd.h>
+
+/*
+ * memory layout for 32M uncompressed/compressed kernel,
+ * 1M fdt, 1M script, 1M pxe and 1M for overlay
+ * and the ramdisk at the end.
+ */
+#define __KERNEL_ADDR_R __stringify(0xc2000000)
+#define __FDT_ADDR_R __stringify(0xc4000000)
+#define __SCRIPT_ADDR_R __stringify(0xc4100000)
+#define __PXEFILE_ADDR_R __stringify(0xc4200000)
+#define __FDTOVERLAY_ADDR_R __stringify(0xc4300000)
+#define __RAMDISK_ADDR_R __stringify(0xc4400000)
+
+#define STM32MP_MEM_LAYOUT \
+ "kernel_addr_r=" __KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" __FDT_ADDR_R "\0" \
+ "scriptaddr=" __SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \
+ "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \
+ "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ STM32MP_MEM_LAYOUT \
+ STM32MP_BOOTCMD \
+ BOOTENV \
+ STM32MP_EXTRA \
+ STM32MP_BOARD_EXTRA_ENV
+
+#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
+
+#endif /* __CONFIG_STM32MP13_COMMMON_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STMicroelectronics STM32MP13x boards
+ */
+
+#ifndef __CONFIG_STM32MP13_ST_COMMON_H__
+#define __CONFIG_STM32MP13_ST_COMMON_H__
+
+#define STM32MP_BOARD_EXTRA_ENV \
+ "usb_pgood_delay=1000\0" \
+ "console=ttySTM0\0"
+
+#include <configs/stm32mp13_common.h>
+
+#endif
BOOT_TARGET_PXE(func)
/*
- * default bootcmd for stm32mp1:
+ * default bootcmd for stm32mp15:
* for serial/usb: execute the stm32prog command
* for mmc boot (eMMC, SD card), distro boot on the same mmc device
* for nand or spi-nand boot, distro boot with ubifs on UBI partition
projects / u-boot.git / commitdiff