riscv: Clear pending interrupts before enabling IPIs

On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 5f1c220e0ca84102581ed1fa95e80013cbdc83b3..f408e41ab9dc74311acf7386817dc2df16663996 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -65,6 +65,8 @@ _start:
 #else
        li      t0, SIE_SSIE
 #endif
+       /* Clear any pending IPIs */
+       csrc    MODE_PREFIX(ip), t0
        csrs    MODE_PREFIX(ie), t0
 #endif