armv8: mmu: fix page table mapping

To page mapping the lowest 2 bits needs to be 0x3.
If not fix this, the final lowest 3 bits for page mapping is 0x1
which is marked as reserved.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index adc7e1746f5ca01bea6487da069167a92f762182..6548f3c9121f2bfe3823259a65b0c5bcc53735f2 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -230,7 +230,10 @@ static void add_map(struct mm_region *map)
                                /* Page fits, create block PTE */
                                debug("Setting PTE %p to block virt=%llx\n",
                                      pte, virt);
-                               *pte = phys | attrs;
+                               if (level == 3)
+                                       *pte = phys | attrs | PTE_TYPE_PAGE;
+                               else
+                                       *pte = phys | attrs;
                                virt += blocksize;
                                phys += blocksize;
                                size -= blocksize;

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 6121aab547fc8a0f8015c05479ef8b4ef77edc35..765914c7e269f03adf1d1d9ead59bd21d2f86ee8 100644 (file)
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -43,6 +43,7 @@
 #define PTE_TYPE_MASK          (3 << 0)
 #define PTE_TYPE_FAULT         (0 << 0)
 #define PTE_TYPE_TABLE         (3 << 0)
+#define PTE_TYPE_PAGE          (3 << 0)
 #define PTE_TYPE_BLOCK         (1 << 0)
 #define PTE_TYPE_VALID         (1 << 0)