riscv: mbv: Align addresses with default DT

Better to align everything with memory map described in DT to avoid
mistakes. Execute both modes form the same address to make address map more
understandable.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/be54c668d5626ccd702507a86c2a95d1eaefc690.1707911544.git.michal.simek@amd.com

diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig
index 4bc9f72c541bf9300783b06d9d31f6ae125072af..553c2320697d45894895a0cda26bde49bbd33e5e 100644 (file)
--- a/board/xilinx/mbv/Kconfig
+++ b/board/xilinx/mbv/Kconfig
@@ -13,8 +13,7 @@ config SYS_CONFIG_NAME
        default "xilinx_mbv"
 
 config TEXT_BASE
-       default 0x80000000 if !RISCV_SMODE
-       default 0x80400000 if RISCV_SMODE && ARCH_RV32I
+       default 0x21200000
 
 config BOARD_SPECIFIC_OPTIONS
        def_bool y

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 2689495057b0e1004462f0b21f9af7c419bf6f9f..912355f42911757b3884cce9eae263a887e56ffe 100644 (file)
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -1,5 +1,4 @@
 CONFIG_RISCV=y
-CONFIG_TEXT_BASE=0x21200000
 CONFIG_SYS_MALLOC_LEN=0x800000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -10,7 +9,7 @@ CONFIG_DEBUG_UART_BASE=0x40600000
 CONFIG_DEBUG_UART_CLOCK=1000000
 CONFIG_SYS_CLK_FREQ=100000000
 CONFIG_BOOT_SCRIPT_OFFSET=0x0
-CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_SYS_LOAD_ADDR=0x20200000
 CONFIG_DEBUG_UART=y
 CONFIG_TARGET_XILINX_MBV=y
 CONFIG_FIT=y

diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig
index c724d1bad742de28ccaa6a86a7103ed24db881c0..3c911607a8d944ea366eb9624cdf8bf5cd3f9baa 100644 (file)
--- a/configs/xilinx_mbv32_smode_defconfig
+++ b/configs/xilinx_mbv32_smode_defconfig
@@ -1,5 +1,4 @@
 CONFIG_RISCV=y
-CONFIG_TEXT_BASE=0x21200000
 CONFIG_SYS_MALLOC_LEN=0x800000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -10,7 +9,7 @@ CONFIG_DEBUG_UART_BASE=0x40600000
 CONFIG_DEBUG_UART_CLOCK=1000000
 CONFIG_SYS_CLK_FREQ=100000000
 CONFIG_BOOT_SCRIPT_OFFSET=0x0
-CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_SYS_LOAD_ADDR=0x20200000
 CONFIG_TARGET_XILINX_MBV=y
 CONFIG_RISCV_SMODE=y
 CONFIG_FIT=y