ddr: altera: Fix scc_mgr_set() argument order

The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index bf74b4e6518355eb3463be2e40c2b90708ba9cff..3859e66a00b11932e6a94d886b357a6fcbd191bf 100644 (file)
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -279,7 +279,7 @@ static void scc_mgr_initialize(void)
        for (i = 0; i < 16; i++) {
                debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
                           __func__, __LINE__, i);
-               scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
+               scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
        }
 }