* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton64.dtsi"
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/clock/sun9i-a80-ccu.h>
+#include <dt-bindings/clock/sun9i-a80-de.h>
+#include <dt-bindings/clock/sun9i-a80-usb.h>
+#include <dt-bindings/reset/sun9i-a80-ccu.h>
+#include <dt-bindings/reset/sun9i-a80-de.h>
+#include <dt-bindings/reset/sun9i-a80-usb.h>
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ cci-control-port = <&cci_control0>;
+ clock-frequency = <12000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ cci-control-port = <&cci_control0>;
+ clock-frequency = <12000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x1>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ cci-control-port = <&cci_control0>;
+ clock-frequency = <12000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ cci-control-port = <&cci_control0>;
+ clock-frequency = <12000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x3>;
};
cpu4: cpu@100 {
compatible = "arm,cortex-a15";
device_type = "cpu";
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <18000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x100>;
};
cpu5: cpu@101 {
compatible = "arm,cortex-a15";
device_type = "cpu";
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <18000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x101>;
};
cpu6: cpu@102 {
compatible = "arm,cortex-a15";
device_type = "cpu";
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <18000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x102>;
};
cpu7: cpu@103 {
compatible = "arm,cortex-a15";
device_type = "cpu";
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <18000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x103>;
};
};
- memory {
- /* 8GB max. with LPAE */
- reg = <0 0x20000000 0x02 0>;
- };
-
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
* would also throw all the PLL clock rates off, or just the
* downstream clocks in the PRCM.
*/
- osc24M: osc24M_clk {
+ osc24M: clk-24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
/*
* The 32k clock is from an external source, normally the
- * AC100 codec/RTC chip. This clock is by default enabled
- * and clocked at 32768 Hz, from the oscillator connected
- * to the AC100. It is configurable, but no such driver or
- * bindings exist yet.
+ * AC100 codec/RTC chip. This serves as a placeholder for
+ * board dts files to specify the source.
*/
- osc32k: osc32k_clk {
+ osc32k: clk-32k {
#clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
+ compatible = "fixed-factor-clock";
+ clock-div = <1>;
+ clock-mult = <1>;
clock-output-names = "osc32k";
};
- usb_mod_clk: clk@00a08000 {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "allwinner,sun9i-a80-usb-mod-clk";
- reg = <0x00a08000 0x4>;
- clocks = <&ahb1_gates 1>;
- clock-output-names = "usb0_ahb", "usb_ohci0",
- "usb1_ahb", "usb_ohci1",
- "usb2_ahb", "usb_ohci2";
- };
-
- usb_phy_clk: clk@00a08004 {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "allwinner,sun9i-a80-usb-phy-clk";
- reg = <0x00a08004 0x4>;
- clocks = <&ahb1_gates 1>;
- clock-output-names = "usb_phy0", "usb_hsic1_480M",
- "usb_phy1", "usb_hsic2_480M",
- "usb_phy2", "usb_hsic_12M";
- };
-
- pll3: clk@06000008 {
- /* placeholder until implemented */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-rate = <0>;
- clock-output-names = "pll3";
- };
-
- pll4: clk@0600000c {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-pll4-clk";
- reg = <0x0600000c 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll4";
- };
-
- pll12: clk@0600002c {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-pll4-clk";
- reg = <0x0600002c 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll12";
- };
-
- gt_clk: clk@0600005c {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-gt-clk";
- reg = <0x0600005c 0x4>;
- clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
- clock-output-names = "gt";
- };
-
- ahb0: clk@06000060 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-ahb-clk";
- reg = <0x06000060 0x4>;
- clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
- clock-output-names = "ahb0";
- };
-
- ahb1: clk@06000064 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-ahb-clk";
- reg = <0x06000064 0x4>;
- clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
- clock-output-names = "ahb1";
- };
-
- ahb2: clk@06000068 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-ahb-clk";
- reg = <0x06000068 0x4>;
- clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
- clock-output-names = "ahb2";
- };
-
- apb0: clk@06000070 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-apb0-clk";
- reg = <0x06000070 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "apb0";
- };
-
- apb1: clk@06000074 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-apb1-clk";
- reg = <0x06000074 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "apb1";
- };
-
- cci400_clk: clk@06000078 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-gt-clk";
- reg = <0x06000078 0x4>;
- clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
- clock-output-names = "cci400";
- };
-
- mmc0_clk: clk@06000410 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-mmc-clk";
- reg = <0x06000410 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "mmc0", "mmc0_output",
- "mmc0_sample";
- };
-
- mmc1_clk: clk@06000414 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-mmc-clk";
- reg = <0x06000414 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "mmc1", "mmc1_output",
- "mmc1_sample";
- };
-
- mmc2_clk: clk@06000418 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-mmc-clk";
- reg = <0x06000418 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "mmc2", "mmc2_output",
- "mmc2_sample";
- };
-
- mmc3_clk: clk@0600041c {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-mmc-clk";
- reg = <0x0600041c 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "mmc3", "mmc3_output",
- "mmc3_sample";
- };
-
- ahb0_gates: clk@06000580 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
- reg = <0x06000580 0x4>;
- clocks = <&ahb0>;
- clock-indices = <0>, <1>, <3>,
- <5>, <8>, <12>,
- <13>, <14>,
- <15>, <16>, <18>,
- <20>, <21>, <22>,
- <23>;
- clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
- "ahb0_ss", "ahb0_sd", "ahb0_nand1",
- "ahb0_nand0", "ahb0_sdram",
- "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
- "ahb0_spi0", "ahb0_spi1", "ahb0_spi2",
- "ahb0_spi3";
- };
-
- ahb1_gates: clk@06000584 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
- reg = <0x06000584 0x4>;
- clocks = <&ahb1>;
- clock-indices = <0>, <1>,
- <17>, <21>,
- <22>, <23>,
- <24>;
- clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
- "ahb1_gmac", "ahb1_msgbox",
- "ahb1_spinlock", "ahb1_hstimer",
- "ahb1_dma";
- };
-
- ahb2_gates: clk@06000588 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
- reg = <0x06000588 0x4>;
- clocks = <&ahb2>;
- clock-indices = <0>, <1>,
- <2>, <4>, <5>,
- <7>, <8>, <11>;
- clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
- "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
- "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
- };
-
- apb0_gates: clk@06000590 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-apb0-gates-clk";
- reg = <0x06000590 0x4>;
- clocks = <&apb0>;
- clock-indices = <1>, <5>,
- <11>, <12>, <13>,
- <15>, <17>, <18>,
- <19>;
- clock-output-names = "apb0_spdif", "apb0_pio",
- "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
- "apb0_lradc", "apb0_gpadc", "apb0_twd",
- "apb0_cirtx";
- };
-
- apb1_gates: clk@06000594 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-apb1-gates-clk";
- reg = <0x06000594 0x4>;
- clocks = <&apb1>;
- clock-indices = <0>, <1>,
- <2>, <3>, <4>,
- <16>, <17>,
- <18>, <19>,
- <20>, <21>;
- clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
- "apb1_uart0", "apb1_uart1",
- "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5";
- };
-
- cpus_clk: clk@08001410 {
+ cpus_clk: clk@8001410 {
compatible = "allwinner,sun9i-a80-cpus-clk";
reg = <0x08001410 0x4>;
#clock-cells = <0>;
- clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
+ clocks = <&osc32k>, <&osc24M>,
+ <&ccu CLK_PLL_PERIPH0>,
+ <&ccu CLK_PLL_AUDIO>;
clock-output-names = "cpus";
};
- ahbs: ahbs_clk {
+ ahbs: clk-ahbs {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
clock-output-names = "ahbs";
};
- apbs: clk@0800141c {
+ apbs: clk@800141c {
compatible = "allwinner,sun8i-a23-apb0-clk";
reg = <0x0800141c 0x4>;
#clock-cells = <0>;
clock-output-names = "apbs";
};
- apbs_gates: clk@08001428 {
+ apbs_gates: clk@8001428 {
compatible = "allwinner,sun9i-a80-apbs-gates-clk";
reg = <0x08001428 0x4>;
#clock-cells = <1>;
"apbs_i2s1", "apbs_twd";
};
- r_1wire_clk: clk@08001450 {
+ r_1wire_clk: clk@8001450 {
reg = <0x08001450 0x4>;
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
clock-output-names = "r_1wire";
};
- r_ir_clk: clk@08001454 {
+ r_ir_clk: clk@8001454 {
reg = <0x08001454 0x4>;
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
};
};
+ de: display-engine {
+ compatible = "allwinner,sun9i-a80-display-engine";
+ allwinner,pipelines = <&fe0>, <&fe1>;
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
*/
ranges = <0 0 0 0x20000000>;
- ehci0: usb@00a00000 {
+ sram_b: sram@20000 {
+ /* 256 KiB secure SRAM at 0x20000 */
+ compatible = "mmio-sram";
+ reg = <0x00020000 0x40000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00020000 0x40000>;
+
+ smp-sram@1000 {
+ /*
+ * This is checked by BROM to determine if
+ * cpu0 should jump to SMP entry vector
+ */
+ compatible = "allwinner,sun9i-a80-smp-sram";
+ reg = <0x1000 0x8>;
+ };
+ };
+
+ ehci0: usb@a00000 {
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a00000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_mod_clk 1>;
- resets = <&usb_mod_clk 17>;
+ clocks = <&usb_clocks CLK_BUS_HCI0>;
+ resets = <&usb_clocks RST_USB0_HCI>;
phys = <&usbphy1>;
phy-names = "usb";
status = "disabled";
};
- ohci0: usb@00a00400 {
+ ohci0: usb@a00400 {
compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
reg = <0x00a00400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
- resets = <&usb_mod_clk 17>;
+ clocks = <&usb_clocks CLK_BUS_HCI0>,
+ <&usb_clocks CLK_USB_OHCI0>;
+ resets = <&usb_clocks RST_USB0_HCI>;
phys = <&usbphy1>;
phy-names = "usb";
status = "disabled";
};
- usbphy1: phy@00a00800 {
+ usbphy1: phy@a00800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a00800 0x4>;
- clocks = <&usb_phy_clk 1>;
+ clocks = <&usb_clocks CLK_USB0_PHY>;
clock-names = "phy";
- resets = <&usb_phy_clk 17>;
+ resets = <&usb_clocks RST_USB0_PHY>;
reset-names = "phy";
status = "disabled";
#phy-cells = <0>;
};
- ehci1: usb@00a01000 {
+ ehci1: usb@a01000 {
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a01000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_mod_clk 3>;
- resets = <&usb_mod_clk 18>;
+ clocks = <&usb_clocks CLK_BUS_HCI1>;
+ resets = <&usb_clocks RST_USB1_HCI>;
phys = <&usbphy2>;
phy-names = "usb";
status = "disabled";
};
- usbphy2: phy@00a01800 {
+ usbphy2: phy@a01800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a01800 0x4>;
- clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
- <&usb_phy_clk 3>;
- clock-names = "hsic_480M", "hsic_12M", "phy";
- resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
- reset-names = "hsic", "phy";
+ clocks = <&usb_clocks CLK_USB1_HSIC>,
+ <&usb_clocks CLK_USB_HSIC>,
+ <&usb_clocks CLK_USB1_PHY>;
+ clock-names = "hsic_480M",
+ "hsic_12M",
+ "phy";
+ resets = <&usb_clocks RST_USB1_HSIC>,
+ <&usb_clocks RST_USB1_PHY>;
+ reset-names = "hsic",
+ "phy";
status = "disabled";
#phy-cells = <0>;
/* usb1 is always used with HSIC */
phy_type = "hsic";
};
- ehci2: usb@00a02000 {
+ ehci2: usb@a02000 {
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a02000 0x100>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_mod_clk 5>;
- resets = <&usb_mod_clk 19>;
+ clocks = <&usb_clocks CLK_BUS_HCI2>;
+ resets = <&usb_clocks RST_USB2_HCI>;
phys = <&usbphy3>;
phy-names = "usb";
status = "disabled";
};
- ohci2: usb@00a02400 {
+ ohci2: usb@a02400 {
compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
reg = <0x00a02400 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
- resets = <&usb_mod_clk 19>;
+ clocks = <&usb_clocks CLK_BUS_HCI2>,
+ <&usb_clocks CLK_USB_OHCI2>;
+ resets = <&usb_clocks RST_USB2_HCI>;
phys = <&usbphy3>;
phy-names = "usb";
status = "disabled";
};
- usbphy3: phy@00a02800 {
+ usbphy3: phy@a02800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a02800 0x4>;
- clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
- <&usb_phy_clk 5>;
- clock-names = "hsic_480M", "hsic_12M", "phy";
- resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
- reset-names = "hsic", "phy";
+ clocks = <&usb_clocks CLK_USB2_HSIC>,
+ <&usb_clocks CLK_USB_HSIC>,
+ <&usb_clocks CLK_USB2_PHY>;
+ clock-names = "hsic_480M",
+ "hsic_12M",
+ "phy";
+ resets = <&usb_clocks RST_USB2_HSIC>,
+ <&usb_clocks RST_USB2_PHY>;
+ reset-names = "hsic",
+ "phy";
status = "disabled";
#phy-cells = <0>;
};
- mmc0: mmc@01c0f000 {
+ usb_clocks: clock@a08000 {
+ compatible = "allwinner,sun9i-a80-usb-clks";
+ reg = <0x00a08000 0x8>;
+ clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
+ clock-names = "bus", "hosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cpucfg@1700000 {
+ compatible = "allwinner,sun9i-a80-cpucfg";
+ reg = <0x01700000 0x100>;
+ };
+
+ mmc0: mmc@1c0f000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
- <&mmc0_clk 1>, <&mmc0_clk 2>;
+ clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 0>;
reset-names = "ahb";
#size-cells = <0>;
};
- mmc1: mmc@01c10000 {
+ mmc1: mmc@1c10000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
- <&mmc1_clk 1>, <&mmc1_clk 2>;
+ clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 1>;
reset-names = "ahb";
#size-cells = <0>;
};
- mmc2: mmc@01c11000 {
+ mmc2: mmc@1c11000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
- <&mmc2_clk 1>, <&mmc2_clk 2>;
+ clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 2>;
reset-names = "ahb";
#size-cells = <0>;
};
- mmc3: mmc@01c12000 {
+ mmc3: mmc@1c12000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c12000 0x1000>;
- clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
- <&mmc3_clk 1>, <&mmc3_clk 2>;
+ clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
+ <&ccu CLK_MMC3_OUTPUT>,
+ <&ccu CLK_MMC3_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 3>;
reset-names = "ahb";
#size-cells = <0>;
};
- mmc_config_clk: clk@01c13000 {
+ mmc_config_clk: clk@1c13000 {
compatible = "allwinner,sun9i-a80-mmc-config-clk";
reg = <0x01c13000 0x10>;
- clocks = <&ahb0_gates 8>;
+ clocks = <&ccu CLK_BUS_MMC>;
clock-names = "ahb";
- resets = <&ahb0_resets 8>;
+ resets = <&ccu RST_BUS_MMC>;
reset-names = "ahb";
#clock-cells = <1>;
#reset-cells = <1>;
"mmc2_config", "mmc3_config";
};
- gic: interrupt-controller@01c41000 {
+ gic: interrupt-controller@1c41000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c41000 0x1000>,
- <0x01c42000 0x1000>,
+ <0x01c42000 0x2000>,
<0x01c44000 0x2000>,
<0x01c46000 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
- ahb0_resets: reset@060005a0 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x060005a0 0x4>;
+ cci: cci@1c90000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x01c90000 0x1000>;
+ ranges = <0x0 0x01c90000 0x10000>;
+
+ cci_control0: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control1: slave-if@5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1";
+ reg = <0x9000 0x5000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
- ahb1_resets: reset@060005a4 {
+ de_clocks: clock@3000000 {
+ compatible = "allwinner,sun9i-a80-de-clks";
+ reg = <0x03000000 0x30>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_SDRAM>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "dram",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
#reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x060005a4 0x4>;
};
- ahb2_resets: reset@060005a8 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x060005a8 0x4>;
+ fe0: display-frontend@3100000 {
+ compatible = "allwinner,sun9i-a80-display-frontend";
+ reg = <0x03100000 0x40000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
+ <&de_clocks CLK_DRAM_FE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_clocks RST_FE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_deu0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&deu0_in_fe0>;
+ };
+ };
+ };
};
- apb0_resets: reset@060005b0 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x060005b0 0x4>;
+ fe1: display-frontend@3140000 {
+ compatible = "allwinner,sun9i-a80-display-frontend";
+ reg = <0x03140000 0x40000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
+ <&de_clocks CLK_DRAM_FE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_clocks RST_FE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe1_out_deu1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&deu1_in_fe1>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@3200000 {
+ compatible = "allwinner,sun9i-a80-display-backend";
+ reg = <0x03200000 0x40000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
+ <&de_clocks CLK_DRAM_BE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_clocks RST_BE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_deu0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&deu0_out_be0>;
+ };
+
+ be0_in_deu1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&deu1_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_in_be0>;
+ };
+ };
+ };
+ };
+
+ be1: display-backend@3240000 {
+ compatible = "allwinner,sun9i-a80-display-backend";
+ reg = <0x03240000 0x40000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
+ <&de_clocks CLK_DRAM_BE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_clocks RST_BE1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be1_in_deu0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&deu0_out_be1>;
+ };
+
+ be1_in_deu1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&deu1_out_be1>;
+ };
+ };
+
+ be1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be1_out_drc1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc1_in_be1>;
+ };
+ };
+ };
+ };
+
+ deu0: deu@3300000 {
+ compatible = "allwinner,sun9i-a80-deu";
+ reg = <0x03300000 0x40000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_DEU0>,
+ <&de_clocks CLK_IEP_DEU0>,
+ <&de_clocks CLK_DRAM_DEU0>;
+ clock-names = "ahb",
+ "mod",
+ "ram";
+ resets = <&de_clocks RST_DEU0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ deu0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ deu0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_deu0>;
+ };
+ };
+
+ deu0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ deu0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_deu0>;
+ };
+
+ deu0_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_deu0>;
+ };
+ };
+ };
+ };
+
+ deu1: deu@3340000 {
+ compatible = "allwinner,sun9i-a80-deu";
+ reg = <0x03340000 0x40000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_DEU1>,
+ <&de_clocks CLK_IEP_DEU1>,
+ <&de_clocks CLK_DRAM_DEU1>;
+ clock-names = "ahb",
+ "mod",
+ "ram";
+ resets = <&de_clocks RST_DEU1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ deu1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ deu1_in_fe1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe1_out_deu1>;
+ };
+ };
+
+ deu1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ deu1_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_deu1>;
+ };
+
+ deu1_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_deu1>;
+ };
+ };
+ };
+ };
+
+ drc0: drc@3400000 {
+ compatible = "allwinner,sun9i-a80-drc";
+ reg = <0x03400000 0x40000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_DRC0>,
+ <&de_clocks CLK_IEP_DRC0>,
+ <&de_clocks CLK_DRAM_DRC0>;
+ clock-names = "ahb",
+ "mod",
+ "ram";
+ resets = <&de_clocks RST_DRC0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ drc0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ drc0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_drc0>;
+ };
+ };
+
+ drc0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ drc0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_drc0>;
+ };
+ };
+ };
+ };
+
+ drc1: drc@3440000 {
+ compatible = "allwinner,sun9i-a80-drc";
+ reg = <0x03440000 0x40000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_DRC1>,
+ <&de_clocks CLK_IEP_DRC1>,
+ <&de_clocks CLK_DRAM_DRC1>;
+ clock-names = "ahb",
+ "mod",
+ "ram";
+ resets = <&de_clocks RST_DRC1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ drc1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ drc1_in_be1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be1_out_drc1>;
+ };
+ };
+
+ drc1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ drc1_out_tcon1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon1_in_drc1>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@3c00000 {
+ compatible = "allwinner,sun9i-a80-tcon-lcd";
+ reg = <0x03c00000 0x10000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
+ clock-names = "ahb", "tcon-ch0";
+ resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
+ reset-names = "lcd", "edp";
+ clock-output-names = "tcon0-pixel-clock";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
};
- apb1_resets: reset@060005b4 {
+ tcon1: lcd-controller@3c10000 {
+ compatible = "allwinner,sun9i-a80-tcon-tv";
+ reg = <0x03c10000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
+ reset-names = "lcd", "edp";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon1_in_drc1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+ ccu: clock@6000000 {
+ compatible = "allwinner,sun9i-a80-ccu";
+ reg = <0x06000000 0x800>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
#reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x060005b4 0x4>;
};
- timer@06000c00 {
+ timer@6000c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x06000c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
clocks = <&osc24M>;
};
- wdt: watchdog@06000ca0 {
+ wdt: watchdog@6000ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x06000ca0 0x20>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
};
- pio: pinctrl@06000800 {
+ pio: pinctrl@6000800 {
compatible = "allwinner,sun9i-a80-pinctrl";
reg = <0x06000800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 5>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#size-cells = <0>;
#gpio-cells = <3>;
- i2c3_pins_a: i2c3@0 {
- allwinner,pins = "PG10", "PG11";
- allwinner,function = "i2c3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ i2c3_pins: i2c3-pins {
+ pins = "PG10", "PG11";
+ function = "i2c3";
+ };
+
+ lcd0_rgb888_pins: lcd0-rgb888-pins {
+ pins = "PD0", "PD1", "PD2", "PD3",
+ "PD4", "PD5", "PD6", "PD7",
+ "PD8", "PD9", "PD10", "PD11",
+ "PD12", "PD13", "PD14", "PD15",
+ "PD16", "PD17", "PD18", "PD19",
+ "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ function = "lcd0";
};
- mmc0_pins: mmc0 {
- allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
- "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1" ,"PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
};
- mmc1_pins: mmc1 {
- allwinner,pins = "PG0", "PG1" ,"PG2", "PG3",
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1" ,"PG2", "PG3",
"PG4", "PG5";
- allwinner,function = "mmc1";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
};
- mmc2_8bit_pins: mmc2_8bit {
- allwinner,pins = "PC6", "PC7", "PC8", "PC9",
- "PC10", "PC11", "PC12",
- "PC13", "PC14", "PC15",
- "PC16";
- allwinner,function = "mmc2";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ mmc2_8bit_pins: mmc2-8bit-pins {
+ pins = "PC6", "PC7", "PC8", "PC9",
+ "PC10", "PC11", "PC12",
+ "PC13", "PC14", "PC15",
+ "PC16";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
};
- uart0_pins_a: uart0@0 {
- allwinner,pins = "PH12", "PH13";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart0_ph_pins: uart0-ph-pins {
+ pins = "PH12", "PH13";
+ function = "uart0";
};
- uart4_pins_a: uart4@0 {
- allwinner,pins = "PG12", "PG13", "PG14", "PG15";
- allwinner,function = "uart4";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart4_pins: uart4-pins {
+ pins = "PG12", "PG13", "PG14", "PG15";
+ function = "uart4";
};
};
- uart0: serial@07000000 {
+ uart0: serial@7000000 {
compatible = "snps,dw-apb-uart";
reg = <0x07000000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 16>;
- resets = <&apb1_resets 16>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
- uart1: serial@07000400 {
+ uart1: serial@7000400 {
compatible = "snps,dw-apb-uart";
reg = <0x07000400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 17>;
- resets = <&apb1_resets 17>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
- uart2: serial@07000800 {
+ uart2: serial@7000800 {
compatible = "snps,dw-apb-uart";
reg = <0x07000800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 18>;
- resets = <&apb1_resets 18>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
- uart3: serial@07000c00 {
+ uart3: serial@7000c00 {
compatible = "snps,dw-apb-uart";
reg = <0x07000c00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 19>;
- resets = <&apb1_resets 19>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};
- uart4: serial@07001000 {
+ uart4: serial@7001000 {
compatible = "snps,dw-apb-uart";
reg = <0x07001000 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 20>;
- resets = <&apb1_resets 20>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
status = "disabled";
};
- uart5: serial@07001400 {
+ uart5: serial@7001400 {
compatible = "snps,dw-apb-uart";
reg = <0x07001400 0x400>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 21>;
- resets = <&apb1_resets 21>;
+ clocks = <&ccu CLK_BUS_UART5>;
+ resets = <&ccu RST_BUS_UART5>;
status = "disabled";
};
- i2c0: i2c@07002800 {
+ i2c0: i2c@7002800 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07002800 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 0>;
- resets = <&apb1_resets 0>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c1: i2c@07002c00 {
+ i2c1: i2c@7002c00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07002c00 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 1>;
- resets = <&apb1_resets 1>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c2: i2c@07003000 {
+ i2c2: i2c@7003000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003000 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 2>;
- resets = <&apb1_resets 2>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c3: i2c@07003400 {
+ i2c3: i2c@7003400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003400 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 3>;
- resets = <&apb1_resets 3>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c4: i2c@07003800 {
+ i2c4: i2c@7003800 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003800 0x400>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 4>;
- resets = <&apb1_resets 4>;
+ clocks = <&ccu CLK_BUS_I2C4>;
+ resets = <&ccu RST_BUS_I2C4>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- r_wdt: watchdog@08001000 {
+ r_wdt: watchdog@8001000 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x08001000 0x20>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
};
- apbs_rst: reset@080014b0 {
+ prcm@8001400 {
+ compatible = "allwinner,sun9i-a80-prcm";
+ reg = <0x08001400 0x200>;
+ };
+
+ apbs_rst: reset@80014b0 {
reg = <0x080014b0 0x4>;
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
- nmi_intc: interrupt-controller@080015a0 {
+ nmi_intc: interrupt-controller@80015a0 {
compatible = "allwinner,sun9i-a80-nmi";
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
- r_ir: ir@08002000 {
+ r_ir: ir@8002000 {
compatible = "allwinner,sun5i-a13-ir";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
status = "disabled";
};
- r_uart: serial@08002800 {
+ r_uart: serial@8002800 {
compatible = "snps,dw-apb-uart";
reg = <0x08002800 0x400>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- r_pio: pinctrl@08002c00 {
+ r_pio: pinctrl@8002c00 {
compatible = "allwinner,sun9i-a80-r-pinctrl";
reg = <0x08002c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apbs_gates 0>;
+ clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
resets = <&apbs_rst 0>;
gpio-controller;
interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
+ #interrupt-cells = <3>;
#gpio-cells = <3>;
- r_ir_pins: r_ir {
- allwinner,pins = "PL6";
- allwinner,function = "s_cir_rx";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ r_ir_pins: r-ir-pins {
+ pins = "PL6";
+ function = "s_cir_rx";
};
- r_rsb_pins: r_rsb {
- allwinner,pins = "PN0", "PN1";
- allwinner,function = "s_rsb";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ r_rsb_pins: r-rsb-pins {
+ pins = "PN0", "PN1";
+ function = "s_rsb";
+ drive-strength = <20>;
+ bias-pull-up;
};
};
- r_rsb: i2c@08003400 {
+ r_rsb: i2c@8003400 {
compatible = "allwinner,sun8i-a23-rsb";
reg = <0x08003400 0x400>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
projects / u-boot.git / commitdiff