dm: cpu: bmips: add BCM6368 support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 1eb744adcdcfc13be9868e195f7e013022bd60f3..2e3f1de74e4bd1cb8e825a9e105ab7cdf272073e 100644 (file)
--- a/drivers/cpu/bmips_cpu.c
+++ b/drivers/cpu/bmips_cpu.c
@@ -46,6 +46,17 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DMIPSPLLCFG_6358_N2_SHIFT      29
 #define DMIPSPLLCFG_6358_N2_MASK       (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
 
+#define REG_BCM6368_DDR_DMIPSPLLCFG    0x12a0
+#define DMIPSPLLCFG_6368_P1_SHIFT      0
+#define DMIPSPLLCFG_6368_P1_MASK       (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
+#define DMIPSPLLCFG_6368_P2_SHIFT      4
+#define DMIPSPLLCFG_6368_P2_MASK       (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
+#define DMIPSPLLCFG_6368_NDIV_SHIFT    16
+#define DMIPSPLLCFG_6368_NDIV_MASK     (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
+#define REG_BCM6368_DDR_DMIPSPLLDIV    0x12a4
+#define DMIPSPLLDIV_6368_MDIV_SHIFT    0
+#define DMIPSPLLDIV_6368_MDIV_MASK     (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
+
 #define REG_BCM63268_MISC_STRAPBUS     0x1814
 #define STRAPBUS_63268_FCVO_SHIFT      21
 #define STRAPBUS_63268_FCVO_MASK       (0xf << STRAPBUS_63268_FCVO_SHIFT)
@@ -157,6 +168,22 @@ static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
        return (16 * 1000000 * n1 * n2) / m1;
 }
 
+static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+       unsigned int tmp, p1, p2, ndiv, m1;
+
+       tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG);
+       p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT;
+       p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT;
+       ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
+              DMIPSPLLCFG_6368_NDIV_SHIFT;
+
+       tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV);
+       m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT;
+
+       return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
+}
+
 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
 {
        unsigned int mips_pll_fcvo;
@@ -230,6 +257,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
        .get_cpu_count = bcm6358_get_cpu_count,
 };
 
+static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
+       .get_cpu_desc = bmips_short_cpu_desc,
+       .get_cpu_freq = bcm6368_get_cpu_freq,
+       .get_cpu_count = bcm6358_get_cpu_count,
+};
+
 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
        .get_cpu_desc = bmips_long_cpu_desc,
        .get_cpu_freq = bcm63268_get_cpu_freq,
@@ -326,6 +359,9 @@ static const struct udevice_id bmips_cpu_ids[] = {
        }, {
                .compatible = "brcm,bcm6358-cpu",
                .data = (ulong)&bmips_cpu_bcm6358,
+       }, {
+               .compatible = "brcm,bcm6368-cpu",
+               .data = (ulong)&bmips_cpu_bcm6368,
        }, {
                .compatible = "brcm,bcm63268-cpu",
                .data = (ulong)&bmips_cpu_bcm63268,