arm: vf610: lpuart: disable FIFO on initializaton

UART does not use the UART FIFO, but we should also not rely that
the UART FIFO is diabled by default. For instance, when loading
U-Boot using the boot ROMs serial downloader protocol over UART,
FIFO is enabled at U-Boot start time.

This patch disables the RX and TX FIFO, sets back their thresholds
and flushes them.

Signed-off-by: Stefan Agner <stefan@agner.ch>

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 96173ca440986143c913f72ad60e6ba784d86e53..0a5e15919f63a60984bf7bf6274be498de7de097 100644 (file)
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -17,6 +17,10 @@
 #define US1_OR          (1 << 3)
 #define UC2_TE          (1 << 3)
 #define UC2_RE          (1 << 2)
+#define CFIFO_TXFLUSH   (1 << 7)
+#define CFIFO_RXFLUSH   (1 << 6)
+#define SFIFO_RXOF      (1 << 2)
+#define SFIFO_RXUF      (1 << 0)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -85,6 +89,12 @@ static int lpuart_serial_init(void)
        __raw_writeb(0, &base->umodem);
        __raw_writeb(0, &base->uc1);
 
+       /* Disable FIFO and flush buffer */
+       __raw_writeb(0x0, &base->upfifo);
+       __raw_writeb(0x0, &base->utwfifo);
+       __raw_writeb(0x1, &base->urwfifo);
+       __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
+
        /* provide data bits, parity, stop bit, etc */
 
        serial_setbrg();