int ret;
ret = spi_nor_read_write_reg(nor, &op, val);
- if (ret < 0)
- dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
+ if (ret < 0) {
+ /*
+ * spi_slave does not have a struct udevice member without DM,
+ * so use the bus and cs instead.
+ */
+#if CONFIG_IS_ENABLED(DM_SPI)
+ dev_dbg(nor->spi->dev, "error %d reading %x\n", ret,
code);
+#else
+ log_debug("spi%u.%u: error %d reading %x\n",
+ nor->spi->bus, nor->spi->cs, ret, code);
+#endif
+ }
return ret;
}
/* Check current Quad Enable bit value. */
ret = read_cr(nor);
if (ret < 0) {
- dev_dbg(dev, "error while reading configuration register\n");
+ dev_dbg(nor->dev,
+ "error while reading configuration register\n");
return -EINVAL;
}
/* Keep the current value of the Status Register. */
ret = read_sr(nor);
if (ret < 0) {
- dev_dbg(dev, "error while reading status register\n");
+ dev_dbg(nor->dev, "error while reading status register\n");
return -EINVAL;
}
sr_cr[0] = ret;
}
if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
- dev_dbg(dev, "address width is too large: %u\n",
+ dev_dbg(nor->dev, "address width is too large: %u\n",
nor->addr_width);
return -EINVAL;
}