x86: coreboot: Add default TSC frequency in the device tree

It was observed sometimes U-Boot as the coreboot payload fails to
boot on QEMU. This is because TSC calibration fails with no valid
frequency. This adds default TSC frequency in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index a94f7818331c1f601073c47c3bd3cbf816f42575..e212f3dc7dbe12f19ef49ef99bc4d2565c8b8679 100644 (file)
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -30,6 +30,10 @@
                stdout-path = "/serial";
        };
 
+       tsc-timer {
+               clock-frequency = <1000000000>;
+       };
+
        pci {
                compatible = "pci-x86";
                u-boot,dm-pre-reloc;