rockchip: include: grf: Add GRF register declaration for mipi dsi

Add GRF register declaration for mipi dsi.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index 7df25fd31d10a3dccc30ebbf46d8f2e611092714..eda99560ed3039c8769e9f68ab6ef0b1c56b6931 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -525,9 +525,32 @@ enum {
        GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT,
 
        /* GRF_SOC_CON7 */
-       GRF_UART_DBG_SEL_SHIFT  = 10,
-       GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
-       GRF_UART_DBG_SEL_C      = 2,
+       GRF_UART_DBG_SEL_SHIFT  = 10,
+       GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
+       GRF_UART_DBG_SEL_C      = 2,
+
+       /* GRF_SOC_CON20 */
+       GRF_DSI0_VOP_SEL_SHIFT  = 0,
+       GRF_DSI0_VOP_SEL_MASK   = 1 << GRF_DSI0_VOP_SEL_SHIFT,
+       GRF_DSI0_VOP_SEL_B      = 0,
+       GRF_DSI0_VOP_SEL_L      = 1,
+
+       /* GRF_SOC_CON22 */
+       GRF_DPHY_TX0_RXMODE_SHIFT = 0,
+       GRF_DPHY_TX0_RXMODE_MASK  = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
+       GRF_DPHY_TX0_RXMODE_EN    = 0xb,
+       GRF_DPHY_TX0_RXMODE_DIS   = 0,
+
+       GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
+       GRF_DPHY_TX0_TXSTOPMODE_MASK  = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
+       GRF_DPHY_TX0_TXSTOPMODE_EN    = 0xc,
+       GRF_DPHY_TX0_TXSTOPMODE_DIS   = 0,
+
+       GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
+       GRF_DPHY_TX0_TURNREQUEST_MASK  =
+               0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
+       GRF_DPHY_TX0_TURNREQUEST_EN    = 0x1,
+       GRF_DPHY_TX0_TURNREQUEST_DIS   = 0,
 
        /*  PMUGRF_GPIO0A_IOMUX */
        PMUGRF_GPIO0A6_SEL_SHIFT        = 12,