arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error

Add 1ms delay to avoid L3 timeout error during suspend resume.

Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>

diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index 816d4e8e0568bb22daa120afa9562443ebdd5858..5d947a68c3deac731fd019b4599977e3b133fe01 100644 (file)
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -138,6 +138,9 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
                /* Enable read leveling */
                writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 
+               /* Wait 1ms because of L3 timeout error */
+               udelay(1000);
+
                /*
                 * Enable full read and write leveling.  Wait for read and write
                 * leveling bit to clear RDWRLVLFULL_START bit 31