dm: cache: Create a uclass for cache

The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/drivers/Kconfig b/drivers/Kconfig
index e6702eced46c26acf411dfc7ab39dee9d1bba262..96ff4f566ab3ec253eae94d2c7650ef12ecebd69 100644 (file)
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
 
 source "drivers/bootcount/Kconfig"
 
+source "drivers/cache/Kconfig"
+
 source "drivers/clk/Kconfig"
 
 source "drivers/cpu/Kconfig"

diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed564b0dfc4035be3254a81abd1612a9f0..0a00096332b6ae25bf0dfe03fb8bb369ecf67977 100644 (file)
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
 obj-y += block/
 obj-y += board/
 obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
 obj-$(CONFIG_CPU) += cpu/
 obj-y += crypto/
 obj-$(CONFIG_FASTBOOT) += fastboot/

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644 (file)
index 0000000..8b7c9c7
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,16 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+       bool "Enable Driver Model for Cache controllers"
+       depends on DM
+       help
+         Enable driver model for cache controllers that are found on
+         most CPU's. Cache is memory that the CPU can access directly and
+         is usually located on the same chip. This uclass can be used for
+         configuring settings that be found from a device tree file.
+
+endmenu

diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644 (file)
index 0000000..2ba6806
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o

diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
new file mode 100644 (file)
index 0000000..97ce024
--- /dev/null
+++ b/drivers/cache/cache-uclass.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <dm.h>
+
+int cache_get_info(struct udevice *dev, struct cache_info *info)
+{
+       struct cache_ops *ops = cache_get_ops(dev);
+
+       if (!ops->get_info)
+               return -ENOSYS;
+
+       return ops->get_info(dev, info);
+}
+
+UCLASS_DRIVER(cache) = {
+       .id             = UCLASS_CACHE,
+       .name           = "cache",
+       .post_bind      = dm_scan_fdt_dev,
+};

diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
new file mode 100644 (file)
index 0000000..14cc6b0
--- /dev/null
+++ b/drivers/cache/sandbox_cache.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <dm.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+       info->base = 0x11223344;
+
+       return 0;
+}
+
+static const struct cache_ops sandbox_cache_ops = {
+       .get_info       = sandbox_get_info,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+       { .compatible = "sandbox,cache" },
+       { }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+       .name           = "cache_sandbox",
+       .id             = UCLASS_CACHE,
+       .of_match       = sandbox_cache_ids,
+       .ops            = &sandbox_cache_ops,
+};

diff --git a/include/cache.h b/include/cache.h
new file mode 100644 (file)
index 0000000..c6334ca
--- /dev/null
+++ b/include/cache.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+/*
+ * Structure for the cache controller
+ */
+struct cache_info {
+       phys_addr_t base; /* Base physical address of cache device. */
+};
+
+struct cache_ops {
+       /**
+        * get_info() - Get basic cache info
+        *
+        * @dev:        Device to check (UCLASS_CACHE)
+        * @info:       Place to put info
+        * @return 0 if OK, -ve on error
+        */
+       int (*get_info)(struct udevice *dev, struct cache_info *info);
+};
+
+#define cache_get_ops(dev)     ((struct cache_ops *)(dev)->driver->ops)
+
+/**
+ * cache_get_info() - Get information about a cache controller
+ *
+ * @dev:       Device to check (UCLASS_CACHE)
+ * @info:      Returns cache info
+ * @return 0 if OK, -ve on error
+ */
+int cache_get_info(struct udevice *dev, struct cache_info *info);
+
+#endif

diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 86e59781b058fdf15ea741c0bcefa893430fad50..09e0ad5391b9771f97bbcc20b6e3fa989ff740c0 100644 (file)
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -34,6 +34,7 @@ enum uclass_id {
        UCLASS_BLK,             /* Block device */
        UCLASS_BOARD,           /* Device information from hardware */
        UCLASS_BOOTCOUNT,       /* Bootcount backing store */
+       UCLASS_CACHE,           /* Cache controller */
        UCLASS_CLK,             /* Clock source, e.g. used by peripherals */
        UCLASS_CPU,             /* CPU, typically part of an SoC */
        UCLASS_CROS_EC,         /* Chrome OS EC */

diff --git a/test/dm/cache.c b/test/dm/cache.c
new file mode 100644 (file)
index 0000000..d4144aa
--- /dev/null
+++ b/test/dm/cache.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+
+static int dm_test_reset(struct unit_test_state *uts)
+{
+       struct udevice *dev_cache;
+       struct cache_info;
+
+       ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
+       ut_assertok(cache_get_info(dev, &info));
+
+       return 0;
+}
+DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);