Add i.MX6ULZ cpu type and helper.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
#define MXC_CPU_MX6Q 0x63
#define MXC_CPU_MX6UL 0x64
#define MXC_CPU_MX6ULL 0x65
+#define MXC_CPU_MX6ULZ 0x6B
#define MXC_CPU_MX6SOLO 0x66 /* dummy */
#define MXC_CPU_MX6SLL 0x67
#define MXC_CPU_MX6D 0x6A
#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
+#define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
return "6UL"; /* Ultra-Lite version of the mx6 */
case MXC_CPU_MX6ULL:
return "6ULL"; /* ULL version of the mx6 */
+ case MXC_CPU_MX6ULZ:
+ return "6ULZ"; /* ULZ version of the mx6 */
case MXC_CPU_MX51:
return "51";
case MXC_CPU_MX53:
type = MXC_CPU_MX6D;
}
+ if (type == MXC_CPU_MX6ULL) {
+ if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
+ type = MXC_CPU_MX6ULZ;
+ }
}
major = ((reg >> 8) & 0xff);
if ((major >= 1) &&