least one non-MTD partition type as well.
- IDE Reset method:
- CONFIG_IDE_RESET_ROUTINE - this is defined in several
- board configurations files but used nowhere!
-
CONFIG_IDE_RESET - is this is defined, IDE Reset will
be performed by calling the function
ide_set_reset(int reset)
*/
#ifdef CONFIG_IDE
#define __io
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
/* The FMAN driver uses the PHYLIB infrastructure */
-/* All PPC boards must swap IDE bytes */
-#define CONFIG_IDE_SWAP_IO
-
#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
/*
* TODO: Convert this to a clock driver exists that can give us the UART
#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
-#ifndef CONFIG_SYS_ATA_PORT_ADDR
-#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
-#endif
+#define ATA_PORT_ADDR(port) (port)
#ifdef CONFIG_IDE_RESET
extern void ide_set_reset(int idereset);
{
debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
dev, port, val,
- (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+ (ATA_CURR_BASE(dev) + ATA_PORT_ADDR(port)));
#if defined(CONFIG_IDE_AHB)
if (port) {
outb(val, (ATA_CURR_BASE(dev)));
}
#else
- outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+ outb(val, (ATA_CURR_BASE(dev) + ATA_PORT_ADDR(port)));
#endif
}
#if defined(CONFIG_IDE_AHB)
val = ide_read_register(dev, port);
#else
- val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+ val = inb((ATA_CURR_BASE(dev) + ATA_PORT_ADDR(port)));
#endif
debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
dev, port,
- (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
+ (ATA_CURR_BASE(dev) + ATA_PORT_ADDR(port)), val);
return val;
}
*/
#ifdef CONFIG_IDE
#define __io
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
-#define CONFIG_IDE_SWAP_IO
/*
* SuperH PCI Bridge Configration
CONFIG_ICS307_REFCLK_HZ
CONFIG_IDE_PREINIT
CONFIG_IDE_RESET
-CONFIG_IDE_SWAP_IO
CONFIG_IMA
CONFIG_IMX
CONFIG_IMX6_PWM_PER_CLK
CONFIG_SYS_ATA_DATA_OFFSET
CONFIG_SYS_ATA_IDE0_OFFSET
CONFIG_SYS_ATA_IDE1_OFFSET
-CONFIG_SYS_ATA_PORT_ADDR
CONFIG_SYS_ATA_REG_OFFSET
CONFIG_SYS_ATA_STRIDE
CONFIG_SYS_ATMEL_CPU_NAME