mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it

If the DDR3 module supports industrial temperature range and requires
the x2 refresh rate for that temp range, the refresh period must be
3.9us instead of 7.8 us.

This was successfuly tested on kmp204x board with some MT41K128M16 DDR3
RAM chips (no module used, chips directly soldered on board with an SPD
EEPROM).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix minor conflicts in fsl_ddr_dimm_params.h,
	   lc_common_dimm_params.c, common_timing_params.h]
Acked-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
index 17d8d9f74005da842079fe73010916388e2bc886..76338d4e6c163a4069848a647d96459ccf075fe4 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
@@ -28,6 +28,7 @@ typedef struct {
        unsigned int trc_ps;    /* maximum = 254 ns + .75 ns = 254750 ps */
 
        unsigned int refresh_rate_ps;
+       unsigned int extended_op_srt;
 
        unsigned int tis_ps;    /* byte 32, spd->ca_setup */
        unsigned int tih_ps;    /* byte 33, spd->ca_hold */

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index d7333ba3dd41e7116cc8cae104817ea69c3cc781..dcfc48aa957f6774c488b34b8eb00a2bd645626c 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -765,6 +765,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
                                const memctl_options_t *popts,
+                               const common_timing_params_t *common_dimm,
                                const unsigned int unq_mrs_en)
 {
        unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
@@ -782,6 +783,10 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
                rtt_wr = popts->rtt_wr_override_value;
        else
                rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
+
+       if (common_dimm->extended_op_srt)
+               srt = common_dimm->extended_op_srt;
+
        esdmode2 = (0
                | ((rtt_wr & 0x3) << 9)
                | ((srt & 0x1) << 7)
@@ -1626,7 +1631,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
        set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
        set_ddr_sdram_mode(ddr, popts, common_dimm,
                                cas_latency, additive_latency, unq_mrs_en);
-       set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
+       set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
        set_ddr_sdram_interval(ddr, popts, common_dimm);
        set_ddr_data_init(ddr);
        set_ddr_sdram_clk_cntl(ddr, popts);

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index d82eb674d344a560c0c967f1dc406e8bc11736b7..4c8645da569c7da6efee644d3a032439f2552e76 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -321,6 +321,10 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
         *       = 3.9 us at ext temperature range
         */
        pdimm->refresh_rate_ps = 7800000;
+       if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) {
+               pdimm->refresh_rate_ps = 3900000;
+               pdimm->extended_op_srt = 1;
+       }
 
        /*
         * min four active window delay time

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 3affcee7df72604a08b24e7492e55bc295b2ea21..332fe25c4816ae7913736f4439e3b8fefbbed80d 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -92,6 +92,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
        unsigned int trrd_ps = 0;
        unsigned int trc_ps = 0;
        unsigned int refresh_rate_ps = 0;
+       unsigned int extended_op_srt = 1;
        unsigned int tis_ps = 0;
        unsigned int tih_ps = 0;
        unsigned int tds_ps = 0;
@@ -166,6 +167,9 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
                tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
                refresh_rate_ps = max(refresh_rate_ps,
                                      dimm_params[i].refresh_rate_ps);
+               /* extended_op_srt is either 0 or 1, 0 having priority */
+               extended_op_srt = min(extended_op_srt,
+                                     dimm_params[i].extended_op_srt);
 
                /*
                 * Find maximum tdqsq_max_ps to find slowest.
@@ -195,6 +199,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
        outpdimm->trrd_ps = trrd_ps;
        outpdimm->trc_ps = trc_ps;
        outpdimm->refresh_rate_ps = refresh_rate_ps;
+       outpdimm->extended_op_srt = extended_op_srt;
        outpdimm->tis_ps = tis_ps;
        outpdimm->tih_ps = tih_ps;
        outpdimm->tds_ps = tds_ps;

diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index 2cad6e28578a6e6904b48b22b08f75a6b1fa85bb..99a72bc6e16d6b88f57692ec3c76a81db564d927 100644 (file)
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -78,6 +78,7 @@ typedef struct dimm_params_s {
        unsigned int trc_ps;    /* maximum = 254 ns + .75 ns = 254750 ps */
 
        unsigned int refresh_rate_ps;
+       unsigned int extended_op_srt;
 
        /* DDR3 doesn't need these as below */
        unsigned int tis_ps;    /* byte 32, spd->ca_setup */