clk: sunxi: a80: Fix reset description

Clock gates and reset lines share a common structure in the sunxi clock
driver descriptions, but use different flags to tell them apart.

The description of the Allwinner A80 MMC clock reset lines was
erroneously using the "GATE" macro, which made the reset driver ignore
that entry, complaining with:
sunxi_set_reset: (RST-reset:#0) unhandled

Change that to the correct "RESET" macro, to make the reset driver
happy.

Fixes e0c7ce7e52b7 ("sunxi: clk: A80: add MMC clock support")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index 6751af8a8031170c6ebf24462f558089bba2ea3c..091aaeee987fda0520d95c307e5350170dff5090 100644 (file)
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -75,10 +75,10 @@ static const struct ccu_clk_gate a80_mmc_gates[] = {
 };
 
 static const struct ccu_reset a80_mmc_resets[] = {
-       [0]                     = GATE(0x0, BIT(18)),
-       [1]                     = GATE(0x4, BIT(18)),
-       [2]                     = GATE(0x8, BIT(18)),
-       [3]                     = GATE(0xc, BIT(18)),
+       [0]                     = RESET(0x0, BIT(18)),
+       [1]                     = RESET(0x4, BIT(18)),
+       [2]                     = RESET(0x8, BIT(18)),
+       [3]                     = RESET(0xc, BIT(18)),
 };
 
 const struct ccu_desc a80_ccu_desc = {