IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
};
-#ifdef CONFIG_CMD_NAND
-static iomux_v3_cfg_t const nfc_pads[] = {
- IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_gpmi_nand(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* config gpmi nand iomux */
- SETUP_IOMUX_PADS(nfc_pads);
-
- /* config gpmi and bch clock to 100 MHz */
- clrsetbits_le32(&mxc_ccm->cs2cdr,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
- /* enable gpmi and bch clock gating */
- setbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#endif
-
static void setup_iomux_enet(int gpio)
{
SETUP_IOMUX_PADS(enet_pads);
setup_ventana_i2c(0);
board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
-#ifdef CONFIG_CMD_NAND
- if (gpio_cfg[board_type].nand)
- setup_gpmi_nand();
-#endif
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
/* Serial */
#define CONFIG_MXC_UART_BASE UART2_BASE
-#if !defined(CONFIG_SPI_FLASH) && defined(CONFIG_SPL_NAND_SUPPORT)
-/* Enable NAND support */
-#ifdef CONFIG_CMD_NAND
- #define CONFIG_SYS_MAX_NAND_DEVICE 1
- #define CONFIG_SYS_NAND_BASE 0x40000000
- #define CONFIG_SYS_NAND_5_ADDR_CYCLE
- #define CONFIG_SYS_NAND_ONFI_DETECTION
-
- /* DMA stuff, needed for GPMI/MXS NAND support */
-#endif
-
-#endif /* CONFIG_SPI_FLASH */
+/* NAND */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* I2C Configs */
#define CONFIG_SYS_I2C