mx6: compute PLL PFD frequencies rather than using defines

Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index df11678609b060b75af3ae12b13a8cca94c75b6c..3bf80e2b016c3b2055de25fad81ce096e0e7e26f 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -100,6 +100,32 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
        }
        /* NOTREACHED */
 }
+static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
+{
+       u32 div;
+       u64 freq;
+
+       switch (pll) {
+       case PLL_BUS:
+               if (pfd_num == 3) {
+                       /* No PFD3 on PPL2 */
+                       return 0;
+               }
+               div = __raw_readl(&imx_ccm->analog_pfd_528);
+               freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
+               break;
+       case PLL_USBOTG:
+               div = __raw_readl(&imx_ccm->analog_pfd_480);
+               freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
+               break;
+       default:
+               /* No PFD on other PLL                                       */
+               return 0;
+       }
+
+       return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
+                             ANATOP_PFD_FRAC_SHIFT(pfd_num));
+}
 
 static u32 get_mcu_main_clk(void)
 {
@@ -144,13 +170,14 @@ u32 get_periph_clk(void)
                        freq = decode_pll(PLL_BUS, MXC_HCLK);
                        break;
                case 1:
-                       freq = PLL2_PFD2_FREQ;
+                       freq = mxc_get_pll_pfd(PLL_BUS, 2);
                        break;
                case 2:
-                       freq = PLL2_PFD0_FREQ;
+                       freq = mxc_get_pll_pfd(PLL_BUS, 0);
                        break;
                case 3:
-                       freq = PLL2_PFD2_DIV_FREQ;
+                       /* static / 2 divider */
+                       freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
                        break;
                default:
                        break;
@@ -184,7 +211,7 @@ static u32 get_ipg_per_clk(void)
 static u32 get_uart_clk(void)
 {
        u32 reg, uart_podf;
-       u32 freq = PLL3_80M;
+       u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);
 #ifdef CONFIG_MX6SL
        if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
@@ -204,7 +231,7 @@ static u32 get_cspi_clk(void)
        reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
        cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-       return  PLL3_60M / (cspi_podf + 1);
+       return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }
 
 static u32 get_axi_clk(void)
@@ -217,9 +244,9 @@ static u32 get_axi_clk(void)
 
        if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
                if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
-                       root_freq = PLL2_PFD2_FREQ;
+                       root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
                else
-                       root_freq = PLL3_PFD1_FREQ;
+                       root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
        } else
                root_freq = get_periph_clk();
 
@@ -244,10 +271,10 @@ static u32 get_emi_slow_clk(void)
                root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
                break;
        case 2:
-               root_freq = PLL2_PFD2_FREQ;
+               root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
                break;
        case 3:
-               root_freq = PLL2_PFD0_FREQ;
+               root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
                break;
        }
 
@@ -270,13 +297,14 @@ static u32 get_mmdc_ch0_clk(void)
                freq = decode_pll(PLL_BUS, MXC_HCLK);
                break;
        case 1:
-               freq = PLL2_PFD2_FREQ;
+               freq = mxc_get_pll_pfd(PLL_BUS, 2);
                break;
        case 2:
-               freq = PLL2_PFD0_FREQ;
+               freq = mxc_get_pll_pfd(PLL_BUS, 0);
                break;
        case 3:
-               freq = PLL2_PFD2_DIV_FREQ;
+               /* static / 2 divider */
+               freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
        }
 
        return freq / (podf + 1);
@@ -359,9 +387,9 @@ static u32 get_usdhc_clk(u32 port)
        }
 
        if (clk_sel)
-               root_freq = PLL2_PFD0_FREQ;
+               root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
        else
-               root_freq = PLL2_PFD2_FREQ;
+               root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 
        return root_freq / (usdhc_podf + 1);
 }

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 2813593e25bb2c38f7516b83ee6222f4ace0b973..720207303b01adbd34f94eba215468d9c0a408c6 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -890,15 +890,4 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
        (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
 
-#define PLL2_PFD0_FREQ         352000000
-#define PLL2_PFD1_FREQ         594000000
-#define PLL2_PFD2_FREQ         396000000
-#define PLL2_PFD2_DIV_FREQ     200000000
-#define PLL3_PFD0_FREQ         720000000
-#define PLL3_PFD1_FREQ         540000000
-#define PLL3_PFD2_FREQ         508200000
-#define PLL3_PFD3_FREQ         454700000
-#define PLL3_80M               80000000
-#define PLL3_60M               60000000
-
 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */